BIPOLAR SELECTOR WITH INDEPENDENTLY ADJUSTABLE THRESHOLD VOLTAGES

Abstract

Memory cell (102) comprising: a data storage element (106) having a variable resistor; and a bipolar selector (104) electrically coupled in series with the data storage element (106), the bipolar selector comprising a first unipolar selector (108) and a second unipolar selector (110), and the first and second unipolar selectors being electrically coupled in parallel with opposite orientations; where: the bipolar selector (104) has a first threshold voltage (VT1) at a first polarity and a second threshold voltage (VT2) at a second polarity; the first and second unipolar selectors (108, 110) individually define the first and second threshold voltages; the first and second threshold voltages are different; the data storage element (106) comprises a magnetic tunnel junction, and the magnetic tunnel junction comprises a ferromagnetic reference element (202) and a free ferromagnetic element (204); and the free ferromagnetic element (204) is electrically separated from the bipolar selector (104) by the ferromagnetic reference element (202), the ferromagnetic reference element is electrically separated from an anode (406) of the first unipolar selector (108) by a cathode (402) of the first unipolar selector, and a width (W1) of the first unipolar selector (108) is greater than a width (W2) of the second unipolar selector (110); or the ferromagnetic reference element (202) is electrically separated from the bipolar selector (104) by the free ferromagnetic element (204), the free ferromagnetic element is electrically separated from an anode (406) of the first unipolar selector by a cathode (402) of the first unipolar selector (108), and a width (W1) of the first unipolar selector (108) is smaller than a width (W2) of the second unipolar selector (110).

Description

BACKGROUND

[0001] Many modern electronic devices contain electronic memory. A cross-point memory architecture with single-selector, single-resistor (1S1R) memory cells is increasingly being considered for use in next-generation electronic memory due to its high density. Examples of next-generation electronic memory include resistive random access memory (RRAM), phase-change random access memory (PCRAM), magnetoresistive random access memory (MRAM), and conductive bridging random access memory (CBRAM).

[0002] US 6 130 814 A describes a magnetoresistive element connected in series with two diodes connected in parallel, the diodes being connected with opposite polarity and having the same threshold voltage. US 2012 / 0044736 A1 describes an MRAM cell that uses a first diode and a second diode as programming selectors. The MRAM cell has the two diodes and a magnetic tunnel junction, wherein the magnetic tunnel junction comprises a free layer, a fixed layer, and a dielectric film therebetween. The free layer is coupled to a supply voltage V. The first diode has its N-terminal connected to the fixed layer and its P-terminal to V+ for programming a 1. The second diode has its P-terminal connected to the fixed layer and its N-terminal to V- for programming a 0. When the voltage V+ is higher than V, a current flows from V+ to V to program the magnetic tunnel junction to state 1. Similarly, when the voltage V- is lower than V, a current flows from V to V- to program the magnetic tunnel junction to state 0.During programming, the other diode should be turned off. For reading, V+ and V- can both be set to 0 V, and the resistance between nodes V and V+ / V- can be measured to determine whether the magnetic tunnel junction is in the 0 or 1 state. US 7,035,141 B1 describes a memory structure comprising a first conductor, a second conductor, a resistive memory cell connected to the second conductor, a first diode connected to the resistive memory cell and the first conductor and oriented in the forward direction from the resistive memory cell to the first conductor, and a second diode connected to the resistive memory cell and the first conductor, connected in parallel with the first diode, and oriented in the reverse direction from the resistive memory cell to the first conductor. The first and second diodes have different threshold voltages. US 2014 / 0 319 634 A1 and US 2017 / 0 110 512 A1 describe further prior art. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying drawings. Note that, in accordance with industry practice, various features are not drawn to scale. Indeed, the dimensions of the various features may be arbitrarily exaggerated or reduced for clarity of description. Fig. 1 shows a schematic diagram of some embodiments of a memory cell with a bipolar selector with independently adjustable threshold voltages. The Fig. 2A and Fig. 2B show schematic diagrams of various more detailed embodiments of the memory cell of Fig. 1, in which a data storage element of the memory cell is a magnetic tunnel junction (MTJ). The Fig. 3A and Fig. 3B show schematic diagrams of some alternative embodiments of the memory cells of the Fig. 2A and 2B, respectively, where individual selectors of the bipolar selector have different sizes. The Fig. 4A and Fig. 4B show schematic diagrams of some more detailed embodiments of the memory cells of the Fig. 3A and 3B, respectively, in which the individual selectors of the bipolar selector are multilayer stacks. Fig. Figure 5 shows a graphical representation of some embodiments of current-voltage curves (IV curves) for the bipolar selector of Fig. 1. The Fig. 6A and Fig. 6B show cross-sectional views of various embodiments of an integrated chip that includes the memory cell of Fig. 1 includes. Fig. 7 shows a schematic view of some embodiments of a memory array having a plurality of memory cells, wherein the memory cells include bipolar selectors with independently adjustable threshold voltages. The Fig. 8A to 8C show schematic views of some embodiments of the memory array of Fig. 7 in different operating states. The Fig. 9A to 9D show schematic views of various alternative embodiments of the memory array of Fig. 7. The Fig. 10A and Fig. 10B show schematic views of various embodiments of a three-dimensional memory array (3D memory array) having a plurality of memory cells, wherein the memory cells comprise bipolar selectors with independently adjustable threshold voltages. The Fig. 11A and Fig. 11B show cross-sectional views of various embodiments of an integrated chip including a pair of stacked memory cells in the Fig. 10A and 10B respectively. The Fig. 12 to 17 show a series of cross-sectional views of some embodiments of a method for forming an integrated chip comprising a memory array, wherein memory cells of the memory array comprise bipolar selectors with independently adjustable threshold voltages. Fig. 18 shows a block diagram of some embodiments of the method of Fig. 12 to 17 DETAILED DESCRIPTION

[0004] The present disclosure contemplates many different embodiments or examples for implementing different elements of this disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, only examples. For example, in the following description, forming a first feature over or on top of a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first feature and the second feature such that the first and second features need not be in direct contact. Additionally, the present disclosure may repeat reference numbers and / or letters in the various examples.This repetition is for the purpose of simplicity and clarity and does not in itself impose any relationship between the various embodiments and / or configurations described.

[0005] Furthermore, spatially relative terms such as "below," "under," "lower," "above," "upper," and the like may be used herein for convenience of description to describe the relationship of one element or feature to one or more other elements or features as shown in the figures. The spatially relative terms are intended to encompass various orientations of the device being used or operated, in addition to the orientation shown in the figures. The device may be oriented differently (rotated 90 degrees or in a different orientation), and the spatially relative terms used herein may also be interpreted accordingly.

[0006] For example, a cross-point memory array may include multiple single-selector, single-resistor (1S1R) memory cells located at intersections of bit lines and word lines, respectively. By appropriately biasing a bit line and a word line, a 1S1R memory cell located at an intersection of the bit line and word line is selected, and current flows through the 1S1R memory cell. When a 1S1R memory cell is selected, a selector of the 1S1R memory cell is biased with a voltage higher than a threshold voltage of the selector. Furthermore, selectors of unselected memory cells on a bit line of the 1S1R memory cell and selectors of unselected memory cells on a word line of the 1S1R memory cell are biased because the bit line and word line are shared.However, the voltages at the selectors of the unselected memory cells are lower than the threshold voltages of the selectors, so no current flows through the other 1S1R memory cells.

[0007] 1S1R memory cells can be unipolar or bipolar. A unipolar 1S1R memory cell is read and written with a single polarity. A bipolar 1S1R memory cell is read and / or written with two polarities. For example, a bipolar 1S1R memory cell can be set to different states at different polarities. Therefore, selectors for unipolar 1S1R memory cells (i.e., unipolar selectors) switch with a single polarity and / or have a single threshold voltage, and selectors for bipolar 1S1R memory cells (i.e., bipolar selectors) switch with two polarities and / or have multiple threshold voltages at each of the two polarities.

[0008] Bipolar selectors typically have symmetrical threshold voltages. A symmetrical threshold voltage has a similar value for a first polarity as for a second polarity and cannot be adjusted for one polarity without adjusting for the other polarity. However, bias voltages used for a first polarity may differ from bias voltages used for a second polarity, which can make it difficult to match a symmetrical threshold voltage to the bias voltages for both the first and second polarities. Due to a mismatched threshold voltage, unselected 1S1R memory cells that share a bit or word line with a selected 1S1R memory cell may have selectors that are not fully turned OFF.As a result, a leakage current may flow through the unselected 1S1R memory cells, causing a read fault and / or a write fault. Furthermore, a selected 1S1R memory cell may have a selector that is not fully turned ON due to a mismatched threshold voltage. As a result, the selector may introduce a high degree of parasitic resistance into the selected 1S1R memory cell, causing a read fault. A read fault may narrow a read window of a selected 1S1R memory cell and / or cause a read error. A write fault may cause the state of an unselected 1S1R memory cell to change.

[0009] Various embodiments of the present application relate to a bipolar selector with independently adjustable threshold voltages, as well as to a memory cell including the bipolar selector and a memory array including the memory cell. In some embodiments, the bipolar selector comprises a first unipolar selector and a second unipolar selector. A unipolar selector may, for example, switch at a single polarity and / or have a single threshold voltage, while a bipolar selector may, for example, be a selector that switches at multiple polarities and / or has multiple threshold voltages, respectively, at the multiple polarities. The first and second unipolar selectors are electrically coupled in parallel with opposite orientations and may, for example, be diodes or other suitable unipolar selectors.

[0010] By arranging the first and second unipolar selectors in parallel with opposite orientations, the first unipolar selector independently defines a first threshold voltage of the bipolar selector, and the second unipolar selector independently defines a second threshold voltage of the bipolar selector. As a result, the first and second threshold voltages can be adjusted independently of each other by tuning the parameters of the first and second unipolar selectors. Independent adjustment allows the first and second threshold voltages to be better adapted to bias conditions for reading and / or writing the memory cell when the polarity of the memory cell changes between read and / or write operations. By better adapting to the bias conditions, read disturbances and / or write disturbances can be reduced.

[0011] With reference to Fig. 1, a schematic diagram 100 of some embodiments of a memory cell 102 is provided, including a bipolar selector 104 with independently adjustable threshold voltages. The bipolar selector 104 is electrically coupled in series with a data storage element 106 from a bit line BL to a source line SL. In some embodiments, the positions of the bit line BL and the source line SL are reversed. The bipolar selector 104 further has a first threshold voltage at a first polarity and further has a second threshold voltage at a second polarity. Here, the first and second threshold voltages are different. For example, the first threshold voltage may be 5 V, while the second threshold voltage may be 4 V, or vice versa. However, other values ​​are usable for the first and second threshold voltages. In further embodiments, the first and second threshold voltages are the same.

[0012] The bipolar selector 104 has the first polarity when the voltage across the bipolar selector 104 from the bit line BL to the data storage element 106 is positive, while the bipolar selector 104 has the second polarity when the voltage across the bipolar selector 104 from the data storage element 106 to the bit line BL is positive. At the first polarity, the bipolar selector 104 conducts and / or is in a low resistance state when the voltage across the bipolar selector 104 from the bit line BL to the data storage element 106 exceeds the first threshold voltage. Otherwise, at the first polarity, the bipolar selector 104 is non-conductive and / or is in a high resistance state. At the second polarity, the bipolar selector 104 conducts and / or is in a low resistance state when the voltage across the bipolar selector 104 from the data storage element 106 to the bit line BL exceeds the second threshold voltage.Otherwise, the bipolar selector 104 is non-conductive and / or in a high resistance state at the second polarity.

[0013] The bipolar selector 104 includes a first unipolar selector 108 and a second unipolar selector 110. The first and second unipolar selectors 108, 110 are electrically coupled in parallel with opposite orientations. A unipolar selector is a device that switches at a single polarity and / or has a single threshold voltage. At a first polarity, the unipolar selector conducts and / or is in a low resistance state when the voltage across the unipolar selector exceeds a threshold voltage. Otherwise, at the first polarity, the unipolar selector is non-conductive and / or is in a high resistance state. At the second polarity, the unipolar selector is non-conductive and / or is in a high resistance state.For example, the first and second unipolar selectors 108, 110 may have opposite directions in that the first unipolar selector 108 is configured to selectively allow current to flow in a first direction while blocking current flow in a second direction, while the second unipolar selector 110 is configured to selectively allow current to flow in the second direction while blocking current flow in the first direction.The first and second unipolar selectors 108, 110 may be, for example, PIN diodes, polysilicon diodes, punch-through diodes, varistor selectors, ovonic threshold switches (OTS), doped chalcogenide-based selectors, Mott effect selectors, MIEC (“Mixed Ionic Electronic Conductivity”)-based selectors, FAST (“Field Assisted Superlinear Threshold”)-based selectors, filament-based selectors, doped hafnium oxide-based selectors, or some other suitable diodes and / or selectors.

[0014] By arranging the first and second unipolar selectors 108, 110 in parallel with opposite directions, the first unipolar selector 108 independently defines the first threshold voltage, and the second unipolar selector 110 independently defines the second threshold voltage. As a result, the first and second threshold voltages can be adjusted independently of each other by tuning the parameters of the first and second unipolar selectors 108, 110. Independent adjustment allows the first and second threshold voltages to be better adapted to bias conditions for reading and / or writing the memory cell 102 when the polarity of the memory cell 102 changes between read and / or write operations. By better adapting to the bias conditions, read disturbances when reading the memory cell 102 can be reduced.Furthermore, write disturbances to neighboring memory cells (not shown) may be reduced while the memory cell 102 is being read and / or written.

[0015] In some embodiments, the first unipolar selector 108 has only two terminals and / or the second unipolar selector 110 has only two terminals. In some embodiments, the first unipolar selector 108 has more than two terminals and / or the second unipolar selector 110 has more than two terminals. In some embodiments (e.g., when the first and second unipolar selectors 108, 110 are diodes), a cathode of the first unipolar selector 108 is electrically coupled to an anode of the second unipolar selector 110, and an anode of the first unipolar selector 108 is electrically coupled to a cathode of the second unipolar selector 110. In alternative embodiments, bipolar selectors and / or another suitable type of selector are used instead of the unipolar selectors for the first and second unipolar selectors 108, 110.

[0016] The data storage element 106 stores a bit of data. In some embodiments, a resistance of the data storage element varies depending on a data state of the data storage element 106. For example, the data storage element 106 may have a low resistance in a first data state and a high resistance in a second data state. In further embodiments, the capacitance or another suitable parameter of the data storage element 106 varies depending on a data state of the data storage element 106. In some embodiments, the data storage element 106 is a magnetic tunnel junction (MTJ) or other suitable magnetic junction and / or the memory cell 102 is a spin-transfer torque MRAM (STT-MRAM) cell or other suitable MRAM cell.In some embodiments, the data storage element 106 is a metal-insulator-metal (MIM) stack and / or the memory cell 102 is a resistive random access memory (RRAM) cell. However, other structures for the data storage element 106 and / or other memory cell types for the memory cell 102 are possible.

[0017] In some embodiments, the data storage element 106 is set to a first data state at the first polarity and to a second data state at the second polarity, such that writing to the data storage element 106 is bipolar. For example, if the data storage element 106 is an MTJ, the data storage element 106 may be set to a first data state at the first polarity and to a second data state at the second polarity. Accordingly, the first threshold voltage is used while the data storage element 106 is set to the first data state, whereas the second threshold voltage is used while the data storage element 106 is set to the second data state. In some embodiments, the data storage element 106 is read with the first polarity, such that reading from the data storage element 106 is unipolar.Accordingly, only the first threshold voltage is used when reading from the data storage element 106.

[0018] With reference to Fig. 2A is a schematic diagram 200A of some more detailed embodiments of the memory cell 102 of Fig. 1, in which the data storage element 106 is an MTJ. The data storage element 106 includes a reference element 202, a free element 204, and a barrier element 206. The barrier element 206 is non-magnetic and is disposed between the reference element 202 and the free element 204. The reference element and the free element 202, 204 are ferromagnetic, and the free element 204 overlies the reference element 202 and the barrier element 206. Furthermore, the reference element 202 has a fixed magnetization, while the free element 204 has a variable magnetization.

[0019] Depending on whether the magnetizations of the reference and free elements 202, 204 are parallel or antiparallel, the data storage element 106 has a low resistance or a high resistance. For example, the data storage element 106 may have a low resistance when the magnetizations of the reference and free elements 202, 204 are parallel, and may have a high resistance when the magnetizations are antiparallel. The low and high resistances, in turn, can be used to represent different data states of the data storage element 106.

[0020] A first write voltage is applied to the data storage element 106 with a first polarity to place the data storage element 106 in an anti-parallel state, and a second write voltage is applied to the data storage element 106 with a second polarity to place the data storage element 106 in a parallel state. In some embodiments, the second write voltage is higher than the first write voltage because the data storage element 106 is typically, but not always, in a high resistance state (i.e., the anti-parallel state) when the data storage element 106 is placed in the parallel state. For example, the second write voltage may be approximately 1.5 to 3.0 times higher than the first write voltage. However, other factors greater than one (e.g., 5.0 or another value) are possible.In some embodiments where the second write voltage is higher than the first write voltage, the second threshold voltage is higher than the first threshold voltage because the first threshold voltage is used with the same polarity as the first write voltage and the second threshold voltage is used with the same polarity as the second write voltage. This can be schematically shown, for example, by an increased length L2 of the second unipolar selector 110 compared to a length L1 of the first unipolar selector 108.

[0021] In some embodiments, the barrier element 206 is a tunnel barrier that selectively allows quantum mechanical tunneling of electrons through the barrier element 206. For example, quantum mechanical tunneling may be allowed when the reference element 202 and the free element 204 have parallel magnetizations and may be blocked when the reference element 202 and the free element 204 have antiparallel magnetizations. The barrier element 206 may, for example, be or comprise an amorphous barrier, a crystalline barrier, or another suitable barrier. The amorphous barrier may, for example, be aluminum oxide (e.g., AlO x ), titanium oxide (e.g. TiO x ) or another suitable amorphous barrier. The crystalline barrier may be or comprise manganese oxide (e.g., MgO), spinel (e.g., MgAl2O4), or another suitable crystalline barrier.

[0022] In some embodiments, the reference element 202 is or comprises cobalt iron (e.g., CoFe), cobalt iron boron (e.g., CoFeB), or another suitable ferromagnetic material, or any combination of the foregoing. In some embodiments, the reference element 202 is adjacent to or otherwise adjacent to an antiferromagnetic element (not shown) and / or is part of a synthetic antiferromagnetic (SAF) element (not shown). In some embodiments, the free element 204 is or comprises cobalt iron (e.g., CoFe), cobalt iron boron (e.g., CoFeB), or another suitable ferromagnetic material, or any combination of the foregoing.

[0023] With reference to Fig. 2B is a schematic diagram 200B of some alternative embodiments of the memory cell 102 of Fig. 2A, in which the reference element 202 is located above the free element 204. Since the reference element 202 is located above the free element 204, the polarities at which the first and second write voltages are applied to the data storage element 106 are different compared to Fig. 2A in reverse. The first write voltage is applied to the data storage element 106 with the second polarity to place the data storage element 106 in the anti-parallel state, and the second write voltage is applied to the data storage element 106 with the first polarity to place the data storage element 106 in the parallel state. In some embodiments where the second write voltage is higher than the first write voltage, the first threshold voltage is higher than the second threshold voltage because the first threshold voltage is used with the same polarity as the second write voltage and the second threshold voltage is used with the same polarity as the first write voltage. This can be schematically shown, for example, by an increased length L1 of the first unipolar selector 108 compared to the length L2 of the second unipolar selector 110.

[0024] With reference to Fig. 3A is a schematic diagram 300A of some alternative embodiments of the memory cell 102 of Fig. 2A, in which a size of the first unipolar selector 108 is larger than a size of the second unipolar selector 110. This can be schematically shown, for example, by an increased width W1 of the first unipolar selector 108 compared to a width W2 of the second unipolar selector 110. In some embodiments, the first and second unipolar selectors 108, 110 are each formed by a multilayer stack, and the size of the first unipolar selector 108 is larger than the size of the second unipolar selector 110 with respect to the cross-sectional width of the multilayer stack.

[0025] In some embodiments, the first unipolar selector 108 has a lower ON resistance than the ON resistance of the second unipolar selector 110 due to its larger size. Furthermore, in some embodiments, the first unipolar selector 108 is turned ON while the memory cell 102 is being read, whereas the second unipolar selector 110 is turned OFF while the memory cell 102 is being read. Therefore, the larger size of the first unipolar selector 108 may reduce the parasitic resistance while the memory cell 102 is being read, thereby increasing the read window.

[0026] With reference to Fig. 3B is a schematic diagram 300B of some alternative embodiments of the memory cell 102 of Fig. 2B, in which a size of the second unipolar selector 110 is larger than a size of the first unipolar selector 108. This can be schematically shown, for example, by an increased width W2 of the second unipolar selector 110 compared to the width W1 of the first unipolar selector 108. The larger size of the second unipolar selector 110 can, for example, reduce the parasitic resistance during reading of the memory cell 102, which increases the read window and reduces read disturbance.

[0027] With reference to Fig. 4A is a schematic diagram 400A of some more detailed embodiments of the memory cell 102 of Fig. 3A, in which the first and second unipolar selectors 108, 110 are multilayer stacks. The first and second unipolar selectors 108, 110 each include a single cathode 402, a single insulator 404, and a single anode 406. The insulators 404 are each disposed between a respective cathode 402 and a respective anode 406. The multilayer stacks may be or include, for example, PIN diodes, MIM devices, or some other multilayer devices.

[0028] In some embodiments where the multilayer stacks are PIN diodes, the cathodes 402 are or comprise n-type semiconductor material, the anodes 406 are or comprise p-type semiconductor material, and the insulators 404 are or comprise intrinsic or lightly doped semiconductor material. For example, the insulators 404 may be lightly doped relative to the cathodes 402 and / or the anodes 406. The semiconductor material of the multilayer stacks may be or comprise, for example, polysilicon, single-crystal silicon, germanium, indium gallium arsenide, or another suitable semiconductor material. In some embodiments where the multilayer stacks are MIM devices, the cathodes 402 and the anodes 406 are or comprise metal or another suitable conductive material, and / or the insulators 404 are or comprise doped hafnium oxide, another suitable metal oxide, or another suitable insulating material.

[0029] In some embodiments, the thickness of the insulators 404 is varied to tune the threshold voltages of the first and second unipolar selectors 108, 110. For example, increasing a thickness of an insulator may increase a threshold voltage of the corresponding unipolar selector, while decreasing the thickness may decrease the threshold voltage. In some embodiments, a second insulator thickness T2 of the second unipolar selector 110 is greater than a first insulator thickness T1 of the first unipolar selector 108, such that the second unipolar selector 110 has a higher threshold voltage than the first unipolar selector 108. In some embodiments, the doping concentration of the insulators 404 is varied to tune the threshold voltages of the first and second unipolar selectors 108, 110.For example, increasing a doping concentration of an insulator may decrease a threshold voltage of the corresponding selector, while decreasing the doping concentration may increase the threshold voltage.

[0030] In some embodiments, the width of the first and second unipolar selectors 108, 110 is varied to adjust the ON resistances of the first and second unipolar selectors 108, 110. For example, increasing a width of a selector may decrease an ON resistance of the selector, while decreasing the width may increase the ON resistance. In some embodiments, a second width W2 of the second unipolar selector 110 is smaller than a first width W1 of the first unipolar selector 108, such that the first unipolar selector 108 has a lower ON resistance than the second unipolar selector 110. As mentioned above, the lower ON resistance may increase the read window for the memory cell 102 when the first unipolar selector 108 is turned ON during reading.

[0031] With reference to Fig. 4B is a schematic diagram 400B of some more detailed embodiments of the memory cell 102 of Fig. 3B, in which the first and second unipolar selectors 108, 110 are multilayer stacks. The first and second unipolar selectors 108, 110 each include a single cathode 402, a single insulator 404, and a single anode 406. The cathodes 402, the insulators 404, and the anodes 406 may, for example, be as described above with reference to Fig. 4A. In some embodiments, the first insulator thickness T1 of the first unipolar selector 108 is greater than the second insulator thickness T2 of the second unipolar selector 110, such that the first unipolar selector 108 has a higher threshold voltage than the second unipolar selector 110. In some embodiments, the second width W2 of the second unipolar selector 110 is greater than the first width W1 of the first unipolar selector 108, such that the second unipolar selector 110 has a lower ON resistance than the first unipolar selector 108.

[0032] With reference to Fig. 5 is a graph 500 of some embodiments of current-voltage (IV) curves for the bipolar selector 104 of Fig. 1. A horizontal axis of the graph 500 corresponds to voltage, and a vertical axis of the graph 500 corresponds to current. Furthermore, an upper right quadrant of the graph 500 corresponds to a first polarity of the bipolar selector 104, and a lower left quadrant of the graph 500 corresponds to a second polarity of the bipolar selector 104. The graph 500 includes a first IV curve 502 and a second IV curve 504.

[0033] Looking at the first IV curve 502, the current is approximately zero until the voltage reaches a first threshold voltage V T1 of the bipolar selector 104, and then increases in magnitude with the voltage. Furthermore, the current is approximately zero until the voltage reaches a second threshold voltage V T2of the bipolar selector 104, and then increases in magnitude with the voltage. In some embodiments, the bipolar selector 104 has Fig. 1 the first IV curve 502 when the first and second unipolar selectors 108, 110 of Fig. 1 are polysilicon diodes, PIN diodes, or other suitable type of diode. For example, embodiments of the bipolar selectors 104 in the Fig. 4A and Fig. 4B, the first IV curve 502, since the first and second unipolar selectors 108, 110 may be PIN diodes.

[0034] Looking at the second IV curve 504, the second IV curve 504 has a declining shape. The current is approximately zero until the voltage reaches the first threshold voltage V T1of the bipolar selector 104, and then increases in magnitude. As the current increases in magnitude, the voltage returns toward zero volts before increasing in magnitude. Furthermore, the current is approximately zero until the voltage exceeds the second threshold voltage V T2 of the bipolar selector 104, and then increases in magnitude. As the current increases in magnitude, the voltage returns toward zero volts before increasing in magnitude. In some embodiments, the bipolar selector 104 has the second IV curve 504 when the first and second unipolar selectors 108, 110 are MIM devices that include doped hafnium oxide insulators. For example, embodiments of the bipolar selector 104 in the Fig. 4A and Fig. 4B, the second IV curve 504 may have the first and second unipolar selectors 108, 110, since the first and second unipolar selectors 108, 110 may be MIM devices comprising doped hafnium oxide insulators.

[0035] For example, embodiments of the bipolar selector 104 with the second IV curve 504 may have a lower ON resistance compared to embodiments of the bipolar selector 104 with the first IV curve 502. For a given current (marked by the dashed line 506), the second IV curve 504 has a lower voltage than the first IV curve 502 due to flyback. Therefore, according to Ohm's law, the resistance across the bipolar selector 104 is lower for embodiments of the bipolar selector 104 with the second IV curve 504 than for embodiments of the bipolar selector 104 with the first IV curve 502. The lower resistance, in turn, increases the read window for the memory cell 102 of Fig. 1, because there is less parasitic resistance.

[0036] Regardless of whether the bipolar selector 104 has the first or the second IV curve 502, 504, the first threshold voltage V T1by the first unipolar selector 108 of Fig. 1 and the second threshold voltage V T2 is determined by the second unipolar selector 110 of Fig. 1. The first and second threshold voltages V T1 , V T2 have a different height, so that the bipolar selector 104 has an asymmetric threshold voltage. In some embodiments, the first and second threshold voltages V T1, V T2 the same height, so that the bipolar selector 104 has a symmetrical threshold voltage.

[0037] With reference to Fig. 6A, a cross-sectional view 600A of some embodiments of an integrated chip is provided that includes the memory cell 102 of Fig. 1. The memory cell 102 overlies a substrate 602 and is located within an interconnect structure 604 covering the substrate 602. The interconnect structure 604 includes a dielectric interconnect layer 606, a plurality of wires 608, and a plurality of vias 610. For ease of illustration, only some of the vias 610 are labeled 610. The dielectric interconnect layer 606 houses the wires 608, the vias 610, and the memory cell 102 and may be or include, for example, silicon oxide, a low-k dielectric, another suitable dielectric, or any combination of the foregoing. As used herein, a low-k dielectric may be, for example, a dielectric having a dielectric constant k of less than about 3.9, 3, 2, or 1.

[0038] The wires 608 and the vias 610 are alternately stacked in the dielectric interconnect layer 606 to define conductive traces that connect components of the memory cell 102 and / or connect the memory cell 102 to other devices (not shown) in the integrated chip. For example, the wires 608 and the vias 610 may define conductive traces that electrically couple the first and second unipolar selectors 108, 110 in parallel. As another example, the wires 608 and the vias 610 may define conductive traces that electrically couple the bipolar selector 104 in series with the data storage element 106 from a wire defining the bit line BL to a wire defining the source line SL. The wires 608 and the vias 610 may be or include, for example, metal, another suitable conductive material, or any combination of the foregoing.

[0039] With reference to Fig. 6B is a cross-sectional view 600B of some alternative embodiments of the integrated chip of Fig. 6A, in which a semiconductor device 612 lies beneath the memory cell 102. For example, disposing the semiconductor device 612 beneath the memory cell 102 may improve a functional density of the integrated chip. In some embodiments, the semiconductor device 612 is electrically separated from the memory cell 102 and / or the wires 608 and the vias 610 do not define a conductive path directly from the semiconductor device 612 to the memory cell 102. In further embodiments, the semiconductor device 612 is electrically connected to the memory cell 102 through the wires 608 and the vias 610. The semiconductor device 612 may be, for example, a metal-oxide-semiconductor (MOS) device, an insulated-gate field-effect transistor (IGFET), or another suitable semiconductor device.

[0040] In some embodiments, the semiconductor device 612 includes a pair of source / drain regions 614, a gate dielectric layer 616, and a gate electrode 618. The source / drain regions 614 are located in the substrate 602 along a top surface of the substrate 602. The gate dielectric layer 616 and the gate electrode 618 are stacked above the substrate 602, vertically between the substrate 602 and the interconnect structure 604, and laterally between the source / drain regions 614.

[0041] With reference to Fig. 7, a schematic view 700 of some embodiments of a memory array 702 is provided, including a plurality of memory cells 102 in a plurality of rows and a plurality of columns. For ease of illustration, only some of the memory cells 102 are labeled 102. In some embodiments, only a portion of the memory array 702 is shown. For example, although three rows and three columns are shown, more rows and more columns may be present outside of the schematic view 700A. In other embodiments, the memory array 702 is shown in its entirety and therefore includes three rows and three columns.

[0042] The memory cells 102 each comprise a single bipolar selector 104 with an independently adjustable threshold voltage and further each comprise a single data storage element 106. For simplicity of illustration, only some of the bipolar selectors 104 are designated 104, and only some of the data storage elements 106 are designated 106. The bipolar selectors 104 are each electrically coupled in series with the data storage elements 106 and each comprise a single first unipolar selector 108 and a single second unipolar selector 110. For clarity, only some of the first unipolar selectors 108 are designated 108, and only some of the second unipolar selectors 110 are designated 110. The first unipolar selectors 108 are electrically coupled in parallel with the second unipolar selectors 110 and define threshold voltages of the bipolar selectors 104 at a first polarity.The second unipolar selectors 110 define threshold voltages of the bipolar selectors 104 at a second polarity. The memory cells 102 may, for example, each be as described with respect to FIG. Fig. 1 is shown and described.

[0043] Bit lines extend laterally along corresponding rows of the memory array and are electrically connected to memory cells in the corresponding rows, whereas source lines extend laterally along corresponding columns of the memory array and are electrically connected to memory cells in the corresponding columns. For clarity, the bit lines are labeled BL. m , BL m+1 and BL m+2 where the indices indicate corresponding rows and m is an integer variable representing a row in the memory array 702. Similarly, the source lines are each labeled SL n , SL n+1 and SLn+2 where the indices indicate corresponding columns and n is an integer variable representing a column in the memory array.

[0044] By appropriately biasing a bit line and a source line, the memory cell at the intersection of the bit line and the source line can be selected and read or written. In some embodiments, the bias conditions have different polarities depending on whether a first data state is being written to a memory cell or a second data state is being written to a memory cell. Furthermore, the bipolar selectors 104 prevent read and / or write disturbance to unselected memory cells that share a bit line or a source line with the selected memory cell.

[0045] With reference to the Fig. 8A to 8C is a schematic diagram 800A to 800C of some embodiments of the memory array 702 of Fig. 7 in various operating states to show the operation of the bipolar selectors 104. Fig. 8A shows the memory array 702 while a selected memory cell 102s is being written with a first data state (e.g., a logical “1”), and Fig. 8B shows the memory array 702 while the selected memory cell 102s is being written with a second data state (e.g., a logic “0”). Fig. Figure 8C shows the memory array 702 reading a state of the selected memory cell 102s.

[0046] As in Fig. 8A, the selected memory cell 102s is located at the crossing point of the source line SL n and the bit line BL m+2 . The bit line BL m+2 is connected to a first write voltage V w1 biased, while the source line SL n is grounded. In some embodiments, the other source lines SL n+1 , SL n+2and the other bit lines BL m , BL m+1 with half the first write voltage V w1 or another fraction of the first write voltage V w1 biased to reduce write disturbances to unselected memory cells. The first write voltage V w1 is positive from the bit line BL m+2 to the source line SL n , so that the selected memory cell 102s has a first polarity and the second unipolar selector 110 of the selected memory cell 102s is turned OFF. Furthermore, the first write voltage V w1 a first threshold voltage of the first unipolar selectors 108, so that the first unipolar selector 108 of the selected memory cell 102s is switched ON and a current I w1 flows through the selected memory cell 102s. The current I w1in turn sets the data storage element 106 of the selected memory cell 102s to the first data state.

[0047] Some unselected memory cells 102u (only some of which are labeled 102u) share the source line SL n or the bit line BL m+2 with the selected memory cell 102s, whereby these unselected memory cells 102u are also biased with the first polarity. For example, the unselected memory cells 102u may be biased with a voltage that is approximately half of the first write voltage V w1However, the bias voltages of the unselected memory cells 102u are lower than the first threshold voltage of the first unipolar selectors 108, thereby turning the first unipolar selectors 108 of the unselected memory cells 102u off. Furthermore, since the unselected memory cells 102u are biased with the first polarity, the second unipolar selectors 110 of the unselected memory cells 102u are off. Accordingly, no current flows through the unselected memory cells 102u, and there is no write disturbance for the unselected memory cells 102u.

[0048] As in Fig. As shown in Figure 8B, the source line SL n with a second write voltage V w0 biased, while the bit line BL m+2 is grounded. In some embodiments, the other source lines SL n+1 , SL n+2 and the other bit lines BL m , BL m+1with half the second write voltage V w0 or another fraction of the second write voltage V w0 biased. The second write voltage V w0 is positive from the source line SL n to the bit line BL m+2 , so that the selected memory cell 102s has a second polarity and the first unipolar selector 108 of the selected memory cell 102s is turned OFF. Furthermore, the second write voltage exceeds V w0 a second threshold voltage of the second unipolar selectors 110, so that the second unipolar selector 110 of the selected memory cell 102s is turned ON and a current V w0 flows through the selected memory cell 102s. The current V w0 in turn sets the data storage element 106 of the selected memory cell 102s to the second data state.

[0049] The unselected memory cells 102u, which share the source line SL nor the bit line BL m+2 with the selected memory cell 102s are also biased with the second polarity. For example, the unselected memory cells 102u may be biased with a voltage that is approximately half of the second write voltage V w0 However, the bias voltages of the unselected memory cells 102u are lower than the second threshold voltage of the second unipolar selectors 110, thereby turning the second unipolar selectors 110 of the unselected memory cells 102u off. Furthermore, since the unselected memory cells 102u are biased with the second polarity, the first unipolar selectors 108 of the unselected memory cells 102u are off. Accordingly, no current flows through the unselected memory cells 102u, and there is no write disturbance for the unselected memory cells 102u.

[0050] As in Fig. As shown in Figure 8C, the bit line BL m+2 with a reading voltage V r biased, while the source line SL n is grounded. Fig. 8C resembles Fig. 8A, except that the reading voltage V r instead of the first write voltage V w1 is used and is small enough that the resulting read current I r a state of the selected memory cell 102s does not change. Since the resistances of the data storage elements 106 vary with the corresponding data states, the selected memory cell 102s is in a state dependent on the level of the read current I r in the first data state or the second data state.

[0051] In some embodiments, the first and second write voltages V w1 , V w0 and the reading voltage V r, which is why the first and second threshold voltages of the bipolar selectors 104 are different so that they are well adapted to the bias conditions during the different operations. A well-adapted threshold voltage for the second polarity can, for example, be a voltage halfway between: 1) a voltage at the bipolar selector 104 of the selected memory cell 102s during the second write operation (see Fig. 8B); and 2) a voltage at the bipolar selectors 104 of the unselected memory cells 102u during the second write operation (see Fig. 8B). Since the first write operation and the read operation are both performed at the first polarity, the bias conditions can be taken into account during both operations if the first threshold voltage is properly selected. A well-matched threshold voltage for the first polarity can, for example, be a voltage halfway between: 1) a voltage at the bipolar selector 104 of the selected memory cell 102s during the read operation (see Fig. 8C); and 2) a voltage at the bipolar selectors 104 of the unselected memory cells 102u during the first write operation (see Fig. 8A). For example, the first threshold voltage can be set independently of the second threshold voltage and vice versa, since the first threshold voltage is determined by the first unipolar selectors 108 and the second threshold voltage is defined separately by the second unipolar selectors 110.

[0052] With reference to Fig. 9A is a schematic view 900A of some alternative embodiments of the memory array 702 of Fig. 7, in which the memory cells 102 are each as they are with respect to Fig. 2A. The data storage elements 106 each include a single reference element 202, a single free element 204, and a single barrier element 206. For ease of illustration, only some of the reference elements 202 are labeled 202, only some of the free elements 204 are labeled 204, and only some of the barrier elements 206 are labeled 206. The free elements 204 overlie the reference elements 202, and the barrier elements are disposed between the reference elements 202 and the free elements 204.

[0053] With reference to Fig. 9B is a schematic view 900B of some alternative embodiments of the memory array 702 of Fig. 9A, in which the memory cells 102 are each shown with reference to Fig. 2B instead of Fig. 2A. With reference to Fig. 9C is a schematic view 900C of some alternative embodiments of the memory array 702 of Fig. 9A, in which the memory cells 102 are each shown with reference to Fig. 3A instead of Fig. 2A. With reference to Fig. 9D is a schematic view 900D of some alternative embodiments of the memory array 702 of Fig. 9A, in which the memory cells 102 are each shown with reference to Fig. 3B instead of Fig. 2A are shown and described.

[0054] With reference to Fig. 10A provides a schematic view 1000A of some embodiments of a three-dimensional (3D) memory array including a first memory array 702a and a second memory array 702b. The first and second memory arrays 702a, 702b are stacked such that the second memory array 702b overlies and is spaced from the first memory array 702a. Stacking the first and second memory arrays 702a, 702b may, for example, improve memory density. In some embodiments, as shown, the first and second memory arrays 702a, 702b are each configured as the memory array 702 in Fig. 7. In further embodiments, the first and second memory arrays 702a, 702b are each as the memory array 702 in one of the Fig. 9A to 9D. In still further embodiments, the first memory array 702a is as the memory array 702 in any of the Fig. 7 and 9A to 9D, and the second memory array 702b is as shown and described in another of the Fig. 7 and 9A to 9D.

[0055] With reference to Fig. 10B is a schematic view 1000B of some alternative embodiments of the 3D memory array of Fig. 10A, in which the first and second memory arrays 702a, 702b share source lines. As above, the source lines are each labeled SL n , SL n+1 and SL n+2 where the indices indicate corresponding columns and n is an integer variable representing a column in the 3D memory array.

[0056] With reference to Fig. 11A, a cross-sectional view 1100A of some embodiments of an integrated chip is provided that includes a pair of stacked memory cells 102 from the 3D memory array of Fig. 10A. The stacked memory cells 102 are located in the same row and column in the 3D memory array. Furthermore, a lower one of the stacked memory cells 102 is located in the first memory array 702a of Fig. 10A, whereas an upper one of the stacked memory cells 102 in the second memory array 702b of Fig. 10A. The stacked memory cells 102 lie above a substrate 602 and are surrounded by a dielectric interconnect layer 606 of an interconnect structure 604. Furthermore, the wires 608 and the vias 610 in the dielectric interconnect layer 606 electrically connect components of the stacked memory cells 102.

[0057] With reference to Fig. 11B is a cross-sectional view 1100B of some alternative embodiments of the integrated chip of Fig. 11A, in which the stacked memory cells 102 are instead formed from the 3D memory array of Fig. 10B. Accordingly, the stacked memory cells 102 share a source line SL defined by one of the wires 608.

[0058] With reference to the Fig. 12 to 17, a series of cross-sectional views 1200 to 1700 of some embodiments of a method for forming an integrated chip with a memory array is provided, in which memory cells of the memory array include bipolar selectors with independently adjustable threshold voltages. For ease of illustration, cross-sectional views 1200 to 1700 show only a first memory cell of the memory array. However, other memory cells of the memory array may, for example, be formed concurrently with the first memory cell, and / or each of the other memory cells may, for example, be formed as shown for the first memory cell.

[0059] As shown in cross-sectional view 1200 of Fig. 12, an interconnect structure 604 is partially formed over a substrate 602. The substrate 602 may be, for example, a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, or another suitable substrate. The interconnect structure 604 includes a first dielectric interconnect layer 606a, a first wire 608a defining a bit line BL, and a first set of vias 610a. The first dielectric interconnect layer 606a receives the first wire 608a and the first vias 610a and may be or include, for example, silicon oxide, a low-k dielectric, another suitable dielectric, or any combination of the foregoing. A low-k dielectric may be, for example, a dielectric having a dielectric constant k of less than about 3.9, 3, 2, or 1.The first wire 608a and the first vias 610a are stacked in the first dielectric interconnect layer 606a such that the first vias 610a overlie the first wire 608a.

[0060] In some embodiments, semiconductor devices (not shown) are located on the substrate 602 between the substrate 602 and the interconnect structure 604. In some embodiments, additional wires (not shown) and / or additional vias (not shown) are alternately stacked in the first dielectric interconnect layer 606a between the substrate 602 and / or the first wire 608a. The additional wires and / or the additional vias may, for example, define conductive traces originating from semiconductor devices (not shown) on the substrate 602.In some embodiments, a process for partially forming the interconnect structure 604 includes: 1) depositing a lower interconnect portion of the first dielectric interconnect layer 606a on the substrate 602; 2) forming the first wire 608a inserted into the lower interconnect portion; 3) forming an upper interconnect portion of the first dielectric interconnect layer 606a on the first wire 608a and the lower interconnect portion; and 4) forming the first vias 610a inserted into the upper interconnect portion. However, other processes for partially forming the interconnect structure 604 are possible.

[0061] As shown in cross-sectional view 1300 of Fig. As shown in Figure 13, a first unipolar selector 108 is formed over the bit line BL and electrically connected to the bit line BL through one of the first vias 610a. The first unipolar selector 108 includes a cathode 402a, an insulator 404a, and an anode 406a. The insulator 404a is located between the cathode 402a and the anode 406a, and the cathode 402a lies above the anode 406a. The cathode 402a, the insulator 404a, and the anode 406a may define, for example, a PIN diode, a MIM device, or another multilayer device.

[0062] In some embodiments where cathode 402a, insulator 404a, and anode 406a define a PIN diode, cathode 402a is or comprises an n-type semiconductor material, anode 406a is or comprises a p-type semiconductor material, and insulator 404a is or comprises intrinsic or lightly doped semiconductor material. For example, insulator 404a may be lightly doped relative to cathode 402a and / or anode 406a. The semiconductor material for cathode 402a, insulator 404a, and anode 406a may be or comprise, for example, polysilicon, single-crystal silicon, or another suitable semiconductor material.In some embodiments where the cathode 402a, the insulator 404a, and the anode 406a define a MIM device, the cathode 402a and the anode 406a are or comprise metal or other suitable conductive material and / or the insulator 404a is or comprises doped hafnium oxide, another suitable metal oxide, or another suitable insulating material.

[0063] In some embodiments, a process for forming the first unipolar selector 108 includes: 1) depositing an anode layer on the interconnect structure 604; 2) depositing an insulating layer on the anode layer; 3) depositing a cathode layer on the insulating layer; and 4) patterning the multilayer film into the first unipolar selector 108. However, other processes are possible. The deposition may be performed, for example, by chemical vapor deposition (CVD), physical vapor deposition (PVD), electroless plating, electroplating, one or more other suitable deposition processes, or any combination of the foregoing. The patterning may be performed, for example, by a photolithography / etching process and / or another suitable patterning process(es).

[0064] As shown in the cross-sectional view 1400 of Fig. As shown in Figure 14, a second unipolar selector 110 is formed over the bit line BL adjacent to the first unipolar selector 108 and electrically connected to the bit line BL through another of the first vias 610a. Similar to the first unipolar selector 110, the second unipolar selector 110 includes a cathode 402b, an insulator 404b, and an anode 406b, and the insulator 404b is located between the cathode 402b and the anode 406b. However, unlike the first unipolar selector 108, the anode 406b is located over the cathode 402b, and the second unipolar selector 110 has a different orientation than the first unipolar selector 108. The cathode 402b, the insulator 404b, and the anode 406b may define, for example, a PIN diode, a MIM device, or another multilayer device.

[0065] In some embodiments where cathode 402b, insulator 404b, and anode 406b define a PIN diode, cathode 402b, insulator 404b, and anode 406b are as described for corresponding counterparts of first unipolar selector 108. In some embodiments where cathode 402b, insulator 404b, and anode 406b define an MIM device, cathode 402b, insulator 404b, and anode 406b are as described for corresponding counterparts of first unipolar selector 108.

[0066] In some embodiments, the insulator 404b of the second unipolar selector 110 has a greater thickness than the insulator 404a of the first unipolar selector 108, such that the second unipolar selector 110 has a higher threshold voltage than the first unipolar selector 108. For example, the differences between the threshold voltages of the first and second unipolar selectors 108, 110 may allow the first and second unipolar selectors 108, 110 to be better matched to the respective bias conditions to reduce read and / or write disturbances. In some embodiments, the first and second unipolar selectors 110 have different widths.

[0067] In some embodiments, a process for forming the second unipolar selector 110 includes: 1) depositing a cathode layer on the interconnect structure 604; 2) depositing an insulating layer on the anode layer; 3) depositing an anode layer on the insulating layer; and 4) patterning the multilayer film into the first unipolar selector 108. However, other processes are possible. For example, the deposition and patterning may be as described for the first unipolar selector 108.

[0068] As shown by the cross-sectional view 1500 of Fig. 15, the interconnect structure 604 is extended around the first and second unipolar selectors 108, 110 such that the interconnect structure 604 electrically couples the first and second unipolar selectors 108, 110 in parallel to define a bipolar selector 104. The extended interconnect structure 604 further includes a second dielectric interconnect layer 606b, a second wire 608b, and a set of second vias 610b. The second dielectric interconnect layer 606b receives the second wire 608b and the second vias 610b and may, for example, be as described for the first dielectric interconnect layer 606a.The second wire 608b and the second vias 610b are stacked in the second dielectric interconnect layer 606b such that the second wire 608b is electrically coupled to the first and second unipolar selectors 108, 110 through some of the second vias 610b and that one of the second vias 610b overlies the second wire 608b.

[0069] In some embodiments, a process for extending the interconnect structure 604 includes: 1) depositing a lower interconnect portion of the second dielectric interconnect layer 606b; 2) simultaneously forming the second wire 608b and second vias 610b beneath the second wire 608b inserted into the lower interconnect portion; 3) forming an upper interconnect portion of the second dielectric interconnect layer 606b on the second wire 608b and the lower interconnect portion; and 4) forming a second via 610b over the second wire 608b and inserted into the upper interconnect portion. However, other processes for extending the interconnect structure 604 are possible.

[0070] As shown in the cross-sectional view 1600 of Fig. 16, a data storage element 106 is formed over the interconnect structure 604 on one of the second vias 610b. The data storage element 106 may, for example, be an MTJ, an MIM stack, or other suitable structure for data storage. In some embodiments where the data storage element 106 is an MTJ, the data storage element 106 includes a reference element 202, a free element 204, and a barrier element 206. The barrier element 206 is non-magnetic and is disposed between the reference element 202 and the free element 204. The reference element and the free element 202, 204 are ferromagnetic, and the free element 204 overlies the reference element 202 and the barrier element 206. Alternatively, the positions of the reference and free elements 202, 204 are reversed.

[0071] In some embodiments, a process for forming the data storage element 106 includes: 1) depositing a reference layer on the interconnect structure 604; 2) depositing a barrier layer on the reference layer; 3) depositing a free layer on the barrier layer; and 4) patterning the reference, barrier, and free layers into the data storage element 106. However, other processes are possible. For example, the free layer may be deposited at 1) and the reference layer may be deposited at 3). The deposition may be performed, for example, by CVD, PVD, electroless plating, electroplating, one or more other suitable deposition processes, or any combination of the foregoing. The patterning may be performed, for example, by a photolithography / etching process and / or another suitable patterning process(es).

[0072] As shown by the cross-sectional view 1700 of Fig. 17, the interconnect structure 604 is completed around the data storage element 106. The completed interconnect structure 604 includes a third dielectric interconnect layer 606c, a third wire 608c defining a source line SL, and a third via 610c. The third dielectric interconnect layer 606c houses the third wire 608c and the third via 610c. Further, the third dielectric interconnect layer 606c may, for example, be as described for the first dielectric interconnect layer 606a. In some embodiments, a process for completing the interconnect structure 604 includes: 1) depositing the third dielectric interconnect layer 606c; and 2) simultaneously forming the third wire 608c and the third via 610c inserted into the third dielectric interconnect layer 606c. However, other processes for extending the connection structure 604 are possible.

[0073] The Fig. 12 to 17 can be used, for example, to form the memory cell in one of the Fig. 1, Fig. 2A, Fig. 2B, Fig. 3A, Fig. 3B, Fig. 4A or Fig. 4B, of the integrated chip in one of the Fig. 6A, Fig. 6B, Fig. 11A or Fig. 11B or the memory array in one of the Fig. 7, 8A to 8C, 9A to 9D, 10A or 10B. While the Fig. 12 to 17 are described with reference to a method, it becomes clear that the cross-sectional views 1200 to 1700 shown in the Fig. The structures shown in Figures 12 to 17 are not limited to the method and can stand alone without the method.

[0074] With reference to Fig. 18 is a block diagram 1800 of some embodiments of the method of Fig. 12 to 17 provided.

[0075] At 1802, an interconnect structure is partially formed on a substrate, the partially formed interconnect structure including a bitline wire and a pair of vias on the bitline wire. See, for example, Fig. 12.

[0076] At 1804, a first unipolar selector and a second unipolar selector are each formed adjacent to the vias, with an anode of the first unipolar selector facing the bitline wire and a cathode of the second unipolar selector facing the bitline wire. See, for example, Fig. 13 and Fig. 14.

[0077] In 1806, the interconnect structure is extended around the first and second unipolar selectors, the extended interconnect structure including an intermediate selector wire electrically coupling a cathode of the first unipolar selector to an anode of the second unipolar selector. See, for example, Fig. 15.

[0078] In 1808, a data storage element is formed on the intermediate selector wire. See, for example, Fig. 16.

[0079] At 1810, the interconnect structure is formed around the data storage element, the completed interconnect structure including a source lead wire overlying and electrically coupled to the data storage element. See, for example, Fig. 17.

[0080] While the block diagram 1800 of Fig.18 is shown and described herein as a sequence of acts or events, it is understood that the shown order of such acts or events is not intended to be interpreted in a limiting sense. For example, some acts may occur in a different order and / or concurrently with other acts or events than those shown and / or described herein. Further, not all acts shown may be required to implement one or more aspects or embodiments of the present description, and one or more of the acts shown herein may be performed in one or more separate steps and / or phases.

[0081] The invention is defined by the main claim and the subordinate claim. The subclaims describe further embodiments of the invention.

Claims

[1] Memory cell (102) comprising: a data storage element (106) having a variable resistor; and a bipolar selector (104) electrically coupled in series with the data storage element (106), the bipolar selector comprising a first unipolar selector (108) and a second unipolar selector (110), and the first and second unipolar selectors being electrically coupled in parallel with opposite orientations; where: the bipolar selector (104) has a first threshold voltage (VT1) at a first polarity and a second threshold voltage (VT2) at a second polarity; the first and second unipolar selectors (108, 110) individually define the first and second threshold voltages; the first and second threshold voltages are different; the data storage element (106) comprises a magnetic tunnel junction, and the magnetic tunnel junction comprises a ferromagnetic reference element (202) and a free ferromagnetic element (204); and the free ferromagnetic element (204) is electrically separated from the bipolar selector (104) by the ferromagnetic reference element (202), the ferromagnetic reference element is electrically separated from an anode (406) of the first unipolar selector (108) by a cathode (402) of the first unipolar selector, and a width (W1) of the first unipolar selector (108) is greater than a width (W2) of the second unipolar selector (110); or the ferromagnetic reference element (202) is electrically separated from the bipolar selector (104) by the free ferromagnetic element (204), the free ferromagnetic element is electrically separated from an anode (406) of the first unipolar selector by a cathode (402) of the first unipolar selector (108), and a width (W1) of the first unipolar selector (108) is smaller than a width (W2) of the second unipolar selector (110). [2] The memory cell (102) of claim 1, wherein the cathode (402) of the first unipolar selector (108) is electrically coupled to an anode (406) of the second unipolar selector (110). [3] Memory cell (102) according to one of the preceding claims, wherein the first and second unipolar selectors (108, 110) are diodes. [4] The memory cell (102) of any one of claims 1 to 3, wherein the free ferromagnetic element (204) is electrically separated from the bipolar selector (104) by the ferromagnetic reference element (202), the ferromagnetic reference element is electrically separated from the anode (406) of the first unipolar selector (108) by the cathode (402) of the first unipolar selector, and the first threshold voltage (VT1) of the first unipolar selector is lower than the second threshold voltage (VT2) of the second unipolar selector (110). [5] The memory cell (102) of any one of claims 1 to 3, wherein the ferromagnetic reference element (202) is electrically separated from the bipolar selector (104) by the free ferromagnetic element (204), the free ferromagnetic element is electrically separated from the anode (406) of the first unipolar selector by the cathode (402) of the first unipolar selector (108), and the first threshold voltage of the first unipolar selector (VT1) is higher than the second threshold voltage (VT2) of the second unipolar selector (110). [6] Integrated chip comprising: an array (702, 702a) having a plurality of memory cells (102) according to any one of the preceding claims, wherein the plurality of memory cells are arranged in a plurality of rows and a plurality of columns; a plurality of first conductive lines (608 / BL) extending along corresponding rows of the array (702, 702a) and electrically coupled to memory cells of the array in the corresponding rows; and a plurality of second conductive lines (608 / SL) extending along corresponding columns of the array (702, 702a) and electrically coupled to memory cells of the array in the corresponding columns. [7] The integrated chip of claim 6, wherein the memory cells (102) are magnetoresistive random access memory cells. [8] Integrated chip according to claim 6 or 7, wherein in each of the memory cells an anode (406) of the first unipolar selector (108) is directly electrically coupled to a cathode (402) of the second unipolar selector (110) and wherein a cathode (402) of the first unipolar selector (108) is directly electrically coupled to an anode (406) of the second unipolar selector (110). [9] Integrated chip according to one of claims 6 to 8, further comprising: a second array (702b) comprising a plurality of second memory cells (102) in a plurality of rows and a plurality of columns, wherein the second memory cells each comprise a single second bipolar selector (104) and a single second data storage element (106), and wherein the second conductive lines (608 / SL) extend along corresponding columns of the second array and are electrically coupled to second memory cells of the second array in the corresponding columns; and a plurality of third conductive lines (608 / BL) extending along corresponding rows of the second array (702b) and electrically coupled to second memory cells (102) of the second array in the corresponding rows, the second conductive lines (608 / SL) being located vertically between the first conductive lines (608 / BL) and the third conductive lines (608 / BL). [10] Method comprising: Providing a memory array (702) having a plurality of memory cells (102) in a plurality of rows and a plurality of columns, wherein the memory cells comprise a first memory cell (102s / 102) according to any one of claims 1 to 5; Applying a first voltage to the first memory cell (102s / 102) having a first polarity, wherein the first unipolar selector (108) is switched ON and the second unipolar selector (110) is switched OFF while the first voltage is applied to the first memory cell; and Applying a second voltage to the first memory cell (102s / 102) having a second polarity different from the first polarity, wherein the first unipolar selector (108) is switched OFF and the second unipolar selector (110) is switched ON while the second voltage is applied to the first memory cell. [11] The method of claim 10, wherein applying the first voltage places the first memory cell (102s / 102) in a first resistance state, and wherein applying the second voltage places the first memory cell in a second resistance state different from the first resistance state. [12] The method of claim 10 or 11, wherein the memory cells (102) further comprise a second memory cell (102u / 102) in the same row or column as the first memory cell (102s / 102), the second memory cell comprising a third unipolar selector (108) and a fourth unipolar selector (110), the third and fourth unipolar selectors being electrically coupled in parallel with opposite orientations, and the method further comprising: Applying a third voltage to the second memory cell (102u / 102) having the first polarity while applying the first voltage to the first memory cell (102s / 102) having the first polarity, wherein the third voltage is less than a threshold voltage of the third unipolar selector and the fourth unipolar selector is turned OFF while the third voltage is applied. [13] The method of claim 12, wherein the method further comprises: Applying a fourth voltage to the second memory cell (102s / 102) having the second polarity while applying the second voltage to the first memory cell (102s / 102) having the second polarity, wherein the third unipolar selector is switched OFF while the fourth voltage is applied, and wherein the fourth voltage is less than a threshold voltage of the fourth unipolar selector. [14] The method of claim 12 or 13, wherein the first threshold voltage of the first unipolar selector (108) is between the first and third voltages. [15] The method of any one of claims 10 to 14, wherein the first and second unipolar selectors (108, 110) are diodes, and wherein the first and second unipolar selectors are each forward biased when turned ON, and wherein the first and second unipolar selectors are each reverse biased when turned OFF.

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