Metal / dielectric interlayer process for non-volatile memory devices

Abstract

Method comprising: Forming a lower interconnect structure (114) within a first interlevel dielectric, ILD, layer (106) over a substrate (102); Forming an intermediate metal / dielectric structure (118) over the lower interconnect structure (114), the intermediate metal / dielectric structure (118) comprising a lower dielectric layer (120) over the lower interconnect structure (114), an upper dielectric layer (122) over the lower dielectric layer (120), and a first metal layer (124) separating the upper dielectric layer (122) from the lower dielectric layer (120); forming a top electrode (116) over the intermediate metal / dielectric structure (118); Applying a first bias voltage between the lower interconnect structure (114) and the upper electrode (116) to induce a first state in the intermediate metal / dielectric structure (118); wherein in the first state, a lower conductive wire (126, 131b, 133b, 135b) extends from the lower interconnect structure (114) through the lower dielectric layer (120) and to the first metal layer (124); and wherein an upper conductive wire (128, 131a, 133a, 135a) extends from the first metal layer (124) through the upper dielectric layer (122) and to the upper electrode (116); and Applying a second bias voltage between the lower interconnect structure (114) and the upper electrode (116) to induce a second state in the intermediate metal / dielectric structure (118); wherein in the second state at least a portion of the lower conductive wire (126, 131b, 133b, 135b) is removed or broken such that the lower dielectric layer (120) separates the lower interconnect structure (114) from the first metal layer (124); and / or at least a portion of the upper conductive wire (128, 131a, 133a, 135a) is removed or broken such that the upper dielectric layer (122) separates the first metal layer (124) from the upper electrode (116).

Description

GENERAL STATE OF THE ART

[0001] Many modern electronic devices include electronic memories designed to store data. Electronic memories can be volatile or non-volatile. Volatile memory stores data when powered, while non-volatile memory is capable of storing data when power is removed. There are many different types of non-volatile memories that fall within the scope of this disclosure, including Programmable Metallization Cell (PMC) Random Access Memory (RAM) (in some contexts also referred to as Conductive Bridge RAM (CBRAM)), Phase Change RAM (PCRAM), Oxide-Based RAM (OxRAM), Magnetic RAM (MRAM), Resistive RAM (RRAM), etc. In particular, RRAM is a promising candidate for a next-generation non-volatile memory technology.RRAM has a simple structure, consumes a small cell area, has a low switching voltage and fast switching times, and is compatible with CMOS manufacturing processes.

[0002] Prior art relating to the subject matter of the invention can be found, for example, in US 2016 / 0 268 505 A1, US 9 419 057 B2 and US 2015 / 0 340 406 A1.

[0003] The invention is defined by the main claim. Further embodiments of the invention are recited in the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Aspects of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying figures. It should be noted that, in accordance with standard industry practices, various features are not drawn to scale. The dimensions of various features may be exaggerated or reduced for clarity of discussion. Fig. 1A-1B illustrate a cross-sectional view of some embodiments of an integrated circuit including a resistive access memory (RRAM) device with an intermediate metal / dielectric structure. Fig. 2A-2B illustrate a cross-sectional view of some embodiments of an integrated circuit including a resistive access memory (RRAM) device with an intermediate metal / dielectric structure. Fig. 3A-3B illustrate a cross-sectional view of some embodiments of an integrated circuit including a resistive access memory (RRAM) device with an interposed metal / dielectric structure. Fig. 4A-4B illustrate a cross-sectional view of some embodiments of an integrated circuit including a resistive access memory (RRAM) device with an interposed metal / dielectric structure. Fig. 5A illustrates a perspective view of some additional embodiments of an integrated circuit in the form of a crossbar RRAM architecture including a resistive random access memory (RRAM) device with an intermediate metal / dielectric structure as a selector and / or storage element. Fig. 5B - 5D provide cross-sectional views of some embodiments of memory cells formed with Fig. 5A. Fig. 6 illustrates a perspective view of some additional embodiments of an integrated circuit including a resistive random access memory (RRAM) device with an interposed metal / dielectric structure as a selector and / or storage element. Fig. 7-13 illustrate some embodiments of cross-sectional views of a method for forming an IC including an RRAM device having a top electrode contacting an overlying bond wire. Fig. 14 illustrates some embodiments of a method in flowchart form for forming an RRAM device with an intermediate metal / dielectric structure. DETAILED DESCRIPTION

[0005] The following disclosure provides many different embodiments, e.g., for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. For example, the formation of a first feature over or on a second feature in the following description may include embodiments in which first and second features are formed in direct contact and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Furthermore, this disclosure may repeat reference numerals and / or letters in the various examples.This repetition is for the purpose of simplification and clarity and does not in itself impose a relationship between the various embodiments and / or designs discussed.

[0006] Furthermore, spatial reference terms such as "beneath," "under," "lower," "over," "above," and the like may be used herein for ease of description to describe an element or the relationship of a feature to another element(s) or feature(s) as depicted in the figures. The spatial reference numerals are intended to encompass different orientations of the device in use or operation, in addition to the orientation depicted in the figures. The device may be oriented differently (rotated 90 degrees or in other orientations), and the spatial descriptions used herein may be interpreted similarly accordingly.

[0007] Resistive Random Access Memory (RRAM) devices generally include a dielectric data storage layer, such as a high-k dielectric layer or silicon dioxide layer, sandwiched between top and bottom conductive electrodes disposed within a back-end-of-the-line (BEOL) metalization layer. RRAM devices are designed to operate based on a process of reversible switching between resistive states. This reversible switching is enabled by selectively forming (or breaking) a conductive wire through the dielectric data storage layer. For example, the first bias condition may be applied across the top and bottom conductive electrodes to selectively form a conductive wire extending through the dielectric data storage layer, thereby switching the RRAM device to a low-resistance state.When a second voltage is applied, the conductive wire is detached and / or broken, electrically isolating the top and bottom electrodes and switching the RRAM device to a high-resistance state. Thus, depending on the bias condition applied to the RRAM device, the RRAM device can be switched between a first (e.g., low) resistance state and a second (e.g., high) resistance state.

[0008] Some aspects of this disclosure recognize that the data storage dielectric in typical RRAM devices is somewhat "thick" to provide adequate insulation between the top and bottom electrodes. This thickness of the data storage dielectric layer causes the conductive wire to take a long time to form, resulting in slow performance. In some embodiments, a "thin" film of the data storage dielectric may separate the top and bottom electrodes. However, such a thin film may pose reliability issues, such as voltage dropout, particularly over a large number of read and write operations.Therefore, in some embodiments of this disclosure, an interleaved metal / dielectric structure made of a number of thin, dielectric data storage layers alternating with a number of metal layers is interleaved between the top electrode and the bottom electrode. Because each dielectric data storage layer is "thin," each is suitable for forming a conductive wire therethrough in a relatively short period of time. As a result, this interleaved metal / dielectric structure provides better reliability while providing higher performance (e.g., write operations when forming conductive wires) than other approaches. Furthermore, it will be appreciated that, although this disclosure is set forth in the context of RRAM, the interleaved metal / dielectric structure may also be used in other types of non-volatile memories, including, for example,of Programmable Metallization Cell (PMC) Random Access Memory (RAM), Phase Change RAM (PCRAM), Oxide-based RAM (OxRAM) and Magnetic RAM (MRAM).

[0009] Fig. 1A-1B illustrate a cross-sectional view of some embodiments of an integrated circuit 100 comprising a resistive access memory (RRAM) device with an interposed metal / dielectric structure. The integrated circuit 100 includes a semiconductor substrate 102 with a back-end-of-the-line (BEOL) interconnect structure 104 disposed over the semiconductor substrate 102. The BEOL interconnect structure 104 includes a number of metal layers disposed within a data storage dielectric structure 106. For example, the illustrated metal layers include a bottom metal line 108 and a top metal line 110 with an RRAM device 112 disposed between the bottom metal line 108 and the top metal line 110.The RRAM device 112 includes a bottom electrode 114, which may be in direct contact with the bottom metal line 108, and a top electrode 116, which may be in direct contact with the top metal line 110. Alternatively, a bottom via and / or other structures (not shown) may couple the bottom electrode 114 to the bottom metal line 108, and / or an top via and / or other structures (not shown) may couple the top electrode 116 to the top metal line 110.

[0010] An intermediate metal / dielectric structure 118 is interposed between the lower electrode 114 and the upper electrode 116. The intermediate metal / dielectric structure 118 is made of a number of thin dielectric layers alternately stacked with a number of metal layers. For example, the embodiment of the Fig. 1A-1B illustrate an intermediate metal / dielectric structure 118 comprising a lower dielectric layer 120 over the lower electrode 114, an upper dielectric layer 122 over the lower dielectric layer, and a first metal layer 124 separating the upper dielectric layer 122 from the lower dielectric layer 120. Although the Fig. 1A - 1B depict two dielectric layers (e.g., 102, 122) separated from each other by a single metal layer (e.g., 124), a number of metal layers with interposed dielectric layers may be disposed between the lower electrode and the upper electrode.

[0011] In some embodiments, the upper dielectric layer 122 and / or the lower dielectric layer 120 comprise a high dielectric material, such as a hafnium-based oxide (e.g., HfO2), a zirconium-based oxide (e.g., ZrO2), and / or a titanium-based oxide (e.g., TiO2). The high-k dielectric material has a dielectric constant greater than that of silicon dioxide; and thus, the high-k dielectric material has a dielectric constant greater than approximately 3.9. In other embodiments, the upper dielectric layer 122 and / or the lower dielectric layer 120 comprise silicon dioxide. In some embodiments, the first metal layer 124 comprises a conductive metal, such as copper, aluminum, tungsten, and / or alloys of these metals, including ternary chalcogenides. The upper electrode 116 and the lower electrode 114 comprise a metal such as tantalum, titanium or titanium nitride.

[0012] In some embodiments, the total thickness of the intermediate metal / dielectric structure 118 is less than 50 nm. Furthermore, the ratio of t metal :t dielectric be adjusted during production; where t metal is the total thickness of all metal layers between the very top surface of the upper electrode and the very bottom surface of the upper electrode, and where t dielectric is the total thickness of the sum of all dielectric layers between the very top surface of the lower electrode and the very bottom surface of the upper electrode. In some embodiments, t metal: t dielectric range from approximately 1:10 to approximately 2:1.

[0013] In some embodiments, the dielectric layers of the intermediate dielectric / metal structure have different thicknesses from one another (although they may also be equal to one another); and the metal layers of the intermediate structure have different thicknesses from one another (although they may also be equal to one another). Furthermore, the thicknesses of the dielectric layers are often different from the thicknesses of the metal layers. In some embodiments, the metal layers have individual thicknesses ranging from 1 nm to 50 nm, and the dielectric layers have individual thicknesses ranging from 0.5 nm to 5 nm. In some cases, each dielectric layer has a thickness less than or equal to 10 nm (or even less than or equal to 5 nm), since thicknesses greater than 10 nm may thwart or hinder wire forming.In some cases, the metal layers can be made of copper alloys and can have individual thicknesses ranging between 15 nm and 30 nm, providing a good compromise between manufacturing cost and quality. If higher quality and / or thinner metal layers are desired, atomic layer deposition (ALD) or other deposition techniques could be used.

[0014] Once device fabrication is complete, a firing (or forming) voltage (Vff) may be applied to the cell to initially form the wire. After the wire is initially formed, SET and RESET biases are subsequently used to write first and second data states to the cell (e.g., "1" and "0"). For example, the firing voltage may include a voltage of +10 V applied to the top electrode; while a voltage of 0 V is applied to the bottom electrode for a time ranging from 10 ns to 1 µs, causing the initial forming of the wire.

[0015] A first bias condition - a so-called SET bias - may be applied across the bottom electrode 114 and top electrode 116 to switch the RRAM device to a low resistance state in which the conductive wires are shaped to extend through the top and bottom dielectric layers as in Fig. 1A. Thus, in Fig. 1A, a lower conductive wire 126 extends from the lower electrode 114 through the lower dielectric layer 120 and the first metal layer 124, and an upper conductive wire 128 extends from the upper metal layer 124 through the upper dielectric layer 122 and to the upper electrode 116. For example, in some embodiments, the first bias condition may be applied—e.g., the top electrode (TE) at +10 V, the bottom electrode (BE) at 0 V—for a period of 10 ns.

[0016] When a second bias condition - a so-called RESET bias - is applied across the lower electrode 114 and the upper electrode 116, at least a portion of the lower conductive wire (126 in Fig. 1A) and / or the upper conductive wire (e.g. 128 in Fig. 1A) is removed or broken such that the lower dielectric layer 120 and / or the upper dielectric layer 122 are a completely separated lower electrode 114 and upper electrode 116, thereby switching the RRAM device to a high resistance state, such as in Fig. 1B. Thus, in Fig. 1B, at least a portion of the lower conductive wire is removed or broken such that the lower dielectric layer 120 completely separates the lower electrode 114 from the first metal layer 124, and at least a portion of the upper conductive wire is removed or broken such that the upper dielectric layer 122 completely separates the first metal layer 124 from the upper electrode 116. For example, in some embodiments, the second bias condition—e.g., TE at 0 V, BE at +5 V—may be applied for a period of 20 ns. Thus, by switching between the first bias condition and the second bias condition, the RRAM device can be repeatedly and reliably switched between the low resistance state ( Fig. 1A) and the high resistance state ( Fig. 1B) can, for example, act as a selector in a crossbar memory array or store data in an RRAM cell.

[0017] Compared to embodiments with only a single dielectric layer between the bottom electrode 114 and the top electrode 116, which includes numerous dielectric layers (e.g., the bottom dielectric layer 120 and the top dielectric layer 122), this provides shorter conductive wires that are formed faster and at reduced voltages, resulting in faster switching times from the high-resistance state to the low-resistance state. Shorter conduction paths can also increase reliability.

[0018] Fig. 2A - 2B to the Fig. 4A-4B show various non-limiting examples of additional ways in which the intermediate metal / dielectric structure 118 may be implemented. Compared to the Fig. 1A - 1B, which illustrate a (single) first metal layer 124 disposed between a lower dielectric layer 120 and an upper dielectric layer 122, show the Fig. 2A - 2B to 4A - 4B (an) additional metal layer(s) and / or (a) dielectric layer(s).

[0019] With reference now to the Fig. 2A-2B illustrate some embodiments of an RRAM device 200 in which the intermediate metal / dielectric layer 118 includes an upper dielectric layer 122 and a lower dielectric layer 120. A first metal layer 124 is disposed between the upper dielectric layer 122 and the lower dielectric layer 120. A second dielectric layer 130 is disposed over the upper dielectric layer 122. The second metal layer 130 separates the upper dielectric layer 122 from the top electrode 116. Fig. Figure 2A illustrates the RRAM device 200 in a high resistance state, while Fig. 2B illustrates the RRAM device 200 in a low resistance state while the conductive wires 131a, 131b are present.

[0020] Fig. 3A-3B show an alternative embodiment of an RRAM device 300 in which the intermediate metal / dielectric layer 118 also includes an upper dielectric layer 122 and a lower dielectric layer 120. A first metal layer 124 is disposed between the upper dielectric layer 122 and the lower dielectric layer 120. A second metal layer 132 is disposed over the lower electrode 114. The second metal layer 132 separates the lower electrode 114 from the lower dielectric layer 120. Fig. Figure 3A illustrates the RRAM device 300 in a high resistance state, while Fig. 3B illustrates the RRAM device 300 in a low resistance state while the conductive wires 133a, 133b are present.

[0021] Fig. 4A-4B show an alternative embodiment of an RRAM device 400 in which the intermediate metal / dielectric layer 118 includes an upper dielectric layer 122 and a lower dielectric layer 120. A first metal layer 124 is again disposed between the upper dielectric layer 122 and the lower dielectric layer 120. In this embodiment, a second metal layer 134 is disposed over the lower electrode 114. The second metal layer 134 separates the lower electrode 114 from the lower dielectric layer 120. A third metal layer 136 is disposed over the upper dielectric layer 122. The third metal layer 136 separates the upper dielectric layer 122 from the upper electrode 116. Fig. Figure 4A illustrates the RRAM device 400 in a high resistance state, while Fig. 4B illustrates the RRAM device 400 in a low resistance state while the conductive wires 135a, 135b are present.

[0022] As can be appreciated, the intermediate metal / dielectric structure 118 can thus take various forms depending on the implementation. Although the Fig. While FIGS. 1A-1B through 4A-4B show some examples with two dielectric layers (e.g., a top dielectric layer 122 and a bottom dielectric layer 120) and one, two, or three metal layers, the intermediate metal / dielectric structure 118 may generally include any number of dielectric layers and any number of metal layers alternately stacked within each other. Typically, the total thickness of the intermediate metal / dielectric structure 118 is sufficiently thin that the RRAM device 112 may be within a height corresponding to the nearest adjacent metal line. For example, in some embodiments, a height of the RAM device may be within a height measured from the bottommost metal line 108 (e.g., the metal 3 line) and a top metal line 110 (e.g., the metal 4 line).In some embodiments, the total thickness of the intermediate metal / dielectric structure 118 is less than 50 nm. Furthermore, a ratio of t. metal :t dielectric be adjusted during production; where t metal is the total thickness of all metal layers between the very top surface of the lower electrode and the very bottom surface of the upper electrode, and where t dielectric is the total thickness of the sum of all dielectric layers between the very top surface of the lower electrode and the very bottom surface of the upper electrode. In some embodiments, t metal :t dielectric range from approximately 1:10 to approximately 2:1.

[0023] In some embodiments, the dielectric layers of the intermediate dielectric / metal structure have different thicknesses from one another; and the metal layers of the intermediate structure have different thicknesses from one another. Furthermore, the thicknesses of the dielectric layers are often different from the thicknesses of the metal layers. In some embodiments, the metal layers have individual thicknesses ranging from 1 nm to 50 nm, and the dielectric layers have individual thicknesses ranging from 0.5 nm to 5 nm. In some cases, the dielectric layer has a thickness less than or equal to 10 nm (or even less than or equal to 5 nm), since thicknesses greater than 10 nm may thwart or hinder wire forming.In some cases, the metal layers can be made of copper alloys and can have individual thicknesses ranging between 15 nm and 30 nm, providing a good compromise between manufacturing cost and quality. If higher quality and / or thinner metal layers are desired, atomic layer deposition (ALD) or other deposition techniques could be used.

[0024] Although there is no limitation on the number of metal layers and dielectric layers disposed between the bottom electrode and the top electrode, in some cases it is advantageous to keep a maximum number of metal / dielectric periods to less than or equal to five (meaning, for example, five dielectric layers and five metal layers alternately disposed between the bottom electrode and the top electrode) because this keeps the wire forming speed at levels similar to conventional approaches that use a single (e.g., "thick") dielectric layer.

[0025] In some embodiments, the upper dielectric layer 122 and the lower dielectric layer 120 comprise a high-k dielectric layer, such as a hafnium-based oxide (e.g., HfO2), a zirconium-based oxide (e.g., ZrO2), and / or a titanium-based oxide (e.g., TiO2). The high-k dielectric layer has a dielectric constant k greater than that of silicon dioxide; and thus, the high-k dielectric layer has a dielectric constant greater than about 3.9. In some embodiments, the first metal layer (e.g., 124), the second metal layer (e.g., 130, 132, 134), and the third metal layer (e.g., 136) comprise a conductive material, such as copper, aluminum, tungsten, and / or alloys of these metals, including ternary chalcogenides. The upper electrode 116 and the lower electrode 114 comprise a metal such as tantalum, tantalum nitride, titanium or titanium nitride.

[0026] Fig. 5A illustrates a perspective view of some additional embodiments of an integrated chip including an array 500 of memory cells 502 arranged in rows and columns in a crossbar configuration. The memory cells 502 are arranged in columns and rows, and for simplicity, only some of the memory cells have been labeled 502. Each memory cell 502 may be generally cylindrical, conical, frusto-conical, pyramidal, frusto-pyramidal, columnar, cubic, or prismatic in shape and may extend between a word row (WL) and the corresponding bit row (BL). The bit rows (BL) extend along corresponding columns of the array and electrically couple to the memory cells in the corresponding columns, while the word rows (WL) extend laterally along corresponding rows of the array and electrically couple to the memory cells in the corresponding rows.For clarity, the bit lines are labeled BU, BL2, ..., and BLN, respectively, where the indices identify corresponding columns and N is a variable integer representing a column in the memory array. For clarity and in a similar manner, the word lines are labeled WU, WL2, and WLM, respectively, where the indices identify corresponding columns and M is a variable integer representing a row in the memory array.

[0027] By approximately biasing a bit row and a word row, the memory cell at the intersection of the bit row and the word row can be selected and read from and written to. In some embodiments, the bias conditions have different polarities depending on whether a first data state is being written to a memory cell or a second data state is being written to a memory cell. Furthermore, the selectors of a non-selected row have a sufficiently high resistance to prevent read and / or write disturbances to non-selected memory cells that share a bit row or a source row with the selected memory cell.

[0028] Fig. 5B - 5D show various embodiments of memory cells 502 that include one or more RRAM devices implemented in the architecture of the Fig. 5A may be included. As in Fig. 5B, for example, each memory cell 502 may include a bottom electrode 114, a selector element 505 over the bottom electrode, an upper electrode 116 over the selector element 505, a storage element 504 over the upper electrode 116, and a tip electrode 506 over the storage element 504. The storage element 504 stores at least one bit of information, while the selector element 505 includes a resistor that controls whether the storage element coupled to the selector element is written and / or read. The selector element 505 may, for example, include the Fig. 1 - 4 described intermediate metal / dielectric structure 118. As in Fig. 5C, the selector element 505 may alternatively include the interposed metal / dielectric structure 118 and be formed over the memory element 504. In some embodiments, the memory element 504 may also be implemented using the interposed metal / dielectric structure 118. Thus, Fig. 5D shows an example in which the memory element 504 and the selector element 505 each include an interposed metal / dielectric structure 118. Thus, in some embodiments, an RRAM device of the Fig. 1A - 1B up to 4A - 4B may be used as the selector element, which has a reduced threshold voltage compared to other approaches. In other embodiments, an RRAM device of the Fig. 1A - 1B up to 4A - 4B may be used as a storage element to store one or more data bits. The resistance of the storage element may be read to determine whether the memory cell is in the high resistance state corresponding to a first logical value (e.g., a logical "0" as in Fig. 1A), or whether the memory cell in the low resistance state corresponds to a second logical value (e.g. a logical “1”, as in Fig. 1B).

[0029] Fig. 6 illustrates a cross-sectional view of some additional embodiments of an integrated chip 600 including a semiconductor substrate 602. The integrated chip includes a memory region 604, such as a memory array 500, and a logic region 606 disposed around an outer periphery of the memory region.

[0030] Transistors 605 and / or other active devices are disposed in or above the substrate. Each transistor includes a source / drain region 608 separated by a channel region 610. A gate electrode 612 overlies each channel region and is separated from the channel region 610 by a gate dielectric 614. Isolation structures 616 (e.g., shallow trench isolation structures) may be disposed in the semiconductor substrate 602 to provide isolation between adjacent transistor devices.

[0031] A back-end-of-the-line (BEOL) interconnect structure 618 is disposed over the semiconductor substrate 602 and operatively couples the transistors together. The back-end-of-the-line (BEOL) interconnect structure 618 includes a dielectric structure having a plurality of conductive features disposed within the dielectric structure. The dielectric structure may include a plurality of stacked interlevel dielectric (ILD) layers 620a-620f. In various embodiments, the plurality of ILD layers 620a-620f may include one or more dielectric materials, such as a low-k dielectric material or an ultra-low-k (ULK) dielectric material. In some embodiments, the one or more dielectric materials may include SiO2, SiCO, fluorosilicate glass (e.g., boron phosphate silicate glass), etc.In some embodiments, etch stop layers (ESLs) 622a-622 may be disposed between adjacent ILD layers 620a-620b. For example, a first ESL 622a is disposed between a first ILD layer 620a and a second ILD layer 620b, a second ESL 622b is disposed between the second ILD layer 620b and a third ILD layer 620c, etc. In various embodiments, the ESLs 622a-622b may comprise a nitride, silicon carbide, carbon-doped oxide, or similar materials.

[0032] A first conductive contact 624a and a second conductive contact 624b are disposed within the first ILD layer 620a. The first conductive contact 624a is electrically connected to a source / drain region of a transistor device in the memory region 604, and the second conductive contact 624b is electrically connected to the source / drain region of a transistor device in the logic region 606. In various embodiments, the first conductive contact 624a and the second conductive contact 624b may be connected to a source region, a drain region, or a gate electrode of a transistor in the memory region or logic region. In some embodiments, the first conductive contact 624a and the second conductive contact 624b may comprise, for example, tungsten.

[0033] Alternating layers of metal bond wires 626a-626e and metal vias 628a-628d are disposed over the first conductive contact 624a and the second conductive contact 624b. The metal bond wires 626a-626e and the metal vias 626a-628b comprise a conductive material. In some embodiments, the metal bond wires 626a-626e and the metal vias 628a-628d comprise a conductive core 630 and a cladding layer 632 separating the conductive core from the surrounding ILD layers. In some embodiments, the cladding layer may comprise titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN). In some embodiments, the conductive core may comprise, for example, copper and / or aluminum.

[0034] Between the metal connecting wire 626c and an upper metal connecting wire 626e in the memory region 604 is a memory cell 502, such as one shown in the Fig. 1-5. Thus, memory cell 502 in memory region 604 has an overall height sufficient to fit between the nearest adjacent metal lines in logic region 606.

[0035] The Fig. 7-13 illustrate some embodiments of cross-sectional views 700-1300 that include a method of forming an RRAM device. Although the Fig. 7-13 are described with reference to a method of molding an RRAM device, it will be appreciated that the structures shown in the figures are not limited to the molding process, but instead may stand alone, separate from the process.

[0036] As shown in cross-sectional view 70 of the Fig. 7, a bottom electrode 114 is formed within a dielectric layer 106 over a semiconductor substrate 102. In various embodiments, the semiconductor substrate 102 may include a semiconductor body (e.g., a monocrystalline silicon, SiGe, silicon on insulator (SOI), such as a semiconductor wafer and / or one or more die(s) on a wafer), as well as any other type of metal layer, device, semiconductor, and / or associated epitaxial layers, etc. The dielectric layer 106 is selectively etched to etch a plurality of recesses within the dielectric layer 10. The plurality of recesses are filled with a first conductive material to form the bottom electrode 114. In various embodiments, the first conductive material may include, for example, copper, tungsten, and / or aluminum. In some embodiments, the first conductive material may be deposited using a plating process (e.g.,an electroplating process, an electroless plating process). In other embodiments, the first conductive material may be applied using a vapor deposition technique (e.g., CVD, PVD, ALD, PE-ALD, etc.). In some embodiments, one or more cladding layers (not shown) may be applied within the plurality of recesses prior to filling the plurality of recesses with the first conductive material.

[0037] As shown in cross-sectional view 80 of the Fig. 8, an intermediate metal / dielectric structure 118 is formed over the dielectric layer 106. In some embodiments, an intermediate metal / dielectric structure 118 may be formed by forming a lower dielectric layer 120 over the upper electrode, a first metal layer 124 over the lower dielectric layer 120, an upper dielectric layer 122 over the first metal layer 124, and a second metal layer 130 over the upper dielectric layer 122. An upper electrode 116 may then be formed over the second metal layer 130. Other configurations may also be formed, e.g., to accommodate the configurations previously described, e.g., in the Fig. To form the structures described in 1 - 5.

[0038] In various embodiments, the bottom electrode 114, the bottom dielectric layer 120, the top dielectric layer 122, and the top electrode 116 may be deposited using vapor deposition techniques (e.g., CVD, PVD, ALD, PE-ALD, etc.). In various embodiments, the first and / or second metal layer are made of a metal and are formed, for example, by sputtering, electroplating, electroless plating, or a vapor deposition technique. In various embodiments, the bottom electrode 114 and the top electrode 116 may comprise a metal nitride or a metal. In some embodiments, for example, the bottom electrode 114 and / or the top electrode 116 may comprise a conductive material, such as a conductive layer. B. platinum (Pt), aluminum-copper (AlCu), titanium nitride (TiN), gold (Au), titanium (Ti), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN) and / or copper (Cu).In various embodiments, the lower dielectric layer 120 and the upper dielectric layer 122 may comprise nickel oxide (NiO), titanium oxide (TiO), hafnium oxide (HfO), zirconium oxide (ZrO), zinc oxide (ZnO), tungsten oxide (WO3), aluminum oxide (Al2O3), tantalum oxide (TaO), molybdenum oxide (MoO), and / or copper oxide (CuO). In various embodiments, the first metal layer 124 and / or the second metal layer 130 comprise a conductive metal, such as copper, aluminum, tungsten, and / or alloys of these metals, including ternary chalcogenides.

[0039] As shown in cross-sectional view 90 of the Fig. 9, a memory element 504 and a tip electrode layer 506 are disposed over the intermediate metal / dielectric structure 118 (the Fig. 8). In some embodiments, the memory element 504 is a non-volatile memory (NVM) device, such as an RRAM device, including one or more chalcogenide-based dielectric layers sandwiched between a pair of electrodes, but in other embodiments, the memory element may take other forms, such as a phase-change memory element or, for example, a metal-insulator-metal capacitor. In some embodiments, the tip electrode layer 506 and / or the top electrode layer 116 may comprise a conductive material, such as platinum (Pt), aluminum-copper (AlCu), titanium nitride (TiN), gold (Au), titanium (Ti), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), and / or copper (Cu). A hard mask 902, such as a silicon dioxide (SiO) mask, may be deposited over the tip electrode 506. B. a nitride hard mask or an oxynitride hard mask.

[0040] As shown in the cross-sectional view 1000 of the Fig. 10, the intermediate metal / dielectric structure 118 ( Fig. 7) to define a patterned structure. The patterned device structure includes a bottom electrode 114, an RRAM device 112 disposed over the bottom electrode 114, and a top electrode 506 disposed over the RRAM device 112. The RRAM device 112 may be generally cylindrical, conical, frusto-conical, pyramidal, frusto-pyramidal, columnar, cubic, or prismatic in shape and may extend between a word row (WL) and the corresponding bit row (BL).

[0041] As shown in cross-sectional view 1100 of the Fig. As shown in Figure 11, a dielectric liner 1102 may be formed over the opposite sides of the patterned device structure. In some embodiments, sidewall spacers may be formed by etching back the dielectric layer 1102 such that the dielectric layer is removed from horizontal surfaces, leaving the sidewall spacers along opposite sides of the patterned device structure. In various embodiments, the dielectric layer 1102 may comprise silicon nitride, a silicon dioxide (SiO2), silicon oxynitride (e.g., SiON), or similar material.

[0042] As shown in cross-sectional view 1200 of the Fig. As shown in Figure 12, a second ILD layer 104b may be formed over the patterned device structure. The second ILD layer 104b may be formed by a vapor deposition technique (e.g., CVD, PVD, ALD, PE-ALD, etc.), spin-on technique, or other technique.

[0043] As shown in cross-sectional view 1300 of the Fig. As shown in Figure 13, the second ILD layer 104b is selectively etched to define a second plurality of recesses within the second ILD layer. In some embodiments, the second ILD layer 104b may be patterned by selectively exposing the second ILD layer 104b to an etchant 1008 in areas not covered by a masking layer. The recesses are then filled with metal to form a via 1302 coupled to the tip electrode 506 and a top metal line 1304 over the via.

[0044] Fig. 14 illustrates a flow diagram of some embodiments of a method 1400 for forming an IC including an RRAM device having a top electrode contacting an overlying bond wire.

[0045] While the disclosed methods (e.g., method 1400) may be illustrated and described as a series of acts or events, it will be understood that the illustrated order of such acts or events should not be interpreted in a limiting sense. For example, some acts may occur in different orders and / or concurrently with other acts or events apart from those illustrated and / or described herein. Furthermore, acts not illustrated may be required to practice one or more aspects or embodiments of the description herein. Furthermore, one or more acts illustrated herein may be performed in one or more acts and / or phases.

[0046] At 1402, a bottom interconnect structure is formed within a first interlevel dielectric (ILD) layer above the substrate. In various embodiments, the bottom interconnect structure may include a bottom electrode, a connection contact, an interconnect via, or a bond wire. Fig. 7 illustrates some embodiments of a cross-sectional view 700 corresponding to action 1402.

[0047] At 1404, an intermediate metal / dielectric structure 118 is formed over the lower interconnect structure. The intermediate metal / dielectric structure includes a lower dielectric layer, an upper dielectric layer over the lower dielectric layer, and a first metal layer separating the upper dielectric layer from the lower dielectric layer. An upper electrode may be formed over the intermediate metal / dielectric structure. Fig. 8 illustrates some embodiments of cross-sectional views 800 corresponding to action 1404.

[0048] In 1406, a storage element is formed over the top electrode and a tip electrode is formed over the storage element. Fig. 9 illustrates some embodiments of a cross-sectional view 900 corresponding to action 1406.

[0049] In 1408, the tip electrode, the storage element, the top electrode, and the metal / dielectric interlayer structure are patterned. Fig. 10 illustrates some embodiments of a cross-sectional view 1000 corresponding to action 1408.

[0050] In 1410, a dielectric cladding may be formed over and opposite sides of the patterned structure of 1408. Fig. 11 illustrates some embodiments of a cross-sectional view 1100 corresponding to action 1410.

[0051] In 1412, a second ILD layer is formed over the dielectric layer. Fig. 12 illustrates some embodiments of a cross-sectional view 1200 corresponding to action 1412.

[0052] In 1414, an interconnect via is formed through the second ILD layer and a top metal line is formed over the interconnect via. Fig. 13 illustrates some embodiments of a cross-sectional view 1300 corresponding to action 1414.

[0053] Thus, some embodiments relate to an integrated chip including a memory device. The memory device includes a bottom electrode disposed over a semiconductor substrate. An top electrode is disposed over the bottom electrode. An interposing metal / dielectric structure is interposed between the bottom electrode and the top electrode. The interposing metal / dielectric structure includes a bottom dielectric layer over the bottom electrode, an top dielectric layer over the bottom dielectric layer, and a first metal layer separating the top dielectric layer from the bottom dielectric layer.

[0054] Further embodiments relate to an integrated chip comprising: a lower conductive interconnect structure surrounded by a first interlevel dielectric (ILD) layer and disposed over a substrate; a lower electrode disposed over the lower interconnect structure; a tip electrode disposed over the lower electrode, the tip electrode disposed below the upper interconnect structure; and a plurality of metal layers and a plurality of dielectric layers alternately stacked one above the other and interposed between the tip and lower electrodes. Still further embodiments relate to a method. In the method, a lower interconnect structure is formed within a first interlevel dielectric (ILD) layer over the substrate. An interposed metal / dielectric structure is formed over the lower interconnect structure.The intermediate metal / dielectric structure includes a lower dielectric layer over the lower interconnect structure, an upper dielectric layer over the lower dielectric layer, and a first metal layer separating the upper dielectric layer from the lower dielectric layer. An upper electrode is formed over the intermediate metal / dielectric structure.

Claims

[1] Method comprising: forming a lower interconnect structure (114) within a first interlevel dielectric, ILD, layer (106) over a substrate (102); Forming an intermediate metal / dielectric structure (118) over the lower interconnect structure (114), the intermediate metal / dielectric structure (118) comprising a lower dielectric layer (120) over the lower interconnect structure (114), an upper dielectric layer (122) over the lower dielectric layer (120), and a first metal layer (124) separating the upper dielectric layer (122) from the lower dielectric layer (120); forming a top electrode (116) over the intermediate metal / dielectric structure (118); Applying a first bias voltage between the lower interconnect structure (114) and the upper electrode (116) to induce a first state in the intermediate metal / dielectric structure (118); wherein in the first state, a lower conductive wire (126, 131b, 133b, 135b) extends from the lower interconnect structure (114) through the lower dielectric layer (120) and to the first metal layer (124); and wherein an upper conductive wire (128, 131a, 133a, 135a) extends from the first metal layer (124) through the upper dielectric layer (122) and to the upper electrode (116); and Applying a second bias voltage between the lower interconnect structure (114) and the upper electrode (116) to induce a second state in the intermediate metal / dielectric structure (118); wherein in the second state at least a portion of the lower conductive wire (126, 131b, 133b, 135b) is removed or broken such that the lower dielectric layer (120) separates the lower interconnect structure (114) from the first metal layer (124); and / or at least a portion of the upper conductive wire (128, 131a, 133a, 135a) is removed or broken such that the upper dielectric layer (122) separates the first metal layer (124) from the upper electrode (116). [2] The method of claim 1, further comprising: forming a memory element over the top electrode (116); forming a tip electrode (506) over the storage element; and Patterning the tip electrode (506), the memory element, the top electrode (116), and the intermediate metal / dielectric structure (118), thereby forming a patterned device structure. [3] The method of claim 2, further comprising: forming a second ILD layer over the patterned device structure; and Forming a via and a tip metal line within the second ID layer, the via coupling the tip metal layer to an upper portion of the upper electrode (116). [4] The method of any one of the preceding claims 1 to 3, wherein the intermediate metal / dielectric structure (118) comprises five or fewer dielectric layers between the lower interconnect structure (114) and the upper electrode (116). [5] A method according to any one of the preceding claims, wherein the intermediate metal / dielectric structure (118) further comprises: a second metal layer disposed over the upper dielectric layer (122), the second metal layer separating the upper dielectric layer (122) from the upper electrode (116). [6] The method of any one of the preceding claims 1 to 4, wherein the intermediate metal / dielectric structure (118) further comprises: a second metal layer disposed over the lower interconnect structure (114), the second metal layer separating the lower interconnect structure (114) from the lower dielectric layer (120). [7] The method of claim 6, wherein the intermediate metal / dielectric structure (118) further comprises: a third metal layer disposed over the upper dielectric layer (122), the third metal layer separating the upper dielectric layer (122) from the upper electrode (116). [8] The method of claim 7, wherein the upper dielectric layer (122) and the lower dielectric layer (120) comprise a high-k dielectric material; the first metal layer (124), the second metal layer, and the third metal layer comprise copper, aluminum, or tungsten; and the upper electrode (116) and the lower interconnect structure (114) comprise tantalum or titanium. [9] A method according to any one of the preceding claims, wherein a resistive random access memory, RRAM, cell is disposed over the top electrode (116), the RRAM cell comprising: a dielectric data storage layer disposed over the upper electrode (116), and a tip electrode disposed above the dielectric data storage layer. [10] A method according to any one of the preceding claims, wherein a dielectric cladding is disposed along sidewalls of the intermediate metal / dielectric structure (118). [11] The method of any preceding claim, wherein the intermediate metal / dielectric structure (118) comprises a plurality of metal layers and a plurality of dielectric layers alternately stacked one above the other and interposed between the upper electrode (116) and the lower interconnect structure (114), at least two of the plurality of metal layers having different thicknesses from one another. [12] The method of claim 11, wherein at least two of the plurality of dielectric layers have different thicknesses from each other. [13] The method of any one of claims 11 or 12, wherein the one maximum thickness of each of the plurality of dielectric layers is less than 10 nm.

Images