Crystal seed layer for magnetic direct access memory (MRAM)

Abstract

Semiconductor device comprising: a lower electrode (106) arranged over a semiconductor substrate (300); an MTJ stack (102) arranged over the lower electrode (106); and a conductive seed layer (120) comprising a CrNiFe layer (204) or CrNi layer separating the lower electrode (106) from the MTJ stack (102), wherein the conductive seed layer contains only a single CrNiFe crystal (206) between the lower electrode (106) and the MTJ stack (102).

Description

BACKGROUNDMany modern electronic devices include electronic memory, such as hard disk drives or random access memory (RAM). A magnetic random access memory (MRAM) device includes an array of densely packed MRAM cells. In each MRAM cell, an MTJ (Magnetic Tunneling Junction) element is integrated into a transistor to store data.A magnetic random access memory is known, for example, from WO 2016 / 105 665 A1. A further magnetic random access memory is known from U.S. Pat. No. 7,488,609 B1. A method for producing a magnetic random access memory is known, for example, from U.S. Pat. No. 2016 / 0 248 003 A1.BRIEF DESCRIPTION OF THE DRAWINGSAspects of the present disclosure will be best understood from the following detailed description when read in conjunction with the accompanying figures. It should be appreciated that, in accordance with standard practice in the industry, various elements are not drawn to scale. Indeed, for clarity of discussion, the dimensions of the various elements may be arbitrarily increased or decreased. FIG. 1A illustrates a cross-sectional view of some embodiments of a memory device including a magnetic tunneling junction (MTJ) stack formed over a seed layer, in accordance with the present disclosure. FIG. 1B illustrates a diagram illustrating some embodiments of how the magnetization of the layers in FIG. 1A may be changed to switch between a high impedance state and a low impedance state. FIGS. 2A-2D illustrate cross-sectional views of some embodiments of forming a seed layer for an MTJ stack according to the present disclosure. FIG. 3A illustrates a cross-sectional view of some embodiments of a memory device including two MRAM cells each having a magnetic tunnel junction (MTJ) formed over a seed layer, in accordance with the present disclosure. FIG. 3B illustrates a top view of some embodiments of the memory device of FIG. 3A, in accordance with the present disclosure. FIG. 4 illustrates a cross-sectional view of some embodiments of a more detailed memory device including an MTJ stack formed over a seed layer, in accordance with the present disclosure. FIGS. 5-11 illustrate cross-sectional views of some embodiments of a method of forming a memory device including an MRAM cell with an MTJ, in accordance with the present disclosure. FIG. 12 illustrates a flow chart approach illustrating some embodiments of a method of forming an MRAM cell over a seed layer, in accordance with the present disclosure.DETAILED DESCRIPTIONThe present disclosure provides many different embodiments or examples for implementing different features of this disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, the formation of a first element over or on a second element in the following description may include embodiments in which the first and second elements are formed in direct contact, and may also include embodiments in which additional elements may be formed between the first and second elements such that the first and second elements may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not itself dictate a relationship between the various embodiments and / or configurations discussed.Further, spatially-related terms such as "below," "below," "lower," "above," "upper," and / or the like may be used herein to facilitate the description to describe the relationship of one element or feature to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may also be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially related descriptors used herein may also be interpreted accordingly.A magnetic tunnel junction (MTJ) stack includes first and second ferromagnetic films separated by a barrier layer. One of the ferromagnetic films (often referred to as a "reference layer") has a fixed direction of magnetization, while the other ferromagnetic film (often referred to as a "free layer") has a variable direction of magnetization. When the magnetization directions of the reference layer and the free layer are in a parallel orientation, electrons are more likely to pass through a tunnel through the barrier layer, so that the MTJ stack is in a low impedance state. Conversely, when the magnetization directions of the reference layer and the free layer are in an anti-parallel orientation, electrons are less likely to pass through a tunnel through the tunnel barrier layer, such that the MTJ stack is in a high impedance state. Thus, the MTJ stack can be switched between two states of electrical resistance, a first state with a low resistance (R P: the magnetization directions of reference layer and free layer are parallel) and a second state with a high resistance (R AP: the magnetization directions of reference layer and free layer are anti-parallel). Due to this binary nature, MTJ stacks are used in memory cells to store digital data, where the low-ohmic state R P corresponds to a first data state (e.g., the logic "o") and the high-ohmic state R AP corresponds to a second data state (e.g., the logic "1").Typically, an MTJ stack is disposed between a lower electrode and an upper electrode, and the reference layer, the free layer, and the barrier layer are formed to have a face-centered cubic (fcc) structure with (111) orientation. In attempting to form the MTJ stack with this structure and alignment, the MTJ stack is grown from a seed layer. However, as will be understood in some aspects of the present disclosure, growing MTJ stacks from conventional seed layers results in defects in the MTJ stacks. For example, conventional MTJ stacks may have a significant number of grain boundaries per unit area, and these grain boundaries make the MTJ stacks susceptible to diffusive species, such as tantalum or ruthenium, from the bottom electrode, which diffuse from the bottom electrode into the MTJ stack, for example. These grain boundaries may also degrade the fcc structure and (111) alignment quality for the MTJ stack, which may degrade the performance of the MTJ stack, particularly as thermal stress and aging progress. Thus, among other features, the present disclosure provides a seed layer and an MTJ stack having a higher quality lattice structure that improves the operational characteristics (e.g., the tunnel magnetoresistance (TMR) effect) of the MTJ stack.FIG. 1A illustrates an MTJ device 100, in accordance with some embodiments. The MTJ device 100 includes an MTJ stack 102 disposed between a bottom electrode 106 and a top electrode 108. The MTJ stack 102 includes a reference layer 110 and a free layer 112 separated by a barrier layer 114. The reference layer 110 has a fixed magnetization, while the free layer 112 has a variable magnetization that can be switched to transition between two binary data states for the MTJ device 100. A hard bias layer 116 is disposed below the reference layer 110 to fix the magnetization of the reference layer. An anti-parallel coupling (APC) layer 118 is disposed between the reference layer 110 and the hard bias layer 116. The APC layer 118 causes the magnetization of the reference layer 110 to be opposite to that of the hard bias layer 116.A source line (SL) is coupled to one end of the MTJ stack 102 via the top electrode 108, and a bit line (BL) is coupled to an opposite end of the MTJ stack 102 via an access transistor 104. The BL and the source line may be interchanged in other embodiments such that the BL is coupled to the upper electrode 108 and the source line is coupled to the lower electrode 106 via the access transistor 104. Thus, applying an appropriate WL (wordline) voltage to a gate electrode of the access transistor 104 couples the MTJ stack 102 between the BL and the SL. Thus, by providing suitable bias conditions, the MTJ stack 102 may be switched between two states of the electrical resistor to store data (see, e.g., FIG. 1B, discussed further below).To allow well-patterned formation of the MTJ stack 102, a seed layer 120 separates the bottom electrode 106 from the MTJ stack 102. The seed layer 120 has a strong fcc structure with (111) orientation to assist the MTJ stack 102 in growing so as to reduce the presence of defect sites (e.g., grain boundaries) in the MTJ stack 102. This provides the MTJ with a higher quality fcc (111) lattice than previously achievable and improves the TMR effect for the MTJ stack 102. For example, by limiting imperfections in the MTJ stack 102, the seed layer 120 helps prevent diffusive species (e.g., Ta and / or Ru) from diffusing from the bottom electrode 106 into the MTJ stack 102. Additionally, the seed layer 120 enhances the crystalline structure of the MTJ stack 102 such that diffusion for layers containing diffusive species above the seed layer 120 is also reduced. For example, even if the reference layer 110 includes a diffusive species (e.g., Ta or Ru), the fact that the reference layer 110 has been formed over the seed layer 120 (and not directly on the underlying bottom electrode 106) limits imperfections in the lattice of the MTJ stack 102, and thus limits diffusion of the diffusive species through the MTJ stack 102. This contributes to a limitation of the diffusive species's deterioration of the TMR of the MTJ stack 102, and also contributes to a limitation of the deterioration of the MTJ performance.In some embodiments, the seed layer 120 is made of a crystalline non-magnetic binary alloy of CrNi having a top surface that is planar or planar. In another embodiment, the seed layer 120 is comprised of a crystalline non-magnetic ternary alloy of CrNiFe having a top surface that is planar or planar. For example, in some cases, the composition of this seed layer 120 may have the form Cr x Ni 1-x-y Fe y where x=0.1-0.5, y=0-0.2. Additionally, in some embodiments, the seed layer 102 may include a NiFe layer disposed over the top surface of the CrNi or CrNiFe.FIG. 1B shows example magnetizations of the reference layer 110, the free layer 112, and the hard bias layer 116 for a low impedance state 115 and a high impedance state 117. The low impedance state 115 (R P, which may correspond to an "o" state, for example), occurs when the magnetization of the reference layer 110 and the free layer 112 are parallel (e.g., both point "up"), while the high impedance state 117 (R AP, which may correspond to an "1" state, for example), occurs when the magnetization of the reference layer 110 and the free layer 112 are antiparallel (e.g., one point "up" and the other point "down"). In this example, the magnetization of the hard bias layer 116 points "down" and the magnetization of the reference layer 110 points "up" and is antiparallel to that of the hard bias layer 116. However, in other embodiments, the magnetization of the hard bias layer 116 could also be interchanged to point "up", provided that the magnetization of the reference layer 110 remains antiparallel to that of the hard bias layer 116 (e.g., points "down"). In addition, although FIG. 1B shows an example in which the magnetizations are perpendicular to the planes in which the hard bias layer 116, the reference layer 110, and the free layer 112 are disposed, in-plane MTJs in which the magnetizations are parallel to the planes in which the hard bias layer 116, the reference layer 110, and the free layer 112 are disposed shall also be considered to fall within the scope of this disclosure. For example, the magnetization of the hard bias layer 116 could point to "left" and the magnetization of the reference layer 110 could point to "right", where the magnetization of the free layer 112 would be either parallel ("right") or antiparallel ("left") to that of the reference layer 110.FIGS. 2A-2D show an example of some embodiments of how seed layer 120 may be formed. In FIG. 2A, a CrNiFe layer 204 is deposited over a bottom electrode 106 of CMP planarized titanium nitride (TiN) or tantalum nitride (TaN). The CrNiFe layer 204 may be formed by plasma vapor deposition (PVD), for example. The CrNiFe layer 204 is made of CrNiFe crystals 206 (e.g., the individual CrNiFe crystals 206 a, 206 b, 206 c). The CrNiFe crystals 206 have a (111) fcc lattice structure. These CrNiFe crystals 206 also have an initial average grain size, where a grain size for a CrNiFe crystal is the largest lateral distance measured between grain boundaries 208 surrounding that CrNiFe crystal and separating that CrNiFe crystal from other adjacent CrNiFe crystals. For example, the first grain boundary 208 aseparates the first CrNiFe crystal 206 afrom the second CrNiFe crystal 206 band the second grain boundary 208 bseparates the second CrNiFe crystal 206 bfrom the third CrNiFe crystal 206 c. The first CrNiFe crystal 206 ahas a first greatest lateral distance (e.g., a width w 1), the second CrNiFe crystal 206 bhas a second greatest lateral distance (e.g., a width w 2), and the third CrNiFe crystal 206 bhas a third greatest lateral distance (e.g., a width w 3), wherein the initial mean grain size of the crystals 206 a, 206 b, and 206 cis (w1+w2+w 3) / 3. In some embodiments, CrNi may be substituted for the CrNiFe, such that each individual crystal is a CrNi crystal having grain boundaries separating individual CrNi crystals from each other.In FIG. 2B, a NiFe layer 209 is deposited over an upper surface of the CrNiFe layer 204, for example, by PVD. The NiFe layer 209 is deposited to have a strong fcc (111) orientation.In FIG. 2C, it can be seen that when the NiFe layer 209 comes into contact with the underlying CrNiFe layer 204, the NiFe layer 209 causes the initial lattice structure of the CrNiFe layer 204 to be recrystallized and an enlarged crystal lattice structure of the CrNiFe layer 204' to be formed. This may result from, for example, a lattice strain resulting from a lattice mismatch between the CrNiFe layer 204 and the NiFe layer 209. Specifically, the NiFe layer 209 increases the average grain size of the CrNiFe crystals 206 from the initial average grain size to an increased grain size. Thus, this change in the lattice structure reduces the number of grain boundaries 208 in the CrNiFe layer 204 and makes the lattice structure of the CrNiFe layer 204 stronger fcc (111). For example, in some embodiments, the initial average grain size of CrNiFe crystals (based on widths w1, w2, and w3in FIG. 2B ) may be about 5 nm-20 nm, and the increased average grain size of CrNiFe crystals (based on the largest lateral widths w1', w2', and w3' in FIG. 2C ) may be in the range of 20 nm-40 nm between outer sidewalls of each grain, where the increase in average grain size is in a range of 5% to 120% in some embodiments.Referring to the left side of FIG. 2D, the NiFe layer 209 may then be removed along with a top portion of the CrNiFe layer 204' such that a top surface 220 of the CrNiFe layer is planarized and now corresponds to an embodiment of the seed layer 120 in FIG. 1A. After planarization, planarized CrNiFe layer 204" has a strong fcc (111) lattice and still has CrNiFe crystals 206 of increased grain size. The hard bias layer (e.g., 116 in FIG. 1 ) may then be formed in direct contact with the planarized top surface of the CrNiFe layer, as shown in FIG. 1A. In some cases, the planarization routine of FIG. 2D also "thins" the CrNiFe layer, for example, to a thickness in the range of 1 nm to 5 nm, and is about 2 nm in some embodiments. Thinning the CrNiFe layer 204 helps reduce the lateral "spread" of any grain boundaries and also reduces the electrical resistance of the CrNiFe layer 204. In some embodiments, the left side of FIG. 2D is achieved by performing a chemical mechanical planarization (CMP) operation, wherein a polishing head applies downward pressure while rotating in the presence of a chemical slurry to planarize the top surface 220 of the CrNiFe layer 204. In other embodiments, the left side of FIG. 2D is achieved by sputtering off the NiFe layer ( 209 in FIG. 2C ) and the top portion of the CrNiFe layer ( 204 in FIG. 2C ) by directing an ion current at a non-normal angle towards the structure and ejecting atoms of the NiFe layer 209 and the CrNiFe layer 204. As shown in the right portion of FIG. 2D, in some cases, the NiFe layer 209 may also be left in place completely or partially, such that the seed layer 120 of FIG. 1A includes a CrNiFe layer 204' (or CrNi layer) with a NiFe layer 209 over it, and the hard bias layer (FIGS. 1, 116) may be formed in direct contact with the top surface of the NiFe layer 209. Leaving the NiFe layer 209 in place is a small disadvantage in that it tends to increase the resistance of the final seed layer, but it also tends to somewhat simplify the manufacturing process. Portions of the NiFe layer 209 may be removed by, for example, CMP or sputtering.FIG. 3A illustrates a schematic cross-sectional view of MTJ stacks 102 included in an interconnect structure 320 on a semiconductor substrate 300. A lower interconnect via 125 is disposed over an interconnect line stack 432 / 434 and is surrounded by an insulating layer 241. A lower electrode 106 is disposed over the lower interconnect via 125. An upper electrode 108 is disposed over the lower electrode 106. The lower electrode 106 is preferably made of a 5 nm thick tantalum nitride (TaN) film. The upper electrode 108 is preferably made of a 5 nm thick titanium nitride (TiN) film. An upper electrode via 126 is disposed over the MTJ stack 102 and is surrounded by an insulating layer 243.The substrate 300 may be, for example, a ground substrate (e.g., a monocrystalline silicon ground substrate) or a silicon-on-insulator (SOI) substrate. Two access transistors 410, 104 are arranged in and / or above the substrate 300. Access transistors 410, 104 include gate electrodes 414, 416, gate dielectrics 418, 420, and source / drain regions 424, respectively. The source / drain regions 424 are disposed within the substrate 300 and are doped to have a first conductivity type opposite a second conductivity type of a channel region under the gate dielectrics 418, 420, respectively. The gate electrodes 414, 416 may be, for example, doped polysilicon or a metal such as aluminum or copper, or combinations thereof. The gate dielectrics 418, 420 may be, for example, an oxide such as silicon dioxide or a high-κ dielectric material.The interconnect structure 320 is disposed over the substrate 300 and couples devices (e.g., the access transistors 410, 104) to each other. The interconnect structure 320 includes a plurality of inter-metal dielectric (IMD) layers (e.g., 426, 428) and a plurality of metallization layers (e.g., 432, 434) that are alternately stacked. The IMD layers 426, 428 may be comprised of, for example, a low-κ dielectric material, such as undoped silicate glass, or an oxide, such as silicon dioxide, or an ultra-low-κ dielectric layer. The metallization layers 432, 434 include metal lines formed within trenches and which may be made of a metal such as copper or aluminum. The contacts 444 extend from the bottom metallization layer 432 to the source / drain regions 424 and / or the gate electrodes 414, 416, and the vias (e.g., 446) extend between the metallization layers 432, 434. The contacts 444 and the vias 446 may be made of, for example, a metal such as copper or tungsten.The MTJ stacks 102 configured to store corresponding data states are disposed within the interconnect structure 320 between adjacent metal layers. The MTJ stack 102 is grown from a seed layer 120 over the bottom electrode 106. In some embodiments, the seed layer 120 is in the form of a column, which is a single crystal, over each bottom electrode 106. As shown in the top view of FIG. 3B, the seed layer 120 may be round or circular in some cases when viewed from above. In other embodiments, the seed layer 120 may be square, square with rounded corners, rectangular, rectangular with rounded corners, or oval shaped when viewed from above.FIG. 4 shows a more detailed example of a memory device 400 including an MTJ stack 102, in accordance with some embodiments. The MTJ stack 102 is disposed between the lower electrode 106 and the upper electrode 108. The MTJ stack includes a seed layer 120, a hard bias layer 116, an APC layer 118, a reference layer 110, a barrier layer 114, a free layer 112, and a capping layer 140.In some embodiments, the bottom electrode 106 includes, for example, tantalum (Ta), tantalum nitride (TaN), or ruthenium (Ru). Although tantalum and ruthenium are transition metals and thus conductive, tantalum and ruthenium may also be diffusive species with respect to the materials in the MTJ stack 102.In some embodiments, seed layer 120 includes a CrNiFe layer 204. In some embodiments, the CrNiFe layer 204 is a crystalline non-magnetic ternary alloy of CrNiFe having a top surface that is planar or planar. For example, in some cases, the composition of this crystalline layer 204 may have the form Cr x Ni 1-x-y Fe y where x=0.1-0.5, y=0-0.2. In other embodiments, the CrNiFe layer 204 may be replaced with a non-magnetic binary alloy of CrNi. A NiFe layer 209, which is optional, may also be present over a top surface of the CrNiFe layer 204 in some embodiments.The hard bias layer 116 is a ferromagnetic material having a magnetization direction that is constrained or "fixed.". This "fixed" direction of magnetization can be achieved in some cases by exposing the chip to a strong magnetic field after the entire chip has been manufactured. In some embodiments, the hard bias layer 116 comprises a laminated structure of N repeats of alternating layers of Co and platinum (Pt). In some embodiments, N is an integer greater than one, in some embodiments, N is 5, in alternative embodiments, N is within a range of about 5 to 20, or is another suitable number. In the illustrated embodiment, the hard bias layer 116 includes a first hard bias layer 210 disposed over and in direct contact with a top surface of the seed layer 120, a second hard bias layer 212 disposed over the first hard bias layer 210, a first Co (cobalt) layer 214 over the second hard bias layer 212, and a third hard bias layer 216 disposed over the first Co layer 214. In some embodiments, the first hard bias layer 210 is made of cobalt nickel (CoNi), cobalt palladium (CoPd), or cobalt platinum (CoPt), or the first hard bias layer 210 is made of a multilayer stack of the aforementioned materials. In some embodiments, the second hard bias layer 212 is made of nickel (Ni), palladium (Pd), or platinum (Pt). In some embodiments, the third hard bias layer 216 is made of nickel (Ni), palladium (Pd), or Pt. In some embodiments, layers within the hard bias layer 116 are respectively formed to a thickness of 0.3 nm or within a range of 0.2 nm to 0.4 nm.The APC (anti-parallel coupling) layer 118 is disposed over the hard bias layer 116 and separates the hard bias layer 116 from the reference layer 110. The APC layer 118 ensures that the magnetization of the reference layer 110 is opposite to that of the hard bias layer 116 by an exchange bias coupling effect. In some embodiments, the APC layer 118 is made of Ru formed to a thickness of 0.4 nanometers or within a range of about 0.3 nanometers to about 0.5 nanometers, or is made of iridium (Ir) formed to a thickness of 0.5 nanometers or within a range of about 0.4 nanometers to about 0.6 nanometers.The reference layer 110 is a ferromagnetic layer that also has a magnetization direction that is "fixed.". However, the magnetization direction of the reference layer 110 is opposite to that of the hard bias layer 116. The reference layer 110 includes a second cobalt layer 218 formed over the APC layer 118 and a first CoFeB (cobalt iron boron) layer 222 disposed over the second cobalt layer 218. A first Mo (molybdenum) or W (tungsten) layer 224 is disposed over the first CoFeB layer 222 and a second CoFeB layer 226 is disposed over the first M (molybdenum) or W (tungsten) layer 224. In some embodiments, the layers within the reference layer 110 are respectively formed to a thickness of 0.3 nm, 0.8 nm, or 1 nm, or are within a range of 0.15 nm to 1.5 nm.The barrier layer 114, which may be a thin dielectric layer or a non-magnetic metal layer in some cases, separates the reference layer 110 from the free layer 112. In some embodiments, the barrier layer 114 may comprise an amorphous barrier such as alumina (AlO x) or titania (TiO x), or a crystalline barrier such as manganese oxide (MgO) or a spinel (e.g., MgAl 2 O 4). The barrier layer 114 may also include, for example, aluminum oxide (e.g., Al 2 O 3), nickel oxide, gadolinium oxide, tantalum oxide, molybdenum oxide, titanium oxide, tungsten oxide, or the like. In embodiments where the ferromagnetic memory stack is a magnetic tunnel junction (MTJ), the barrier layer 114 is a tunnel barrier layer that is thin enough to allow quantum mechanical tunneling of current between the reference layer 110 and the free layer 112.The free layer 112 is capable of changing its direction of magnetization between one of the two states of magnetization corresponding to binary data states stored in the memory cell. In the illustrated embodiment, the free layer 112 includes a third CoFeB layer 230 disposed over the barrier layer 114, a first free layer 232 disposed over the third CoFeB layer 230, and a fourth CoFeB layer 234 disposed over the first free layer 232. In some embodiments, the first free layer 232 comprises molybdenum (Mo) or tungsten (W). In some embodiments, the layers within the free layer 112 are respectively formed to a thickness of 0.2 nm or 1 nm or are within a range of 0.10 nm to 1.5 nm. In some embodiments, the free layer 112 includes iron, cobalt, nickel, iron cobalt, nickel cobalt, cobalt iron boride, iron boride, iron platinum, iron palladium, or the like.The capping layer 140, which in some contexts may also be referred to as a PMA (Perpendicular Magnetic Anisotropy) protection layer, is disposed over the free layer 112. The capping layer 140 often increases anisotropy for the MTJ stack or protects it from degradation when the stack is built up. It will be appreciated that the cover layer 140 may have many shapes, and thus FIG. 4 is merely an example. The capping layer 140 includes a capping MgO (magnesium oxide) layer 236 disposed over the fourth CoFeB layer 234, a capping CoFeB layer 238 disposed over the MgO capping layer 236, a first capping layer 240 disposed over the capping CoFeB layer 238, and a second capping layer 242 disposed over the first capping layer 240. In some embodiments, the first capping layer 240 comprises molybdenum (Mo) or tungsten (W). In some embodiments, the layers within the capping layer 140 are respectively formed to thicknesses of 0.4 nm, 0.6 nm, or 2 nm, or are within a range of 0.20 nm to 3 nm. In some embodiments, the capping layer 140 comprises ruthenium (Ru) formed to a thickness of 6 nm or within a range of 3 nm to 9 nm.FIGS. 5-11 illustrate cross-sectional views 500- 1100 of some embodiments of a method of forming a memory device including an MRAM cell including an MTJ, in accordance with the present disclosure. Although the cross-sectional views 500- 1100 shown in FIGS. 5- 11 are described with reference to a method, it will be understood that the structures shown in FIGS. 5- 11 are not limited to the method, but rather may be separate from the method alone. Although FIGS. 5-11 are described as a sequence of acts, it will be understood that these acts are not limiting in that the order of acts may be changed in other embodiments and that the disclosed methods are also applicable to other structures. In other embodiments, some acts illustrated and / or described may be omitted, in whole or in part.As shown in cross-sectional view 500 of FIG. 5, an interconnect via 125 is formed within a second dielectric layer 241. A bottom electrode layer 106, which may be made of tantalum nitride, for example, is formed over the interconnect via 125. A seed layer precursor 204, which may be made of, for example, NiCr or NiCrFe, is formed over the bottom electrode layer 106. The seed layer precursor 204 may be formed by plasma vapor deposition (PVD), for example. The seed layer precursor 204 is comprised of individual crystals having a (111) fcc lattice structure and separated by grain boundaries between nearest neighboring crystals, for example as previously described in FIG. 2A.As shown in cross-sectional view 600 of FIG. 6, a recrystallization inducing layer 209 is then formed, for example, by PVD, over the seed layer precursor. The recrystallization inducing layer 209 may include NiFe in some embodiments and may have a strong (111) fcc lattice structure. When the recrystallization inducing layer 209 contacts the underlying seed layer precursor, the recrystallization inducing layer 209 induces the recrystallization of the initial lattice structure of the seed layer precursor, thereby forming a seed layer 120 having a layer 204' with enlarged crystal grains, for example, as previously described in FIG. 2C. In some embodiments, the recrystallization inducing layer 209 may be partially or completely removed, although illustrated as remaining in place in FIGS. 7-11 as an example.Then, as shown in cross-sectional view 700 of FIG. 7, a hard mask layer 702 made of, for example, titanium nitride is formed and patterned over the recrystallization inducing layer 209. After the hard mask layer 702 is deposited, an etch is then performed to form a bottom electrode structure 106 and a pillar corresponding to a seed layer structure 120 over each bottom electrode. In some embodiments, the increased crystal lattice structure of seed layer structure 120, in conjunction with the patterning and etching in FIG. 7, results in seed layer structure 120 including only a single crystal over each bottom electrode, which may help improve the quality of the fcc (111) lattice structure of the MTJ to be formed. Further, the sidewalls of the bottom electrode 106, seed layer structure 120, and recrystallization inducing layer 209 may all be tapered at the same angle so as to be aligned and / or coplanar with each other. Further, the sidewalls of the bottom electrode 106, the seed layer structure 120, and the recrystallization inducing layer 209 may be angled in a direction opposite to that of the sidewalls of the via 308. For example, the sidewall angle of the bottom electrode 106 may be about 80 degrees to 90 degrees relative to the top surface of the via 308, while the sidewall angle of the via 308 may be about negative 80 degrees to negative 90 degrees relative to the top surface of the via 308.As shown in cross-sectional view 800 of FIG. 8, a passivation or CMP stop layer 802, which may be made of silicon nitride, for example, is formed over the structure. A CMP process is then performed. The CMP process may optionally remove the recrystallization inducing layer ( 209 in FIG. 7 ) completely or partially, and may thin the seed layer structure 120 from its initial thickness to a non-zero thinned thickness, in some embodiments.As shown in cross-sectional view 900 of FIG. 9, an MTJ stack 102 is then grown from seed layer structure 120, and a top electrode 108 made of, for example, titanium nitride is formed over MTJ stack 102. Typically, the MTJ stack 102 and the top electrode 108 are formed and are then patterned using lithography techniques.As shown in cross-sectional view 1000 of FIG. 10, an insulating layer 1002, such as a low-k dielectric material, is then formed over the top electrode 108 and along the sidewalls of the MTJ stack 102.As shown in the cross-sectional view 1100 of FIG. 11, a chemical mechanical planarization (CMP) process is performed on the upper electrode 108 and the insulating layer 1002. An upper insulating layer 330 is formed over the upper electrode 108 and the insulating layer 1002. An upper electrode via 126 is formed over the upper electrode 108. A conductive wire, such as a source line SL, is formed over the upper electrode via 126.Referring to FIG. 12, a block diagram 1200 of some embodiments of the method of FIGS. 5-11 is provided.At 1202, a bottom electrode layer is formed in an interconnect structure over a semiconductor substrate. In some embodiments, the bottom electrode layer is a TaN or TiN layer, and in some embodiments, 1202 may correspond to FIG. 5, as discussed above.At 1204, a polycrystalline seed layer, e.g., made of CrNiFe, is formed over the bottom electrode layer. In this initial formation, the crystals of the polycrystalline seed layer have an initial mean grain size. In some embodiments, 1204 may correspond to FIG. 5, as discussed above.At 1206, a recrystallization inducing layer, e.g., made of NiFe, is formed over and in direct contact with the polycrystalline seed layer. The formation of the NiFe layer causes the polycrystalline layer to be recrystallized to produce a recrystallized polycrystalline layer. The crystals of the recrystallized polycrystalline layer have enlarged crystals having an enlarged average grain size larger than the initial average grain size. In some embodiments, 1206 may correspond to FIG. 6, as discussed above.At 1208, a mask is formed over the recrystallization inducing layer, and after the mask is deposited, an etch is performed to remove portions of the recrystallization inducing layer, the recrystallized polycrystalline layer, and the bottom electrode layer. In some embodiments, 1208 may correspond to FIG. 7, as discussed above.At 1210, a dielectric layer is formed over the structure and CMP is performed. In some embodiments, 1210 may correspond to FIG. 8, as discussed above.At 1212, an MTJ stack and a top electrode are formed over a top surface of the recrystallized polycrystalline layer. The MTJ stack and top electrode are then patterned and etched using, for example, photolithography techniques. In some embodiments, 1212 may correspond to FIG. 9, as discussed above.At 1214, a dielectric is formed over a top surface and sidewalls of the MTJ stack and top electrode. In some embodiments, 1214 may correspond to FIG. 10, as discussed above.At 1216, CMP is performed and the upper interconnect layers are formed, for example, as illustrated and described above with reference to FIG. 11.The invention is defined by the main claim and the subordinate claims. Further embodiments of the invention are set forth in the dependent claims.

Claims

A semiconductor device, comprising: a bottom electrode (106) disposed over a semiconductor substrate (300); an MTJ stack (102) disposed over the bottom electrode (106); and a conductive seed layer (120) comprising a CrNiFe layer (204) or CrNi layer separating the bottom electrode (106) from the MTJ stack (102), wherein the conductive seed layer includes only a single CrNiFe crystal (206) between the bottom electrode (106) and the MTJ stack (102).The semiconductor device of claim 1, wherein the conductive seed layer (120) comprises Cr x Ni 1-x-y Fe y where x = 0.1 - 0.5, y = 0 - 0.2.The semiconductor device of claim 1 or 2, wherein a thickness of the conductive seed layer (120) as defined between a top surface of the bottom electrode (106) and a bottom surface of the MTJ stack (102) is between 1 nm and 3 nm.The semiconductor device of any preceding claim, wherein the conductive seed layer (120) comprises: a CrNiFe layer (204) disposed directly on the bottom electrode (106); and a NiFe layer (209) in direct contact with a top surface of the CrNiFe layer (204).The semiconductor device of any preceding claim, wherein the MTJ stack (102) comprises: a hard bias layer (116) disposed over the conductive seed layer (120); a reference layer (110) disposed over the hard bias layer (116); an APC layer (118) separating the hard bias layer (116) from the reference layer (110); a barrier layer (114) over the reference layer (110); a free layer (112) over the barrier layer (114); and a capping layer (140) disposed over the free layer (112).The semiconductor device of claim 5, further comprising: a top electrode (108) disposed over the capping layer (140); and a top electrode via (126) disposed over the top electrode (108).The semiconductor device of any preceding claim, wherein the bottom electrode (106) is formed over and electrically coupled to a via (446), wherein sidewalls of the bottom electrode (106) and the conductive seed layer (120) are angled in a first direction that is opposite a second direction in which sidewalls of the via (446) are angled.A method comprising: forming a bottom electrode layer (106); forming a polycrystalline CrNiFe layer (204) over the bottom electrode layer (106), wherein the polycrystalline CrNiFe layer (204) contains CrNiFe crystals having an initial mean grain size; forming a NiFe layer (209) over and in direct contact with the CrNiFe polycrystalline layer (204), wherein forming the NiFe layer (209) causes recrystallization of the CrNiFe polycrystalline layer (204) to produce a recrystallized CrNiFe polycrystalline layer (204), wherein the recrystallized CrNiFe polycrystalline layer (204) includes enlarged CrNiFe crystals having an enlarged average grain size greater than the initial average grain size, the method further comprising: forming a mask over the recrystallized CrNiFe polycrystalline layer (204); and removing portions of the recrystallized CrNiFe polycrystalline layer (204) and the bottom electrode layer (106) to form a patterned recrystallized CrNiFe polycrystalline structure and a bottom electrode structure (106), wherein the patterned recrystallized CrNiFe polycrystalline structure is made of a single CrNiFe crystal (206) over the bottom electrode structure (106).The method of claim 8, further comprising: removing the NiFe layer (209) over the recrystallized CrNiFe polycrystalline layer (204) and thinning the recrystallized CrNiFe polycrystalline layer (204); and forming an MTJ stack (102) in direct contact with a top surface of the thinned recrystallized CrNiFe polycrystalline layer (204) after the NiFe layer (209) is removed.The method of claim 9, wherein forming the MTJ stack (102) comprises: forming a hard bias layer (116) over the polycrystalline CrNiFe layer (204); forming an APC layer over the hard bias layer (116); forming a reference layer (110) over the APC layer (118); forming a barrier layer (114) over the reference layer (110); and forming a free layer (112) over the barrier layer (114).The method of claim 9 or 10, further comprising: forming a second mask over the MTJ stack (102); and removing portions of the MTJ stack (102) such that a patterned MTJ stack (102) remains over the recrystallized CrNiFe polycrystalline layer (204).The method of any of claims 9 to 11, further comprising: forming the MTJ stack (102) in direct contact with a top surface of the NiFe layer (209).The method of claim 8, further comprising: forming an MTJ stack (102) in direct contact with a top surface of the NiFe layer (209).The method of any of claims 8 to 13, wherein the bottom electrode layer (106) is formed over and electrically coupled to a via (446), wherein sidewalls of the bottom electrode (106), a seed layer structure (120), and a recrystallization inducing layer are angled in a first direction that is opposite a second direction in which sidewalls of the via (446) are angled.A semiconductor device, comprising: a semiconductor substrate (300); an interconnect structure (320) disposed over the semiconductor substrate (300); a bottom electrode (106) disposed over the semiconductor substrate (300) within the interconnect structure (320); a conductive seed layer (120) comprising a CrNiFe layer (204) or a CrNi layer disposed on the bottom electrode (106); a magnetic tunnel junction (102) disposed over the conductive seed layer (120) and separated from the bottom electrode (106) by the conductive seed layer (120); and an upper electrode (108) disposed over the magnetic tunnel junction (102), wherein the conductive seed layer (120) includes only a single CrNiFe crystal (206) separating the lower electrode (106) and the magnetic tunnel junction (102).The semiconductor device of claim 15, wherein the bottom electrode layer (106) is formed over and electrically coupled to a via (446) in the interconnect structure (320), wherein sidewalls of the bottom electrode (106), a seed layer structure (120), and a recrystallization inducing layer are angled in a first direction that is opposite a second direction in which sidewalls of the via (446) are angled.The semiconductor device of any one of claims 15 to 16, wherein the conductive seed layer (120) comprises Cr x Ni 1-x-y Fe y where x = 0.1 - 0.5, y = 0 - 0.2.The semiconductor device of any of claims 15 to 17, wherein a thickness of the conductive seed layer (120) as defined between a top surface of the bottom electrode (106, 202) and a bottom surface of the magnetic tunnel junction (102) is between 1 nm and 3 nm.

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