LAYOUT METHOD FOR THE FINS OF INTEGRATED CIRCUITS

Abstract

Method for operating an integrated circuit manufacturing system, IC manufacturing system (1200), wherein the method comprises: Determine whether an active n-region of a cell (200C, 300C, 600A-D, 710, 810, 820, 830, 840, 850, 860) or active p-region of the cell (200C, 300C, 600A-D, 710, 810, 820, 830, 840, 850, 860) is a first active region (AR1, AR2) based on a time-critical path of the cell (200C, 300C, 600A-D, 710, 810, 820, 830, 840, 850, 860), wherein a gate region (Gro - Gr3) intersects the first active region (AR1, AR2) at a position corresponding to a transistor (P1, P2, N1, N2) corresponds to or a corresponding gate structure refers to a dummy gate structure; Positioning the first active region along a cell height direction (Y) in the IC layout diagram of the cell (200C, 300C, 600A-D, 710, 810, 820, 830, 840, 850, 860), wherein the first active region (AR1, AR2) comprises a first total number of fins (F1-F5) with the fins extending in a direction (X) perpendicular to the cell height direction (Y); Positioning a second active region (AR1, AR2) in the cell (200C, 300C, 600A-D, 710, 810, 820, 830, 840, 850, 860) along the cell height direction (Y), wherein a gate region (Gro - Gr3) intersects the second active region (AR1, AR2) at a position corresponding to a transistor (P1, P2, N1, N2) or a corresponding gate structure related to a dummy gate structure, wherein the second active region (AR1, AR2) is of the n-type or p-type opposite the n-type or p-type of the first active region (AR1, AR2) and includes a second total number of fins (F1-F5) that is less than the first total number of fins, the fins of the second total number of fins extending in the direction (X). Positioning a third active area (AR1, AR2) adjacent to the second active area (AR1, AR2) in the cell (200C, 300C, 600A-D, 710, 810, 820, 830, 840, 850, 860) along the cell height direction (Y), wherein the third active area (AR1, AR2) is of the same n-type or p-type as the second active area (AR1, AR2) and comprises the first total number of fins (F1-F5); and Positioning a fourth active area (AR2, AR2) adjacent to the third active area (AR1, AR2) in the cell (200C, 300C, 600A-D, 710, 810, 820, 830, 840, 850, 860) along the cell height direction (Y), wherein the fourth active area (AR1, AR2) is of the same n-type or p-type as the first active area (AR1, AR2) and comprises the second total number of fins (F1-F5); and Storing the IC layout diagram (200, 300, 500, 600, 700, 800) of the cell (200C, 300C, 600A-D, 710, 810, 820, 830, 840, 850, 860) in a cell library (1120).

Description

BACKGROUND

[0001] An integrated circuit (IC) typically contains a number of semiconductor devices, also known as IC components. One way to represent an IC is with a top-down diagram, called a layout diagram or IC layout diagram. An IC layout diagram is hierarchical and contains modules that implement high-level functions according to the IC component's layout specifications. The modules are often built from a combination of cells, which can be either standard or custom-designed, each representing one or more semiconductor structures.

[0002] Cells are configured to provide conventional low-level functions, often performed by transistors based on gate regions that intersect active regions, sometimes known as oxide definition (OD) regions. The elements of a cell are arranged within a cell boundary and electrically connected to other cells through interconnection structures. DE 10 2017 125 395 A1 relates to a semiconductor device with active regions and a structure wherein the active regions are formed as predetermined shapes on a substrate and arranged with respect to a grid. US 2017 / 0 323 047 A1 relates to a method for triple-structuring-friendly placement. US 2009 / 0 083 681 A1 relates to methods and devices for analyzing and / or designing integrated circuits using virtual transparent cells. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Aspects of the present invention are best understood from the following detailed description when read in conjunction with the accompanying figures. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of the various features may have been arbitrarily increased or decreased for clarity of discussion. Fig. Figure 1 is a flowchart of a method for operating an IC manufacturing system in accordance with some embodiments. Fig. Figure 2 shows an IC layout diagram in accordance with some embodiments. Fig. Figure 3 shows an IC layout diagram in accordance with some embodiments. Fig. Figure 4 is a flowchart of a method for operating an IC manufacturing system in accordance with some embodiments. Fig. Figure 5 shows an IC layout diagram in accordance with some embodiments. Fig. Figure 6 shows an IC layout diagram in accordance with some embodiments. Fig. Figure 7 shows an IC layout diagram in accordance with some embodiments. Fig. Figure 8 shows an IC layout diagram in accordance with some embodiments. Fig. Figure 9 is a diagram of an IC structure in accordance with some embodiments. Fig. Figure 10 is a flowchart of a process for manufacturing an IC structure in accordance with some embodiments. Fig. Figure 11 is a block diagram of an IC layout diagram generation system in accordance with some embodiments. Fig. Figure 12 is a block diagram of an IC manufacturing system and an associated IC manufacturing process in accordance with some embodiments. DETAILED DESCRIPTION

[0004] The following disclosure provides many different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components, values, operations, materials, arrangements, or the like are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. Other components, values, operations, materials, arrangements, or the like are considered. For example, the formation of a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are formed in direct contact, and may also include embodiments in which additional elements may be formed between the first and second elements, so that the first and second elements need not be in direct contact.Additionally, this disclosure may repeat reference numbers and / or symbols in the different examples. This repetition serves the purpose of simplification and clarity and does not itself establish any relationship between the different embodiments and / or configurations discussed.

[0005] Furthermore, spatially relative expressions such as "below," "under," "lower," "above," "above," and the like may be used herein to facilitate description and to describe the relationship of one element or feature to another element(s) or feature(s), as illustrated in the figures. These spatially relative expressions are intended to encompass various orientations of the component in use or operation in addition to the orientation depicted in the figures. The device may be oriented differently (rotated by 90 degrees or in other orientations), and the spatially relative descriptive expressions used herein may be interpreted accordingly.

[0006] In different embodiments, a method, system, and structure correspond to an IC layout diagram of a cell comprising fin field-effect transistors (FinFETs) having different numbers of fins. For a given cell height containing at least one FinFET with a larger number of fins than at least one other FinFET, the driving capability of the linked IC device increases compared to approaches where each FinFET in a cell contains the same number of fins.In some embodiments, the IC layout diagram includes a fin track arrangement configured to support placement of a variety of cells, including those with FinFETs having different numbers of fins, thereby enabling increased multi-cell driving capability compared to approaches that do not include fin track arrangements configured to support placement of cells with FinFETs having different numbers of fins.

[0007] Fig. Figure 1 is a flowchart of a method 100 for operating an IC manufacturing system in accordance with some embodiments. In some embodiments, operating the IC manufacturing system includes an IC layout diagram, e.g., an IC layout diagram 200 or 300, which is shown below in relation to Fig. 2 and Fig. 3 is discussed, to create an IC structure, e.g. an IC structure 900, which is discussed below in relation to Fig. Section 9 discusses the IC component, which is manufactured as part of an integrated circuit (IC) based on the generated IC layout diagram. Non-exhaustive examples of IC components include memory circuits, logic devices, processing devices, signal processing circuits, and the like.

[0008] In some embodiments, some or all of method 100 is performed by a computer processor. In some embodiments, some or all of method 100 is performed by a processor 1102 of an IC layout diagram generation system 1100, described below with respect to Fig. 11 will be discussed.

[0009] Some or all of the operations of procedure 100 are capable of being performed as part of a layout procedure carried out in a layout plant, e.g., layout plant 1220, which relates to Fig. 12 will be discussed.

[0010] In some embodiments, the operation of method 100 is performed in the Fig. The operation is carried out in the sequence shown in Figure 1. In some embodiments, the operation of method 100 is performed simultaneously and / or in a different order than that shown in Figure 1. Fig. The sequence shown in 1 is performed. In some embodiments, one or more operations are performed before, between, during and / or after one or more operations of procedure 100.

[0011] Fig. 2 and Fig. Figure 3 are non-restrictive examples of the respective IC layout diagrams 200 and 300, which, in some embodiments, are generated by performing one or more operations of Method 100 as discussed below. IC layout diagrams 200 and 300 are simplified for illustrative purposes. In different embodiments, one or more of IC layout diagrams 200 and 300 include additional features beyond those shown in Figure 3. Fig. 2 and Fig. 3 shown, e.g. one or more transistor elements, busbars, insulation structures, trays, conductive elements or the like.

[0012] Each of Fig. 2 and Fig. Figure 3 further depicts an X-direction and a Y-direction perpendicular to the X-direction. The X-direction, depicted as horizontal with respect to the page, and the Y-direction, depicted as vertical, are non-restrictive examples for illustrative purposes. In different embodiments, the X- and Y-directions are perpendicular to each other and have orientations other than those shown in Figure 3. Fig. 2 and Fig. 3 shown.

[0013] The X-direction contains a positive X-direction, which is in Fig. 2 and Fig. Figure 3 shows a negative X-direction (unlabeled) opposite the positive X-direction. The Y-direction includes a positive Y-direction, which is shown in Fig. 2 and Fig. Figure 3 is shown, and a negative Y direction (not labeled) opposite the positive Y direction.

[0014] In some embodiments, operation 110 involves receiving an IC layout diagram of a cell. In some embodiments, receiving the cell's IC layout diagram is referred to as receiving the cell. In some embodiments, receiving the cell's IC layout diagram is part of receiving one or more IC layout diagrams of a plurality of cells.

[0015] In various embodiments, receiving the IC layout diagram of the cell includes receiving the IC layout diagram of a standard cell, a custom cell, an engineering change order (ECO) cell, a logic gate cell, a memory cell, or any other cell type or combination of cells capable of being defined in an IC layout diagram. In various embodiments, a logic gate cell includes one or more AND, OR, NAND, NOR, XOR, INV, AND-OR-Invert (AOI), OR-AND-Invert (OAI), MUX, flip-flop, BUFF, buffer, delay, or clock element.In various embodiments, a memory cell contains one or more cells of a static random access memory (SRAM), a dynamic random access memory (DRAM), a resistive RAM (RRAM), a magnetoresistive RAM (MRAM), a read-only memory (ROM), or another component capable of having multiple states representing logical values.

[0016] Receiving the IC layout diagram of the cell involves receiving the cell, which contains a pair of active regions. An active region, e.g., active region AR1 or AR2, is shown below with respect to... Fig. 2 and Fig. 3 discussed is an area in an IC layout diagram that is included in a manufacturing process as part of defining an active region in a semiconductor substrate, which in some embodiments is also referred to as an oxide diffusion or definition (OD).

[0017] An active region is a continuous section of the semiconductor substrate containing either n- or p-type dopants and various semiconductor structures, including, in some embodiments, one or more fins of a FinFET. In different embodiments, an active region is located within a well, i.e., either an n-well or a p-well, within the semiconductor substrate and / or is electrically isolated from other elements in the semiconductor substrate by one or more isolation structures, e.g., one or more shallow trench isolation (STI) structures.

[0018] A fin is a raised, elongated section of an active region extending in a first direction that contains one or more elements of an elemental semiconductor, e.g. silicon (Si) or germanium (Ge), a compound semiconductor, e.g. silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs) or indium antimonide (ISb), or an alloy semiconductor, e.g. GaAsP, AlInAs, AlGaAs, GaInAs, GaInP or GaInAsP, or the like.

[0019] In some embodiments, an active region contains one or more source / drain (S / D) structures, corresponding to one or more S / D regions within the active region used to define the active region. An S / D structure is a semiconductor structure within an active region that borders or contains portions of the one or more fins and is configured to have a dopant opposite to that of other portions of the active region. In some embodiments, an S / D structure is configured to have a lower resistivity than other portions of the active region, for example, by containing one or more portions that have higher dopant concentrations than one or more dopant concentrations otherwise present in the active region. In various embodiments, S / D structures contain epitaxial regions of a semiconductor material, e.g.,Si, SiGe and / or SiC.

[0020] In some embodiments, receiving the IC layout diagram of the cell includes receiving the IC layout diagram, which contains one or more of a gate area, a metal-like defined (MD) area, a conductive area, or a via area.

[0021] A gate area, e.g., one of gate areas GRo-GR3, which is in Fig. Figures 2 and / or 3 depict an area in an IC layout diagram that, as part of a manufacturing process, defines a gate structure superimposed on the semiconductor substrate. In the non-restrictive examples shown in Fig. 2 and Fig. As shown in Figure 3, gate areas GRo-GR3 have an alignment along the Y direction.

[0022] As in Fig. In some cases, a position where a gate region intersects an active region in an IC layout diagram corresponds to a transistor, e.g., one of transistors P1, P2, N1, or N2, in the corresponding IC structure. This structure includes the portion of the corresponding gate structure that overlays the corresponding active region, portions of the active region beneath and partially surrounded by the gate structure, and S / D structures adjacent to the gate structure. In other cases, a gate region, e.g., one of gate region GRo or Gr3, intersects one of active region AR1 or AR2 at a position that does not correspond to a transistor, and the corresponding gate structure is referred to as a dummy gate structure in some embodiments.

[0023] A gate structure is a volume containing one or more conductive segments, which in turn contain one or more conductive materials, e.g., polysilicon, one or more metals, and / or one or more other suitable materials, substantially surrounded by one or more insulating materials, e.g., silicon dioxide, and / or one or more other suitable materials. The one or more conductive segments are configured to control a voltage applied to underlying and adjacent dielectric layers. In various embodiments, a dielectric layer contains one or more silicon dioxide and / or a high-k dielectric material, e.g., a dielectric material having a k-value higher than 3.8 or 7.0. In some embodiments, a high-k dielectric material contains aluminum oxide, hafnium oxide, lanthanum oxide, or another suitable material.

[0024] An MD area, e.g., one of in Fig. The 3 MD regions MDR1-MDR5 shown are conductive areas in an IC layout diagram, included as part of a manufacturing process to define an MD segment in and / or on a semiconductor substrate. Fig. In the 3 illustrated non-restrictive examples, MD areas MDR1-MDR5 exhibit an alignment along the Y direction.

[0025] In some embodiments, an MD segment includes a section of at least one metal layer, e.g., a contact layer, that overlays and contacts the substrate and has a thickness sufficiently small to allow the formation of an insulating layer between the MD segment and an overlying metal layer, e.g., a zero metal layer. In other embodiments, an MD segment includes one or more of copper (Cu), silver (Ag), tungsten (W), titanium (Ti), nickel (Ni), tin (Sn), aluminum (Al), or another metal or material suitable for providing a low-resistance electrical connection between IC structural elements, i.e., a resistance level below a predetermined threshold corresponding to one or more tolerance levels of a resistance-based effect on circuit work performance.

[0026] In various embodiments, an MD segment contains a portion of the semiconductor substrate and / or an epitaxial layer exhibiting a dopant level, e.g., based on an implantation process, sufficient to induce the segment to exhibit the low resistance level. In various embodiments, a doped MD segment contains one or more of silicon (Si), silicon germanium (SiGe), silicon carbide (SiC), boron (B), phosphorus (P), arsenic (As), gallium (Ga), a metal as discussed above, or another material suitable for providing the low resistance level. In some embodiments, an MD segment contains a dopant having a dopant concentration of approximately 1 × 10⁻⁶. 16 per cubic centimeter (cm³) -3 ) or larger.

[0027] In different embodiments, one or more MD regions, e.g., one or more MD regions MDR1-MDR5, superimpose one or more active regions, e.g., one or both of active region AR1 or AR2, and the corresponding one or more MD segments contain at least a section within the corresponding one or more active regions. In different embodiments, one or more MD segments abut or contain some or all of one or more S / D structures in the corresponding one or more active regions.

[0028] A conductive area, e.g., one of in Fig. The 3 depicted conductive areas MoR or M1R is a conductive area in an IC layout diagram that is included as part of a manufacturing process to define a segment of a conductive layer of the manufacturing process.

[0029] A conductive segment, e.g., a polysilicon, metal zero, metal one, or metal two segment, is a section of a corresponding polysilicon or metal layer, e.g., a metal zero, metal one, or metal two layer, containing one or more of polysilicon, copper (Cu), silver (Ag), tungsten (W), titanium (Ti), nickel (Ni), tin (Sn), aluminum (Al), or any other metal or material suitable for providing a low-resistance electrical connection between IC structural elements.

[0030] A via-hole area, e.g. one of in Fig. The three via areas VR1-VR5 shown in the diagram define an area in an IC layout diagram that, as part of a manufacturing process, defines a via structure configured to provide a low-resistance electrical connection between conductive segments in two or more planes and / or layers of the manufacturing process. Via structures contain one or more of copper (Cu), silver (Ag), tungsten (W), titanium (Ti), nickel (Ni), tin (Sn), aluminum (Al), or another metal or material suitable for providing low-resistance electrical connections between IC structure layers.

[0031] Receiving the IC layout diagram of the cell includes receiving the active regions of the pair of active regions corresponding to different n- or p-type dopants. In some embodiments, receiving the active regions includes receiving each of the pair of active regions configured to define the same number of fins from one or more FinFETs extending in the first direction. In other embodiments, receiving the IC layout diagram of the cell includes receiving each of the pair of active regions configured to define one, two, or three fins of one or more FinFETs.

[0032] In some embodiments, receiving each of the pair of active areas configured to define the same number of fins includes receiving each of the pair of active areas that has the same height in a cell height direction perpendicular to the first direction. In some embodiments, receiving each of the pair of active areas that has the same height includes receiving each of the pair of active areas that has a height AH2 defined below with respect to Fig. 2 and Fig. 3 will be discussed.

[0033] In some embodiments, receiving the cell's IC layout diagram includes receiving the cell's IC layout diagram from a cell library, i.e., a database or collection of electronic files configured to store and provide access to a plurality of IC layout diagrams from different cells. In some embodiments, receiving the cell's IC layout diagram includes receiving the cell's IC layout diagram from a cell library 1120 of IC layout generation system 1100, which is described below in relation to Fig. 11 will be discussed.

[0034] In some embodiments, receiving the cell's IC layout diagram includes receiving one or more electronic files containing data that can be used by an IC manufacturing system as part of an IC manufacturing process, e.g., IC manufacturing system 1200, which is described below in relation to Fig. 12 will be discussed.

[0035] In some embodiments of Operation 120, the active n- or p-region of the cell is determined to be the first active region, as discussed below in relation to Operation 130. Determining whether the active n- or p-region is the first active region is based on a time-critical path of the cell. In some embodiments, the active n-region is determined to be the first active region if the time-critical path contains one or more n-transistors that have a significant effect on time-related cell work performance, or the active p-region is determined to be the first active region if the time-critical path contains one or more p-transistors that have a significant effect on time-related cell work performance. The significance of an effect on time-related cell work performance is based on one or more predefined criteria, such as rise time, fall time, switching speed, circuit bandwidth, or the like.

[0036] In different embodiments, a determination of whether the active n- or p-region is the first active region is carried out by receiving a user input and / or executing one or more algorithms, e.g., one or more circuit simulations, based on a layout corresponding to the IC layout diagram of the cell.

[0037] In different embodiments, the determination of whether the active n- or p-region is the first active region is based on one or more manufacturing recipe parameters, one or more circuit work performance specifications and / or one or more circuit configuration criteria, e.g., parallel or series transistor arrangements.

[0038] In Operation 130, the first active region is positioned along the cell height direction in the IC layout diagram, wherein the first active region is of the n-type or p-type and contains a first total number of fins. In some embodiments, positioning of the first active region in the IC layout diagram is performed in conjunction with positioning of the second active region in the IC layout diagram, as discussed below with respect to Operation 140.

[0039] In some embodiments, positioning the first active region in the IC layout diagram includes positioning the first active region in the IC layout diagram of the cell received in operation 110. In some embodiments, positioning the first active region in the IC layout diagram includes generating a new IC layout diagram of a cell and positioning a newly generated first active region in the newly generated IC layout diagram of the cell.

[0040] In some embodiments, positioning the first active region in the IC layout diagram includes positioning the first active region, which is determined by performing operation 120. In some embodiments, positioning the first active region in the IC layout diagram includes positioning an active region otherwise referred to as the first active region, e.g., based on a user input.

[0041] The first active region containing the first total number of fins is the first active region that has a predetermined total number of fins. The predetermined total number of fins contained in a given active region is based on various manufacturing layout criteria, such as a combination of IC feature sizes and circuit work performance specifications. In different embodiments, the predetermined total number of fins contained in the first active region is two, three, or four fins.

[0042] Positioning the first active region includes positioning the first active region that has a first height in the cell height direction. In some embodiments, positioning the first active region that has the first height includes that the first height corresponds to the first total number of fins.

[0043] In some embodiments, positioning the first active region, which has the first height, includes increasing the height of an active region of the IC layout diagram in operation 110 along the cell height direction. In some embodiments, positioning the first active region, which has the first height, includes defining the first height of a newly created first active region in a newly created IC layout diagram of the cell in the cell height direction.

[0044] In some embodiments, positioning the first active region involves positioning the first active region at a first distance from a first cell edge segment along the cell height direction. In some embodiments, positioning the first active region at the first distance from the first cell edge segment involves the first distance being greater than or equal to a first minimum distance rule. In some embodiments, the first minimum distance rule defines a minimum separation distance between an active region and a cell edge in a given manufacturing recipe. Positioning the first active region at the first distance from the first cell edge segment is discussed further below with reference to Operation 140.

[0045] Fig. Figure 2 depicts the IC layout diagram 200 of a cell 200C, which includes a border BR, a cell height CH in the Y direction, an active region AR1 containing fins F1-F3 extending in the X direction, an active region AR2 containing fins F4 and F5 extending in the X direction, and gate regions GR1 and GR2 extending in the Y direction and intersecting each of the active regions AR1 and AR2, thus defining at least one or more transistors (not labeled) of cell 200C. In different embodiments, active region AR1 is an active p-region and active region AR2 is an active n-region, or active region AR1 is an active n-region and active region AR2 is an active p-region. In different embodiments, cell 200C has a configuration, e.g., a logic gate, that includes one or more features, e.g., MD, vias, and / or conductive areas, in addition to those specified in Fig. 2 illustrated, which are not shown for illustrative purposes.

[0046] In some embodiments, positioning the first active area in the IC layout diagram, active area AR1, which contains three fins F1-F3 and has a height AH1 in the Y direction, is to be positioned at a distance D1 along the Y direction from a boundary segment B1 of boundary BR of cell 200C, as discussed below with reference to operation 140.

[0047] Fig. Figure 3 depicts the IC layout diagram 300 of a cell 300C, the boundary BR, active p-region AR1, the fins F1-F3 (in Fig. 3 not shown) contains, active n-area AR2, the fin F4 and F5 (in Fig. 3 not shown) contains, gate areas GRo-GR3, each intersecting the active area AR1 and AR2, MD areas MDR1-MDR5, via areas VR1-VR5 and conductive area M0R and M1R.

[0048] P-transistor P1 contains gate region GR1, the portion of active region AR1 superimposed on gate region GR1, and S / D regions (unlabeled) of active region AR1 adjacent to gate region GR1; p-transistor P2 contains gate region GR2, the portion of active region AR1 superimposed on gate region GR2, and S / D regions (unlabeled) of active region AR1 adjacent to gate region GR2; n-transistor N1 contains gate region GR1, the portion of active region AR2 superimposed on gate region GR1, and S / D regions (unlabeled) of active region AR2 adjacent to gate region GR1; and n-transistor N2 contains gate region GR2, the section of active region AR2 superimposed on gate region GR2, and S / D regions (unlabeled) of active region AR2 adjacent to gate region GR2.

[0049] Gate region GR1 overlays the active region section AR1 corresponding to transistor P1, the active region section AR2 corresponding to transistor N1, and via region VR2, partially defining an input node (not otherwise shown) configured to be electrically connected via a via defined by via region VR2. Gate region GR2 overlays the active region section AR1 corresponding to transistor P2, the active region section AR2 corresponding to transistor N2, and via region VR3, partially defining an input node (not otherwise shown) configured to be electrically connected via a via defined by via region VR3.

[0050] MD region MDR1 superimposes a signal-to-discharge (S / D) region of the active region AR1 between gate regions GR1 and GR2, and correspondingly transistor P1, thereby partially defining a conductive path (otherwise not shown) between transistor P1 and a mains voltage source (not shown). The S / D region of the active region AR1 between gate regions GR1 and GR2 is shared by transistors P1 and P2, thus defining a series connection between transistors P1 and P2.

[0051] The S / D region of active region AR1 between gate regions GR2 and GR3, and correspondingly transistor P2, is superimposed by MD region MDR2, via region VR1, and conductive region M1R. Conductive region M1R also superimposes via region VR5 and conductive region M0R, which in turn superimposes via region VR4, MD region MDR4, and the S / D region of active region AR2 between gate regions GR1 and GR2, which is shared by transistors N1 and N2. MD regions MDR2 and MDR4, via regions VR2, VR4, and VR5, and conductive regions M1R and M1R thus partially define an output node (otherwise not shown) containing transistors P2, N1, and N2, configured to be electrically connected by a metal segment defined by conductive region M1R.

[0052] MD region MDR3 superimposes an S / D region of the active region AR2 between gate regions GRo and GR1 and correspondingly transistor N1, thereby partially defining a conductive path (otherwise not shown) between transistor N1 and a mains voltage or ground reference (not shown). MD region MDR5 superimposes an S / D region of the active region AR2 between gate regions GR2 and GR3 and correspondingly transistor N2, thereby partially defining a conductive path (otherwise not shown) between transistor N2 and the mains voltage reference.

[0053] Through the in Fig. The configuration shown and discussed above corresponds to IC layout diagram 300 of cell 300C, a NOR gate containing gates of transistors P1 and N1 arranged as a first input, gates of transistors P2 and N2 arranged as a second input, transistors P1 and P2 connected in series between the mains voltage and the output node, and transistors N1 and N2 connected in parallel between the output node and the mains voltage reference.

[0054] In some embodiments, positioning the first active region in the IC layout diagram includes positioning active region AR1, which has height AH1, in cell 300C, as further discussed below with reference to Operation 140.

[0055] In Operation 140, a second active region is positioned along the cell height direction in the IC layout diagram, wherein the second active region is the other n-type or p-type and contains a second total number of fins that is less than the first total number of fins. In some embodiments, positioning of the second active region in the IC layout diagram is performed in conjunction with positioning of the first active region in the IC layout diagram, as discussed above with respect to Operation 130.

[0056] In some embodiments, positioning the second active region in the IC layout diagram includes positioning the second active region in the IC layout diagram of the cell received in operation 110. In some embodiments, positioning the second active region in the IC layout diagram includes positioning a newly created second active region in the IC layout diagram of the cell newly created in operation 130.

[0057] In some embodiments, positioning the second active region in the IC layout diagram includes positioning the second active region, which is determined together with the first active region by performing operation 120. In some embodiments, positioning the second active region in the IC layout diagram includes positioning an active region that is designated differently from the second active region, e.g., based on user input.

[0058] The second active area, containing the second total number of fins, includes a second active area with a predetermined total number of fins. The predetermined total number of fins contained in the second active area is less than the predetermined total number of fins contained in the first active area. In some embodiments, the difference between the predetermined number of fins in the first and second active areas is one. In other embodiments, the predetermined total number of fins contained in the second active area is one, two, or three fins.

[0059] Positioning the second active area includes positioning the second active area to have a second height in the cell height direction that is less than the first height of the first active area. In some embodiments, positioning the second active area to have the second height includes the second height corresponding to the second total number of fins.

[0060] In some embodiments, positioning the second active area, which has the second height, includes maintaining the height of an active area of ​​the IC layout diagram received in operation 110. In some embodiments, positioning the second active area, which has the second height, includes defining the second height in the cell height direction of a newly created second active area in the IC layout diagram of the cell newly created in operation 130.

[0061] In some embodiments, positioning the second active region involves positioning the second active region at a second distance along the cell height direction from a second cell border segment opposite to the first cell border segment. In some embodiments, positioning the second active region at the second distance from the second cell border segment involves the second distance being greater than or equal to the first minimum distance rule. In some embodiments, positioning the second active region at the second distance from the second cell border segment involves the second distance being equal to the first distance between the first active region and the first cell border segment discussed above with respect to Operation 130.

[0062] In some embodiments, one or both of the positioning of the first active region, as discussed in Operation 130, or the positioning of the second active region, includes separating the first and second active regions by a third distance along the cell height direction. In some embodiments, separating the first and second active regions by the third distance includes the third distance being greater than or equal to a second minimum distance rule. In some embodiments, the second minimum distance rule defines a minimum separation distance between adjacent active regions in a given manufacturing recipe.

[0063] In some embodiments, a combination of the first and second active regions, having the first and second heights respectively, includes positioning the first active region at the first distance from the first cell boundary segment, positioning the second active region at the second distance from the second cell boundary segment, and separating the first and second active regions by the third distance, such that the sum of the first and second heights and the first to third distances equals the height of the cell.

[0064] In some embodiments, positioning the second active area in the IC layout diagram involves positioning the active area AR2, which has height AH2 in the Y direction, corresponding to two fins F4 and F5, at a distance D1 along the Y direction from an edge segment B2 of edge BR in the IC layout diagram 200 of the Fig. 2 illustrated cell 200C. In some embodiments, positioning one or both of the first or the second active area includes positioning one or both of them separated from the active area AR1 or AR2 by a distance D2 along the Y-direction, such that the sum of height AH1 and AH2 and distance D1 (2x) and D2 equals that shown in Fig. The cell height shown in the image is CH.

[0065] In some embodiments, distance D1 and / or the first minimum distance rule have one or more values ​​ranging from 10 nanometers (nm) to 50 nm. In some embodiments, distance D1 and / or the first minimum distance rule have one or more values ​​ranging from 25 nm to 40 nm.

[0066] In some embodiments, distance D2 and / or the second minimum distance rule have one or more values ​​ranging from 20 nm to 120 nm. In some embodiments, distance D2 and / or the second minimum distance rule have one or more values ​​ranging from 50 nm to 100 nm.

[0067] In some embodiments, height AH1 has a value ranging from 30 nm to 100 nm. In some embodiments, height AH1 has a value ranging from 45 nm to 85 nm.

[0068] In some embodiments, height AH2 has a value ranging from 20 nm to 65 nm. In some embodiments, height AH2 has a value ranging from 35 nm to 50 nm.

[0069] In some embodiments, height CH has a value ranging from 100 nm to 400 nm. In some embodiments, height CH has a value ranging from 200 nm to 300 nm.

[0070] In the Fig. In the embodiment shown in Figure 2, distance D1 equals the first minimum distance rule, distance D2 is greater than or equal to the second minimum distance rule, and height AH1 is greater than height AH2 by a height difference DAH. In some embodiments, the height difference DAH has a value ranging from 5 nm to 50 nm. In other embodiments, the height difference DAH has a value ranging from 10 nm to 35 nm.

[0071] The height difference DAH thus represents a difference between distance D2 and a larger distance D2 + DAH, which would otherwise separate active area AR1 and AR2 if both active area AR1 and AR2 had height AH2 correspondingly two fins.

[0072] Conversely, if both active areas AR1 and AR2 were to have height AH1 correspondingly three fins, the height difference DAH would represent the difference between distance D2 and a shorter distance D2 - DAH, which would otherwise separate active areas AR1 and AR2. In the Fig. In the embodiment shown in Figure 2, the shorter distance D2 - DAH is less than the second minimum distance rule, so that positioning both active area AR1 and AR2, which have height AH1, in cell 200C is not possible without violating the first or second minimum distance rule and / or increasing cell height CH.

[0073] In the Fig. In the embodiment shown in Figure 2, the first and second minimum distance rules, height AH1 and AH2, cell height CH and distance D1 and D2 are related to each other such that for the given cell height CH, the total number of five fins (fins F1-F3 in the active area AR1 plus fins F4 and F5 in the active area AR2) is a maximum total number of fins capable of being contained in the area AR1 and AR2, which are positioned in operation 130 and 140 in IC layout diagram 200 of cell 200C.

[0074] In different embodiments, cells other than cell 200C are similarly based on minimum spacing rules and contain heights and distances configured such that, for a given cell height, the maximum total number of three, five, or seven fins can be contained in the first and second active areas, as positioned in operations 130 and 140 in IC layout diagrams of the cells.

[0075] In some embodiments, positioning the second active area in the IC layout diagram includes positioning the active area AR2, which has height AH2, in the IC layout diagram 300 of cell 300C, which is in Fig. Figure 3 is shown. Positioning the active area AR2, which has height AH2, in IC layout diagram 300 of cell 300v corresponds to both n-transistors N1 and N2 containing a total of two fins, and positioning the active area AR1, which has height AH1, in operation 130 in IC layout diagram 300 of cell 300C corresponds to both p-transistors P1 and P2 containing a total of three fins.

[0076] In the Fig. In the illustrated embodiment 3, p-transistors P1 and P2 are part of a time-critical path of the NOR gate, corresponding to IC layout diagram 300 of cell 300C. Transistors P1 and P2 are thus capable of exhibiting an increased drive current compared to approaches in which p-transistors of a NOR gate contain fewer fins. In some embodiments, the NOR gate, according to IC layout diagram 300 of cell 300C, exhibits a switching speed increase of 10-20% by including three fins in transistors P1 and P2, compared to an approach in which similarly arranged p-transistors contain two fins.

[0077] In different embodiments, IC layout diagrams of cells other than cell 300C corresponding to a NOR gate, e.g. cells corresponding to other NOR gate arrangements or NAND, OAI, AOI or other logic gates, are configured differently so that one or more transistors in a time-critical path are able to exhibit increased drive current compared with approaches in which the one or more transistors have relatively fewer fins.

[0078] In some embodiments of Operation 150, the third and fourth active regions are positioned within the cell along the cell height direction. Positioning the third active region involves positioning the third active region, which is of the same type as the second active region and contains a total number of fins equal to the total number of fins in the first active region. Positioning the fourth active region involves positioning the fourth active region, which is of the same type as the first active region and contains a total number of fins equal to the total number of fins in the second active region. Positioning the third and fourth active regions involves positioning the third active region between the second and fourth active regions.

[0079] Because the first and fourth active regions are of the same type, the second and third active regions are of the same type, the first and third active regions contain the same total number of fins, and the second and fourth active regions contain the same total number of fins, positioning the third and fourth active regions causes the IC layout diagram of the cell, in some embodiments, to have the same total number of fins of each type. In other embodiments, positioning the third and fourth active regions causes the IC layout diagram of the cell to have a total number of fins of each type of three, five, or seven.

[0080] In some embodiments, the IC layout diagram of the cell, which contains the third and fourth active regions positioned as discussed above, can be placed within an IC layout diagram containing fin tracks corresponding to the first to fourth active regions, e.g., an IC layout diagram 700 shown below in relation to method 400 and Fig. 4 and Fig. 7 will be discussed.

[0081] In some embodiments, operation 160 generates the IC layout diagram and stores it in a data storage device. The generation of the IC layout diagram is performed by a processor, e.g., processor 1102 of IC layout diagram generation system 1100, which is described below in relation to Fig. 11 is discussed. In some embodiments, generating the IC layout diagram includes generating some or all of IC layout diagram 1222, which is discussed below with respect to Fig. 12 will be discussed.

[0082] In different embodiments, storing the IC layout diagram in the data storage element includes storing the IC layout diagram in non-volatile, computer-readable memory or a cell library, e.g., a database, and / or storing the IC layout diagram over a network. In different embodiments, storing the IC layout diagram in the data storage element includes storing the IC layout diagram in cell library 1120 or over network 1114 from IC layout diagram generation system 1100, as described below with reference to Fig. 11 discussed.

[0083] In different embodiments, the generation and storage of the IC layout diagram includes one or more IC layout diagrams 200 or 300, which are described above in relation to Fig. 2 and Fig. 3 are discussed, or IC layout diagrams 500-800, which are below in relation to Fig. 4-8 will be discussed, generated and stored.

[0084] In some embodiments of Operation 170, at least one of one or more semiconductor masks, or at least one component in a layer of a semiconductor IC, is manufactured based on the IC layout diagram. The manufacturing of one or more semiconductor masks, or at least one component in a layer of a semiconductor IC, is described below with reference to IC manufacturing system 1200 and Fig. 12 discussed.

[0085] In different embodiments, the manufacturing of one or more semiconductor masks, or at least one component in the layer of the semiconductor IC, is based on one or more of the IC layout diagrams 200 or 300 shown above in relation to Fig. 2 and Fig. 3 are discussed, or IC layout diagrams 500-800, which are below in relation to Fig. 4-8 will be discussed.

[0086] In some embodiments, the fabrication of one or more semiconductor masks, or at least one component in the layer of the semiconductor IC, is part of a process 1000 for fabricating an IC structure, which is described below in relation to Fig. 10 will be discussed.

[0087] In some embodiments, Operation 180 involves performing one or more manufacturing operations based on the IC layout diagram. In some embodiments, performing one or more manufacturing operations includes performing one or more lithographic exposures based on the IC layout diagram. Performing one or more manufacturing operations, such as one or more lithographic exposures, based on the IC layout diagram is described below in relation to Fig. 12 discussed.

[0088] In different embodiments, the execution of one or more manufacturing operations is based on one or more of the IC layout diagrams 200 or 300 shown above in relation to Fig. 2 and Fig. 3 are discussed, or IC layout diagrams 500-800, which are below in relation to Fig. 4-8 will be discussed.

[0089] In some embodiments, performing one or more manufacturing operations is part of Method 1000 for manufacturing an IC structure, which is described below in relation to Fig. 10 will be discussed.

[0090] By performing some or all of the operations of Procedure 100, an IC layout diagram, e.g., one from IC Layout Diagram 200 or 300, is generated in which a cell contains at least one FinFET that has a larger number of fins than at least one other FinFET in the cell. For a given cell height, the different number of fins enables an increased driving capability of an interconnected IC device compared to approaches in which each FinFET in a cell contains the same number of fins. Furthermore, the relative increase in the total number of fins, and thus the driving capability, is achieved without increasing the cell area compared to approaches in which each FinFET in a cell contains the same number of fins.

[0091] Fig. Figure 4 is a flowchart of a method 400 for operating an IC manufacturing system in accordance with some embodiments. In some embodiments, operating the IC manufacturing system includes an IC layout diagram, e.g., an IC layout diagram 500-800, which is shown below in relation to Fig. 5-8 is discussed, according to an IC structure, e.g. IC structure 900, which is discussed below in relation to Fig. 9 is discussed, which is manufactured as part of an IC component based on the generated IC layout diagram.

[0092] In some embodiments, some or all of Method 400 is performed by a computer processor. In some embodiments, some or all of Method 400 is performed by processor 1102 of an IC layout diagram generation system 1100, as described below with reference to Fig. 11 discussed.

[0093] Some or all of the operations of Procedure 400 can be performed as part of a layout procedure carried out in a layout plant, e.g., in the one described below with respect to Fig. 12 discussed layout work 1220.

[0094] In some embodiments, the operation of method 400 is performed in the Fig. The operation of procedure 400 is carried out in the sequence shown in Figure 4. In some embodiments, the operation of procedure 400 is performed simultaneously and / or in a different order than that shown in Figure 400. Fig. 4 illustrated. In some embodiments, one or more operations are performed before, between, during and / or after performing one or more operations of procedure 400.

[0095] Fig. Figures 5-8 are illustrations of non-restrictive examples of corresponding IC layout diagrams 500-800, which in some embodiments are generated by performing one or more operations of Method 400 as discussed below. IC layout diagrams 500-800 are simplified for clarity. In different embodiments, one or more of the IC layout diagrams 500-800 include features in addition to those shown in Fig. 5-8 illustrated, e.g., one or more transistor elements, busbars, insulation structures, trays, conductive elements, or the like. Each of Fig. Figure 5-8 further illustrates the X and Y directions, which are shown above in relation to Fig. 2 and Fig. 3 have been discussed.

[0096] In Operation 410, a first plurality of fin tracks is arranged in a first subset, which has a first number of fin tracks corresponding to a first type, and a second subset, which has a second number of fin tracks corresponding to a second type, where the first number is greater than the second number.

[0097] Arranging the first plurality of fin tracks involves arranging the first plurality of fin tracks extending in a first direction in an IC layout diagram. Fin tracks are rows in the IC layout diagram that define, at least in part, potential positions of FinFET fins and correspond to active regions that can be used to define active p- or n-regions as described above in relation to Procedure 100 and Fig. 1-3 discussed to define.

[0098] In different embodiments, an arrangement of the first plurality of fin tracks includes the first subset, which has fin tracks according to the first type, being p-fins and the second subset, which has fin tracks according to the second type, being n-fins, or includes the first subset, which has fin tracks according to the first type, being n-fins and the second subset, which has fin tracks according to the second type, being p-fins.

[0099] In some embodiments, an arrangement of the first plurality of fin tracks includes the first number of fin tracks being one greater than the second number of fin tracks. In different embodiments, an arrangement of the first plurality of fin tracks includes the first subset having two, three, or four fin tracks. In different embodiments, an arrangement of the first plurality of fin tracks includes the second subset having one, two, or three fin tracks.

[0100] In some embodiments, arranging the first plurality of fin tracks includes arranging the first plurality of fin tracks according to a first row of cells in the IC layout diagram.

[0101] In some embodiments, an arrangement of the first plurality of fin tracks includes fin tracks FT1-FT5, which are arranged in the X direction in IC layout diagram 500, which is shown in Fig. 5 is shown, and / or IC layout diagram 700, which is in Fig. Figure 7 is shown. The arrangement of fin tracks FT1-FT5 includes arranging fin tracks FT1-FT5 in first and second subsets according to a subset S11, the first of which has three fin tracks FT1-FT3, and a subset S12, the second of which has two fin tracks FT4 and FT5. In different embodiments, subset S11 corresponds to the first type being p-fins, and subset S12 corresponds to the second type being n-fins, or subset S11 corresponds to the first type being n-fins, and subset S12 corresponds to the second type being p-fins. The arrangement of fin tracks FT1-FT5 includes arranging fin tracks FT1-FT5 according to a series R1 having a cell height CH, as above with respect to Fig. 1-3 have been discussed.

[0102] Operation 420 involves arranging a second plurality of fin tracks extending in the first direction in a second subset containing the first number of fin tracks of the second type, and a second subset containing the second number of fin tracks of the first type. Arranging the second plurality of fin tracks involves arranging the second plurality of fin tracks in the IC layout diagram.

[0103] In some embodiments, arranging the second plurality of fin tracks involves arranging the second plurality of fin tracks according to a second row of cells in the IC layout diagram.

[0104] In some embodiments, an arrangement of the second plurality of fin tracks includes arranging fin tracks FT6-FT10, which are oriented in the X-direction in the Fig. 5 IC layout diagram 500 and / or in the Fig. The IC layout diagram 700 shown in section 7 is extended. Arranging fin tracks FT6-FT10 involves arranging fin tracks FT6-FT10 in a first and a second subset corresponding to a subset S21, which has the first number equal to three fin tracks FT6-FT8, and a subset S22, which has the second number equal to two fin tracks FT9 and FT10. Subset S21 corresponds to the second fin type of subset S12, and subset S22 corresponds to the first fin type of subset S11. Arranging fin tracks FT6-FT10 involves arranging fin tracks FT6-FT10 according to a row R2, which has a cell height CH.

[0105] In operation 430, the second subset of the first plural of fin tracks is adjacent to the first subset of the second plural of fin tracks. Attaching the second subset of the first plural of fin tracks to the first subset of the first plural of fin tracks involves positioning a fin track of the second subset of the first plural of fin tracks adjacent to a fin track of the first subset of the second plural of fin tracks along a second direction perpendicular to the first direction. In some embodiments, attaching the second subset of the first plural of fin tracks to the first subset of the second plural of fin tracks involves attaching the first row to the second row.

[0106] Applying the second subset of the first plural of fin tracks to the first subset of the second plural of fin tracks implies that an area in the IC layout diagram between the first and second plural of fin tracks is free of any fin track. In different embodiments, applying the second subset of the first plural of fin tracks to the first subset of the second plural of fin tracks implies that the area in the IC layout diagram between the first and second plural of fin tracks contains one or more features, e.g., a conductive area corresponding to a busbar or a MD area other than a fin track.

[0107] In some embodiments, applying the second subset of the first plurality of fin tracks to the first subset of the second plurality of fin tracks, applying subset S12 to subset S21, and connecting row R1 to row R2 by positioning fin track FT5, which borders fin track FT6, along the Fig. 5 and Fig. to create the Y-direction shown in 7.

[0108] In some embodiments, applying the second subset of the first plural of fin tracks to the first subset of the second plural of fin tracks includes applying the second subset of the second plural of fin tracks to a first subset of an additional plural of fin tracks along the second direction, wherein the additional plural of fin tracks has the same configuration as the first plural of fin tracks.

[0109] In some embodiments, applying the second subset of the first plural of fin tracks to the first subset of the second plural of fin tracks includes applying a second subset of an additional plural of fin tracks to the first subset of the first plural of fin tracks along the second direction, wherein the additional plural of fin tracks has the same configuration as the second plural of fin tracks.

[0110] In some embodiments, applying the second subset of the first plural of fin tracks to the first subset of the second plural of fin tracks includes applying the first and second plural of fin tracks to one or more additional first and second plurals of fin tracks along the second direction, thereby arranging the first and second plurals of fin tracks within a pattern of repeated plurals of first and second fin tracks.

[0111] In some embodiments of Operation 440, a third plurality of fin tracks is aligned with one of the first plurality of fin tracks or the second plurality of fin tracks along the first direction. Aligning the third plurality of fin tracks involves aligning the third plurality of fin tracks, which comprises a first subset having the second number of fin tracks and being of the same type as the first subset of the first or second plurality of fin tracks, and a second subset having the second number of fin tracks and being of the same type as the second subset of one of the first or second plurality of fin tracks.

[0112] Aligning the third plural of fin tracks involves aligning each fin track of the first clause of the third plural of fin tracks with a corresponding fin track of the first clause of one of the first or the second plural of fin tracks along the first direction, and aligning each fin track of the second clause of the third plural of fin tracks with a corresponding fin track of the second clause of one of the first or the second plural of fin tracks along the first direction.

[0113] Because the first clause of the third plural of Finnish tracks has a second number of Finnish tracks lower than the first number of Finnish tracks of the first clause of either the first or second plural of Finnish tracks, at least one Finnish track of the first clause of either the first or second plural of Finnish tracks is not aligned with a Finnish track of the first clause of the third plural of Finnish tracks along the first direction. Aligning the first clause of the third plural of Finnish tracks therefore involves creating a Finnish track discontinuity between the first clauses of the third plural of Finnish tracks and either the first or second plural of Finnish tracks.

[0114] In embodiments where the first number of fin tracks is one greater than the second number of fin tracks, generating the fin track discontinuity includes generating the fin track discontinuity based on a single fin track of the first subset of one of the first or second plurality of fin tracks that is not aligned with a fin track of the first subset of the third plurality of fin tracks along the first direction. In some embodiments, generating the fin track discontinuity includes generating the fin track discontinuity based on more than one fin track of the first subset of one of the first or second plurality of fin tracks that is not aligned with a fin track of the first subset of the third plurality of fin tracks along the first direction.

[0115] In some embodiments, aligning the third plural of fin tracks involves separating the third plural of fin tracks from one of the first or second plural of fin tracks by a gap. Separating the third plural of fin tracks from one of the first or second plural of fin tracks by the gap corresponds to the fin track discontinuity between the first subsets of one of the first or second plural of fin tracks and the third plural of fin tracks. In some embodiments, separating the third plural of fin tracks from one of the first or second plural of fin tracks by the gap is part of complying with one or more manufacturing recipe rules based on the fin track discontinuity.

[0116] In some embodiments, the gap has a value ranging from 20 nm to 150 nm. In some embodiments, the gap has a value ranging from 50 nm to 100 nm.

[0117] In some embodiments, aligning the third plural of fin tracks includes fin tracks FT11-FT14 with fin tracks FT1-FT5 along the X-direction in the Fig. 5 IC layout diagram 500 and / or in Fig. To align the IC layout diagram 700 shown in Figure 7. Aligning fin tracks FT11-FT14 involves aligning fin tracks FT11-FT14, which have first and second subsets, corresponding to a subset S31, which has the second number of two fin tracks FT11 and FT12 of the same type as subset S11, and a subset S32, which has the second number of two fin tracks FT13 and FT14 of the same type as subset S12.

[0118] Aligning subset S31 with subset S11 involves aligning fin track FT11 with fin track FT1 along the X-direction and aligning fin track FT12 with fin track FT2 along the X-direction. Aligning subset S32 with subset S12 involves aligning fin track FT13 with fin track FT4 along the X-direction and aligning fin track FT13 with fin track FT5 along the X-direction. Because subset S11 has the first number of three fin tracks greater than the first number of two fin tracks in subset S31, fin track FT3 is not aligned with any fin track in subset S31 along the X-direction. Aligning fin tracks FT11-FT14 with fin tracks FT1-FT5 creates a fin track discontinuity between subset S11 and S31 at a gap G1.

[0119] In the non-restrictive example, which is in Fig. 5 and Fig. Figure 7 illustrates that fin track FT3 is not aligned with a fin track of subset S31, which corresponds to fin track FT3 being aligned along the X-direction with a space between subset S31 and S32. In different embodiments, the fact that a given fin track of the first subset of one of the first or second plurality of fin tracks is not aligned along the first direction with a fin track of the first subset of the third plurality of fin tracks, e.g., fin track FT3 is not aligned with a fin track of subset S31 along the X-direction, corresponds to the fact that the given fin track along the first direction is aligned with a space other than a space between the first and second subset of the third plurality of fin tracks.a space between adjacent fin tracks of the first clause of the third plural of fin tracks or a space outside a space occupied by the first and second clauses of the third plural of fin tracks.

[0120] In some embodiments, aligning the third plurality of fin tracks with one of the first plurality of fin tracks or the second plurality of fin tracks along the first direction includes aligning the third plurality of fin tracks with the first plurality of fin tracks along the first direction and aligning a fourth plurality of fin tracks with the second plurality of fin tracks along the first direction, wherein both the third and fourth plurality of fin tracks have the same configuration as discussed above.

[0121] In some embodiments, the first and second plural fin tracks are arranged in a pattern of repeated plurals of first and second fin tracks, the third plural fin tracks is one of several third plurals of fin tracks configured as above, and aligning the third plural fin tracks involves aligning each of the several third plurals of fin tracks with different plurals of first and second fin tracks along the first direction.

[0122] In some embodiments of Operation 450, a cell is aligned with one of the first plurality of fin tracks, the second plurality of fin tracks, or the third plurality of fin tracks based on a cell type. This involves aligning the cell containing one of the first, second, or third plurality of fin tracks with the fin track arrangement of one of the first, second, or third plurality of fin tracks along the first direction.

[0123] In some embodiments, the cell contains a fin configuration that is free from containing a fin, and aligning the cell with one of the first, second or third plurality of fin tracks to align the cell in the gap between the third plurality of fin tracks and one of the first or second plurality of fin tracks.

[0124] In some embodiments, aligning the cell with one of the first, second, or third plurality of fin tracks, based on the cell type, includes placing the cell in the IC layout diagram containing the first, second, and / or third plurality of fin tracks. In some embodiments, placing the cell in the IC layout diagram becomes part of an automated placement and routing (APR) procedure, as discussed above.

[0125] In some embodiments, aligning the cell with one of the first, second, or third plurality of fin tracks includes receiving an IC layout diagram of the cell. In some embodiments, receiving the IC layout diagram of the cell includes receiving the IC layout diagram of the cell from a cell library, as described above in relation to Method 100 and Fig. 1 discussed.

[0126] In some embodiments, aligning the cell with one of the first, second, or third plurality of fin tracks includes receiving one or more IC layout diagrams 200 or 300 and aligning one or more of cells 200C or 300C, each above with respect to Fig. 1-3 discussed. In some embodiments, aligning the cell with one of the first, second or third plurality of fin tracks involves generating one or more cells, e.g. one or more of cells 200C or 300C.

[0127] In some embodiments, aligning the cell with one of the first, second, or third plurality of fin tracks includes one or more of cells 600A-600D of a Fig. To align the IC layout diagram 600 shown in Figure 6. In the diagram shown in Fig. In the embodiment shown in Figure 6, IC layout diagram 600 contains each of cells 600A-600D. In different embodiments, IC layout diagram 600 contains a subset of cells 600A-600D and / or one or more cells (not shown) in addition to cells 600A-600D.

[0128] As in Fig. As shown in Figure 6, each of the cells 600A-600D has a cell height of CH, which is shown above in relation to Fig. 2 and Fig. As discussed in section 5, cell 600A is free of any fin configuration and therefore has a total number of fins equal to zero. Cell 600B has a fin configuration consisting of a first set of two p-fins FP1 and FP2 and a second set of two n-fins FN1 and FN2. Cell 600C has a fin configuration consisting of a first set of three p-fins FP1-FP3 and a second set of two n-fins FN1 and FN2. Cell 600D has a fin configuration consisting of a first set of two p-fins FP1 and FP2 and a second set of three n-fins FN1-FN3.

[0129] In some embodiments, an alignment of the cell with one of the first, second or third plurality of fin tracks includes cells 600A-600D with pluralitys of fin tracks FT1-FT5, FT6-FT10 and FT11-FT14 corresponding to rows R1 and R2, which are described above in relation to Fig. 5 are discussed, in the Fig. To align the IC layout diagram 700 shown in Figure 7. In the diagram shown in Fig. In the embodiment shown in Figure 7, each of subsets S11, S22 and S31 corresponds to the p-type and each of subsets S12, S21 and S32 corresponds to the n-type.

[0130] In the Fig. In the embodiment shown in Figure 7, aligning cell 600A is based on the fact that cell 600A has zero fins and involves placing cell 600A in gap G1 between fin tracks FT1-FT5 and fin tracks FT11-FT14, thereby placing cell 600A in row R1. Aligning cell 600B involves aligning p-fins FP1 and FP2 with their respective p-fin tracks FT11 and FT12, and aligning n-fins FN1 and FN2 with their respective n-fin tracks FT13 and FT14, thereby placing cell 600B in row R1. Aligning cell 600C involves aligning p-fins FP1-FP3 with their respective p-fin tracks FT1-FT3 and aligning n-fins FN1 and FN2 with their respective n-fin tracks FT4 and FT5, thereby placing cell 600C in row R1.

[0131] Based on the configuration of cell 600D, aligning cell 600D involves reversing cell 600D with respect to the Y direction, thereby aligning n-fins FN3-FN1 with their respective fin tracks FT6-FT8 and p-fins FP2 and FP1 with their respective p-fin tracks FT9 and FT10, thus placing cell 600D in row R2.

[0132] In the Fig. The embodiments illustrated in Figure 7 include aligning the cell with one of the first, second, or third plurality of fin tracks, and further, aligning a cell 710 with fin tracks FT1-FT10 according to the first and second plurality of fin tracks. Cell 710 has a configuration comprising a height (not specified) equal to or twice the cell height CH, a first subset of three p-fins FP1-FP3, a second subset of n-fins FN1 and FN2, a third subset of three n-fins FN3-FN5, and a fourth subset of two p-fins FP4 and FP5.

[0133] Aligning cell 710 with the first and second plural fin tracks involves aligning p-fins FP1-FP3 with their respective p-fin tracks FT1-FT3, aligning n-fins FN1 and FN2 with their respective n-fin tracks Ft4 and FT5, aligning n-fins FN3-FN5 with their respective fin tracks FT6-FT8, and aligning p-fins FP4 and FP5 with their respective p-fin tracks FT9 and FT10, thereby placing cell 710 in rows R1 and R2. Thus, aligning cell 710 with the first and second plural fin tracks involves aligning cell 710 to have the same total number (five) of p-fins and n-fins.

[0134] As through the in Fig. As illustrated in Figure 7, a non-restrictive example, in some embodiments the cell is a cell of a plurality of cells, and aligning the cell with one of the first, second, or third plurality of fin tracks aligns one or more cells of the plurality of cells with the corresponding one or more of the first, second, or third plurality of fin tracks. In different embodiments, the plurality of cells contains subsets corresponding to each of one or more fin configurations having zero or one or more fins, and aligning the one or more cells of the plurality of cells aligns each subset with one of the corresponding one or more plurality of fin tracks arranged as discussed above, thereby placing the plurality of cells in the IC layout diagram.

[0135] In some embodiments, the fin configuration of a given cell, e.g., one of cells 600B-600D or 710, corresponds to a cell type based on time criteria, as above in relation to method 100 and Fig. 1-3 discussed, and an alignment of the given cell with one of the first, second or third plurality of fin tracks is therefore based on the cell type and the time criteria.

[0136] In some embodiments, placing the majority of cells in the IC layout diagram includes placing the majority of cells in the Fig. to place the IC layout diagram 800 shown in Figure 8. IC layout diagram 800 contains continuous regions 810, 830, 840, and 860, and gaps 820 and 850. Continuous regions 810 and 830 have different fin track arrangements, so a fin track discontinuity is created at gap 820 as discussed above, and continuous regions 840 and 860 have different fin track arrangements, so a fin track discontinuity is created at gap 850.

[0137] In the Fig. The embodiment shown in Figure 8 includes placing the plurality of cells in IC layout diagram 800, placing a first subset of the plurality of cells in the continuous area 810 based on the fin configuration of the first subset, which is matched with the fin track arrangement of the continuous area 810, placing a second subset of the plurality of cells in the continuous area 830 based on the fin configuration of the second subset, which is matched with the fin track arrangement of the continuous area 830, placing a third subset of the plurality of cells in the continuous area 840 based on the fin configuration of the third subset, which is matched with the fin track arrangement of the continuous area 840, and placing a fourth subset of the plurality of cells in the continuous area 860 based on the fin configuration of the fourth subset.which is aligned with the fin track arrangement of the continuous area 860, and to place a fifth subset of the plurality of cells in columns 820 and 850 based on the fifth subset which has a fin configuration containing zero fins.

[0138] In some embodiments, some or all of the following, aligning the cell with one of the first plurality of fin tracks, the second plurality of fin tracks, or the third plurality of fin tracks based on a cell type, comprising placing the plurality of cells in the IC layout diagram, is part of an APR procedure performed by an APR system. In some embodiments, the APR procedure further comprises some or all of operations 410 to 430.

[0139] In different embodiments, the APR method includes one or a combination of a constructive algorithm, an iterative algorithm, or an integrated algorithm. In a constructive algorithm, placement and routing operations are performed on a cell-by-cell basis. After an IC layout diagram has been updated to include the placement of a given cell and its associated routing connections, an additional layout diagram revision includes the placement of an additional cell and its associated routing connections. In an iterative algorithm, an initial IC layout diagram containing multiple cells and associated routing connections is iteratively analyzed and corrected based on circuit work performance and trade-off criteria.In an integrated algorithm, circuit work performance and compromise criteria are applied when an IC layout diagram is revised to include the placement of a given cell and / or its forward connections.

[0140] In different embodiments, method 400 includes one or more of operations 160-180, each described above in relation to method 100 and Fig. 1 have been discussed.

[0141] By performing some or all of the operations of Procedure 400, an IC layout diagram, e.g., one of IC layout diagrams 500-800, is generated in which multiple fin tracks are arranged to support the placement of a variety of cells, including those with FinFETs having different numbers of fins. IC layout diagrams containing multiple fin tracks thus enable the fabrication of IC devices that incorporate the increased driving capability of cells with FinFETs having different numbers of fins, compared to approaches that do not include fin track arrangements configured to support the placement of cells with FinFETs having different numbers of fins.

[0142] Furthermore, in the different embodiments, by performing some or all of the operations of Method 400, IC layout diagrams are generated in which the multiples of fin tracks support cell placement in addition to those with FinFETs having different numbers of fins, e.g., cells 600B and / or 710. The corresponding cell placement operation and resulting IC layout diagrams thus efficiently integrate the cells containing FinFETs with different numbers of fins with those containing FinFETs with the same number of fins.

[0143] Fig. Figure 9 is a diagram of an IC structure 900 in accordance with some embodiments. IC structure 900 is formed by performing some or all of the operations of methods 100 and / or 400 and is configured in accordance with one or more of the IC layout diagrams 200, 300, or 500-800, which are described above in relation to Fig. 1-8 are discussed. In some embodiments, IC structure 900 is formed in accordance with method 1000 for the fabrication of IC structure, which is described below in relation to Fig. 10 will be discussed.

[0144] The illustration of IC structure 900 in Fig. 9 has been simplified for the sake of clarity. Fig. Figure 9 shows a top view of IC structure 900 with various features included and excluded to facilitate the discussion below. Fig. Figure 9 further depicts the X and Y directions, which are shown above in relation to Fig. 2 and Fig. 3 have been discussed.

[0145] As in Fig. Figure 9 shows structure 900 containing multiples of fins PF1-PF6 located on a substrate 900S, and an IC device 900D containing multiples of fins PF1-PF6. In some embodiments, IC structure 900 does not contain IC device 900D.

[0146] Each plurality of fins PF1-PF6 contains one or more p- or n-fins extending in the X-direction in an active region (not shown) in substrate 900S and in accordance with a FinFET fabrication process as above in relation to process 100 and Fig. 1-3 are configured as discussed.

[0147] Plural of fins PF1 is a first plural of fins of a first type of n-type or p-type and corresponds to the first subset of the first plural of fin tracks, e.g. subset S11, which contains fin tracks FT1-FT3, which are referred to above in relation to procedure 4 and Fig. 4-7 are discussed. Plural of fins PF2 is a second plural of fins of a second type of n-type or p-type, is parallel to and adjacent to the plural of fins PF1, and corresponds to the second sub-clause of the first plural of fin tracks, e.g., sub-clause S12, which contains the fin tracks FT4 and FT5 discussed above. Plural of fins PF3 is a third plural of fins of the second type, is parallel to and adjacent to the second plural of fins, and corresponds to the first sub-clause of the second plural of fins, e.g., sub-clause S21, which contains the fin tracks FT6-FT8 discussed above. Plural of fins PF4 is a fourth plural of fins of the first type, is parallel to and adjacent to the third plural of fins, and corresponds to the second sub-clause of the second plural of fin tracks, e.g., sub-clause S22, which contains the fin tracks FT9 and FT10 discussed above.

[0148] The majority of fins PF1 and the majority of fins PF3 have the same first number of fins, the majority of fins PF2 and the majority of fins PF4 have the same second number of fins, and the first number is larger than the second number. In the Fig. In the embodiment shown in Figure 9, the first number of fins is three and the second number of fins is two. In different embodiments, one or both of the first or the second number of fins have values ​​other than three and four, respectively, in accordance with the embodiments discussed in relation to Method 400.

[0149] In the Fig. In the embodiment shown in Figure 9, IC structure 900 contains a plurality of fins PF5 and PF6. In some embodiments, IC structure 900 contains neither or neither of the plurality of fins PF5 or PF6. The plurality of fins PF5 is a fifth plurality of fins of the first type and has the second number of fins. The plurality of fins PF5 corresponds to the first subset of the third plurality of fin tracks, e.g., subset S31, which contains fin tracks FT11 and FT12, discussed above and accordingly aligned with a subset of the first plurality of fins PF1 and separated from the plurality of fins PF1 by a fin discontinuity area 900G corresponding to gap G1, which is described above with respect to Fig. 5 and Fig. 7 is discussed. Plural of fins PF6 is a sixth plural of fins of the second type, parallel to and adjacent to the fifth plural of fins and corresponds to the second subset of the third plural of fin tracks, e.g. subset S32, which contains fin track FT13 and FT14, which are discussed above.

[0150] In some embodiments, IC structure 900 includes one or more pluralityes of fins (not shown) in addition to the plurality of fins PF1-PF4, and in some embodiments, pluralityes of fins PF5 and PF6. In some embodiments, plurality of fins PF1-PF4 is arranged in a repeating pattern of pluralityes of fins in accordance with the discussion above regarding method 400 and Fig. 4-8 included.

[0151] IC component 900D is an IC component that incorporates IC structure 900 and one or more IC features, e.g., one or more FinFETs containing one or more gates, in accordance with one or both of procedure 100 and IC layout diagrams 200 and 300, which are described above in relation to Fig. 1-3 are discussed, or procedures 400 and IC layout diagrams 500-800, which are discussed above in relation to Fig. The details discussed in sections 4-8 are configured. Details of the IC 900D component are in... Fig. Figure 9 is not shown for illustrative purposes.

[0152] Fig. Figure 10 is a flowchart of a process 1000 for manufacturing an IC structure in accordance with some embodiments.

[0153] Method 1000 is operational to form an IC structure, e.g., IC structure 900, which is described above in relation to Fig. 9 is discussed. In some embodiments, method 1000 can be used by an IC manufacturing system as part of an IC manufacturing process, e.g., IC manufacturing system 1200, which is discussed below in relation to Fig. 12 will be discussed.

[0154] The sequence in which the operation of procedure 1000 in Fig. The figures shown in 10 are for illustrative purposes only; the operation of procedure 1000 can be performed simultaneously and / or in sequences that differ from the one shown in Fig. The 10 illustrated operations differ and are performed. In some embodiments, operations are performed in addition to those shown. Fig. 10 depicted before, between, during and / or after the in Fig. The 10 illustrated operations were performed.

[0155] In Operation 1010, the first to fourth parallel and adjacent plurals of fins are formed. In some embodiments, images of the first to fourth parallel and adjacent plurals of fins correspond to plurals of fins PF1-PF4, which are shown above in relation to Fig. 9 have been discussed, to form.

[0156] Forming a plurality of fins, e.g., one or more of the plurality of fins PF1-PF4, involves using one or more suitable processes, e.g., photolithography and / or etching processes. In some embodiments, the photolithography process involves forming a photoresist layer superimposed on a substrate, e.g., substrate 900S, wherein the photoresist layer is exposed with a pattern, a baking process is performed after exposure, and the photoresist layer is developed to form a masking element containing the photoresist layer. In some embodiments, the masking element is used to protect predetermined areas of the substrate, while an etching process, e.g., reactive ion etching, is used to form depressions in the substrate, leaving an extending fin.

[0157] In operation 1020, in some embodiments, the fifth and sixth plurals of fins are aligned with the first and second or third and fourth plurals of fins. In some embodiments, forming the fifth and sixth plurals of fins corresponds to forming a plural of fins PF5 and PF6, as described above in relation to Fig. 9 have been discussed.

[0158] In some embodiments, Operation 1030 involves constructing an IC device containing the first to fourth plurality of fins. In some embodiments, the construction of the IC device includes constructing IC device 900D, which is described above in relation to Fig. 9 is discussed.

[0159] The operations of procedure 1000 can be used to form an IC structure, e.g. IC structure 900, which contains first to fourth plurals of finites arranged in accordance with procedure 400 and is thereby configured to have the properties and thus advantages discussed above in relation to procedures 100 and 400.

[0160] Fig. Figure 11 is a block diagram of IC layout diagram generation system 1100 in accordance with some embodiments. In some embodiments, IC layout diagram generation system 1100 includes electronic layout automation (EDA). In some embodiments, IC layout diagram generation system 1100 includes or is part of an APR system. Methods described herein for generating IC layout diagrams representing fin arrangements, in accordance with one or more embodiments, can be implemented, for example, by IC layout diagram generation system 1100 in accordance with some embodiments.

[0161] In some embodiments, the IC layout diagram generation system 1100 is a general-purpose computing device comprising a processor 1102 and a non-transitory, computer-readable data storage medium 1104. The computer-readable data storage medium 1104 is, among other things, encoded with, i.e., stored with, computer program code 1106, i.e., a set of executable instructions. The execution of instructions 1106 by the processor 1102 constitutes (at least in part) an IC layout diagram generation tool that implements a section or all of, for example, method 100, described above with respect to Fig. 1 discussed, and / or procedure 400, which refers above to Fig. 4 is discussed, (the processes and / or procedures mentioned below).

[0162] Processor 1102 is electrically coupled to computer-readable storage medium 1104 via a bus 1108. Processor 1102 is also electrically coupled to an I / O interface 1110 via bus 1108. A network interface 1112 is also electrically connected to processor 1102 via bus 1108. Network interface 1112 is connected to a network 1114 such that processor 1102 and computer-readable storage medium 1104 are able to connect to external elements via network 1114. Processor 1102 is configured to execute computer program code 1106, which is encoded in computer-readable storage medium 1104, in order to cause IC layout diagram generation system 1100 to be usable for carrying out a section or all of the aforementioned processes and / or procedures.In one or more embodiments, processor 1102 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC) and / or a suitable processing unit.

[0163] In one or more embodiments, computer-readable data storage medium 1104 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or such a device or component). For example, computer-readable data storage medium 1104 includes a semiconductor or solid-state memory, a magnetic tape, a removable computer disk, random access memory (RAM), read-only memory (ROM), a rigid magnetic data carrier, and / or an optical data carrier. In one or more embodiments using optical data carriers, computer-readable data storage medium 1104 includes a compact disk read-only memory (CD-ROM), a compact disk read / write (CD-R / W), and / or a digital video disc (DVD).

[0164] In one or more embodiments, computer-readable data storage medium 1104 stores computer program code 1106, which is configured to cause IC layout diagram generation system 1100 (where such embodiment constitutes (at least in part) the IC layout diagram generation tool) to be usable for carrying out a portion or all of the processes and / or procedures mentioned. In one or more embodiments, computer-readable data storage medium 1104 also stores information that facilitates the carrying out of a portion or all of the processes and / or procedures mentioned. In one or more embodiments, computer-readable data storage medium 1104 stores a library 1120 of standard cells containing IC layout diagrams as disclosed herein, e.g., one or more of IC layout diagrams 200, 300, or 500-800, which are described above in relation to Fig. 1-8 are discussed. In one or more embodiments, a computer-readable data storage medium 1104 stores one or more fin track arrangements 1122 as disclosed herein, e.g. above with reference to method 400 and Fig. 4-8 discussed.

[0165] The IC layout diagram generation system 1100 includes an I / O interface 1110. The I / O interface 1110 is coupled to an external circuit. In one or more embodiments, the I / O interface 1110 includes a keyboard, keypad, mouse, trackball, touchpad, touchscreen, and / or pointer direction keys for communicating information and commands to the processor 1102.

[0166] The IC layout diagram generation system 1100 also includes a network interface 1112, which is coupled to a processor 1102. Network interface 1112 allows the IC layout diagram generation system 1100 to communicate with a network 1114, to which one or more other computer systems are connected. Network interface 1112 includes wireless network interfaces such as Bluetooth, Wi-Fi, WiMAX, GPRS, or WCDMA; or wired interfaces such as Ethernet, USB, or IEEE-1364. In one or more embodiments, a section or all of the aforementioned processes and / or methods are implemented in two or more IC layout diagram generation systems 1100.

[0167] The IC layout diagram generation system 1100 is configured to receive information through I / O interface 1110. The information received through I / O interface 1110 contains one or more instructions, data, layout rules, libraries of standard cells, and / or other parameters for processing by processor 1102. The information is transferred to processor 1102 via bus 1108. The IC layout diagram generation system 1100 is also configured to receive user interface (UI) information through I / O interface 1110.

[0168] In some embodiments, a section or all of the processes and / or methods mentioned are implemented as a standalone software application for execution by a processor. In some embodiments, a section or all of the processes and / or methods mentioned are implemented as a software application that is part of an additional software application. In some embodiments, a section or all of the processes and / or methods mentioned are implemented as an extension to a software application. In some embodiments, at least one of the processes and / or methods mentioned is implemented as a software application that is a section of an EDA tool. In some embodiments, a section or all of the processes and / or methods mentioned are implemented as a software application used by IC Layout Diagram Generation System 1100.In some embodiments, a layout diagram containing standard cells is generated using a tool such as VIRTUOSO®, available from CADENCE DESIGN SYSTEMS Inc., or another suitable layout generation tool.

[0169] In some embodiments, the processes are implemented as functions of a program stored in a non-transitory, computer-readable recording medium. Examples of a non-transitory, computer-readable recording medium include, but are not limited to, external / removable and / or internal / built-in data storage or memory unit, e.g., one or more optical media such as a DVD, magnetic media such as a hard drive, semiconductor memory such as a ROM, RAM, memory card, and the like.

[0170] Fig. Figure 12 is a block diagram of IC fabrication system 1200 and an associated IC fabrication process in accordance with some embodiments. In some embodiments, based on a layout diagram, at least one of (A) one or more semiconductor masks or (B) at least one component in a layer of a semiconductor integrated circuit is fabricated using fabrication system 1200.

[0171] In Fig. System 1200 comprises IC manufacturing system 1200 entities, such as a layout plant 1220, a masking plant 1230, and an IC manufacturer / fabricator (“Fab”) 1250, which interact with each other in the layout, development, and manufacturing cycles and / or services related to the manufacture of an IC component 1260. The entities in system 1200 are connected by a communication network. In some embodiments, the communication network is a single network. In other embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more of the other entities, providing services to and / or receiving services from one or more of the other entities.In some embodiments, two or more of the Layout Plant 1220, Masking Plant 1230, and IC-Fab 1250 are owned by a single larger company. In some embodiments, two or more of the Layout Plant 1220, Masking Plant 1230, and IC-Fab 1250 exist side-by-side in a common facility and use common resources.

[0172] Layout work (or layout team) 1220 generates an IC layout diagram 1222. IC layout diagram 1222 contains various geometric patterns, e.g., one or more from IC layout diagrams 200, 300, or 500-800, which are described above in relation to Fig. 1-8 are discussed, designed for an IC component 1260, e.g. an IC component containing IC structure 900, which is discussed above in relation to Fig. 9 and Fig. 10 is discussed. The geometric patterns correspond to patterns of metal, oxide, or semiconductor layers that form the different components of the IC device 1260 to be manufactured. The different layers are combined to form different IC features. For example, a section of IC layout diagram 1222 contains different IC features, such as an active area, gate electrode, source and drain, metal traces or vias of an interlayer interconnect, and openings for bonding pads to be formed in a semiconductor substrate (such as a silicon wafer), and different material layers deposited on the semiconductor substrate. Layout work 1220 implements a suitable layout procedure to form IC layout diagram 1222. The layout procedure includes one or more logic layouts, physical layouts, or location and path considerations.IC Layout Diagram 1222 exists in one or more data files containing information about the geometric patterns. For example, IC Layout Diagram 1222 can be expressed in a GDSII or DFII file format.

[0173] Masking Unit 1230 includes Data Preparation Unit 1232 and Mask Production Unit 1244. Masking Unit 1230 uses IC Layout Diagram 1222 to produce one or more masks 1245, which are used to fabricate the different layers of IC component 1260 according to IC Layout Diagram 1223. Masking Unit 1230 performs Mask Data Preparation Unit 1232, where IC Layout Diagram 1222 is translated into a Representative Data File (RDF). Mask Data Preparation Unit 1232 provides the RDF to Mask Production Unit 1244. Mask Production Unit 1244 includes a mask writer. A mask writer converts the RDF into an image on a substrate, such as a mask (crosshair) 1245 or a semiconductor wafer 1253. The layout diagram 1222 is manipulated by mask data preparation 1232 to meet certain properties of the mask writer and / or requirements of IC-Fab 1250. Fig.Figure 12 illustrates mask data preparation 1232 and mask production 1233 as separate elements. In some embodiments, mask data preparation 1232 and mask production 1244 can be referred to collectively as mask data preparation.

[0174] In some embodiments, mask data preparation 1232 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image defects such as those that may arise from refraction, interference, other process effects, and the like. OPC adapts IC layout diagram 1222. In some embodiments, mask data preparation 1232 includes further resolution enhancement techniques (RET), such as axis angle illumination, sub-resolution assist features, phase-shift masks, other suitable techniques, and the like, or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as an inverse imaging problem.

[0175] In some embodiments, mask data preparation 1232 includes a mask rule checker (MRC) that checks the IC layout diagram 1222, which has undergone processes in OPC, against a set of mask generation rules that include certain geometric and / or connectivity constraints to ensure sufficient leeway to accommodate variability in semiconductor manufacturing processes and the like. In some embodiments, the MRC modifies the IC layout diagram 1222 to compensate for constraints during mask manufacturing 1244 that may undo some of the modifications made by OPC to satisfy mask generation rules.

[0176] In some embodiments, Mask Data Preparation 1232 includes Lithography Process Checking (LPC), which simulates the processing as implemented by IC-Fab 1250 to manufacture IC device 1260. LPC simulates this processing based on IC Layout Diagram 1222 to generate a simulated manufactured device, such as IC device 1260. The processing parameters in LPC simulation may include parameters associated with different processes of the IC manufacturing cycle, parameters associated with tools used to manufacture the IC, and / or other aspects of the manufacturing process. LPC considers various factors, such as aerial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), or other suitable factors, and the like, or combinations thereof.In some embodiments, after a simulated manufactured component has been created by LPC, if the simulated component is not close enough to the shape to meet layout rules, OPC and / or MRC are repeated to further refine IC layout diagram 1222.

[0177] It should be understood that the description above of mask data preparation 1232 has been simplified for clarity. In some embodiments, data preparation 1232 includes additional features, such as a logic operation (LOP), to modify the IC layout diagram 1222 according to manufacturing rules. Additionally, the processes applied to the IC layout diagram 1222 during data preparation 1232 can be performed in a variety of different sequences.

[0178] Following mask data preparation 1232 and during mask fabrication 1244, a mask 1245 or a group of masks 1245 are fabricated based on the modified IC layout diagram 1222. In some embodiments, mask fabrication 1244 includes performing one or more lithographic exposures based on the IC layout diagram 1222. In some embodiments, an electron beam (e-beam) or a mechanism of multiple electron beams is used to form a pattern on a mask (photomask or crosshair) 1245 based on the IC layout diagram 1222. The mask 1245 can be formed using different technologies. In some embodiments, the mask 1245 is formed using binary technology. In some embodiments, a mask pattern contains opaque and transparent areas. A beam of light, such as an ultraviolet (UV) beam, is used to expose the image-sensitive material layer (e.g.,The photoresist layered onto a wafer is blocked by the opaque area and passes through the transparent areas. In one example, a binary mask version of Mask 1245 contains a transparent substrate (e.g., quartz glass) and a turbid material (e.g., chromium) deposited in the turbid areas of the binary mask. In another example, Mask 1245 is formed using a phase-shift technology. In a phase-shift mask (PSM) version of Mask 1245, various features in the pattern formed on the phase-shift mask are configured to have a suitable phase difference to improve resolution and image quality. In other examples, the phase-shift mask may be attenuated PSM or alternating PSM. The mask(s) produced by Mask Fabrication 1244 are used in a variety of processes.For example, such a mask(s) are used in an ion implantation process to form different doped areas in the semiconductor wafer 1253, in an etching process to form different etched areas in the semiconductor wafer 1253, and / or in other suitable processes.

[0179] IC-Fab 1250 includes a wafer fabrication unit 1252. IC-Fab 1250 is an IC manufacturing company that includes one or more manufacturing units for producing a variety of different IC products. In some embodiments, IC-Fab 1250 is a semiconductor foundry. For example, there may be one manufacturing unit for the front-end manufacturing of multiple IC products (front-end-of-line (FEOL) manufacturing), while a second manufacturing unit may provide the back-end manufacturing for wiring and packaging the IC product (back-end-of-line (BEOL) manufacturing), and a third manufacturing unit may provide other services to the foundry.

[0180] IC-Fab 1250 uses mask(s) 1245, manufactured by masking unit 1230, to fabricate IC device 1260. In some embodiments, semiconductor wafer 1253 is fabricated by IC-Fab 1250 using mask(s) 1245 to form IC device 1260. In some embodiments, the IC fabrication includes performing one or more lithographic exposures based, at least indirectly, on IC layout diagram 1222. Semiconductor wafer 1253 contains a silicon substrate or other suitable substrate having material layers formed on it. Semiconductor wafer 1253 further contains one or more different doped regions, dielectric features, multi-layer wiring, and the like (formed in successive fabrication steps).

[0181] (End of detailed description) In some embodiments, a method for operating an IC manufacturing system includes determining whether an active n-region or an active p-region of a cell is a first active region, based on a time-critical path of the cell; positioning the first active region along a cell height direction in an IC layout diagram of a cell, wherein the first active region has a first total number of fins extending in a direction perpendicular to the cell height direction; positioning a second active region in the cell along the cell height direction, wherein the second active region is the n-type or p-type opposite to the n-type or p-type of the first active region and has a second total number of fins that is less than the first total number of fins and extends in the same direction; and storing the IC layout diagram of the cell in a cell library.In some embodiments, determining whether the active n-region or the active p-region is the first active region involves performing a circuit simulation based on a layout corresponding to the IC layout diagram of the cell. In some embodiments, positioning the first active region involves positioning the first active region at a first distance from a first cell edge segment along the cell height direction; positioning the second active region involves positioning the second active region at a first distance along the cell height direction from a second cell edge segment opposite to the first cell edge segment, and the first distance corresponds to a first minimum distance rule.In some embodiments, one or both of the positioning of the first active area or the positioning of the second active area includes separating the first and second active areas by a second distance along the cell height direction that is greater than or equal to a second minimum distance rule.In some embodiments, positioning the first active region includes positioning the first active region, which has a first height in the cell height direction corresponding to the first total number of fins; positioning the second active region includes positioning the second active region, which has a second height in the cell height direction corresponding to the second total number of fins; and the first and second minimum spacing rules, the first and second heights, a cell height in the cell height direction, and the first and second spacings are related to each other such that the sum of the first and second total numbers of fins is a maximum number of fins that can be included in the cell's IC layout diagram when positioning the first and second active regions. In some embodiments, the first total number of fins is three and the second total number of fins is two.In some embodiments, the method includes receiving the IC layout diagram of the cell, positioning the first active region in the cell, and increasing the height of an existing active region of the cell along the cell height direction. In some embodiments, the method includes positioning a third active region in the cell along the cell height direction, wherein the third active region is of the same n-type or p-type as the second active region and has the same total number of fins, and positioning a fourth active region in the cell along the cell height direction, wherein the fourth active region is of the same n-type or p-type as the first active region and has the same total number of fins.In some embodiments, the method, based on the IC layout diagram of the cell, includes at least one of the fabrication of a semiconductor mask or component or the performance of one or more manufacturing operations.

[0182] In some embodiments, an IC layout generation system includes a processor and a non-transitory, computer-readable data storage medium containing computer program code for one or more programs. The non-transitory, computer-readable data storage medium and the computer program code are configured, with the processor, to cause the system to arrange a first plurality of fin tracks into a first subset containing a first total number of fin tracks corresponding to a first type of n-type or p-type, and a second subset containing a second total number of fin tracks corresponding to a second type of n-type or p-type, wherein the first plurality of fin tracks extends in a first direction and the first total number is greater than the second total number, and a second plurality of fin tracks extending in the first direction into a first subset,which contains the first total number of fin tracks corresponding to the second type, and a second subset containing the second total number of fin tracks corresponding to the first type, to arrange the second subset of the first plural of fin tracks with the first subset of the second plural of fin tracks along a second direction perpendicular to the first direction, and to generate an IC layout diagram based on the first plural of fin tracks and the second plural of fin tracks. In some embodiments, the first total number of fin tracks is equal to three and the second total number of fin tracks is equal to two, or the first total number of fin tracks is equal to two and the second total number of fin tracks is equal to one. In some embodiments, the non-transitory, computer-readable data storage medium and the computer program code are configured to cause the processor to further instruct the system toto position a cell by aligning a fin configuration of the cell with at least one of the first plurality of fin tracks or the second plurality of fin tracks along the first direction in the IC layout diagram. In some embodiments, the non-transitory, computer-readable data storage medium and the computer program code are configured to further cause the processor to align, along the first direction, each fin track of a third plurality of fin tracks with a corresponding fin track of one of the first plurality of fin tracks or the second plurality of fin tracks, wherein the third plurality of fin tracks includes a first subset comprising the second total number of fin tracks of the first type, and a second subset comprising the second total number of fin tracks of the second type.and the third plurality of fin tracks and one of the first plurality of fin tracks or the second plurality of fin tracks are separated by a gap. In some embodiments, the non-transitory, computer-readable data storage medium and the computer program code are configured to further instruct the processor to receive a plurality of cells, each cell of the plurality of cells having a cell type, and to align a fin configuration of each cell of the plurality of cells along the first direction with one of the first plurality of fin tracks, the second plurality of fin tracks, or the third plurality of fin tracks based on the cell type of each cell of the plurality of cells. In some embodiments, the cell types are based on time criteria associated with one or more logic functions. In some embodiments, the non-transitory,The computer-readable data storage medium and the computer program code are configured to further instruct the processor to receive a cell that has a total number of fins equal to zero, and to place the cell in the gap and adjacent to both the third plurality of fin tracks and one of the first plurality of fin tracks or the second plurality of fin tracks.

[0183] In some embodiments, an IC structure comprises a first plurality of fins of a first type of n-type or p-type, a second plurality of fins of a second type of n-type or p-type, wherein the second plurality of fins is parallel to and adjacent to the first plurality of fins, a third plurality of fins of the second type, wherein the third plurality of fins is parallel to and adjacent to the second plurality of fins, and a fourth plurality of fins of the first type, wherein the fourth plurality of fins is parallel to and adjacent to the third plurality of fins. The first plurality of fins and the third plurality of fins have the same first number of fins, the second plurality of fins and the fourth plurality of fins have the same second number of fins, and the first number is greater than the second number. In some embodiments, the first number is three and the second number is two.In some embodiments, the IC structure includes a fifth plurality of fins, comprising the second plurality of fins, wherein the fins of the fifth plurality of fins are of the first type, aligned with a subset of the first plurality of fins and separated from the first plurality of fins by a fin discontinuity region. In some embodiments, the IC structure includes a sixth plurality of fins, comprising the second plurality of fins, wherein the fins of the sixth plurality of fins are parallel to and adjacent to the fifth plurality of fins.

Claims

[1] Method for operating an integrated circuit manufacturing system, IC manufacturing system (1200), wherein the method comprises: Determine whether an active n-region of a cell (200C, 300C, 600A-D, 710, 810, 820, 830, 840, 850, 860) or active p-region of the cell (200C, 300C, 600A-D, 710, 810, 820, 830, 840, 850, 860) is a first active region (AR1, AR2) based on a time-critical path of the cell (200C, 300C, 600A-D, 710, 810, 820, 830, 840, 850, 860), wherein a gate region (Gro - Gr3) intersects the first active region (AR1, AR2) at a position corresponding to a transistor (P1, P2, N1, N2) corresponds to or a corresponding gate structure refers to a dummy gate structure; Positioning the first active region along a cell height direction (Y) in the IC layout diagram of the cell (200C, 300C, 600A-D, 710, 810, 820, 830, 840, 850, 860), wherein the first active region (AR1, AR2) comprises a first total number of fins (F1-F5) with the fins extending in a direction (X) perpendicular to the cell height direction (Y); Positioning a second active region (AR1, AR2) in the cell (200C, 300C, 600A-D, 710, 810, 820, 830, 840, 850, 860) along the cell height direction (Y), wherein a gate region (Gro - Gr3) intersects the second active region (AR1, AR2) at a position corresponding to a transistor (P1, P2, N1, N2) or a corresponding gate structure related to a dummy gate structure, wherein the second active region (AR1, AR2) is of the n-type or p-type opposite the n-type or p-type of the first active region (AR1, AR2) and includes a second total number of fins (F1-F5) that is less than the first total number of fins, the fins of the second total number of fins extending in the direction (X). Positioning a third active area (AR1, AR2) adjacent to the second active area (AR1, AR2) in the cell (200C, 300C, 600A-D, 710, 810, 820, 830, 840, 850, 860) along the cell height direction (Y), wherein the third active area (AR1, AR2) is of the same n-type or p-type as the second active area (AR1, AR2) and comprises the first total number of fins (F1-F5); and Positioning a fourth active area (AR2, AR2) adjacent to the third active area (AR1, AR2) in the cell (200C, 300C, 600A-D, 710, 810, 820, 830, 840, 850, 860) along the cell height direction (Y), wherein the fourth active area (AR1, AR2) is of the same n-type or p-type as the first active area (AR1, AR2) and comprises the second total number of fins (F1-F5); and Storing the IC layout diagram (200, 300, 500, 600, 700, 800) of the cell (200C, 300C, 600A-D, 710, 810, 820, 830, 840, 850, 860) in a cell library (1120). [2] Method according to claim 1, wherein determining whether the active n-area or the active p-area is the first active area (AR1, AR2) comprises performing a circuit simulation based on a layout according to the IC layout diagram of the cell (200C, 300C, 600A-D, 710, 810, 820, 830, 840, 850, 860). [3] Method according to claim 1 or 2, wherein the positioning of the first active area (AR1, AR2) includes positioning the first active area (AR1, AR2) at a first distance (D1) from a first cell border segment (B1, B2) along the cell height direction (Y), the positioning of the second active area (AR1, AR2) includes positioning the second active area (AR1, AR2) at the first distance (D1) along the cell height direction (Y) from a second cell border segment (B1, B2) opposite to the first cell border segment, and the first distance (D1, D2) corresponds to a first minimum distance rule. [4] Method according to any of the preceding claims, wherein one or both of the positioning of the first active area (AR1, AR2) or of the positioning of the second active area (AR1, AR2) comprises separating the first and second active area (AR1, AR2) by a second distance (D1, D2) along the cell height region which is greater than or equal to a second minimum distance rule. [5] Method according to claims 3 and 4, wherein: the positioning of the first active area (AR1, AR2) includes positioning the first active area (AR1, AR2) which has a first height (AH1, AH2) in the cell height direction (Y) corresponding to the first total number of fins (F1-F5), the positioning of the second active area (AR1, AR2) includes positioning the second active area (AR1, AR2) which has a second height (AH1, AH2) in the cell height direction (Y) corresponding to the second total number of fins (F1-F5), and The first and second minimum distance rules, the first and second heights (AH1, AH2), a height (CH) of the cell (200C, 300C, 600A-D, 710, 810, 820, 830, 840, 850, 860) in the cell height direction (Y), and the first and second distances (D1, D2) are related to each other such that the sum of the first and second total number of fins (F1-F5) is a maximum number of fins (F1-F5) that are set up to position the first and second active areas (AR1, AR2) in the IC layout diagram (200, 300, 500, 600, 700, 800) of the cell (200C, 300C, 600A-D, 710, 810, 820, 830, 840, 850, 860). [6] Method according to any one of the preceding claims, wherein: the first total number of Finns (F1-F5) is three, and The second total number of Finns (F1-F5) is two. [7] Method according to any of the preceding claims, further comprising receiving the IC layout diagram (200, 300, 500, 600, 700, 800) of the cell (200C, 300C, 600A-D, 710, 810, 820, 830, 840, 850, 860), wherein positioning the first active area (AR1, AR2) in the cell comprises raising a height (AH1, AH2) of an existing active area (AR1, AR2) of the cell (200C, 300C, 600A-D, 710, 810, 820, 830, 840, 850, 860) along the cell height direction (Y). [8] Method according to any one of the preceding claims, further comprising, based on the IC layout diagram (200, 300, 500, 600, 700, 800) of the cell (200C, 300C, 600A-D, 710, 810, 820, 830, 840, 850, 860), at least one of: Manufacturing a semiconductor mask or component, or Performing one or more manufacturing operations. [9] Integrated circuit layout diagram generation system, IC layout diagram generation system (1100), comprising: a processor (1102); and a non-transitory, computer-readable data storage medium (1104) containing computer program code (1106) for one or more programs, wherein the non-transitory, computer-readable data storage medium (1104) and the computer program code (1106) are configured to cause the processor (1102) to: Arranging a first plurality of fin tracks (FT1-FT14) into a first subset comprising a first total number of fin tracks (FT1-FT14) corresponding to a first type of an n-type or a p-type, and a second subset comprising a second total number of fin tracks (FT1-FT14) corresponding to a second type of the n-type or the p-type, wherein the fin tracks of the first plurality of fin tracks (FT1-FT14) extend in a first direction (X) and the first total is greater than the second total; Arranging a second plurality of fin tracks (FT1-FT14), wherein the fin tracks of the second plurality of fin tracks (FT1-FT14) extend in the first direction (X), into a first subset comprising the first total number of fin tracks (FT1-FT14) according to the second type, and a second subset comprising the second total number of fin tracks (FT1-FT14) according to the first type; Applying the second subset of the first plural of fin tracks (FT1-FT14) to the first subset of the second plural of fin tracks (FT1-FT14) along a second direction (Y) perpendicular to the first direction (X), wherein fin tracks (FT1-FT14) are rows in the IC layout diagram (200, 300, 500, 600, 700, 800) that define at least some potential positions of FinFET fins (F1-F5) and correspond to active regions (AR1, AR2), wherein a gate region (GRo-GR3) intersects one of the active regions (AR1, AR2) at a position corresponding to a transistor (P1, P2, N1, N2) or a corresponding gate structure refers to a dummy gate structure; and Generating the IC layout diagram (200, 300, 500, 600, 700, 800) based on the first plurality of fin tracks (FT1-FT14) and the second plurality of fin tracks (FT1-FT14). [10] IC layout diagram generation system (1100) according to claim 9, wherein: the first total number of fin tracks (FT1-FT14) is three and the second total number of fin tracks (FT1-FT14) is two, or the first total number of fin tracks (FT1-FT14) is two and the second total number of fin tracks (FT1-FT14) is one. [11] IC layout diagram generation system (1100) according to claim 9 or 10, wherein the non-transitory, computer-readable data storage medium (1104) and the computer program code (1106) are configured with the processor (1102) to further cause the system (1100) to: Placing a cell (200C, 300C, 600A-D, 710, 810, 820, 830, 840, 850, 860) in the IC layout diagram (200, 300, 500, 600, 700, 800) by aligning a fin configuration of the cell with at least one of the first plurality of fin tracks (FT1-FT14) or the second plurality of fin tracks (FT1-FT14) along the first direction (X). [12] IC layout diagram generation system (1100) according to one of claims 9 to 11, wherein the non-transitory, computer-readable data storage medium (1104) and the computer program code (1106) are configured with the processor (1102) to further cause the system (1100) to: Align, along the first direction (X), each fin track (FT1-FT14) of a third plurality of fin tracks (FT1-FT14) with a corresponding fin track (FT1-FT14) of one of the first plurality of fin tracks (FT1-FT14) or the second plurality of fin tracks (FT1-FT14), wherein: the third plural of fin tracks (FT1-FT14) comprises a first subset comprising the second total number of fin tracks (FT1-FT14) corresponding to the first type, and a second subset comprising the second total number of fin tracks (FT1-FT14) corresponding to the second type, and the third plural of fin tracks (FT1-FT14) and the one of the first plural of fin tracks (FT1-FT14) or the second plural of fin tracks (FT1-FT14) are separated by a gap (G1). [13] IC layout diagram generation system (1100) according to any one of claims 9 to 12, wherein the non-transitory, computer-readable data storage medium (1104) and the computer program code (1106) are configured with the processor (1102) to further cause the system (1100) to: Receiving a plurality of cells (200C, 300C, 600A-D, 710, 810, 820, 830, 840, 850, 860), wherein each cell (200C, 300C, 600A-D, 710) of the plurality of cells (200C, 300C, 600A-D, 710) has a cell type; and Aligning a fin configuration of each cell (200C, 300C, 600A-D, 710, 810, 820, 830, 840, 850, 860) of the plurality of cells (200C, 300C, 600A-D, 710, 810, 820, 830, 840, 850, 860) along the first direction (X) with one of the first plurality of fin tracks (FT1-FT14), the second plurality of fin tracks (FT1-FT14) or the third plurality of fin tracks (FT1-FT14), based on the cell type of each cell (200C, 300C, 600A-D, 710, 810, 820, 830, 840, 850, 860) the majority of cells (200C, 300C, 600A-D, 710, 810, 820, 830, 840, 850, 860). [14] IC layout diagram generation system according to one of claims 9 to 13, wherein the cell types are based on time criteria linked to one or more logic functions. [15] IC layout diagram generation system (1100) according to any one of claims 9 to 14, wherein the non-transitory, computer-readable data storage medium (1104) and the computer program code (1106) are configured with the processor (1102) to further cause the system (1100) to: Receiving a cell (820,850) that has a total number of fins (F1-F5) equal to zero; and Placing the cell (820,850) in the gap (G1) and adjacent to each of the third plurality of fin tracks (PT1-FT14) and one of the first plurality of fin tracks (FT1-FT14) or the second plurality of fin tracks (FT1-FT14). [16] Integrated circuit structure, IC structure (900D), comprising: a first plurality of fins (PF1-PF6) of a first type of an n-type or a p-type, wherein the fins of the first plurality of fins (PF1-PF6) extend in a first direction (X); a second plurality of fins (PF1-PF6) of a second type of n-type or p-type, wherein the fins of the second plurality of fins (PF1-PF6) extend parallel to the fins of the first plurality of fins (PF1-PF6) in the first direction (X) and the second plurality of fins (PF1-PF6) is arranged in a second direction (Y) perpendicular to the first direction (X) adjacent to the first plurality of fins (PF1-PF6); a third plurality of fins (F1-F5) of the second type, wherein the fins of the third plurality of fins (PF1-PF6) extend parallel to the fins of the second plurality of fins (PF1-PF6) in the first direction (X) and the third plurality of fins (PF1-PF6) is arranged adjacent to the second plurality of fins (PF1-PF6) in the second direction (Y); and a fourth plurality of fins (PF1-PF6) of the first type, wherein the fins of the fourth plurality of fins extend parallel to the fins of the third plurality of fins (PF1-PF6) in the first direction (X) and the fourth plurality of fins (PF1-PF6) is arranged adjacent to the third plurality of fins in the second direction (Y), where the first plural of Finns (F1-F5) and the third plural of Finns (PF1-PF6) have the same first number of Finns (PF1-PF6), the second plural of Finns (PF1-PF6) and the fourth plural of Finns (PF1-PF6) have the same second number of Finns (PF1-PF6), and the first number is greater than the second number, wherein each plurality of fins (PF1-PF6) contains one or more of a p- or n-fin (F1-F5) extending in one direction (X) in each active region (AR1, AR2) in a substrate (900S), wherein a gate region (GRo-GR3) intersects one of the active regions (AR1, AR2) at a position corresponding to a transistor (P1, P2, N1, N2) or a corresponding gate structure refers to a dummy gate structure. [17] IC structure (900D) according to claim 16, wherein the first number is equal to three and the second number is equal to two. [18] IC structure according to claim 16 or 17, further comprising a fifth plurality of fins (PF1-PF6) comprising the second plurality of fins (PF1-PF6), wherein the fins (PF1-PF6) of the fifth plurality of fins (PF1-PF6) are of the first type, are aligned with a subset of the first plurality of fins (PF1-PF6) and are separated from the first plurality of fins (PF1-PF6) by a fin discontinuity area 900G. [19] IC structure according to claim 18, further comprising a sixth plurality of fins (PF1-PF6) having the second plurality of fins (PF1-PF6), wherein the fins (PF1-PF6) of the sixth plurality of fins (PF1-PF6) are parallel to and adjacent to the fifth plurality (PF1-PF6) of fins.

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