Electrical component

Abstract

Electrical components: - a carrier substrate (1) with a top side (10), - a trap-rich layer (2) on the top (10), - a dielectric layer (3) on the trap-rich layer (2), - an electroacoustic resonator (4) on the dielectric layer (3), - a coil (5), wherein - the dielectric layer (3) and the trap-rich layer (2) are located between the coil (5) and the carrier substrate (1), - the carrier substrate (1) is based on a semiconductor material, - the trap-rich layer (2) has a higher charge carrier trap density than the carrier substrate (1), wherein the charge carrier trap density in the trap-rich layer (2) is at least ten times the charge carrier trap density in the carrier substrate (1).

Description

[0001] An electrical component is specified.

[0002] The following state of the art is known from the examination procedure: - The first publication, US 2017 / 0063332 A1, concerns the use of SAW resonators and describes the problem that RF losses due to interference currents can remain in known SAW structures. An oxide layer can be present between the piezoelectric material of the SAW resonator arrangement and the substrate. A surface area with a high trap density and reduced charge carrier mobility can be provided between the substrate and the oxide layer. The surface area with a high trap density represents a high probability of trapping (or annihilating) free charge carriers, which significantly reduces the generation of RF interference currents due to electric fields from the electrodes of the SAW resonator component. - The second publication, DE 10 2018 108961 A1, relates to a method for manufacturing a TF-SAW resonator with an improved quality factor. The TF-SAW resonator may further include a charge reduction layer containing traps for trapping electrical charge. This is used to reduce parasitic surface conduction by trapping free charge carriers. - The third publication, US 2018 / 0358951 A1, relates to two acoustic wave elements, each with metal patterns located on the bottom surface of the substrates. The substrates are mounted in a flip-chip geometry. It is shown that the functional element may not necessarily be the acoustic wave element, but rather a passive element, which can be implemented in the form of a coil on the underside of one of the substrates. - The fourth publication, DE 10 2019 119 239 A1 (filing date: July 16, 2019, disclosure date: January 21, 2021), is considered prior art within the meaning of Section 3 (2) of the Patent Act (PatentG) and describes a multiplexer. At least three acoustic filter circuits are arranged on a single chip. At least two of them are already electrically connected on the chip for multiplexing. This reduces space requirements and leads to a smaller device size.

[0003] One object of the present invention is to specify an electrical component with improved performance. The invention is defined by the independent claims.

[0004] According to at least one embodiment, the electrical component comprises a carrier substrate with a top surface. The carrier substrate may be self-supporting. In particular, the carrier substrate is the mechanically stabilizing component of the electrical component. The carrier substrate may be formed in one piece, i.e., it may be molded in one piece from a material or a material composition.

[0005] According to at least one embodiment, the electrical component comprises a trap-rich layer on the top side of the carrier substrate. The trap-rich layer can be formed either directly on the top side or in the carrier substrate on the top side. In the second case, the trap-rich layer itself can form the top side.

[0006] The trap-rich layer may be a continuous layer, e.g., without interruptions. The trap-rich layer may be formed in one piece. For example, the trap-rich layer covers at least 50%, or at least 75%, or at least 90% of the top surface of the carrier substrate. An average thickness of the trap-rich layer is, e.g., at most 1.5 µm, or at most 1.0 µm, or at most 500 nm, or at most 200 nm. Additionally or alternatively, the average thickness of the trap-rich layer is at least 10 nm, or at least 50 nm, or at least 100 nm.

[0007] According to at least one embodiment, the electrical component comprises a dielectric layer on the trap-rich layer. The dielectric layer may be in direct contact with the trap-rich layer. Thus, the trap-rich layer is embedded between the dielectric layer and the carrier substrate. The dielectric layer may be a continuous layer, e.g., without interruptions. The dielectric layer may be formed in one piece or consist of a multilayer stack. For example, the dielectric layer covers the trap-rich layer to at least 50%, or at least 75%, or at least 90%. An average thickness of the dielectric layer is, e.g., at most 10 µm, or at most 5 µm, or at most 2 µm. Additionally or alternatively, the thickness of the dielectric layer may be at least 100 nm or at least 500 nm.

[0008] According to at least one embodiment, the electrical component comprises an electroacoustic resonator on the dielectric layer. In particular, both the dielectric layer and the trap-rich layer are located between the carrier substrate and the active area of ​​the electroacoustic resonator. The active area of ​​the electroacoustic resonator is the region in which acoustic waves are excited and propagate. The electroacoustic resonator can be a BAW resonator (BAW = bulk acoustic wave). Alternatively, the electroacoustic resonator can be a SAW resonator (SAW = surface acoustic wave).

[0009] According to at least one embodiment, the electrical component comprises a coil. The coil is formed from an electrically conductive material, for example, a metal. The coil may comprise one or more of the following materials: Al, Cu, Ti, Pd, Au, Ag, Ni.

[0010] The coil may have an inductance between 0.1 nH and 20 nH inclusive, in particular between 1 nH and 10 nH inclusive. The inductance of the coil is measured, for example, by applying an alternating voltage with a frequency of 100 MHz.

[0011] The coil can be electrically connected to the electroacoustic resonator. The coil can be electrically connected to the electroacoustic resonator in series or in parallel. The electrical component is, for example, an electrical filter comprising several electroacoustic resonators arranged, for example, in a conductor structure. The electroacoustic resonator and the coil can be part of a shunt path and can be connected in series in the shunt path.

[0012] According to at least one embodiment, the dielectric layer and the trap-rich layer are located between the coil and the carrier substrate. In particular, the magnetic field generated by the coil during intended operation of the electrical component penetrates the dielectric layer and the trap-rich layer. For example, the trap-rich layer and the dielectric layer are located between each part of the coil and the carrier substrate, in particular between each winding of the coil and the carrier substrate. In other words, when the coil, the dielectric layer, and the trap-rich layer are projected onto the top side, all three elements overlap each other. For example, in this projection, the coil completely overlaps the trap-rich layer and / or the dielectric layer.

[0013] According to at least one embodiment, the carrier substrate is based on a semiconductor material. This means that the carrier substrate comprises the semiconductor material in addition to impurities and dopants. The semiconductor material is, for example, silicon. The semiconductor material can be doped, for example, n-doped or p-doped. A doping concentration can be at least 1 × 10 14 cm -3 or at least 1 · 10 15 cm -3 or at least 1 · 10 16 cm -3 For example, the specific resistance of the carrier substrate is at least 500 Ω cm.

[0014] According to at least one embodiment, the trap-rich layer has a higher density of charge carrier traps than the carrier substrate. In particular, the trap-rich layer has a higher trap density for those charge carriers that constitute the majority of the charge carriers in the carrier substrate.

[0015] The charge carrier traps in the trap-rich layer may have an average depth Et of at least k T, for example of at least 10 k T, where k is the Boltzmann constant, T is the room temperature or the operating temperature and E t is the energy required to remove an electron or hole from the trap into the valence or conduction band. The carrier traps can be realized by surface states, crystallographic defects, and / or impurities such as transition metals, particularly iron, nickel, copper, gold, or silver. Especially for impurity-induced carrier traps, the base material of the trap-rich layer and the supporting substrate can be the same. For example, the trap-rich layer is formed by implanting impurities into the supporting substrate.

[0016] According to at least one embodiment, the distance between the coil and the top side of the carrier substrate is at most 120 µm, or at most 80 µm, or at most 60 µm, or at most 40 µm, or at most 5 µm. The distance between two elements is defined as the shortest connection between the two elements. In particular, the distance between an electrically conductive part of the coil and the top side of the carrier substrate or between the center of gravity of the coil and the top side is given by the above-mentioned values.

[0017] In at least one embodiment, the electrical component comprises a carrier substrate having a top surface, a trap-rich layer on the top surface, a dielectric layer on the trap-rich layer, an electroacoustic resonator on the dielectric layer, and a coil. The dielectric layer and the trap-rich layer are located between the coil and the carrier substrate. The carrier substrate is based on a semiconductor material. The trap-rich layer has a higher density of charge carrier traps than the carrier substrate.

[0018] Inductors are generally used in electrical components, especially in electrical filters, to improve performance in terms of matching, selection, isolation, and bandwidth. The critical parameters of such an inductor are its inductance and its quality factor (Q value). The Q value often has a direct influence on the filter's insertion loss, the steepness of the filter slope, and the depth of the transmission zero point. A high Q value is generally desirable.

[0019] There are electrical components in which the acoustic structures are not only applied to a piezoelectric substrate, but in which a multilayer substrate is used. Such a multilayer substrate generally comprises a thicker semiconductor carrier substrate, a thinner dielectric layer, and a thin piezoelectric layer. The reason for this is that a higher Q value and lower temperature dependence can be achieved with such a multilayer substrate. Typically, however, a conductive layer forms between the dielectric layer and the carrier substrate, with the conductive layer having a thickness of approximately 100 nm. This conductive layer is called a parasitic surface conduction (PSC) layer. The PSC layer is formed, for example, when the dielectric layer has positive charge carriers that attract free negative charge carriers of the semiconductor carrier substrate.These free negative charge carriers from the carrier substrate agglomerate at the interface with the dielectric layer, forming the PSC layer. The thickness and conductivity of the PSC layer naturally depend on several factors, such as the doping concentration of the carrier substrate, the resistance of the carrier substrate, and the number of charge carriers in the dielectric layer.

[0020] To save space, coils in electrical components are often placed close to the electroacoustic resonator. As a result, the magnetic field generated by the coil often penetrates the PSC layer. The resulting eddy currents in the PSC layer reduce the Q value of the coil, thereby diminishing the overall performance of the electrical component.

[0021] The present invention is based, among other things, on the idea that a trap-rich layer between the dielectric layer and the carrier substrate in the coil region can significantly reduce the mobility of free charge carriers in the PSC layer. This makes the Q value of the coil comparable to that of the case where no PSC layer is present.

[0022] According to at least one embodiment, the density of the charge carrier traps in the trap-rich layer is at least 10 times or at least 100 times or at least 1000 times or at least 10,000 times or at least 100,000 times the density of the charge carrier traps in the carrier substrate.

[0023] According to at least one embodiment, the trap-rich layer has a charge carrier trap density of at least 10 11 cm -2 registered association -1 or at least 5 · 10 11 cm -2 registered association -1 or at least 10 12 cm-2 eV -1 Here, the charge carrier traps are integrated across the thickness of the trap-rich layer. Additionally or alternatively, the trap-rich layer has a charge carrier trap density of at least 10 19 cm -3 eV -1 or at least 10 20 cm -3 eV -1 or at least 10 21 cm -3 eV -1 .

[0024] According to at least one embodiment, the trap-rich layer is based on polycrystalline silicon or amorphous silicon.

[0025] According to at least one embodiment, the carrier substrate is based on crystalline silicon.

[0026] An element is based on a specific material if it consists essentially of that material. However, the element may still contain impurities or dopants.

[0027] According to at least one embodiment, the dielectric layer is a silicon oxide layer, in particular a SiO2 layer.

[0028] According to at least one embodiment, the coil has at least one winding or at least two windings or at least three windings or at least four windings or at least five windings.

[0029] According to at least one embodiment, the coil is a flat coil. However, the coil can also be a multilayer coil. In particular, the coil can be formed from conductor tracks. The thickness of the conductive windings of the coil can be between 1 µm and 25 µm inclusive.

[0030] According to at least one embodiment, the electroacoustic resonator is a SAW resonator with a piezoelectric layer and an interdigital electrode structure.

[0031] The piezoelectric layer comprises, for example, LiTaO3, LiNbO3, or quartz. The average thickness of the piezoelectric layer can be at most 10 µm, at most 5 µm, at most 1 µm, or at most 500 nm. Additionally or alternatively, the average thickness of the piezoelectric layer can be at least 10 nm, at least 100 nm, or at least 500 nm.

[0032] The interdigital electrode structure comprises two electrodes, each with a plurality of fingers. The fingers of the electrodes interdigitate with each other (are interlocked). For example, each electrode comprises at least 50 or at least 100 fingers. The fingers of an electrode run substantially parallel to each other and are electrically connected by a busbar. The electrodes are made of an electrically conductive material, for example, a metal. The electrodes may comprise one or more of the following materials: Al, Cu, Pd, Ti, Ni, Mo, W, Au.

[0033] According to at least one embodiment, the piezoelectric layer is located between the dielectric layer and the interdigital electrode structure. In particular, the piezoelectric layer can be in direct contact with the dielectric layer. The piezoelectric layers can be adjacent to one another without interruptions and / or formed in one piece. The piezoelectric layer can cover at least 50%, at least 75%, or at least 90% of the dielectric layer. The interdigital electrode structure, in particular the electrically conductive electrodes, can be applied directly to the piezoelectric layer.

[0034] According to at least one embodiment, the interdigital electrode structure, in particular the fingers of the electrodes, and the coil, in particular the windings of the coil, overlap when both are projected onto the top side. In other words, either the coil is located between the interdigital electrode structure and the top side of the carrier substrate, or the interdigital electrode structure is located between the coil and the top side of the carrier substrate.

[0035] Alternatively, it is also possible for the interdigital electrode structure and the coil windings not to overlap when both are projected onto the top surface. In this case, the interdigital electrode structure can be arranged next to the coil on the top surface.

[0036] According to at least one embodiment, the coil is arranged on the carrier substrate and supported by the carrier substrate. The coil is thus indirectly connected to the carrier substrate. For example, the coil is placed directly on the piezoelectric layer or on the dielectric layer. In this case, the distance between the coil and the top side of the carrier substrate is, for example, at most 10 µm, at most 5 µm, or at most 2 µm.

[0037] According to at least one embodiment, the electrical component comprises a further carrier substrate. The further carrier substrate differs from the carrier substrate and is, for example, self-supporting. The further carrier substrate can be based on a semiconductor material, such as silicon, or on a dielectric material, such as glass or ceramic.

[0038] According to at least one embodiment, the coil is placed on the additional carrier substrate and is supported by the additional carrier substrate. The coil is thus directly or indirectly connected to the additional carrier substrate.

[0039] According to at least one embodiment, the carrier substrate and the further carrier substrate are mechanically connected to one another. In particular, the carrier substrate and the further carrier substrate are connected to one another in such a way that when the coil is projected onto the carrier substrate, the coil overlaps with the trap-rich layer.

[0040] The carrier substrate and the further carrier substrate can be connected to each other by a dielectric film or by a metal frame. Electrically conductive connecting elements can also be present between the carrier substrate and the further carrier substrate. The carrier substrate and the further carrier substrate can be connected to each other such that the sides of the carrier substrate and the further carrier substrate on which the electroacoustic resonator and the coil are located face each other. The carrier substrate and the further carrier substrate can be electrically connected to each other. During normal operation of the electrical component, an electric current can flow from the carrier substrate to the further carrier substrate or vice versa.

[0041] According to at least one embodiment, a further electroacoustic resonator is applied to the further carrier substrate. The further electroacoustic resonator is coupled, for example, to the electroacoustic resonator. The further electroacoustic resonator can be a BAW resonator or a SAW resonator. The further electroacoustic resonator can be arranged on the same side of the further carrier substrate as the coil.

[0042] According to at least one embodiment, a gas-filled, in particular air-filled, space is formed between the electroacoustic resonator and the coil. In particular, the electroacoustic resonator is placed in a gas-filled cavity so that it is protected from mechanical stress. The gas-filled cavity is enclosed, for example, by a dielectric cap. The coil can be applied to the dielectric cap on the side of the dielectric cap facing away from the gas-filled cavity.

[0043] According to at least one embodiment, the electroacoustic resonator has a resonant frequency of at least 0.5 GHz, or at least 3 GHz, or at least 5 GHz, or at least 6 GHz. The same can apply to the additional electroacoustic resonator or to all electroacoustic resonators of the electrical component. The electrical component is, for example, an electrical filter, such as a bandpass filter.

[0044] The electrical component can be used in a multiplexer, such as a duplexer, quadplexer, or pentaplexer. The electrical component can be used in a communications device, such as a mobile phone.

[0045] Further embodiments and further developments of the electrical component are described below in conjunction with the figures. Identical or similar elements, as well as elements with the same function, are designated by the same reference numerals in the figures. The figures and the proportions of the elements shown in the figures are not to be considered true to scale. Rather, individual elements, particularly layers, may be shown enlarged for better illustration and / or understanding.

[0046] In the pictures: The Fig. show exemplary embodiments of the electrical component, Fig. shows a comparative example of an electrical component, Fig. shows an exemplary embodiment of a coil, The Fig. show simulation results of characteristic features of a coil in various electrical components.

[0047] Fig. shows a first exemplary embodiment of an electrical component in cross-section. The electrical component is, for example, a bandpass filter for a mobile phone. The electrical component comprises a carrier substrate 1. The carrier substrate 1 is based, for example, on crystalline silicon. The silicon can be doped. A trap-rich layer 2 is formed on a top side 10 of the carrier substrate 1. The trap-rich layer 2 is applied directly to the top side 10, i.e. directly to the silicon of the carrier substrate 1. The trap-rich layer 2 is based, for example, on polycrystalline silicon or amorphous silicon. In particular, the trap-rich layer 2 has a significantly higher density of charge carrier traps, such as crystallographic defects, than the carrier substrate 1. The average thickness of the trap-rich layer 2 is, for example, 1 µm.

[0048] On the trap-rich layer 2, on the side facing away from the carrier substrate 1, there is a dielectric layer 3. The dielectric layer 3 can be applied directly to the trap-rich layer 2. The dielectric layer 3 is based, for example, on SiO2. An average thickness of the dielectric layer 3 is, for example, 1 µm.

[0049] The electrical component further comprises a piezoelectric layer 40, which is arranged on the dielectric layer 3, in particular directly on the dielectric layer 3. The piezoelectric layer 40 is formed, for example, from LiTaO3 or LiNbO3. The average thickness of the piezoelectric layer 40 is, for example, 1 µm.

[0050] An interdigital electrode structure 41 is attached to a side of the piezoelectric layer 40 facing away from the carrier substrate 1. The interdigital electrode structure 41 comprises two electrodes, each with a plurality of fingers, wherein the fingers of both electrodes are interdigitated with each other. The interdigital electrode structure 41 and the piezoelectric layer 40 together form a SAW resonator 4.

[0051] Furthermore, a coil 5 is placed on the same side of the piezoelectric layer 40 as the interdigital electrode structure 41. The coil 5 comprises several turns and is made of a metal, for example. The coil 5 is placed next to the interdigital electrode structure 41. The coil 5 is connected, for example, in series or parallel to the SAW resonator 4.

[0052] The trap-rich layer 2 between the dielectric layer 3 and the carrier substrate 1 has the technical advantage of suppressing the generation of a parasitic surface conduction (PSC) layer between the dielectric layer 3 and the carrier substrate 1. Such a PSC layer can significantly reduce the Q value of the coil 5.

[0053] Fig. shows a comparative example of an electrical component in which no such trap-rich layer is used. The dielectric layer 3 is applied directly to the carrier substrate 1. A dielectric layer 3 formed, for example, from SiO2 generally comprises positive charge carriers that attract free negative charge carriers of the silicon carrier substrate 1. These negative charge carriers agglomerate in the region of the interface between the dielectric layer 3 and the carrier substrate 1 and form the PSC layer, which has increased conductivity compared to the rest of the carrier substrate 1. When the magnetic field of the coil 5 penetrates the PSC layer, eddy currents arise that reduce the Q value of the coil 5.

[0054] Fig. shows an exemplary embodiment of the coil 5 that can be used in the electrical component, for example in the exemplary embodiment of Fig. Coil 5 is a flat coil formed from conductor tracks. Coil 5 comprises an input and an output terminal and three windings. For example, the coil has an inductance of 2.5 nH when an alternating voltage with a frequency of 1 MHz is applied.

[0055] Fig. shows the simulated inductance of coil 5 from Fig. when used in an electrical component. The y-axis represents the inductance in nH. The x-axis represents the frequency (in GHz) of an alternating voltage applied to coil 5. The curve labeled C1 shows the result when coil 5 is used as coil 5 in the exemplary embodiment of Fig. , in which a trap-rich layer 2 is used. The curve marked with the sign C2 shows the case where the coil 5 is used as coil 5 in the comparison example of Fig. is used when no such trap-rich layer is used. An antiresonance in the inductance appears in curve C2. This antiresonance is suppressed when trap-rich layer 2 is used.

[0056] Fig. shows the simulated Q value for both cases. The x-axis represents the frequency of the alternating voltage in GHz. The y-axis shows the Q value. It is clearly visible that the trap-rich layer significantly improves the Q value.

[0057] Fig. shows a second exemplary embodiment of the electrical component. In contrast to Fig. the coil 5 is not located on the carrier substrate 1, but on another carrier substrate 6. The other carrier substrate 6 is made of a ceramic material, for example. The carrier substrate 1 and the other carrier substrate 6 are mechanically connected to each other by connecting elements 60, for example in the form of a Cu frame. In this case, the distance between the coil 5 and the top side 10 of the carrier substrate 1 is smaller than in the case in Fig. For example, in the case of Fig. 30 µm.

[0058] Fig. shows the simulation results for the Q-value for the exemplary embodiment of Fig. (Curve C1) compared to the case where the same design as in Fig. but without the trap-rich layer (curve C2). The y-axis and x-axis show the same as in Fig. .

[0059] As in Fig. As can be seen, the distance between the coil 5 and the top side 10 of the substrate 1 has increased significantly, but the positive effect of the trap-rich layer on the Q value of the coil 5 is still present.

[0060] Fig. shows the result for the same design as in Fig. , but in the case where the distance between the top surface 10 of the carrier substrate 1 and the coil 5 is further increased up to 120 µm. Here, too, the use of a trap-rich layer (curve C1) improves the Q value of the coil 5 compared to the case where no trap-rich layer is used (curve C2).

[0061] Fig. shows a third exemplary embodiment of an electrical component. Here, the electrical component comprises a carrier substrate 1 and another carrier substrate 6, which are connected to one another by connecting elements 60. The two carrier substrates 1, 6 are based, for example, on crystalline silicon. On the upper sides of the two substrates 1, 6, a trap-rich layer 2, followed by a dielectric layer 3 and a piezoelectric layer 40 are formed. The trap-rich layers 2 are based, for example, on polycrystalline silicon or amorphous silicon. The dielectric layers 3 are based, for example, on SiO2. Interdigital electrode structures 41 are formed on the two piezoelectric layers 40, which, together with the piezoelectric layer 40, each form a SAW resonator. Such a SAW resonator 4 is formed on each carrier substrate 1, 6.

[0062] The coil 5 is applied to the further carrier substrate 6 and is connected to and supported by the further carrier substrate 6. In the exemplary embodiment of the Fig. Both the trap-rich layer 2 on the further carrier substrate 6 and the trap-rich layer 2 on the carrier substrate 1 have a positive effect on the Q value of the coil 5. However, since the trap-rich layer 2 associated with the further carrier substrate 6 is much closer to the coil 5 than the trap-rich layer 2 associated with the carrier substrate 1, the effect of the former is much greater.

[0063] Fig. shows a fourth exemplary embodiment of the electrical component. In contrast to the exemplary embodiment in Fig. The piezoelectric layer 40 is arranged directly on the additional carrier substrate 6. In this case, the additional carrier substrate 6 is constructed, for example, on a glass basis. In this case, no PSC layer is formed on the carrier substrate 6, and therefore no trap-rich layer is used. Nevertheless, the trap-rich layer 2 assigned to the carrier substrate 1 continues to have a positive effect on the Q value of the coil 5.

[0064] In the fifth exemplary embodiment of Fig. The further carrier substrate 6 is a laminate into which the coil 5 is embedded. In particular, the coil 5 is embedded in a dielectric material of the laminate, for example, in a polymer.

[0065] In the exemplary embodiments of the Fig. The coil 5 was always placed over the interdigital electrode structure 41 of a SAW resonator 4 such that both the interdigital electrode structure 41 and the coil 5 overlap when projected onto the top side 10 of the carrier substrate 1. However, in all cases, the coil 5 was separated from the SAW resonator 4 by a gas-filled gap.

[0066] In the sixth exemplary embodiment of the Fig.The coil 5 is again arranged above the SAW resonator 4 and separated from the SAW resonator 4 by a gas-filled gap. The gas-filled gap is formed here by two dielectric layers 8, 9, which form a dielectric cap enclosing a gas-filled cavity. The interdigital electrode structure 41 of the SAW resonator 4 is located in the cavity and is protected from external influences by the dielectric cap 8, 9. The coil 5 is formed on a side of the dielectric cap 8, 9 facing away from the cavity. In this case, too, the trap-rich layer 2 improves the Q value of the coil 5.

[0067] The invention described here is not limited by the description in conjunction with the exemplary embodiments. Rather, the invention encompasses any novel feature and any combination of features, in particular any combination of features in the claims, even if this feature or combination is not explicitly mentioned as such in the claims or exemplary embodiments. List of reference symbols: 1 carrier substrate 2 layer rich in traps 3 dielectric layer 4 electroacoustic resonator 5 coil 6 additional carrier substrates 8 dielectric layer 9 dielectric layer 10 Top side of the carrier substrate 1 40 piezoelectric layer 41 Interdigital electrode structure 60 connecting element C1 simulation curve C2 simulation curve

Claims

[1] Have electrical components: - a carrier substrate (1) with a top surface (10), - a layer rich in traps (2) on the upper surface (10), - a dielectric layer (3) on the trap-rich layer (2), - an electroacoustic resonator (4) on the dielectric layer (3), - a coil (5), wherein - the dielectric layer (3) and the trap-rich layer (2) are located between the coil (5) and the support substrate (1), - the support substrate (1) is based on a semiconductor material, - the trap-rich layer (2) has a higher charge carrier trap density than the support substrate (1), wherein the charge carrier trap density in the trap-rich layer (2) is at least ten times the charge carrier trap density in the support substrate (1). [2] Electrical component according to claim 1, wherein the distance between the coil (5) and the top surface (10) of the support substrate (1) is at most 120 µm. [3] Electrical component according to one of the preceding claims, wherein the trap-rich layer (2) has a charge carrier trap density of at least 10 11 cm -2 eV -1 exhibits. [4] Electrical component according to one of the preceding claims, wherein - the trap-rich layer (2) is based on polycrystalline silicon or amorphous silicon, - the support substrate (1) is based on crystalline silicon. [5] Electrical component according to one of the preceding claims, wherein the dielectric layer (3) is a silicon oxide layer. [6] Electrical component according to one of the preceding claims, wherein the coil (5) has at least two turns. [7] Electrical component according to one of the preceding claims, wherein the coil (5) is a flat coil. [8] Electrical component according to one of the preceding claims, wherein the distance between the coil (5) and the top surface (10) of the support substrate (1) is at most 40 µm. [9] Electrical component according to any of the preceding claims, wherein - the electroacoustic resonator (4) is a SAW resonator with a piezoelectric layer (40) and an interdigital electrode structure (41), - the piezoelectric layer (40) is located between the dielectric layer (3) and the interdigital electrode structure (41). [10] Electrical component according to claim 9, wherein the interdigital electrode structure (41) and the coil (5) overlap when projected onto the top surface (10). [11] Electrical component according to one of the preceding claims, wherein the coil (5) is arranged on the support substrate (1) and is supported by the support substrate (1). [12] Electrical component according to any one of claims 1 to 10, wherein - the electrical component comprises another carrier substrate (6), - the coil (5) is arranged on the further support substrate (6) and is supported by the further support substrate (6), - the support substrate (1) and the further support substrate (6) are mechanically connected to each other. [13] Electrical component according to the preceding claim, wherein a further electroacoustic resonator (4) is arranged on the further support substrate (6). [14] Electrical component according to one of the preceding claims, wherein a gas-filled space is formed between the electroacoustic resonator (4) and the coil (5). [15] Electrical component according to one of the preceding claims, wherein the electroacoustic resonator (4) has a resonant frequency of at least 3 GHz.

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