Backside refraction layer for backside illuminated image sensor and method for its manufacture

Abstract

Optical structure with: Light sensors (630) arranged on a front side of a semiconductor substrate (510); an optical refractive layer (734) arranged on a back side of the semiconductor substrate (510), having a first refractive index and having planar distal surface parts and non-planar distal surface parts with random protrusions; a lattice structure (740) arranged on and in contact with the planar distal surface parts and having openings arranged over the non-planar distal surface parts; an optically transparent layer (770) extending vertically through the openings in the lattice structure (740), contacting the non-planar distal surface parts and having a second refractive index different from the first, thereby providing a refractive interface with the non-planar distal surface parts that refracts incident light in random directions; and an arrangement of masking structures (750) which are arranged outside of areas of the non-planar distal surface parts of the optical refractive layer (734) and have sidewalls which are arranged over and contact a respective part of a top surface of the grating structure (740), wherein the optically transparent layer (770) is arranged over the arrangement of masking structures (750).

Description

background

[0001] The present invention relates to semiconductor devices and in particular to a back-illuminated CMOS image sensor (CMOS: Complementary Metal Oxide Semiconductor) and methods for its manufacture.

[0002] Semiconductor image sensors are used to detect electromagnetic radiation, such as visible light, infrared radiation, and / or ultraviolet light. CMOS image sensors (CIS) and CCD sensors (CCD: charge-coupled device) are used in various applications, such as digital cameras or the internal cameras of mobile devices. In these devices, a matrix of pixels (which can be photodiodes and transistors) is used to detect radiation by photogeneration of electron-hole pairs. A back-illuminated image sensor (BSI image sensor) is an image sensor configured to detect light striking the back side of a semiconductor substrate. A CMOS circuitry can be fabricated on the front side of the semiconductor substrate to detect and process photogenerated signals.

[0003] German patent application DE 10 2017 118 989 A1 describes a method for forming an absorption enhancement structure for an image sensor. The back side of a substrate has projections. Each pixel area is bounded by a rib. One or more absorption enhancement layers are arranged along the back side of the substrate. In one embodiment, an absorption enhancement layer can have a nanopillar structure.

[0004] US Patent 2017 141 151 A1 relates to a solid-state imaging device comprising a semiconductor substrate on which a photoelectric transducer unit is formed for each of the numerous pixels, and an antireflection structure on the light-incident side, from which the light falls onto the semiconductor substrate, on which several types of protrusions of varying heights are formed. The antireflection structure is produced by processing the light-incident surface of the semiconductor substrate in several steps under different processing conditions. The antireflection structure is a structure in which a second protrusion, lower than the first, is formed between the first protrusions of a predetermined height. This technology can be applied, for example, to a CMOS image sensor.

[0005] The invention provides for an optical structure according to claim 1, an image sensor with an optical structure according to claim 10 and a method for manufacturing the optical structure according to claim 15. Brief description of the drawings

[0006] Aspects of the present invention are best understood with reference to the detailed description below in conjunction with the accompanying drawings. It should be noted that, in accordance with common industry practice, various elements are not drawn to scale. Rather, for the sake of clarity of discussion, the dimensions of the various elements may be arbitrarily enlarged or reduced. Fig. Figure 1A is a top view of a first configuration for a matrix of pixels of an image sensor according to an embodiment of the present invention. Fig. Figure 1B is a top view of a second configuration for a matrix of pixels of an image sensor according to an embodiment of the present invention. Fig. Figure 2A is a top view of front-side sensor components in a region of a subpixel in an exemplary structure according to an embodiment of the present invention. Fig. 2B is a vertical sectional view of the exemplary structure along the vertical plane B - B' of Fig. 2A. Fig. Figure 3 is a vertical sectional view of the exemplary structure after the fabrication of metallic connection structures produced in dielectric layers at the connection plane and the attachment of a support substrate according to an embodiment of the present invention. Fig. Figure 4 is a vertical sectional view of the exemplary structure after thinning the semiconductor substrate according to an embodiment of the present invention. Fig. Figure 5 is a vertical sectional view of the exemplary structure after the creation of deep trenches on the back side of the semiconductor substrate according to an embodiment of the present invention. Fig. Figure 6 is a vertical sectional view of the exemplary structure after removal of a hard mask layer and a dielectric pad layer according to an embodiment of the present invention. Fig. Figure 7 is a vertical sectional view of the exemplary structure after the production of a dielectric metal oxide coating and a dielectric insulating layer according to an embodiment of the present invention. Fig. Figure 8 is a vertical sectional view of the exemplary structure after the creation of deep trench isolation structures according to an embodiment of the present invention. Fig. Figure 9 is a vertical sectional view of the exemplary structure after the fabrication of an ARC layer (ARC: antireflective coating), an optical refractive layer, a dielectric grating material layer, a metallic reflective material layer and a structured photoresist layer according to an embodiment of the present invention. Fig. Figure 10A is a vertical sectional view of the exemplary structure after the fabrication of a composite grid structure according to an embodiment of the present invention. Fig. Figure 10B is a top view of the exemplary structure of Fig. 10A. The rotatable vertical plane A - A' corresponds to the plane of the vertical sectional view of Fig. 10A. Fig. Figure 11A is a vertical sectional view of the exemplary structure after the production of a masking material layer and a structured photoresist layer according to an embodiment of the present invention. Fig. Figure 11B is a top view of the exemplary structure of Fig. 11A. The rotatable vertical plane A - A' corresponds to the plane of the vertical sectional view of Fig. 11A. Fig. 11C is a vertical sectional view of the exemplary structure along the vertical plane C - C' of Fig. 11B. Fig. Figure 12A is a vertical sectional view of the exemplary structure after the production of non-planar distal surface parts on the optical refractive layer by anisotropic etching of the masking material layer and additional etching of upper parts of the optical refractive layer according to an embodiment of the present invention. Fig. Figure 12B is a top view of the exemplary structure of Fig. 12A. The rotatable vertical plane A - A' corresponds to the plane of the vertical sectional view of Fig. 12A. Fig. 12C is a vertical sectional view of the exemplary structure along the vertical plane C - C' of Fig. 12B. Fig. 12D is a scanning electron microscope (SEM) image of the top surface of an optical refractive layer of a test specimen according to an embodiment of the present invention. Fig. Figure 13A is a vertical sectional view of the exemplary structure after removal of the structured photoresist layer according to an embodiment of the present invention. Fig. Figure 13B is a top view of the exemplary structure of Fig. 13A. The rotatable vertical plane A - A' corresponds to the plane of the vertical sectional view of Fig. 13A. Fig. 13C is a vertical sectional view of the exemplary structure along the vertical plane C - C' of Fig. 13B. Fig. Figure 14 is a vertical sectional view of the exemplary structure after the production of an optically transparent layer, color filters and lenses according to an embodiment of the present invention. Fig. Figure 15A is a vertical sectional view of the exemplary structure after removal of the support substrate according to an embodiment of the present invention. Fig. 15B is another vertical sectional view of the exemplary structure of Fig. 15A. Fig. Figure 16 is a flowchart of an exemplary process flow for manufacturing an image sensor according to an embodiment of the present invention. Detailed description

[0007] The following description provides many different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present invention. For example, the fabrication of a first element above or on top of a second element in the following description may include embodiments in which the first and second elements are fabricated in direct contact, and it may also include embodiments in which additional elements can be fabricated between the first and second elements such that the first and second elements are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in the various examples in the present invention.This repetition serves the purpose of simplicity and clarity and does not in itself prescribe any relationship between the various designs and / or configurations discussed.

[0008] Furthermore, spatially relative terms, such as "located below," "under," "lower," "located above," "upper," and the like, can be used here to simply describe the relationship of an element or structure to one or more other elements or structures depicted in the figures. These spatially relative terms are intended to encompass orientations of the device in use or operation beyond the orientation shown in the figures. The device may be oriented differently (rotated by 90 degrees or in a different orientation), and the spatially relative descriptors used here can be interpreted accordingly.

[0009] In general, the structures and methods of the present invention can be used to provide an image sensor with a higher quantum yield, which is the fraction of photons that generate an electron-hole pair among all photons that strike a photoreactive material component. An optical refractive layer with a random surface roughness is used to generate random refraction of photons striking a light sensor, thereby increasing the quantum yield of the light sensor.

[0010] A refractive structure in the optical path of photons in an image sensor can have a beneficial effect by increasing the probability of photon absorption in the light sensor. For example, ZY Wang et al., in the article "Broadband optical absorption by tunable Mie resonances in silicon nanocone arrays" (Scientific Reports, Vol. 5, Article number: 7810, 2015), describe how an array of refractive column structures can increase the absorption coefficient for photons of different wavelengths in the optical range. However, fabricating such a periodic array of columns requires lithographic structuring of periodic structures using DUV lithography (DUV: deep ultraviolet) and can therefore be a costly process.Embodiments of the present invention provide a random refractive surface with random protrusions and transverse dimensions on the order of 100 nm, generated by an anisotropic etching process. Process inconsistencies leading to local variations in etch thickness in a masking material layer are amplified in a deeper optically transparent material by using an etching chemical that etches the optically transparent material at a higher etch rate than the masking material. The resulting random refractive surface is placed in the optical path of incident photons in an image sensor to improve the quantum efficiency of the image sensor.

[0011] In the Fig. 1A and Fig. Figure 1B shows a first configuration of a matrix of 1000 pixels of 900 of an image sensor and a second configuration of the matrix of 1000 pixels of the image sensor, each shown in a top view. The image sensor can be a back-illuminated image sensor device (BSI image sensor device). However, it should be understood that embodiments of the invention can also be used in a front-illuminated image sensor (FSI image sensor).

[0012] Each pixel (900) represents the smallest unit of area used to generate an image from the image sensor. The area with a matrix of 1000 pixels (900) is referred to here as a pixel matrix area. The pixels (900) in the pixel matrix area can be arranged in rows and columns. For example, the pixel matrix area can contain M rows and N columns, where M and N are integers in the range from 1 to 2. 16 e.g. 2 8 up to 2 14The rows of pixels 900 can be numbered consecutively with integers from 1 to M, and the columns of pixels 900 can be numbered consecutively with integers from 1 to N. A pixel Pij refers to a pixel 900 in the i-th row and in the j-th column.

[0013] Each Pixel 900 comprises at least one light sensor configured to detect radiation of a given wavelength range. Each Pixel 900 can comprise a plurality of light sensors configured to detect radiation of a respective wavelength range, which may differ between the multiple light sensors. In one embodiment, each Pixel 900 can comprise a plurality of subpixels, each comprising a corresponding combination of a light sensor and an electronic circuit configured to detect radiation incident on the light sensor.For example, a Pixel 900 might include: a subpixel configured to detect radiation in a red wavelength range (such as 635 nm to 700 nm); a subpixel configured to detect radiation in a green wavelength range (such as 520 nm to 560 nm); and a subpixel configured to detect radiation in a blue wavelength range (such as 450 nm to 490 nm). These subpixels are referred to as a red subpixel, a green subpixel, and a blue subpixel, respectively.

[0014] In general, a Pixel 900 generates information upon incident radiation for one detection area unit. A subpixel generates information about the intensity of the incident radiation in a specific wavelength range detected within that area of ​​the detection area unit. A monochromatic Pixel 900 can comprise only one subpixel. A Pixel 900 configured to detect a spectral distribution of incident radiation comprises multiple subpixels with at least two distinct detection wavelength ranges. Light sensors within a pixel matrix area can include photodiodes, CMOS image sensors (CMOS: complementary metal oxide semiconductor), CCD sensors (CCD: charge-coupled device), active sensors, passive sensors, other suitable sensors, or a combination thereof.

[0015] In the Fig. 2A and Fig. Figure 2B shows front-side sensor components 600 in the areas of a subpixel in an image sensor. A semiconductor substrate 500 has a substrate semiconductor layer 601. The front-side sensor components 600 comprise all components of the image sensor that can be fabricated on a front side 609 of the semiconductor substrate 500 or in the substrate semiconductor layer 601. Each subpixel has a light sensor and sensor circuitry for the light sensor. A group of subpixels can be used for a pixel, and a matrix 1000 of pixels can be arranged as shown in Fig. 1A or Fig. 1B is shown, or it can be arranged in another matrix configuration suitable for providing an image sensor.

[0016] Each subpixel can be fabricated on or in the substrate semiconductor layer 601, which has a front side 609 and a back side. The substrate semiconductor layer 601 comprises a semiconductor material, such as silicon or germanium, a silicon-germanium alloy, a compound semiconductor material, or another semiconductor material, having a band gap not greater than the energy of the photons to be detected. The material in the substrate semiconductor layer 601 can be selected based on the energy range of the photons to be detected by the subpixel. In one embodiment, the substrate semiconductor layer 601 can be single-crystal silicon. A commercially available single-crystal semiconductor substrate can be used for the semiconductor substrate 500. The semiconductor substrate 500 provided at this processing stage has a thickness sufficient to withstand normal CMOS processing steps.The thickness of the semiconductor substrate 500 can be, for example, 200 µm to 1 mm, but smaller and larger thicknesses can also be used.

[0017] An upper portion of the substrate semiconductor layer 601 can be suitably doped to have a first conductivity type, which can be p or n. For example, an epitaxial semiconductor deposition process can be carried out to fabricate a single-crystal epitaxial semiconductor material layer on an upper portion of the substrate semiconductor layer 601 such that the atomic concentration of the dopants of the first conductivity type is 1.0 x 10 13 / cm 3 up to 1.0 x 10 16 / cm 3 The concentration is typically 1 µm, but lower and higher atomic concentrations can also be used. The thickness of the single-crystal epitaxial semiconductor material layer can range from 1 µm to 10 µm.

[0018] To create areas where STI structures 620 (STI: shallow trench insulation) can later be fabricated, first-conductivity-type wells 607 can be produced by ion implantation. The atomic concentration of the first-conductivity-type dopants in the first-conductivity-type wells 607 can be 1.0 x 10 15 / cm 3 up to 1.0 x 10 18 / cm 3 The concentrations can be higher, but lower and higher atomic concentrations can also be used. The STI 620 structures can be fabricated to provide electrical insulation against the various components within the subpixel.

[0019] Gate structures (614, 605, 615) can be fabricated on the front face 609 of the semiconductor substrate 500 by depositing and structuring a layer stack comprising a dielectric gate layer and a gate electrode layer. Each structured part of the layer stack represents a gate structure (614, 605, 615), which includes a transfer gate structure (614, 605) and control gate structures (614, 615). The transfer gate structure (614, 605) is the gate structure for a transfer transistor 630 and comprises a stack of a gate dielectric 614 and a transfer gate electrode 605.The control gate structures (614, 615) each comprise a corresponding layer stack of a gate dielectric 614 and a gate electrode 615 of other transistors in a sensor circuit, which may include a reset transistor 640, a source follower transistor 650, a selection transistor 660 and other suitable transistors that can be used to amplify the signal generated by the light sensor of the subpixel.

[0020] The dopants of the second conductivity type can be implanted through the front face 609 of the semiconductor substrate 500 using at least one masked ion implantation process. The second conductivity type is the opposite of the first conductivity type. For example, if the first conductivity type is p, the second conductivity type is n, and vice versa. Using the at least one masked ion implantation process, various doped regions with doping of the second conductivity type can be fabricated. Beneath the front face 609 of the semiconductor substrate 500, a pinned second-conductivity-type photodiode layer 602 can be fabricated such that, in a top view, a periphery of the pinned second-conductivity-type photodiode layer 602 overlaps with an edge of the transfer-gate electrode 605.Several active regions (608, 612) can be fabricated with a second conductivity doping, comprising a floating diffusion region 608 that functions as a drain region of the transfer transistor 630. The pinned second-conductivity photodiode layer 602, which stores electrical charges (such as electrons when the second conductivity is n) during scanning (i.e., while the subpixel actively detects incident photons, for example, to take pictures), functions as a source region of the transfer transistor 630. The active regions 612 comprise the source and drain regions of the various transistors (640, 650, 660) in the sensor circuit.

[0021] A first-conductivity-type pinning photodiode layer 603 can be fabricated by ion implantation of first-conductivity-type dopants directly onto the pinned second-conductivity-type photodiode layer 602. The first-conductivity-type pinning photodiode layer 603 can suppress the depletion of the interface between the pinned second-conductivity-type photodiode layer 602 and the first-conductivity-type pinning photodiode layer 603 and electrically stabilizes the pinned second-conductivity-type photodiode layer 602.

[0022] Dielectric interconnection layer layers 670 can be fabricated on the front surface 609 of the semiconductor substrate 500, and metallic interconnection structures 680 (comprising a metallic conduction structure 684 and a metallic via structure 682) can be fabricated in each subpixel to connect various nodes of the transistors (630, 640, 650, 660). The dielectric interconnection layer layers 670 can comprise a specific dielectric material, such as undoped silicate glass, doped silicate glass, organosilicate glass, a porous dielectric material, or combinations thereof. Optionally, dielectric coatings comprising various dielectric materials, such as silicon nitride, silicon oxide nitride, silicon oxide carbide, and / or dielectric metal oxides, can be used in the dielectric interconnection layer layers 670.The metallic interconnection structures 680 can comprise various metallic via structures 682 and various metallic conduction structures 684. For example, the floating diffusion region 608 can be connected to the gate electrode 615 of the source follower transistor 650 by means of a subset of the metallic interconnection structures 680. A light sensor can include a transfer transistor 630 and can be connected to a sensor circuit comprising further transistors (640, 650, 660).

[0023] In Fig. 3. Additional dielectric interconnect layer layers 670 and additional metallic interconnect structures 680 can be fabricated on the front face 609 of the semiconductor substrate 500. A front face of a group consisting of the semiconductor substrate 500, the dielectric interconnect layer layers 670, and the fabricated structures can be bonded to a support substrate 690. The support substrate 690 can be temporarily attached to the group consisting of the semiconductor substrate 500 and the dielectric interconnect layer layers 670 to allow subsequent thinning of the semiconductor substrate 500 and subsequent handling of a group consisting of a thinned semiconductor substrate 500 and the dielectric interconnect layer layers 670. The support substrate 690 can be a semiconductor material, an insulating material or a metallic material and can have a thickness of 300 µm to 1 mm, but smaller and larger thicknesses can also be used.

[0024] Any suitable bonding method can be used to bond the support substrate 690 to the front face of the dielectric interconnection layer layers 670. Examples of bonding methods that can be used to bond the support substrate 690 to the dielectric interconnection layer layers 670 include oxide-oxide bonding, oxide-semiconductor bonding, fusion bonding, hybrid bonding, anodic bonding, direct bonding, other suitable bonding methods, and / or combinations thereof. Other suitable bonding methods may also be used within the intended scope of protection of the invention. Optionally, a bond buffer layer 689 comprising an intermediate bonding material (e.g., silicon oxide, silicon nitride, or a semiconductor material) can be used to create a bond between the dielectric interconnection layer layers 670 and the support substrate 690.

[0025] In Fig. 4. The back side of the semiconductor substrate 500 can be thinned, for example, by grinding, polishing, isotropic etching, and / or anisotropic etching. The support substrate 690 can mechanically support the semiconductor substrate 500 during the thinning process. In one embodiment, the semiconductor substrate 500 can be thinned to a thickness of 1 µm to 12 µm, e.g., 1.5 µm to 8 µm. The semiconductor substrate 500, thinned after the thinning process, is referred to here as a thinned semiconductor substrate 510 or simply as a semiconductor substrate 500. The thickness of the thinned semiconductor substrate 510 can be determined by the maximum depth of deep grooves that are subsequently to be produced on the back side of the thinned semiconductor substrate 510.In one embodiment, the thickness of the thinned semiconductor substrate 510 can be selected such that the deep grooves to be subsequently produced on the back side of the thinned semiconductor substrate 510 reach proximal surfaces of the STI structures 620. A back side 709 of the thinned semiconductor substrate 510 can be polished to provide a planar horizontal surface parallel to the front side 609 of the thinned semiconductor substrate 510. The exemplary structure can then be turned over for further processing.

[0026] In Fig. An optional dielectric pad layer 711 and a hard mask layer 712 can be fabricated over the back surface 709 of the semiconductor substrate 510. The optional dielectric pad layer 711, if present, can comprise a silicon oxide layer and can have a thickness of 5 nm to 50 nm. The hard mask layer 712 comprises an etch mask material that can subsequently be selectively removed for the dielectric pad layer 711 and / or for the semiconductor substrate 510. The hard mask layer 712 can, for example, comprise silicon nitride, borosilicate glass, or a metallic material. The hard mask layer 712 can have a thickness of 50 nm to 800 nm, but smaller and larger thicknesses can also be used.

[0027] A photoresist layer (not shown) can be deposited over the hard mask layer 712. This photoresist layer can be lithographically patterned to create openings that generally reproduce the structure of the underlying STI structures 620. A first etching process can be performed to transfer the structure in the photoresist layer through the hard mask layer 712 and the optional dielectric pad layer 711. Unmasked portions of the semiconductor substrate 510 can be etched by performing a second anisotropic etching process, which transfers the structure of the openings in the photoresist layer and the hard mask layer 712 through the semiconductor substrate 510 to a top surface of one of the respective STI structures 620. The depth of deep trenches 719 can range from 1 µm to 10 µm, e.g., 1.5 µm to 8 µm. The photoresist layer can be completely consumed during the second anisotropic etching process.The deep trenches 719 can be created by the semiconductor substrate 510.

[0028] The deep trenches 719 can define areas for subpixels 800. Each subpixel 800 can be located in a respective subpixel area, which is itself located within a region of a pixel, i.e., a pixel area. A region of a pixel can, for example, include a region of a first subpixel 801, a region of a second subpixel 802, and a region of a third subpixel 803. In an illustrative example, the first subpixel 801 can be manufactured in a region containing a light sensor configured to detect green light; the second subpixel 802 can be manufactured in a region containing a light sensor configured to detect red light; and the third subpixel 803 can be manufactured in a region containing a light sensor configured to detect blue light.Each subpixel 800 can have a volume containing a structured columnar portion of the semiconductor substrate 510, which may be laterally enclosed by a contiguous group of deep trenches 719. A pixel area of ​​a pixel comprises all subpixel areas for the group of subpixels 800 contained in the pixel.

[0029] In Fig. 6. The hard mask layer 712 can be selectively removed to reveal the semiconductor substrate 510, the dielectric pad layer 711, and the STI structures 620. As an illustrative example, if the hard mask layer 712 contains silicon nitride, a wet etching process using hot phosphoric acid can be performed to remove the hard mask layer 712. Subsequently, the dielectric pad layer 711 can be selectively removed to reveal the semiconductor substrate 510.

[0030] In Fig. A dielectric metal oxide coating 721 can be conformally deposited over the physically exposed surfaces of the semiconductor substrate 510. The dielectric metal oxide coating 721 can be produced on the sidewalls of the deep trenches 719, on the back side 709 of the semiconductor substrate 510, and on the surfaces of the STI structures 620 when the STI structures 620 are physically exposed to the deep trenches 719. The dielectric metal oxide coating 721 is a dielectric metal oxide material with a dielectric constant greater than 7.9 (i.e., a high-k dielectric material). Other suitable high-k dielectric materials can also be used. For example, high-k dielectric materials can have a dielectric constant of 7.9 to 100.Exemplary dielectric metal oxide materials that can be used for the dielectric metal oxide coating 721 are hafnium oxide, aluminum oxide, zirconium oxide, magnesium oxide, calcium oxide, yttrium oxide, tantalum oxide, strontium oxide, titanium oxide, lanthanum oxide, barium oxide, or combinations thereof. Other suitable materials are also within the intended scope of protection of the invention. The dielectric metal oxide coating 721 can be deposited by chemical vapor deposition (CVD) or atomic layer deposition (ALD). The thickness of the dielectric metal oxide coating 721 can be from 2 nm to 6 nm, but smaller and larger thicknesses can also be used.

[0031] The dielectric metal oxide coating 721 can be manufactured to trap negative charges. For example, the dielectric metal oxide coating 721 can be deposited with a non-stoichiometric, oxygen-rich composition, or it can be surface-treated with plasma to create a non-stoichiometric, oxygen-rich surface density. In this case, the dielectric metal oxide coating 721 can exhibit an oxygen-rich dielectric metal oxide material with negatively charged interstitial oxygen atoms and / or free or dissolved metal oxide bonds, thereby storing negative charges within the dielectric metal oxide coating 721. As an illustrative example, the areal density of the stored negative charges in the dielectric metal oxide coating 721 can be 5.0 x 10 9 electrons / cm 2 up to 1.0 x 10 14 electrons / cm 2 e.g. 1.0 x 10 10 electrons / cm2 up to 2.0 x 10 13 electrons / cm 2 The dielectric metal oxide material used in the metal oxide coating 721 can store more negative charges than other dielectric materials, such as silicon nitride or silicon oxide. The negative charge in the dielectric metal oxide coating 721 increases the accumulation of holes in the interface portions of the first-conductivity-type wells 607 and the substrate semiconductor layer 601 of the semiconductor substrate 510. A depletion region can form in portions of the first-conductivity-type wells 607 and the substrate semiconductor layer 601 of the semiconductor substrate 510 that are located near the dielectric metal oxide coating 721. The depletion region reduces dark current and / or white pixels for the image sensor.

[0032] A dielectric insulating layer 722 can be produced by conformal deposition of a dielectric material in the remaining volumes of the deep trenches 719. The dielectric insulating layer 722 comprises a dielectric material such as undoped silicate glass, a doped silicate glass (such as borosilicate glass), or a combination thereof. A combination of the dielectric metal oxide coating 721 and the dielectric insulating layer 722 can fill the deep trenches 719 (with or without seams and / or encapsulated cavities).

[0033] In Fig. 8 Horizontal portions of the dielectric insulating layer 722 and the dielectric metal oxide coating 721 can be removed from the top surface of the back surface 709 of the semiconductor substrate 510 by a planarization process. Recess etching and / or chemical-mechanical polishing can be used to remove the horizontal portions of the dielectric insulating layer 722 and the dielectric metal oxide coating 721. In one embodiment, the dielectric metal oxide coating 721 can be used as an etch stop layer during recess etching, in which the horizontal portions of the dielectric insulating layer 722 are removed, or as a stop layer during chemical-mechanical polishing, in which the horizontal portions of the dielectric insulating layer 722 are removed.The horizontal portions of the dielectric metal oxide coating 721, located above the back surface 709 of the semiconductor substrate 510, can subsequently be removed by performing an isotropic etching process (such as a wet etching process) in which the material of the dielectric metal oxide coating 721 is selectively etched to the semiconductor material of the semiconductor substrate 510. Remaining vertical portions of the dielectric metal oxide coating 721 and the dielectric insulating layer 722 fill the deep grooves 719 and are referred to here as STI structures 720.

[0034] In Fig. 9 an optional ARC layer 732 (ARC: anti-reflective coating), an optical refractive layer 734, a dielectric lattice material layer 742L and a metallic reflective material layer 744L can be deposited successively over the back side 709 of the semiconductor substrate 510.

[0035] The optional ARC layer 732 can incorporate an antireflective coating material that reduces reflection between the semiconductor material of the semiconductor substrate 510 and the material layer above it, i.e., the optical refractive layer 734. The optional ARC layer 732, if present, can have a refractive index between that of the semiconductor material of the semiconductor substrate 510 and that of the optical refractive layer 734. The optional ARC layer 732 can comprise a single layer of material or a stack of multiple layers with progressively changing refractive indices. The optional ARC layer 732 incorporates an optically transparent material and can be a semiconductor material, an insulating material, a conductive material, and / or a polymer material. The ARC layer 732 can have a thickness of 50 nm to 300 nm, but smaller and larger thicknesses are also possible.

[0036] The optical refractive layer 734 can comprise a semiconductor material (such as silicon, germanium, a silicon-germanium alloy, or a III-V compound semiconductor material) or a dielectric material (such as silicon oxide, silicon nitride, silicon nitride, or a dielectric metal oxide such as aluminum oxide). The optical refractive layer 734 can comprise a material that is conducive to the generation of high aspect ratio trenches during a subsequent anisotropic etching process. The optical refractive layer 734 can be fabricated as a non-structured (protective) material layer with two horizontal planar surfaces that are parallel to the back surface 709 of the semiconductor substrate 510. The distal surface of the optical refractive layer 734 can be one of the two horizontal planar surfaces of the optical refractive layer 734 that is farther away from the semiconductor substrate 510, i.e.,, a top surface of the optical refractive layer 734, be.

[0037] The dielectric lattice material layer 742L can comprise a dielectric material such as silicon dioxide, a porous dielectric material, a polyimide, or another suitable dielectric material. The thickness of the dielectric lattice material layer 742L can range from 50 nm to 500 nm, but smaller and larger thicknesses are also possible. The metallic reflective material layer 744L can comprise a metallic material that offers a high degree of reflectivity. For example, the metallic reflective material layer 744L can comprise silver, aluminum, copper, gold, or another highly reflective metallic material. The thickness of the metallic reflective material layer 744L can range from 50 nm to 500 nm, but smaller and larger thicknesses are also possible.

[0038] A photoresist layer 747 can be applied over the metallic reflective material layer 744L. This photoresist layer can be lithographically structured to create openings in regions of the pinned second-conductivity-type photodiode layers 602, i.e., in the regions of the light sensors that have a respective pn junction between the pinned second-conductivity-type photodiode layers 602 and the first-conductivity-type wells 607. The regions of the transistors of the sensor circuit (such as the reset transistors 640, the source follower transistors 650, and the select transistors 660) may or may not be covered by the photoresist layer 747.

[0039] In the Fig. 10A and Fig. In step 10B, portions of the dielectric lattice material layer 742L and the metallic reflective material layer 744L that are not masked by the structured portions of the photoresist layer 747 can be etched to create openings. Remaining portions of the dielectric lattice material layer 742L form a dielectric lattice structure 742, and remaining portions of the metallic reflective material layer 744L form a metallic lattice structure 744. The stack of the dielectric lattice structure 742 and the metallic lattice structure 744 forms a lattice structure 740, which is also referred to as a composite lattice structure.

[0040] The lattice structure 740 can be located over the peripheries of the pinned second-conductivity-type photodiode layers 602 and can define a light collection area for each light sensor arranged in a respective subpixel 800. A pixel 900 can comprise a group of subpixels configured to detect light of different wavelengths. Each pixel 900 can be located in a respective pixel area containing a group of subpixels 800. For example, each pixel 900 can comprise at least one instance of a first subpixel 801, at least one instance of a second subpixel 802, and at least one instance of a third subpixel 803.In the example shown, a pixel can comprise: a first subpixel 801 (such as a green subpixel) located in a first subpixel region; two second subpixels 802 (such as two red subpixels) located in two second subpixel regions; and a third subpixel 803 (such as a blue subpixel) located in a third subpixel region. Typically, a pixel 900 can comprise various combinations of at least two types of subpixels 800 configured to detect light with different wavelength ranges. Alternatively, an image sensor can be a monochromatic image sensor with only one type of subpixel 800. In this case, each pixel 900 can comprise only one subpixel 800.

[0041] In general, the grating structure 740 comprises at least one metallic grating structure 744 having reflective sidewalls. The grating structure 740 can be a composite grating structure with a vertical stack of a metallic grating structure 744 with reflective sidewalls and a dielectric grating structure 742. The grating structure 740 can be fabricated over the distal surface of the optical refractive layer 734. The grating structure 740 has openings located over each of the light sensors 630. The portions of the distal surface of the optical refractive layer 734 that are contacted by the undersides of the grating structure are planar distal surface portions of the distal surface of the optical refractive layer 734.The parts of the distal surface of the optical refractive layer 734 that do not contact the grating structure 740 can be additionally recessed vertically during the anisotropic etching process for structuring the grating structure in relation to the horizontal plane that includes the bottom of the grating structure.

[0042] The lattice structure 740 can subdivide each subpixel 800 into a detector region and a sensor circuit region. For example, a first subpixel 801 can have a first detector region 801D located above the pinned secondary conductivity-type photodiode layer 602 of the first subpixel 801, and a first sensor circuit region 801S located above the sensor circuit (640, 650, 660) of the first subpixel 801. A second subpixel 802 can have a second detector region 802D located above the pinned secondary conductivity-type photodiode layer 602 of the second subpixel 802, and a second sensor circuit region 802S located above the sensor circuit (640, 650, 660) of the second subpixel 802.A third subpixel 803 can have a third detector area 803D located above the pinned second-conductivity-type photodiode layer 602 of the third subpixel 803, and a third sensor circuit area 803S located above the sensor circuit (640, 650, 660) of the third subpixel 803. Typically, the group of all subpixels 800 in a pixel 900 can be arranged in any structure that facilitates periodic repetition of the pixels 900 in the matrix 1000 of the pixels 900.

[0043] In the Fig. In steps 11A to 11C, a masking material layer 750L can be deposited over the grating structure 740 and the optical refractive layer 734. The masking material layer 750L can be composed of a material that can be etched with local etch rate changes in a subsequent anisotropic etching process. For example, the masking material layer 750L can be composed of a material that can be deposited with significant thickness changes during a deposition process, such as a physical vapor deposition process in which a material with particle size changes is deposited. Additionally or alternatively, the masking material layer 750L can be composed of a material that allows a higher etch rate at grain boundaries. Additionally or alternatively, the masking material can be a material that exhibits pitting corrosion properties during a subsequent anisotropic etching process.Additionally or alternatively, the masking material can be a material that exhibits a significant etch rate dependence on local plasma conditions during a subsequent anisotropic etching process. In general, the 750L masking material layer is composed of a material with an unstable etch rate during a subsequent etching process, resulting in significant local thickness variations during such a process.

[0044] The masking material layer 750L can comprise a metallic material, a semiconductor material, or a dielectric material. If a metallic material is used for the masking material layer 750L, it can comprise a conductive metallic top layer, such as TiN, TaN, or WN, or a metallic material, such as Ti, Ta, or W, or a stack of at least two metallic materials. Other suitable materials are also within the intended scope of protection of the invention. In an illustrative example, the masking material layer 750L can comprise a stack of a titanium nitride layer and a titanium layer. The thickness of the horizontal portion of the masking material layer 750L can be from 20 nm to 100 nm, but smaller and larger thicknesses can also be used.

[0045] A photoresist layer 757 can be applied over the masking material layer 750L and lithographically structured to create openings in the detector areas (801D, 802D, 803D) and in the masking areas of the sensor circuit areas (801S, 802S, 803S). During a subsequent anisotropic etching process, the structured portions of the photoresist layer 757 are located above and protect deeper portions of the masking material layer 750L. In one embodiment, edges of the structured portions of the photoresist layer 757 can be located over the areas of the grid structure 740.

[0046] In the Fig. In sections 12A to 12C, the masking material layer 750L can be anisotropically etched by performing an anisotropic etching process, such as a reactive ion etching process. The chemicals used in the anisotropic etching process can be selected to induce random changes in the etch rate across the masking material layer 750L. The causes of these random etch rate changes can include the grain structure of the masking material layer 750L, local variations in the material composition, high sensitivity of the etch rate to local plasma conditions, pitting corrosion during the etching process, plasma sensitivity to local charge storage, or combinations thereof. Different regions of the optical refractive layer 734 can be physically exposed at different times during the anisotropic etching process due to these etch rate changes across the masking material layer 750L.

[0047] The chemicals for the anisotropic etching process can be selected such that the material of the optical refractive layer 734 is additionally etched, and that non-planar distal surface parts 734N with random protrusions 734R are formed on physically exposed parts of the optical refractive layer 734. In general, the non-planar distal surface parts 734N can be produced on the optical refractive layer 734 by anisotropically etching the masking material layer 750L and additionally etching upper parts of the optical refractive layer 734 in a final step of the anisotropic etching process.

[0048] Although a deployment in Fig. Figure 12A shows a type of vertical cross-sectional profile for the random projections 734R in the non-planar distal surface portions 734N of the optical refractive layer 734. Herein, embodiments in which the random projections 734R have different vertical cross-sectional profiles are expressly considered. Generally, changes to the vertical cross-sectional profile of the random projections 734R can be achieved by selecting the material in the masking material layer 750L and the etching chemicals used to etch the masking material layer 750L and the optical refractive layer 734.

[0049] In one embodiment, trenches of varying depths can be created in the optical refractive layer 734 by etching physically exposed portions of the optical refractive layer 734 at a higher etch rate than that of the masking material layer 750L. In other words, portions of the optical masking material layer 750L that are physically exposed before the completion of the anisotropic etching process can be etched during the anisotropic etching process at a higher etch rate than the masking material layer 750L itself.

[0050] In one embodiment, the random projections 734R can have a mean transverse dimension of 10 nm to 200 nm. A mean transverse dimension refers to the diameter of an equivalent circle having the same area as the random projection 734R. In another embodiment, the random projections 734R have a mean vertical dimension of 10 nm to 100 nm. A mean vertical dimension refers to the height of a cylindrical shape having the same cross-sectional shape and volume as the random projection 734R.

[0051] Typically, the optical refractive layer 734 can be arranged on the back side 709 of the semiconductor substrate 510. The optical refractive layer 734 has a first refractive index and features planar distal surface parts and non-planar distal surface parts 734N with random projections 734R. The planar distal surface parts are surface parts that contact the underside of the lattice structure 740, and they can have the same areas as the underside of the lattice structure 740. In one embodiment, the non-planar distal surface parts 734N can each have an area overlap with one of the light sensors 630 in a top view, i.e., in a view along a direction perpendicular to the back side 709 of the semiconductor substrate 510.

[0052] Unetched portions of the masking material layer 750L can form an array of masking structures 750 after the anisotropic etching process. In one embodiment, the array of masking structures 750 can be located outside of areas of the non-planar distal surface portions 734N of the optical refractive layer 734. The array of masking structures 750 can have sidewalls that are located above and in contact with a respective portion of a top surface of the lattice structure 740. In one embodiment, each masking structure 750 in the array of masking structures 750 can be located above one of the sensor circuits (640, 650, 660) and can have an area overlap with it in a top view. In one embodiment, edges of the masking structures 750 can be located on the top surface of the lattice structure 740.In one embodiment, the masking structures 750 do not contact, or are not arranged above, the first side walls of the grid structure 740 that point towards each of the openings in the grid structure 740, but instead they contact second side walls of the grid structure 740 that point away from one of the most proximal openings in the grid structure 740. Each area enclosed by an adjacent group of second side walls of the grid structure 740 can be located in one of the respective sensor circuit areas (801S, 802S, 803S).

[0053] Fig. Figure 12D shows a scanning electron microscope (SEM) image of the top surface of an optical refractive layer 734 of a test specimen after the creation of random protrusions 734R. The random protrusions 734R in the optical refractive layer 734 can have random shapes and a random size distribution and / or a random distance between adjacent pairs of random protrusions 734R.

[0054] In the Fig. Figures 13A to 13C show exemplary structures after removal of the structured photoresist layer 757. Removal of the structured photoresist layer 757 can be achieved, for example, by peeling it off.

[0055] In Fig. 14. An optically transparent layer 770 with a planar top surface can be produced over the lattice structure 740. The optically transparent layer 770 can be produced by depositing a self-planarizing dielectric material, such as a flowable oxide (FOX). Alternatively, an optically transparent dielectric material can be deposited and planarized, for example, by chemical-mechanical planarization, to produce the optically transparent layer 770.

[0056] The optically transparent layer 770 extends vertically through the openings in the lattice structure 740 and has a second refractive index that differs from the first. The optically transparent layer 770 can be fabricated on the non-planar distal surface portions 734N of the optical refractive layer 734. Thus, the non-planar interface between the optically transparent layer 770 and the non-planar distal surface portions 734N of the optical refractive layer 734 allows for random refraction of photons incident on the underlying light sensor 630, and it can increase the quantum efficiency of the light sensors 630 in the image sensor.

[0057] Various color filter materials can be applied over the optically transparent layer 770 and structured to create different color filters 780. These color filters 780 can include: color filters 781 of a first type, produced in the regions of the first subpixels 801; color filters 782 of a second type, produced in the regions of the second subpixels 802; and color filters 783 of a third type, produced in the regions of the third subpixels 803. The composition of each color filter material can be selected such that light within a specified wavelength range passes through the color filter material, while light outside the specified wavelength range is absorbed by the color filter material.

[0058] Optical lenses 790 can be produced over the color filters 780 by applying an optically transparent material over the color filters 780 and by structuring the optically transparent material into material parts with convex surfaces that are centered on one of the openings in the grid structure 740 located below.

[0059] In the Fig. 15A and Fig. In step 15B, the support substrate 690 and the bond buffer layer 689 (if present) can be detached from the dielectric interconnect layer layers 670. The semiconductor substrate 510 and the component structures located on it can be separated into discrete image sensors before or after the support substrate 690 is detached from the semiconductor substrate 510.

[0060] In general, a matrix of 1000 pixels can be fabricated on the semiconductor substrate 510. Each pixel in the matrix of 1000 pixels has at least one subpixel, and each subpixel has a respective light sensor 630 and a respective sensor circuit (640, 650, 660) arranged on a front face 609 of the semiconductor substrate 510. The optically transparent layer 770 can be arranged over the arrangement of masking structures 750.

[0061] In Fig.Figure 16 provides a conventional method for fabricating an image sensor according to an embodiment of the present invention. In step 1610, light sensors 630 can be fabricated on a front side of a semiconductor substrate 500. In step 1620, an optical refractive layer 734 with a first refractive index can be fabricated on a back side of the semiconductor substrate 510, which can be thinned after the fabrication of the light sensors 630 and before the fabrication of the optical refractive layer 734. In step 1630, a lattice structure 740 can be fabricated over a distal surface of the optical refractive layer 734, which can be a planar horizontal surface (i.e., top side) that is removed from the semiconductor substrate 510. The lattice structure 740 has openings located over each of the light sensors 630.In step 1640, a masking material layer 750L can be produced over the lattice structure 740 and the optical refractive layer 734. In step 1650, the masking material layer 750L can be anisotropically etched using an anisotropic etching process, in which the material of the optical refractive layer 734 is additionally etched, producing non-planar distal surface parts 734N that have random protrusions 734R on physically exposed parts of the optical refractive layer 734. In step 1660, an optically transparent layer 770 with a second refractive index different from the first refractive index can be produced on the non-planar distal surface parts 734N of the optical refractive layer 734.

[0062] In all drawings and according to various embodiments of the present invention, an optical structure and a method for fabricating the optical structure are provided, which provides an optical refractive layer of an image sensor for lengthening a photon path of light incident on the image sensor. By lengthening the photon path, light absorption can be increased to improve the quantum efficiency of the image sensor.

[0063] According to one embodiment of the present invention, an optical structure is provided which has front-side sensors 600 (which may include a transfer transistor 630) and can be connected to a sensor circuit which includes further transistors (640, 650, 660) arranged on a front side of a semiconductor substrate 510.The optical structure further comprises: an optical refractive layer 734 arranged on a back side of the semiconductor substrate 510, having a first refractive index and planar distal surface parts and non-planar distal surface parts 734N with random projections 734R; a lattice structure 740 arranged on the planar distal surface parts and having openings located over the non-planar distal surface parts 734N; and an optically transparent layer 770 extending vertically through the openings in the lattice structure 740, contacting the non-planar distal surface parts 734N and having a second refractive index different from the first, thereby providing a refractive interface with the non-planar distal surface parts 734N that refracts incident light in random directions.

[0064] According to a further embodiment of the present invention, an image sensor is provided comprising: a matrix 1000 of pixels 900 arranged on a semiconductor substrate 510, wherein each pixel 900 in the matrix 1000 of pixels 900 has at least one subpixel 800 and each subpixel 800 has a respective front-side sensor 600 (which may include a transfer transistor 630) and may be connected to a sensor circuit comprising further transistors (640, 650, 660) arranged on a front side 609 of the semiconductor substrate 510;an optical refractive layer 734 arranged on a back side of the semiconductor substrate 510, having a first refractive index and comprising planar distal surface parts and non-planar distal surface parts 734N with random projections 734R, each of the non-planar distal surface parts 734N having a surface overlap with one of the light sensors 630 in a top view; a lattice structure 740 arranged on the planar distal surface parts and having openings located over the non-planar distal surface parts 734N; and an optically transparent layer 770 extending vertically through the openings in the lattice structure 740 and having a second refractive index different from the first refractive index.

[0065] According to a further embodiment of the present invention, a method for producing an optical structure comprises a step for producing light sensors 630 on a front side of a semiconductor substrate 510. The method further comprises a step for producing an optical refractive layer 734 with a first refractive index on a back side of the semiconductor substrate. The method further comprises a step for producing a lattice structure 740 with openings arranged over each of the light sensors on a distal surface of the optical refractive layer 734. The method further comprises a step for producing a masking material layer 750L over the lattice structure 740 and the optical refractive layer 734.The process further comprises a step for anisotropic etching of the masking material layer 750L with an anisotropic etching process in which, in addition, a material of the optical refractive layer 734 is etched and non-planar distal surface parts are produced which have random protrusions on physically exposed parts of the optical refractive layer 734; and a step for producing an optically transparent layer 770 with a second refractive index different from the first refractive index on the non-planar distal surface parts of the optical refractive layer 734.

Claims

[1] Optical structure with: Light sensors (630) arranged on a front side of a semiconductor substrate (510); an optical refractive layer (734) arranged on a back side of the semiconductor substrate (510), having a first refractive index and having planar distal surface parts and non-planar distal surface parts with random protrusions; a lattice structure (740) arranged on and in contact with the planar distal surface parts and having openings arranged over the non-planar distal surface parts; an optically transparent layer (770) extending vertically through the openings in the lattice structure (740), contacting the non-planar distal surface parts and having a second refractive index different from the first, thereby providing a refractive interface with the non-planar distal surface parts that refracts incident light in random directions; and an arrangement of masking structures (750) which are arranged outside of areas of the non-planar distal surface parts of the optical refractive layer (734) and have sidewalls which are arranged over and contact a respective part of a top surface of the grating structure (740), wherein the optically transparent layer (770) is arranged over the arrangement of masking structures (750). [2] Optical structure according to claim 1, wherein the random protrusions have a mean transverse dimension of 10 nm to 200 nm. [3] Optical structure according to claim 1 or 2, wherein the random protrusions have a mean vertical dimension of 10 nm to 100 nm. [4] Optical structure according to one of the preceding claims, wherein the optical refractive layer (734) comprises a semiconductor material or a dielectric material. [5] Optical structure according to one of the preceding claims, wherein the lattice structure (740) comprises at least one metallic lattice structure (742) with reflective sidewalls. [6] Optical structure according to one of the preceding claims, wherein edges of the masking structures (750) are located on the top surface of the grid structure (740). [7] Optical structure according to one of the preceding claims, wherein the distal surface parts are facing away from the substrate. [8] Optical structure according to any one of claims 1 to 6, wherein the non-planar distal surface parts have random protrusions produced by etching on a flat initial surface of the refractive layer (734). [9] Optical structure according to one of the preceding claims, wherein the lattice structure (740) comprises a vertical stack of a metal layer (742) and a dielectric layer (744). [10] Image sensor with an optical structure according to one of the preceding claims and with: a matrix of pixels arranged on a semiconductor substrate (510), wherein each pixel in the matrix of pixels has at least one subpixel and each subpixel has a respective light sensor (630) and a respective sensor circuit arranged on a front side of the semiconductor substrate (510); wherein each of the non-planar distal surface parts has a surface overlap with one of the light sensors (630) in a top view. [11] Image sensor according to claim 10, wherein the optical structure has the features of claim 6 and each masking structure in the arrangement of masking structures is arranged over one of the respective sensor circuits and has an area overlap with it in a top view. [12] Image sensor according to claim 10 or 11, wherein the masking structures do not contact or are arranged over first side walls of the grid structure (740) that point towards one of the openings in the grid structure (740), but contact second side walls of the grid structure (740) that point away from one of the most proximal openings in the grid structure (740). [13] Image sensor according to one of claims 10 to 12, wherein the grid structure (740) comprises a composite grid structure (740) comprising a vertical stack of a metallic grid structure (742) with reflective side walls and a dielectric grid structure (743). [14] Image sensor according to any one of claims 10 to 13, further comprising: an arrangement of color filters positioned above the optically transparent layer; and an arrangement of lenses positioned above an arrangement of color filters. [15] Method for producing an optical structure comprising the following steps: Manufacturing light sensors (630) on a front side of a semiconductor substrate (510); Producing an optical refractive layer (734) with a first refractive index on a back side of the semiconductor substrate (510); Producing a lattice structure (740) with openings arranged above each of the light sensors (630) above a distal surface of the optical refractive layer (734); Producing a masking material layer over the grating structure (740) and the optical refractive layer (734); anisotropic etching of the masking material layer with an anisotropic etching process in which, in addition, a material of the optical refractive layer (734) is etched and non-planar distal surface parts are produced that have random protrusions on physically exposed parts of the optical refractive layer (734); and Producing an optically transparent layer with a second refractive index different from the first refractive index on the non-planar distal surface parts of the optical refractive layer (734). [16] Method according to claim 15, wherein: the anisotropic etching process involves random changes in an etch rate across the masking material layer and physically exposes different areas of the optical refractive layer (734) at different times, and Material parts of the optical refractive layer (734) that are physically exposed before the anisotropic etching process is etched at a higher etch rate than a material of the masking material layer during the anisotropic etching process. [17] Method according to claim 15 or 16, further comprising applying and structuring a photoresist layer over the masking material layer, wherein structured parts of the photoresist layer are arranged over parts of the masking material layer and protect them, and after the anisotropic etching process, unetched parts of the masking material layer form an arrangement of masking structures. [18] Method according to any one of claims 15 to 17, wherein the random protrusions have a mean transverse dimension of 10 nm to 200 nm and a mean vertical dimension of 10 nm to 100 nm. [19] Method according to any one of claims 15 to 18, wherein: the optical refractive layer (734) comprises a semiconductor material or a dielectric material, and the lattice structure (740) comprises at least one metallic lattice structure (742) with reflective side walls. [20] Method according to any one of claims 15 to 18, wherein the lattice structure is produced from a stack of a metal layer (742) and a dielectric layer (744).

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