DYNAMIC GATE CONTROL SYSTEM

Abstract

A circuit (55) comprising: a semiconductor switch (34) having a gate terminal (G); first, second, third and fourth gate resistors (40), each having an upstream end (41) and a downstream end (42), the downstream end (42) of each gate resistor (40) being electrically connected to the gate terminal (G) of the semiconductor switch (34); first, second, third and fourth buffer switches (32), each having a gate terminal (G) and a source terminal (S), wherein the source terminal (S) of the first, second, third and fourth buffer switches (32) are each connected to the upstream end (41) of the first, second, third and fourth gate resistors (40); a plurality of sensors (21); a microcontroller (50) in conjunction with a gate driver IC (30) and arranged, to receive a set of circuit measurements from the plurality of sensors (21), and in response thereto, to: Determining, based on the set of circuit measurements, switching control values ​​and gate resistance identities; and Transmitting on / off control signals and a gate resistance selection signal (13) to the gate driver IC (30) to thereby select a respective on / off state of the individual buffer switches (32), the on / off control signals and the gate resistance selection signal (13) according to the switching control values ​​and gate resistance identities; wherein the gate driver IC (30) is connected to the gate terminals of each of the buffer switches (32); and a terminal circuit (45, 46) electrically connected to the semiconductor switch (34) and which is arranged to increase a gate voltage to the semiconductor switch (34) in response to a threshold voltage across the semiconductor switch (34), wherein the threshold voltage transmitted to the gate terminal (G) causes the semiconductor switch (34) to enter a conducting state.

Description

[0001] Solid-state switches are used in a wide variety of power electronic devices. In high-power applications, for example, solid-state switches are an integral part of the internal switching design of inverter modules, voltage converters, power amplifiers, and switching power supplies. In a circuit with a multiphase electrical machine, the individual phase legs of the alternating current (AC) side of the machine are electrically connected to a corresponding pair of solid-state switches of an inverter module. A direct current (DC) side of the inverter module is electrically connected to the positive and negative rails of a DC bus, which in turn is connected to a multi-cell battery pack or other DC power supply.

[0002] In a power conversion process, pulse-width modulation, pulse-density modulation, delta-sigma modulation, pulse-frequency modulation, or other application-specific binary (on / off) switching control signals are transmitted to individual semiconductor switches within the inverter module. The control signals serve to change the conducting state of the switches, thereby generating an AC voltage waveform. The process can be reversed so that an AC voltage waveform supplied to the inverter module is rectified and output as a DC voltage waveform suitable for powering the DC bus or its connected components.

[0003] Semiconductor switches of the types used in high-power applications are typically voltage-controlled, with two common switch designs being the metal-oxide field-effect transistor (MOSFET) and the insulated-gate bipolar transistor (IGBT). A MOSFET has three terminals: an input terminal / gate, an output terminal / drain, and a common terminal / source. A threshold voltage applied to the gate terminal causes a MOSFET to enter a conducting state. An IGBT, generally well-suited for high-speed / high-power switching, is another three-terminal switch with a gate terminal, while the remaining two IGBT terminals are referred to as the collector and emitter. An IGBT is turned on by applying a threshold voltage between the gate and emitter terminals, and then turned off by reducing the gate-emitter voltage to zero or a negative voltage.

[0004] DE 10 2015 116 690 A1 discloses a hybrid electric vehicle with a traction battery, a traction motor, and an intermediate power converter. The power converter converts the DC power of the traction battery into AC power to drive each phase of the traction motor. The power converter contains insulated-gate bipolar transistors (IGBTs) to modulate the power to the traction motor. The speed at which the IGBTs are modulated affects system performance, including power loss, voltage overshoot, and current overshoot. Using a dual-emitter IGBT to provide a current mirror of the drive current, gate drive circuits can be used to dynamically adjust the gate drive speed based on characteristics, including temperature and rotation speed of the traction motor.

[0005] The present disclosure relates to circuit topologies and associated control methods for use in a system when operating a driven load, e.g., a multi-phase electric machine or a resistive load. In particular, a dynamic gate drive system and control method are disclosed which, taken together, take into account the limitations of particular circuit topologies tailored to the worst-case design of the gate resistance. The switching behavior of a particular semiconductor switch is largely determined by the gate capacitance of the switch, with charging and discharging being influenced by the gate resistance near the gate terminal. In order to protect sensitive semiconductor switch hardware from damage caused by excessive voltage overshoot, i.e.Across the collector and emitter terminals of an IGBT or across the drain and source terminals of a MOSFET, the gate resistance is typically chosen to match the worst-case voltage and current operating conditions. Such approaches tend to limit the maximum efficiency and the level of phase currents during switching operations under nominal operating conditions. The present approach aims to address this potential limitation.

[0006] In particular, the optimization strategy enabled by the present disclosure collects a set of circuit measurements at each switching instance. For example, the circuit measurements may include a temperature of a semiconductor switch, e.g., a chip or switch junction temperature, a direct current (DC) bus voltage, and an instantaneous phase current value. The measurements are forwarded to a microcontroller and subsequently used in real time to determine appropriate gate resistance values ​​for the microcontroller to switch to a conductive path leading to a controlled downstream semiconductor switch.

[0007] In response to the collective circuit measurements, a mode-specific gate resistor pair is switched into the above-mentioned conductive path, with two gate resistor pairs being used in one embodiment and controlled by a corresponding buffer switch pair. In alternative embodiments, additional gate resistors and / or buffer switches may be used. Therefore, the switching operation for each controlled semiconductor switch in a particular circuit is regulated by four buffer switches and four gate resistors. The respective pair of gate resistors may be selected based on recorded values, e.g., one or more lookup tables to which the measurements of the received circuit refer, and / or based on calculated values ​​as described herein.The control signals for switching and gate resistance selection are forwarded from the microcontroller to a gate driver integrated circuit (IC) associated with the controlled semiconductor switch. Thus, the gate driver IC is associated with a given controlled semiconductor switch in a particular embodiment, and the microcontroller may control multiple gate driver ICs.

[0008] The values ​​can optionally be included in the lookup table and are based on a corresponding power operating range of the semiconductor switch and / or its driven load, e.g., the aforementioned multiphase electrical machine or a resistive load. The operating ranges can, in certain configurations, be defined by the instantaneous phase currents and the DC link voltage as a power map, with each map having a corresponding switching temperature or range thereof. A resulting reduction in the voltage overshoot of the controlled semiconductor switch can enable the use of higher-amplitude phase currents and the reduction of the size and cost of the switching chip, among other potential advantages and performance benefits, as described herein.

[0009] In one possible embodiment, the circuit may include a voltage-controlled semiconductor switch having a gate terminal. In an exemplary embodiment, the circuit may also include at least first, second, third, and fourth gate resistors arranged in two pairs as described above. Each gate resistor has a corresponding upstream and downstream end located further or closer to the semiconductor switch. The downstream ends are electrically connected to the gate terminal of the semiconductor switch. Additionally, the circuit includes first, second, third, and fourth buffer switches, each having a gate and source terminal. The source terminals are connected to the upstream ends of the first, second, third, and fourth gate resistors.

[0010] The gate driver IC is connected to the gate terminals of each of the buffer switches. The microcontroller is configured to access a lookup table indexed by the circuit measurements in response to a received set of circuit measurements and then select switching control values ​​and gate resistance identities based on the circuit measurements. The microcontroller transmits binary (on / off) switching control signals and a gate resistance selection signal to the gate driver IC to select a respective on / off state of each buffer switch, an action that causes the selection of a specific gate resistance. The gate resistance selection signal ultimately selects the on / off state of the buffer switches connected to the upstream ends of the resistors, with the buffer switches, in a conducting state, passing voltage / current to the controlled downstream semiconductor switch.

[0011] The semiconductor switch may be an IGBT, and the buffer switches may be embodied as MOSFETs in one non-limiting example. The switching circuit includes a clamping circuit electrically connected to the semiconductor switch and configured to increase the gate voltage in response to a threshold voltage across the semiconductor switch.

[0012] Optionally, the clamping circuit can have one or more Zener diodes.

[0013] In certain disclosed embodiments, the clamping circuit is an active clamping circuit connected to the optional gate driver IC, where the gate driver IC is programmed to control a default switching state of the buffer switches in response to detecting the threshold voltage. Alternatively, the clamping circuit may also be a passive clamping circuit connected to the gate terminal of the semiconductor switch and not to the gate driver IC.

[0014] The circuit may include the driven load, wherein the driven load is connected to the semiconductor switch.

[0015] The disclosed circuit may be used as part of an electrical system having a DC link voltage and a multiphase electric machine driven by a plurality of phase currents, e.g., three phase currents in an exemplary three-phase implementation. In such an embodiment, the set of circuit measurements may include a voltage level of the DC link voltage, an instantaneous value of the phase currents, and a temperature of the semiconductor switch, e.g., a junction or chip temperature, where the driven load in this exemplary configuration is the multiphase electric machine.

[0016] The microcontroller can be programmed with a power map that defines a plurality of (two or more) different operating ranges, indexed for a given temperature by the voltage level and instantaneous phase currents—i.e., a relative power level. The microcontroller can use the circuit measurements to determine a current operating range of the driven load on the power map, e.g., as a corresponding point on the power map, and then select the respective pair or pairs of gate resistors based on the current operating range.

[0017] The microcontroller can also be programmed with a table of error codes corresponding to various logical state combinations of the buffer switches and to perform a control action using the table of error codes that responds to the detection of one of the logical state combinations.

[0018] The error code table can contain 256 total error codes, with twelve of the 256 total error codes corresponding to incorrect gate resistor selection by the microcontroller.

[0019] According to another aspect of the present disclosure, a method is provided for controlling a semiconductor switch when such a switch is connected to a driven load via a switching circuit. The method includes receiving circuit measurements using a microcontroller, wherein the microcontroller may be in communication with an optional gate driver IC, and then determining switching control values ​​and gate resistance identities based on the values ​​of the circuit measurements. The method further includes transmitting on / off control signals and a gate resistance selection signal corresponding to the switching control values ​​and the gate resistance identities, respectively, to the gate driver IC via the microcontroller or directly using the microcontroller or other control logic.This action selects a corresponding on / off state of the intermediate buffer switches when driving the driven load. Fig. 1 is a schematic representation of a powertrain system within an exemplary motor vehicle, having a driven load in the form of a multi-phase electric machine and having the electric machine driven via a switching circuit as disclosed herein. Fig. Figure 2 is a schematic diagram of a circuit topology used with an exemplary three-phase implementation of an electric machine. Fig. Figure 3 is a schematic representation of a portion of the circuit topology of Fig. 2 for a corresponding exemplary semiconductor switch. The Fig. 4A and Fig. 4B respectively illustrate active and passive embodiments of an optional clamping circuit that can be used within the circuit topology of Fig. 3 can be used. Fig. Figure 5 is a map of the discrete temperature-specific operating regions, with phase current on the horizontal axis and bus voltage on the vertical axis. Fig. 6 is an exemplary embodiment of a lookup table associated with the operating ranges of Fig. 5 is usable. Fig. 7 is an exemplary phase section with upper / high and lower / low semiconductor switches and corresponding gate driver ICs. Fig. Figure 8 is a fault lookup table illustrating an example set of fault conditions of the disclosed circuit topology of Fig. 7 describes. Fig. 9 is a flowchart illustrating a possible implementation of a method for controlling the circuit topology of the Fig. 2 and Fig. 3 describes. Fig. 10 is a schematic flow diagram illustrating a possible implementation of the present method in the exemplary powertrain system of Fig. 1 represents.

[0020] Referring to the figures, wherein like reference numerals refer to the same or similar components throughout the several figures, a powertrain system 10 is shown in Fig. 1 is shown schematically. For illustrative purposes, the drive train system 10 is shown as part of a motor vehicle. However, the present teachings can also be applied in other mobile or stationary electrical systems in which high-speed electrical switching is performed. Persons of ordinary skill in the art will appreciate that the above-mentioned switching operations are performed in various types of vehicles, e.g., in motor vehicles, rail vehicles, aircraft and watercraft, in drive systems of mobile platforms and robotic applications, as well as in engines, hoists, conveyor systems, equipment, etc. The drive train system 10 shown in a motor vehicle context of Fig. 1 is therefore only one possible example application used below for illustrative consistency without limiting the scope of the disclosure to such an embodiment.

[0021] The powertrain system 10 includes an electrical circuit 55 which is described as follows with reference to the Fig. 2-9. The circuit 55 is designed and controlled as an integral part of a power inverter module (PIM) 24 for driving a multiphase electrical machine (M E) 26. Therefore, in the non-limiting exemplary application, the drive system 10 also includes a rechargeable energy storage system (RESS) 22, e.g., a multi-cell lithium-ion or nickel-metal hydride battery pack. The powertrain system 10 may also include one or more prime movers, such as an internal combustion engine (E) 12 and a planetary gear train (T) 14 or gear set, with the engine 12 coupled to the transmission 14 via an input clutch 16. An output member 15 of the transmission 14 drives one or more drive axles 18 and, in the illustrated exemplary motor vehicle embodiment, ultimately delivers drive torque to a set of road wheels 20.

[0022] The RESS 22, which is a direct current (DC) energy storage system, is electrically connected to a DC side of the PIM 24 via positive (+) and negative (-) busbars of a DC bus 23. An alternating current (AC) side of the PIM 24 is connected to a corresponding AC bus 123, wherein the AC bus 123 is connected to phase lines or windings of the electric machine 26 in the illustrated example embodiment of Fig. 1 ends.

[0023] A switching operation of the PIM 24 via the circuit 55 ultimately provides an alternating voltage (VAC) that supplies power to the electric machine 26. The sensors 21B (see also Fig. 2) can be used to measure the phase currents of the electric machine 26, with two or three such sensors 21B being used for the exemplary three-phase embodiment of Fig. 1 as would be appreciated by those of ordinary skill in the art. The energized electric machine 26, in turn, generates motor torque that rotates a rotor 27 of the electric machine 26. The rotor 27 may be mechanically coupled to an input member 17 of the transmission 14 such that the electric machine 26 is configured as another prime mover in a hybrid electric embodiment of the powertrain system 10 or as the sole prime mover in a battery electric version of the powertrain system 10 when the engine 12 is omitted.

[0024] The powertrain system 10 may also include an auxiliary power module (rechargeable energy storage system, APM) 19, which is electrically connected to the DC bus 23, as shown. The APM 19 may be configured as a DC-DC converter capable of reducing the voltage level from a level present on the DC bus 23 to an auxiliary / low voltage level suitable for charging an auxiliary battery (B AUX) 122 and / or connected low-voltage equipment. In an automotive application, as illustrated, for example, the auxiliary battery 122 may be a 12-15V lead-acid battery. The circuit 55 described herein as part of the PIM 24 may alternatively be used to perform switching functions of the APM 19, as shown in a broken outline within the APM 19, or other electronic devices not shown in the figures, e.g., power amplifiers and switching power supplies.

[0025] The drivetrain system 10 of Fig. 1 includes a microcontroller (MC) 50 that communicates with the PIM 24 and the electric machine 26, e.g., via a controller area network, a serial peripheral interface (SPI), or other suitable communication link or protocol. Although depicted as a unitary device, the microcontroller 50 may alternatively be configured as a distributed control network of control devices. The connection of the microcontroller 50 to the PIM 24 and the electric machine 26 may include various other transmission lines and / or wireless control links suitable for sending / receiving control and feedback signals (arrow CCo), wherein the control and feedback signals (arrow CCo) include switching control signals 13 and a gate resistance selection signal (R g ), both of which are in Fig. 3 and are described in more detail below.

[0026] The microcontroller 50 includes a microprocessor (P) and a tangible, non-volatile memory (M), including read-only memory in the form of optical, magnetic, or flash memory. The microcontroller 50 may also include sufficient amounts of random access memory and electrically erasable programmable read-only memory, as well as a high-speed clock, analog-to-digital and digital-to-analog circuitry, input / output circuitry and devices, and appropriate signal conditioning and buffer circuitry. Computer-readable instructions are recorded in the memory (M), which embodies a method 100, an example of which will be described later with reference to Fig. 9. The execution of such logic by the processor (P) in response to the receipt of a set of input signals (arrow CC I) including the measured power values ​​of the circuit 55, ultimately causes the microcontroller 50 to control the operation of the circuit 55.

[0027] With reference to Fig. 2, an electrical circuit 51 includes the microcontroller 50 and a plurality of switching circuits 55, each connected to the HV voltage bus 23. The switching circuits 55, as shown, control the operation of a high / high or low / low semiconductor switch 34 and 134, respectively. Thus, the semiconductor switches 34 and 134 may be considered part of a given circuit 55 or separate therefrom in various embodiments. As used herein and in the art, the terms "high switch" and "high switch" refer to semiconductor switches connected to a higher potential / positive (+) rail of a low-voltage drive circuit used to power the switching circuits 55, i.e.has a voltage lower than that of the DC bus 23, while "low switch" or "low switch" refers to semiconductor switches connected to the lower potential rail, such as the specified negative (-) bus rail.

[0028] An intermediate circuit capacitor (C L ) can be placed across the positive (+) and negative () power rails upstream of the circuits 55. The terms “upstream” and “downstream” as used herein indicate the relative position with respect to a driven load, in this case the phase windings / AC bus 123 of the Fig. 1. Thus, a particular hardware component located near the driven load is also referred to herein as being “downstream” compared to hardware components located farther from the driven load.

[0029] As appreciated by those skilled in the art, the semiconductor switches 34 and 134 may be incorporated as part of the PIM 24 in the Fig. 1 and can be used to invert a DC voltage into an AC voltage and vice versa, e.g. in response to binary switching control / modulation signals sent as part of the output signals (arrow CCo) from the microcontroller 50. The exemplary three-phase conversion of Fig. 2, ie with its three switching pairs of upper switches 34 and lower switches 134, is, however, exemplary and not restrictive, with other possible applications of the above-disclosed circuits 55, e.g. in the context of the APM 19 of Fig. 1.

[0030] The microcontroller 50 receives circuit measurements from the plurality of sensors 21 located in Fig. 2 as sensors 21A, 21B and 21C, for three exemplary circuit measurements, with the microcontroller 50 processing this as part of the common input signal set (arrow CC I ). For example, a given sensor 21A, 21B and 21C can be used to measure a corresponding one of the bus voltage (VDC) on the DC bus 23, the above-mentioned individual phase currents (I PH ) and to measure a temperature of the circuits 55, e.g., a switch connection or chip temperature of a physical chip on which the semiconductor switches 34 and 134 are located.

[0031] In response to these circuit measurements, the microcontroller 50 calculates and / or accesses a lookup table from memory (M), the exemplary lookup table being indexed or referenced by such circuit measurements. The microcontroller 50 uses the circuit measurements to calculate / select appropriate switching control values ​​and gate resistance identities and to transmit binary on / off control signals and a gate resistance selection signal to the circuits 55 as part of the output signals (arrow CCo), as will now be described with reference to Fig. 3 is described.

[0032] Fig. 3 illustrates the circuit 55 for a particular semiconductor switch, in this case an upper semiconductor switch 34. Each of the upper and lower semiconductor switches 34 and 134 of Fig. 2 has, for illustration purposes, a corresponding circuit 55, with only one semiconductor switch 34 and a circuit 55, as in Fig. 3. A single microcontroller 50 can be used to control the various circuits 55, e.g., via SPI or another suitable communication protocol, as described above. The microcontroller 50 receives the above-mentioned circuit measurements, such as the measured bus voltage (VDC), the instantaneous phase currents (I PH ) and the temperature (TEMP) to determine a corresponding operating range, e.g. of the driven load, as described below with particular reference to Fig. 5. Based on the identified operating range, the microcontroller 50 transmits binary (on / off) switching control signals 11, e.g., PWM signals as shown, PDM signals, or signals generated using other suitable modulation techniques, and a gate resistor (R g) selection signal 13 to an optional gate driver integrated circuit (IC) 30 of the circuit 55 or directly from the microcontroller 50.

[0033] After the gate driver IC 30 in the illustrated embodiment, two pairs of buffer switches 32 (i.e., four buffer switches 32) are arranged on the positive (+) and negative (-) rails that supply the switches 32. That is, the switches (Sa, Sc) and (Sb, Sd) form the two buffer switch pairs 32 and are respectively connected to the above-mentioned positive (+) and negative (-) bus rails (low voltage with respect to the high voltage bus 23 of Fig. 1) to form high and low switches of the indicated pairs, respectively. A different number of buffer switches 32 may be used in other implementations. That is, while in the following example four buffer switches 32 (two switches 32 on the positive rail and two switches on the negative rail) may be used for selected three operating ranges, in other embodiments multiple buffer switches 32 may be used, for example, to implement additional operating ranges. For example, three switches 32 may be used on each of the positive and negative rails to enable up to seven different operating ranges, and so on.

[0034] The circuit 55 further includes two pairs of gate resistors 40, specifically first, second, third, and fourth gate resistors 40, designated Rg1_ON, Rg2_ON, Rg1_OFF, and Rg2_OFF, respectively. Again, the actual number of gate resistors 40 may vary depending on the application, with at least four such gate resistors 40 being provided in the illustrated exemplary embodiments. Each of the gate resistors 40 has a corresponding input / upstream end 41 and an output / downstream end 42, with the downstream ends 42 of each of the gate resistors 40 being electrically connected to a gate terminal (G) of the semiconductor switch 34, which is controlled by the circuit 55. The emitter terminal (E) and the collector terminal (C) of the semiconductor switch 34 are also shown, with the remaining components of the electrical circuit 51 of Fig. 2 for reasons of simplicity Fig. 3 were omitted.

[0035] The buffer switches 32 (Sa, Sb, Sc, and Sd), i.e., the respective first, third, second, and fourth buffer switches 32, also have corresponding gate terminals (G). When configured as exemplary MOSFETs, as shown, the buffer switches 32 have a corresponding source terminal (S) connected to the input / upstream end 41 of the gate resistors 40. The respective drain terminals (D) of the same buffer switches 32 are therefore connected to the positive (+) voltage of the driver circuit, i.e., V G + for the two upper buffer switches (Sa and Sb), and with the negative (-) voltage bus bar (V G -) for the two lower switches (Sc and Sd).

[0036] As shown, the optional gate driver IC 30 can be connected to the gate terminal (G) of the buffer switches 32, so that the gate driver IC 30, responding to instructions from the microcontroller 50, controls the on / off state of the buffer switches 32. In this way, the gate driver IC 30 can control the voltage level supplied to the gate terminal (G) of the semiconductor switch 34, shown in this case as an IGBT. The microcontroller 50 is in communication with the gate driver IC 30 for each semiconductor switch 34 that is in operation and is configured to, in response to the set of circuit measurements contained in the input signals (CC I) to access its memory (M) and any lookup tables contained therein. The optional lookup table(s) are indexed or referenced by the received circuit measurements, allowing the microcontroller 50 to select mode-appropriate switching control values ​​and gate resistance identities from the lookup table based on the circuit measurements and to transmit the on / off control signals 11 and the gate resistance selection signal 13 to the gate driver IC 30 to thereby select a respective on / off state of each of the buffer switches 32.

[0037] The Fig. The circuit topology of the circuit 55 shown in Figure 3 may be modified in some embodiments to provide additional protection for the semiconductor switch 34. This may be achieved using an optional active or passive clamping circuit 45 or 46 according to the Fig. 4A and Fig. 4B, both of which are electrically connected to the semiconductor switch 34 and configured to reduce the gate voltage to the semiconductor switch 34 in response to a threshold voltage above the semiconductor switch 34, but operate in different ways. Other possible approaches include the use of a DESAT (desaturation) fault detection circuit or the use of an IGBT (on-die current sensor) to detect a short circuit / overcurrent demand. In such an embodiment, the circuit topology may be based on the use of a clamping circuit such as the exemplary clamping circuits 45 and 46 of Fig. 4A or 4B.

[0038] In the actively controlled / active embodiment of Fig. 4A, the clamping circuit 45 is positioned between the gate driver IC 30 and the collector terminal (C) of the semiconductor switch 34. The clamping circuit 45 may include a Zener diode (D1) in series with a diode (D2) and a resistor (R1). An RC pair 47 (resistor R2 and capacitor C1) is arranged between the diode (D1) and resistor (R1), with the clamping circuit 45 being configured to protect the semiconductor switch 34 from excessive voltage during a fault condition.

[0039] If the company Fig. 3 shown buffer switch 32 and / or the Fig. 3 shown gate resistors 40, which for reasons of clarity are shown in the Fig. 4A and Fig. 4B, fail in any way or no longer function as intended, the control voltage supplied to the gate (G) of the semiconductor switch 34 may exceed the rated voltage limits of the semiconductor switch 34. The Zener voltage of the Zener diode (D1) can be selected such that, when the Zener voltage is exceeded, a current can flow freely through the diode (D2) and resistor (R1) to the gate driver IC 30. The current can be read by the gate driver IC 30, causing the gate driver IC 30 to respond with an appropriate switching control action of the buffer switches 32, possibly informing the microcontroller 50 of a particular fault and / or interrupting the switching operation of the semiconductor switch 34.

[0040] The passively controlled / passive embodiment of Fig. 4B and the illustrated clamping circuit 46 functions with the same effect, but in a manner that does not require any programmed functionality of the gate driver IC 30 or its control. Thus, the clamping circuit 46 is not connected to the gate driver IC 30. The resistors (R1) and (R2) of Fig. 4A are rearranged as shown, with one or two series Zener diodes (D1) directing the current back to the gate terminal (G) of the semiconductor switch 34 during a voltage overshoot condition. The circuit topology of Fig. 4B therefore reduces the switching speed of the semiconductor switch 34 by effectively reducing its gate voltage or the potential across the semiconductor switch 34.

[0041] Fig. Figure 5 illustrates an exemplary performance map 60 that defines a variety of different operating ranges that can be used to control the Fig. 1-3. In a non-limiting exemplary embodiment, three different operating regions 62, 64, and 66 are labeled Reg-1, Reg-2, and Reg-3, respectively, for clarity. The characteristic map 60 is determined by the instantaneous phase current (I PH ) is referenced or indexed on the horizontal axis, with the current in amperes (A) and the bus voltage (VDC) being represented on the vertical axis. A perimeter 61 of the map 60 forms the worst-case scenario described above, which is defined in terms of bus voltage and phase current. While in the illustrative embodiment of Fig. 5 illustrates three operating ranges 62, 64, and 66. Within the scope of the disclosure, more than three or only two operating ranges may be used to achieve a desired control accuracy. The different ranges may be defined by the corresponding power level, i.e., voltage x current. Microcontroller 50 may select a range based on the current power level or divide the ranges into subranges, etc., using the calculated power or other suitable parameters. Therefore, the illustrated example application is not intended to be limiting.

[0042] With reference to Fig. 6, an exemplary lookup table 70 can be stored in the memory (M) of the Fig. 1 and Fig. 2 shown microcontroller 50. The information in the lookup table 70 corresponds to the embodiment of Fig. 5 and thus list three operating ranges (Reg-1, Reg-2, and Reg-3). Other implementations may use two operating ranges or more than three operating ranges, depending on the desired degree of performance enhancement. The lookup table 70 also contains a gate resistance code (Rg code (13)) that corresponds to the gate resistance selection signal 13 of Fig. 3, e.g. a numeric bit code such as 01, 10 and 11, which the microcontroller 50 finally transmits to the gate driver IC 30.

[0043] In other words, the microcontroller 50, which is in communication with the gate driver IC 30, can automatically access the lookup table 70, which is responsive to the receipt of the above-mentioned set of circuit measurements, to select appropriate switching control values ​​or otherwise calculate or determine such values ​​that are in Fig. 6 as "PWM" and "OFF", and gate resistance identities of the respective gate resistors 40, which are encoded as selection signal 13. The gate driver IC 30 receives this information from the microcontroller 50. In response, the gate driver IC 30 sends switching control signals (e.g., PWM) to the buffer switches 32 (Sa, Sb, Sc, Sd) to individually select the corresponding ON / OFF conduction state of each buffer switch 40, as shown. Furthermore, the relationship between Rg1 and Rg2 is such that Rg1_OFF is always greater than Rg2_OFF, but the same is not necessarily true for the ON resistors. Thus, the selection of the actual values ​​of the gate resistors can be determined experimentally / offline for a given application.

[0044] When operating in range 62 (Reg-1) of Fig. 5, for example, both the bus voltage and the phase currents are high. The buffer switches 32 (Sa and Sc) are controlled via PWM or other switching control signals 11, and the other buffer switch pair 32 (Sb and Sd) is rotated and held. Thus, the Fig. 3 gate resistors 40, labeled Rg1_ON and Rg1_OFF, in the conductive path from the actively controlled buffer switches 32 to the gate terminal (G) of the semiconductor switch 34. The temperature can be considered as part of the present approach, e.g., when working in region 62 with low chip or switch junction temperature, a faster turn-off can be used.

[0045] In the area 64 of Fig. 5 (Reg-2), the buffer switch pair 32 (Sb and Sd) are rotated and held via the switching control signals 11 and the buffer switch pair 32 (Sa and Sc). Thus, the Fig. 3 gate resistors marked Rg2_ON and Rg2_OFF are placed in the conductor track from the actively controlled buffer switches 32 to the gate terminal (G) of the semiconductor switch 34.

[0046] The operation in area 66 (Reg-3) of Fig. 5 is reserved for lower power operation with respect to the power stages of areas 62 (Reg-1) and 64 (Reg-2). Here, the buffer switches 32 (Sa, Sb, Sc, and Sd) are actively controlled, and the four gate resistors 40 are placed on conductor tracks to the gate terminal (G). As can be seen from the Fig. 5 and Fig. As shown in Figure 6, microcontroller 50 is capable of selectively reducing the gate resistance to semiconductor switch 34 as the bus voltage (VDC) decreases by selecting specific buffer switches 32 for active switching and specific buffer switches 32 for rotating and holding in the off state. As a result of selectively reducing the gate resistance upstream of the gate connection (G) to semiconductor switch 34 based on voltage or current at a given junction temperature, the switching speed of semiconductor switch 34 can be increased in lower-power modes, while the gate resistance can be increased to reduce the switching speed in higher-power modes.

[0047] Fig. Figure 7 illustrates an exemplary phase section 58 with semiconductor switches 34 and 134 arranged as the respective upper and lower switches. Thus, semiconductor switch 34 is connected to the positive (+) rail and semiconductor switch 134 to the negative (-) rail of the DC bus 23. Two separate gate driver ICs 30 are used to control switches 34 and 134. For clarity and simplicity, Fig. 7 to the microcontroller 50 of the Fig. 1-3 are omitted. The buffer switches 32 that control the semiconductor switch 34 are labeled SH1, SH2, SL1, and SL2, where "H" represents the position of the upper / high switch and "L" represents the position of the lower / low switch. Likewise, the buffer switches 32 of the semiconductor switch 134 are labeled SH3, SH4, SL3, and SL4 using the same nomenclature. Each of the switches 34 and 134 therefore has two pairs of buffer switches 32, each pair comprising high-side and low-side switches, which are again illustrated as example MOSFETs.

[0048] The Fig. 1-7 can therefore be used to implement a switching control strategy when operating a driven load, such as the example of an electric machine 26 from Fig. 1. Such a strategy may, for example, involve receiving the set of circuit measurements via the microcontroller 50, then selecting the switching control values ​​and gate resistance identities from a lookup table, e.g., the lookup table 70 of Fig. 6, based on the set of circuit measurements. The microcontroller 50 then transmits the on / off control signals 11 and a gate resistance selection signal 13 ( Fig. 3), respectively corresponding to the switching control values ​​and the gate resistance identities from the lookup table 70, to the gate driver IC 30 to thereby select a corresponding on / off state of the buffer switches 32 when driving the electric machine 26 or another driven load.

[0049] The fault diagnosis according to the method 100 can be carried out with reference to the Fig. 8 and Fig. 9. Although such faults may go undetected for certain switching events, the method 100 triggers fault codes in other switching states or regions. It is possible that some faults may go undetected for a few switching operations. In the presence of a high intermediate circuit voltage on capacitor C L from Fig. 2, for example, a lower than a nominal gate resistance during turn-off can trigger an overshoot of the high voltage at the semiconductor switch 34 or 134. Such a failure mode can be avoided, e.g. active cutter clamping, transient voltage suppression (TVS) diodes as in the active clamping circuit of Fig. 4A or on-chip current sensing when used in conjunction with bus voltage measurements for optimal switching.

[0050] The microcontroller 50 can therefore be programmed with a table of error codes corresponding to various logical state combinations of the buffer switches 32 and to execute a control action using a table of error codes responsive to the detection of one of the 256 total possible logical state combinations, eighteen of which are shown in Fig. 8, and twelve correspond to an incorrect selection of the gate resistors.

[0051] This means that the target state numbers are in Fig. 8 shown on the far left. At eight in Fig. 7 total buffer switches 32 shown there are 2 8various logic states that can result, i.e., 256 unique logic states in total. Each logic state is assigned a unique identification number in the range 1 to 256 in the logic of the microcontroller 50. Of the 256 possible logic states, six of the states are normal (N) operating states, and 238 of these are error states. The remaining twelve error states (F) are unique to the present topology; such logic states (F) lead to an incorrect selection of the gate resistors and the associated gate resistance, with this result being designated "Inc. Rg." Therefore, the desired error handling can be encoded in the memory (M) of the microcontroller 50 and used in the ongoing control of the circuit 55.

[0052] An exemplary embodiment of the method 100 is shown in Fig. 9. The use of method 100 provides a way to handle certain errors in real time in a system using the disclosed circuit 55. For example, microcontroller 50 can be programmed with a table of the appropriate error codes corresponding to the various logic states. The buffer switches 32 forming a particular switching pair, ie (Sa and Sc) or (Sb and Sd) of Fig. 3, should exhibit opposite conducting states, i.e., when switch (Sa) is ON / conducting, switch (Sc) is OFF / non-conducting, and vice versa. Thus, as expected, certain faults such as overcurrent / shoot-through or current imbalance may be present when the buffer switches 32 of a given switch pair are ON or OFF simultaneously, or ON or OFF in a manner different from that expected for a given switching state. Thus, different switching faults can be detected by the microcontroller 50 in real time by evaluating the respective logic states of the individual buffer switches 32.

[0053] Beginning after initialization (*) of microcontroller 50, and referring to the control of a single exemplary semiconductor switch 34 for simplicity, microcontroller 50 detects defined faults in steps S101, S103, S105, and S107. Microcontroller 50 may detect the presence of such faults using reported on / off logic state signals or measured voltages or other suitable detection strategies.

[0054] At step S101, microcontroller 50 determines whether an overcurrent / shoot-through condition of semiconductor switch 34 has been detected. If such an overcurrent / shoot-through condition is detected, method 100 proceeds to step S102.

[0055] Step S102 involves terminating the gate voltage to the semiconductor switch 34 to thereby turn off the semiconductor switch 34, and then recording a corresponding error code in the memory (M) of the microcontroller 50 before proceeding to step S108.

[0056] At step S103, microcontroller 50 determines whether a current imbalance fault condition is detected. If such a fault condition is detected, method 100 proceeds to step S104.

[0057] At step S104, the microcontroller 50 records a corresponding error code in its memory (M) before proceeding to step S108.

[0058] Step S105 involves detecting an incorrect selection of the gate resistors 40, with examples of such logic states being Fig. 8. The method 100 proceeds to step S106 if this condition is detected.

[0059] Step S106 involves determining whether the clamping circuit 45 of Fig. 4A was triggered. If so, the method 100 continues with step S120. Otherwise, the method 100 is completed (**).

[0060] Step S107 involves the detection of normal operation, ie the absence of an error condition. Normal operation can be detected, for example, with the Fig. 8 logic states designated as "N" match. The method 100 is completed (**) when normal operation is detected.

[0061] At step S108, microcontroller 50 waits a calibrated period of time to determine whether the fault conditions detected at step S101, S103, or S105 persist. The method 100 proceeds to step S110 if the faults persist after the calibrated duration has elapsed. The method 100 is complete (**) when the faults self-resolve or otherwise no longer persist.

[0062] At step S110, the microcontroller 50 identifies a current operating range, e.g., from the three in Fig. 5. The method 100 proceeds to step S112 if the microcontroller 50 determines that operation will continue in region 62 (Reg-1), to step S114 if the microcontroller 50 detects operation in region 64 (Reg-2), and to step S116 if it is operating in region 66 (Reg-3).

[0063] Step S112 involves setting region 62 (Reg-1) as "unavailable" in the logic of microcontroller 50 and then restricting further operation to region 64 (Reg-2) as a control action. This effectively reduces power, torque, and current in the controlled system, e.g., the exemplary powertrain system 10 of Fig. 1. In the event that operation in region 64 (Reg-2) is unavailable to the microcontroller 50, such as due to operating limits for the electric machine 26 or other driven loads, thermal limits, or other defined limits, the microcontroller 50 may store a diagnostic code in memory (M) indicating that the defined regions 62, 64, and 66 are unavailable to the microcontroller 50 as control options. The method 100 then proceeds to step S118.

[0064] Step S114 involves setting region 64 (Reg-2) as "unavailable" in the logic of microcontroller 50 and then restricting further operation to region 62 (Reg-1) as the control action. The power, torque, current, etc., of the controlled plant are effectively increased. In the event that operation in region 62 (Reg-1) is unavailable to microcontroller 50, such as for the reasons outlined above with reference to step S112, microcontroller 50 may store a diagnostic code in memory (M) indicating that regions 62, 64, and 66 are unavailable as control options. Method 100 then proceeds to step S118.

[0065] Step S116 involves setting region 66 (Reg-3) as "unavailable" in the logic of microcontroller 50 and then restricting operation to region 64 (Reg-2) as a control action. This increases the power, torque, and current of the controlled plant. In the event that operation in region 64 (Reg-2) is unavailable to microcontroller 50, such as for the reasons set forth above with reference to step S112, microcontroller 50 may restrict operation to region 62 (Reg-1) and store a diagnostic code in memory (M) indicating operation in region 62. If operation in regions 62, 64, and 66 are not available as control options, microcontroller 50 may record another diagnostic code in memory (M) indicating such a result. Method 100 then proceeds to step S118.

[0066] At step S118, microcontroller 50 determines whether ranges 62, 64, and 66 are unavailable. As previously mentioned, a diagnostic code is recorded if a particular range 62, 64, or 66 is unavailable due to applicable limits. Thus, step S118 may include checking the presence or absence of such diagnostic codes in the memory (M) of microcontroller 50. Method 100 proceeds to step S120 if operation in ranges 62, 64, and 66 is not available as a control option. If one or more of ranges 62, 64, and 66 are available, method 100 is complete (**).

[0067] Step S120 involves executing a control action that responds to the unavailability of the areas 62, 64 and 66. Such a control action may result in the operation of the Fig. 1 or other device is turned off using circuit 55.

[0068] Fig. 10 is a schematic flow diagram illustrating one possible implementation of the above teachings, e.g., when used with the powertrain system 10 of Fig. 1. The input signals (CC I ) are measured and entered into the performance map 60 described above with reference to Fig. 5, whereby the microcontroller 50 receives the input signals (CC I ) with the defined ranges 62, 64 and 66 of the power card 60 in order to determine a desired operating range (REG DES ) according to the input signals (CC I ) to be determined. The method 100 of Fig. 9 is used simultaneously to display available areas (REG AVAIL ) as current control options.

[0069] The desired operating range (REG DES ) and the available areas (REGA VAIL) are then fed into a transition management logic block (TRANS MGMT) 63 to determine the region to be controlled. Edges between the defined regions 62, 64, and 66 are farther from the design corner (i.e., higher phase currents, highest DC voltage, and lowest chip or junction temperature). Therefore, a hysteresis loop can be implemented as the transition management logic block (TRANS MGMT) 63 to avoid noise and ensure a smooth transition between regions 62, 64, and 66.

[0070] Depending on the maximum amplitudes or values ​​of the input signals (CC I ), ie the instantaneous phase currents (I PH ), the intermediate circuit voltage (VDC) and the temperature (TEMP), there are also a maximum of four (4) cases where the gate resistance selection code is changed in a basic electrical cycle of the motor current. Thus, the topology of Fig. 10 to account for the sensor delay, the processing delay of the microcontroller 50, and the signal propagation time when selecting the operating range. The range selection does not have to be at the switching frequency, but can be performed at a slower speed that more closely corresponds to the fundamental frequency of the electric machine 26.

[0071] The commanded range (REGcc) is output by the transition management logic block 63 and fed into a state control logic block 65, which is filled with a lookup table 170. The lookup table 170 can be analogous to the lookup table 70 described above from Fig. 6. In the example table 170, the various buffer switches 32, ie the switches S a , S b , S c and S d, and the corresponding regions 62 (Reg-1), 64 (Reg-2), and 66 (Reg-3) are listed. As described above, the gate resistances (Rg) decrease with the transition from region 62 (Reg-1) to region 64 (Reg-2) and from region 64 to region 66 (Reg-3). Based on the values ​​contained in the lookup table 170, the microcontroller 50 outputs the switching signals 13 from Fig. 1 as corresponding binary status signals (1, 0), where a logic state of 1 activates the specified buffer switch 32 (S a , S b , S c , S d ) to turn on, and a state of 0 instructs the specified buffer switch 32 to turn off. In this way, optimal switching speeds for the semiconductor switch 34 are achieved.

[0072] The circuit 55, when constructed as described above, thus enables instantaneous delay decisions and the implementation of mode-appropriate gate resistance values ​​for the semiconductor switch 34, as shown in Fig. 3. The operation of the circuit 55 can help maximize the operating efficiency and the safe operating area (SOA) of the semiconductor switch 34, that is, the voltage, current, and junction temperature conditions over which the semiconductor switch 34 operates without damage.

[0073] In addition, the present approach can exploit the commonality of the PIM 24 of Fig. 1 with different configurations of the RESS 22, such as a different number of battery cells, as well as with different configurations of the electric machine 26. The present teachings may be used with other types of converters and other types of power switches not expressly described herein. The resulting reduction in switching losses through the enabled selective use of range-appropriate gate resistance values ​​when the circuit 55 in the example of the powertrain system 10 of Fig. 1 or battery- or fuel cell-powered alternatives may contribute to overall increased fuel consumption or energy efficiency. These and other related benefits will be readily appreciated by those of ordinary skill in the art in light of the above disclosure.

Claims

[1] A circuit (55) comprising: a semiconductor switch (34) having a gate terminal (G); first, second, third and fourth gate resistors (40), each having an upstream end (41) and a downstream end (42), the downstream end (42) of each gate resistor (40) being electrically connected to the gate terminal (G) of the semiconductor switch (34); first, second, third and fourth buffer switches (32), each having a gate terminal (G) and a source terminal (S), wherein the source terminal (S) of the first, second, third and fourth buffer switches (32) are each connected to the upstream end (41) of the first, second, third and fourth gate resistors (40); a plurality of sensors (21); a microcontroller (50) in conjunction with a gate driver IC (30) and arranged, to receive a set of circuit measurements from the plurality of sensors (21), and in response thereto, to: Determining, based on the set of circuit measurements, switching control values ​​and gate resistance identities; and Transmitting on / off control signals and a gate resistance selection signal (13) to the gate driver IC (30) to thereby select a respective on / off state of the individual buffer switches (32), the on / off control signals and the gate resistance selection signal (13) according to the switching control values ​​and gate resistance identities; wherein the gate driver IC (30) is connected to the gate terminals of each of the buffer switches (32); and a terminal circuit (45, 46) electrically connected to the semiconductor switch (34) and which is arranged to increase a gate voltage to the semiconductor switch (34) in response to a threshold voltage across the semiconductor switch (34), wherein the threshold voltage transmitted to the gate terminal (G) causes the semiconductor switch (34) to enter a conducting state. [2] The circuit (55) of claim 1, further comprising: a gate driver integrated circuit (IC) (30) connected to the gate terminal (G) of each of the first, second, third and fourth buffer switches (32), wherein the microcontroller (50) is in communication with the gate driver IC (30) and is configured to transmit a gate resistance selection signal (13) to the gate driver IC (30) to thereby select a respective on / off state of each of the buffer switches (32). [3] The circuit (55) of claim 2, wherein the gate driver IC (30) is programmed to command a default switching state of each of the first, second, third and fourth buffer switches (32) in response to the threshold voltage. [4] The circuit (55) of claim 1, wherein the clamping circuit (46) is a passive clamping circuit connected to the gate terminal (G) of the semiconductor switch (34) and including a Zener diode (D1). [5] The circuit (55) of claim 1, further comprising: a driven load (26) connected to the semiconductor switch (34). [6] The circuit (55) of claim 5, wherein the circuit (55) is configured as part of an electrical system having a direct current (DC) voltage bus (23) and a multi-phase electrical machine (26) driven by a plurality of phase currents, the set of circuit measurements includes a DC voltage level of the DC voltage bus (23), an instantaneous value of the phase currents, and a temperature of the semiconductor switch (34), and the driven load (26) is a phase section of the multi-phase electrical machine (26). [7] The circuit (55) of claim 6, wherein the microcontroller (50) is programmed with a power map defining a plurality of different operating regions, each indexed at temperature by the DC voltage level and the instantaneous phase currents, and wherein the microcontroller (50) is configured to determine a current operating region of the driven load (26) on the power map using the set of circuit measurements and to actively switch at least some of the gate resistors (40) based on the current operating region. [8] The circuit (55) of claim 1, wherein the microcontroller (50) is programmed with a table of error codes corresponding to a plurality of different logical state combinations of the buffer switches (32) and to perform a control action using the table of error codes in response to detecting one of the different logical state combinations. [9] The circuit (55) of claim 8, wherein the table of error codes includes 256 total error codes, and wherein twelve of the 256 total error codes correspond to an incorrect selection of the gate resistors (40) by the microcontroller (50).

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