METHOD FOR SEMICONDUCTOR INTERCONNECT STRUCTURE

Abstract

Procedure comprehensive: Receiving a structure comprising a substrate (110), a conductive feature (160) over the substrate (110) and a dielectric layer (240) over the conductive feature (160) and the substrate (110). Forming a hole (242) in the dielectric layer (240), wherein the hole (242) exposes the conductive feature (160); Forming a first metal-containing layer (300) at least on the side walls of the hole (242); Forming a second metal-containing layer (304) in the hole (242) which is surrounded by the first metal-containing layer (300), wherein the first metal-containing layer (300) and the second metal-containing layer (304) contain different materials; Applying a first chemical (305) to leave out the dielectric layer (240), resulting in an upper section of the first metal-containing layer (300) and an upper section of the second metal-containing layer (304) that project beyond the dielectric layer (240); and Applying a second chemical (307) containing fluorine or chlorine to the upper section of the first metal-containing layer (300) to convert the upper section of the first metal-containing layer (300) into a metal fluoride or a metal chloride, the first chemical (305) is dilute hydrochloric acid.

Description

TECHNICAL BACKGROUND

[0001] The semiconductor integrated circuit (IC) sector is experiencing exponential growth. Technological advances in IC materials and design have produced generations of ICs, with each generation featuring smaller and more complex circuits than the previous generation. As ICs have evolved, functional density (i.e., the number of devices interconnected per chip area) has generally increased, while geometry size (i.e., the smallest device (or row) that can be produced using a manufacturing process) has decreased. The proportional downsizing process presents benefits by increasing production efficiency and reducing associated costs. Such proportional downsizing has also increased the complexity of IC processing and manufacturing.

[0002] For example, when forming interconnect structures (including contacts, vias, wires, etc.) in an IC, metal elements can diffuse and / or migrate from their intended locations. This can occur as a result of etching, chemical mechanical planarization (CMP), or other processes performed on a metal layer. These diffused metal elements can cause short circuits between closely spaced conductive features, such as between a source / drain and a nearby gate contact or between two adjacent metal wires. Methods that can eliminate such metal diffusion are desirable.

[0003] Prior art relating to the subject matter of the invention can be found, for example, in EP 1 039 530 A2 and US 2006 / 0 234 516 A1.

[0004] The invention is defined by the main claim and the subordinate claim. Further embodiments of the invention are recited in the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] This disclosure is best understood by reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not drawn to scale and are for illustrative purposes only. Indeed, the dimensions of various features may be arbitrarily exaggerated or reduced for the purpose of clarity of explanation. Fig. 1A, Fig. 1B and Fig. 1C show a flowchart of a method for forming interconnect structures and / or features in a semiconductor device according to aspects of this disclosure. Fig. 2A, Fig. 2B, Fig. 2C, Fig. 2D, Fig. 2E, Fig. 2F, Fig. 2G, Fig. 2H, Fig. 3A, Fig. 3B, Fig. 3C, Fig. 3D, Fig. 3E, Fig. 3F and Fig. 3G illustrate cross-sectional views of a semiconductor structure during a manufacturing process according to the method of Fig. 1A-1C according to one embodiment. Fig. 2I and Fig. 3H show a plan view of a semiconductor structure during a manufacturing process according to the method of Fig. 1A-1C according to one embodiment. DETAILED DESCRIPTION

[0006] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the following description may include embodiments in which the first and second features are formed in direct contact and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. In addition, this disclosure may repeat reference numbers and / or letters in the various examples.This repetition is for the purpose of simplification and clarity and does not in itself impose any relationship between the various embodiments and / or configurations discussed.

[0007] Furthermore, spatial terms such as "beneath," "under," "lower," "above," "upper," and the like may be used herein for ease of description to describe an element or the relationship of a feature to one or more other elements or features as described in the FIGS. The spatial terms are intended to encompass different orientations of the device in use or operation in addition to the orientation illustrated in the FIGS. The device may be oriented differently (rotated 90 degrees or in other orientations), and the spatial descriptors used herein may be similarly interpreted accordingly. Furthermore, when a number or series of numbers is described with "approximately," "approximately," and the like, the term is intended to encompass numbers that are within + / - 10% of the described number, unless otherwise noted. E.g.the term “approximately 5 mm” covers the dimensional range from 4.5 mm to 5.5 mm.

[0008] This disclosure relates generally to semiconductor devices and manufacturing methods, and more particularly to the fabrication of an interconnect structure in a semiconductor device. The interconnect structure may include a first conductive feature embedded in or surrounded by one or more dielectric layers and a second conductive feature disposed over and electrically connected to the first conductive feature. The first and second conductive features may include source / drain electrodes, gate electrodes, source / drain contacts (or contact plugs), source / drain contact vias (or via plugs), gate vias, other vias, metal wires, and other conductive elements.The interconnected structure can be fabricated by etching a hole in the dielectric layers to expose the first conductive feature, depositing one or more metal materials in the hole, and removing excess metal materials through an etching or CMP process. During the etching or CMP process, metal residues can diffuse or migrate, which can lead to short circuits or other manufacturing defects if not properly handled. One object of this invention is to treat such metal residues with (some) chemical(s) to produce stable metal components.

[0009] In particular, embodiments of this disclosure may deposit a metal or a metal nitride as part of the conductive features in the IC interconnect and further apply a chemical containing fluorine or chlorine to further convert residues of the metal or metal nitride into metal fluorides or metal chlorides. The metal fluorides and metal chlorides are stable (e.g., they do not react with the oxygen in the surrounding dielectric layers). Accordingly, manufacturing defects due to dispersed metal elements are prevented. Some embodiments of this disclosure use a two-step cleaning and etching process following a CMP process. The first step applies a first chemical at a relatively low concentration to recess a dielectric layer, and the second step applies a second chemical at a relatively high concentration to react with metals.The two steps collectively remove metal residues and produce stable metal devices. Aspects of this disclosure are described with reference to the . Fig. 1A-1C, 2A-2I and 3A-3H are discussed in further detail.

[0010] The Fig. 1A-1C illustrate a flowchart of a method 10 for forming a semiconductor device 100 according to one embodiment. The method 10 is merely an example and is not intended to limit this disclosure beyond what is expressly recited in the claims. Additional operations may be provided before, during, and after the method 10, and some described operations may be replaced, removed, or displaced for additional embodiments of the method. The method 10 is described below in connection with the Fig. 2A-3H, which illustrate various cross-sectional and top views of the semiconductor device 100 during the manufacturing steps according to the method 10. Furthermore, the semiconductor device 100 may be an intermediate device that may be manufactured during the processing of a semiconductor integrated circuit (IC) or a portion thereof that may include a static random access memory (SRAM), other memory cells and / or other logic circuits, passive components such as resistors, capacitors and inductors, and active components such asP-type field-effect transistors (PFETs), n-type FETs (NFETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor transistors (CMOS transistors), FinFETs, gate-all-around nanowire transistors (GAA nanowire transistors), GAA nanosheet transistors, other multi-gate transistors, bipolar transistors, high-voltage transistors, high-frequency transistors, and combinations thereof.

[0011] With reference to Fig. 1A, at operation 12, the method 10 provides or is provided with a device structure 100 that includes a substrate and various features and layers over the substrate. An example of the device structure 100 is shown in Fig. 2A. Referring to Fig. 2A, the structure 100 includes a substrate 110 and various components built in or on the substrate 110, including transistor channels 114, gate structures 120 over the transistor channels 114, gate spacers 150 on sidewalls of the gate structures 120, source / drain features 160 on both sides of the transistor channels 114 and adjacent to the gate spacers 150, and dielectric layers 170 and 240. The dielectric layer 170 is disposed over the source / drain features 160 and between the gate spacers 150. The dielectric layer 240 is disposed over the dielectric layer 170, the gate structure 120, and the gate spacers 150. The device structure 100 may include other components (such as a contact etch stop layer over the source / drain features 160) that may be Fig. 2A are not shown. The various components of structure 100 are described in further detail below.

[0012] The substrate 110 is a silicon substrate, such as a silicon wafer in this embodiment. Alternatively, the substrate 110 may comprise another semiconductor, such as germanium; a device semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide; an alloy semiconductor including silicon germanium, gallium arsenide phosphide, aluminum indium phosphide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and gallium indium arsenide phosphide; or combinations thereof.

[0013] The transistor channels 114 and the source / drain features 160 may be formed in or on (unlabeled) active regions of the structure 100. The active regions may have a planar shape (for planar MOSFETs), a three-dimensional shape, such as fins (for FinFETs) or vertically stacked multiple semiconductor layers (for GAA-FETs), or other suitable shapes. The transistor channels 114 may include silicon, germanium, silicon germanium, or other suitable semiconductor materials; and may be doped or undoped. The source / drain features 160 may include lightly doped source / drain (LDD) features, heavily doped source / drain (HDD) features, or other doped structures. The source / drain features 160 may include n-doped silicon for NFET devices, p-doped silicon germanium for PFET devices, or other doped semiconductor materials.Furthermore, the source / drain features 160 may contain epitaxially grown semiconductor materials or be otherwise elevated or strained to enhance performance. In particular, the source / drain features 160 are conductive.

[0014] The gate structure 120 may include a polysilicon gate, a high-k metal gate, or other suitable gate structure generally including a wire over a gate dielectric layer. Fig. The example shown in Figure 2A includes a high-k metal gate structure. As shown, the gate structure 120 includes a high-k dielectric layer 122, a work function metal layer 124, a metal fill layer 126, and a cap layer (or hard mask layer) 128. The gate structure 120 may include other layers (such as an interface layer and / or a barrier layer) that may be included in Fig. 2A is not shown in some embodiments. The high-k dielectric layer 122 may include one or more high-k dielectric materials (or one or more layers of high-k dielectric materials), such as hafnium silicon oxide (HfSiO), hafnium oxide (HfO2), aluminum oxide (Al2O3), zirconium oxide (ZrO2), lanthanum oxide (La2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), strontium titanate (SrTiO3), or a combination thereof. The high-k dielectric layer 122 may be formed using atomic layer deposition (ALD), chemical vapor deposition (CBD), physical vapor deposition (PVD), or other deposition techniques. The work function metal layer 124 may include a p-type or an n-type work function layer depending on the type (PFET or NFET) of the device.The p-type work function layer may include titanium nitride (TiN), tantalum nitride (TaN), ruthenium (Ru), molybdenum (Mo), tungsten (W), platinum (Pt), other suitable metals, or combinations thereof. The n-type work function layer may include titanium (Ti), aluminum (Al), tantalum carbide (TaC), tantalum carbide nitride (TaCN), tantalum silicon nitride (TaSiN), titanium silicon nitride (TiSiN), other suitable metals, or combinations thereof. The work function metal layer 124 may be formed by ALD, CVD, PVD, or other techniques. The metal fill layer 126 may include aluminum (Al), tungsten (W), cobalt (Co), and / or other suitable materials; and may be formed by ALD, CVD, PVD, plating, or other techniques. The cap layer 128 may include silicon nitride or other suitable dielectric material(s); and can be formed by CVD, PVD, ALD or other techniques.

[0015] The gate spacers 150 may include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, other dielectric material, or combinations thereof, and may include one or more material layers. The gate spacers 150 may be formed by CVD, PVD, ALD, or other techniques.

[0016] The dielectric layer 170 may include silicon oxide, silicon oxynitride, tetraethylorthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide, such as boron phosphosilicate glass (BPSG), fluorosilicate glass (FSG), phosphosilicate glass (PSG), other low-k dielectric materials, and / or other suitable dielectric materials. The dielectric layer 170 may be formed by plasma-enhanced CVD (PECVD), flowable CVD (FCVD), or other suitable processes. The dielectric layer 170 may be referred to as an ILD-o-layer, where ILD stands for interlayer dielectric layer.

[0017] Dielectric layer 240 may be referred to as an ILD-1 layer because it is deposited over ILD-o layer 170. Dielectric layers 170 and 240 may include the same or similar material(s). For example, dielectric layer 240 may include silicon oxide, silicon oxynitride, TEOS oxide, undoped silicate glass, or doped silicon oxide, such as BPSG, FSG, PSG, other low-k dielectric materials, and / or other suitable dielectric materials. Dielectric layer 240 may be formed by PECVD, FCVD, or other suitable processes. Device structure 100 may include a contact etch stop layer (CESL) between dielectric layer 240 and the structures below. The CESL may include silicon nitride, silicon oxynitride, silicon nitride with oxygen (O) or carbon (C) elements, and / or other materials; and can be formed by CVD, PVD, ALD or other suitable processes.

[0018] At operation 14, the procedure etches 10 ( Fig. 1A) Holes 242 are drilled into the dielectric layers 240 and 170 to expose the source / drain features 160. In some embodiments, the holes 242 have an oval shape, a circular shape, a rectangular shape, and / or a rounded rectangular shape with respect to a top view. The resulting structure 100 is shown in Fig. 2B. In one embodiment, operation 14 includes a photolithography process and one or more etching processes.For example, the photolithography process may include depositing one or more hard mask layers over structure 100, coating an opaque layer over the hard mask layers, patterning the opaque layer to form a resistive etch mask, etching the hard mask layers and dielectric layers 240 and 170 through the resistive etch mask, and then removing the resistive etch mask and the hard mask layers. The etching processes may include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes designed to etch the materials in dielectric layers 240 and 170. For example, a dry etching process may use an oxygen-containing gas, a fluorine-containing gas (e.g. CF4, SF6, CH2F2, CHF3, and / or C2F6), a chlorine-containing gas (e.g. Cl2, CHCl3, CCl4 and / or BCl3), a bromine-containing gas (e.g.HBr and / or CHBR3), an iodine-containing gas, other suitable gases and / or plasmas, and / or a combination thereof. For example, a wet etch process may include etching in dilute hydrofluoric acid (HF); potassium hydroxide (KOH) solution; ammonia; a solution containing hydrofluoric acid (HF), nitric acid (HNO3), and / or acetic acid (CH3COOH); or other suitable wet etchants. A top portion of the source / drain features 160 may also be etched by operation 14. The holes 242 are sometimes referred to as source / drain vias.

[0019] In operation 16, the procedure 10 ( Fig. 1A) a metal-containing layer 300 in the holes 242. The resulting structure 100 is Fig. 2C. With reference to Fig. 2C, the metal-containing layer 300 is formed at least on sidewalls of the holes 242. In this embodiment, the metal-containing layer 300 is also formed on the bottom surface of the holes 242 as well as on the top surface of the dielectric layer 240. The metal-containing layer 300 may be formed using CVD, PVD, ALD, or other suitable techniques and may be formed to have a substantially uniform thickness (i.e., surface-facing) in some embodiments or a non-uniform thickness in alternative embodiments. The metal-containing layer 300 may include a metal layer, a metal nitride layer, or a combination thereof. In one embodiment, the metal-containing layer 300 includes a transition metal, a transition metal nitride, or a combination thereof. For example, the metal-containing layer 300 may include titanium (Ti), titanium nitride (TiN), or a combination thereof.In some embodiments, the metal-containing layer 300 may include either cobalt (Co), nickel (Ni), niobium (Nb), ruthenium (Ru), rhodium (Rh), tungsten (W), and rhenium (Re), or a nitride of one of these metals.

[0020] In operation 18, the process 10 ( Fig. 1A) the structure 100 to form silicide 302 over the source / drain features 160. The resulting structure 100 is shown in Fig. 2D. The operation 18 may, for example, be performed at a suitable temperature for a suitable duration to cause a reaction between the metal-containing layer 300 and the semiconductor materials in the source / drain features 160 to form the silicide 302. For example, if the metal-containing layer 300 includes titanium, the operation 18 may include a rapid thermal anneal (RTA) at approximately 700°C to 800°C for 1 second to 240 seconds to form TiSi and / or TiSi2. The portion of the metal-containing layer 300 at a bottom surface of the holes 242 may be fully or partially converted to the silicide 302 in various embodiments. Operation 18 may use RTA, millisecond annealing (MSA), or other annealing techniques.

[0021] In operation 20, procedure 10 ( Fig. 1A) deposits another metal-containing layer 304 to fill the remaining space of the holes 242. With reference to Fig. 2E, the metal-containing layer 304 is deposited over the silicide 302 and over the metal-containing layer 300. In this embodiment, the metal-containing layer 304 is also deposited over the portion of the metal-containing layer 300 on the dielectric layer 240. The metal-containing layer 304 may include W, Co, Ru, other metals, metal nitrides such as TiN, titanium aluminum nitride (TiAlN), tungsten nitride (WN), tantalum nitride (TaN), or combinations thereof. The metal-containing layers 304 may be formed by CVD, PVD, plating, and / or other suitable processes.

[0022] In operation 22, the procedure 10 ( Fig. 1A) performs a CMP process to partially remove (or thin) the metal-containing layer 304 and expose the dielectric layer 240. The dielectric layer 240 may also be partially removed by the CMP process. The resulting structure 100 is shown in Fig. 2F. At this manufacturing stage, the top surface of the structure 100 is substantially planar. However, some metal residues (or particles) may appear on the top surface of the dielectric layer 240. Furthermore, some metal residues from the metal-containing layer 300 may appear on the top surface of the metal-containing layer 304.Since these metal residues may contain transition metal(s) that are highly reactive with oxygen, if not removed, they could react with oxygen elements in the dielectric layer 240 or other dielectric layers deposited on top of layers 240 and 306 to cause manufacturing defects.

[0023] In operation 24, the procedure 10 ( Fig. 1B) a first chemical 305 for recessing the dielectric layer 240. As a result, an upper portion of the metal-containing layer 300 and an upper portion of the metal-containing layer 304 extend above the dielectric layer 240, as in Fig. 2G. In one embodiment, the chemical 305 contains dilute hydrofluoric acid (HF) at a low concentration. For example, the dilute hydrofluoric acid may have a concentration of hydrogen fluoride (HF) in deionized water (DI) of approximately 0.1% or lower. The dilute hydrofluoric acid at such a concentration may dilute the dielectric layer 240 (which, in one example, is primarily silicon dioxide), but does not react well with the metal-containing layers 300 and 304. In another embodiment, the chemical 305 contains dilute hydrochloric acid (HCl) (or chlorane) at a low concentration. For example, the dilute hydrochloric acid may have a concentration of hydrogen chloride (HCl) in deionized water (DI) of approximately 0.1% or lower. The operation 24 may also, in some embodiments, remove some of the metal residues on top of the dielectric layer 240.The dielectric layer 240 may be recessed by several nanometers, such as approximately 2 nm. The depth of the recess is determined by the concentration of the first chemical 305, the duration of the operation 24, and other factors. For example, the operation 24 may apply a dilute hydrofluoric acid at a concentration of 0.1% for approximately 6 to 18 seconds to thin the dielectric layer 240 by approximately 1 to 5 nm. In some embodiments, the depth of the thinning is controlled to be less than 5 nm to avoid excessive loss of the dielectric layer 240.

[0024] In operation 26, the procedure 10 ( Fig. 1B) applies a second chemical 307 to the exposed upper portion of the metal-containing layer 300 and converts it into a metal component 308. The resulting structure 100 is shown in FIGS. 2H and 2I. The second chemical 307 is designed to convert the exposed upper portion of the metal-containing layer 300 into a stable metal component 308 while not significantly diluting the dielectric layer 240. In this embodiment, the second chemical 307 includes a fluoride or chloride component, and the metal component 308 includes a metal fluoride or a metal chloride, respectively. In embodiments where metal residues are present on the upper surface of the dielectric layer 240, the second chemical 307 also converts such metal residues into stable metal components, such as metal fluoride or metal chloride.The chemical 307 may also react with the metal-containing layer 304 to produce some metal features on the top surface of the metal-containing layer 304. Such metal features are removed in subsequent processes (e.g., etching a via formed over the metal-containing layer 304 as shown in FIG. Fig. 3B shown).

[0025] In one embodiment, the second chemical 307 comprises the same components as the first chemical 305, but with a higher chemical concentration. The lower concentration of chemical 305 is designed such that the chemical 305 can dilute the dielectric layer 204 (e.g., primarily comprises silicon dioxide) but does not react well with the metal-containing layer 300 (e.g., comprises a transition metal or a transition metal nitride). The higher concentration of chemical 307 is designed to react well with the metal-containing layer 300.

[0026] For example, Chemicals 305 and 307 may be dilute hydrofluoric acid, but Chemical 307 has a higher HF concentration in DI water than Chemical 305. For example, the HF concentration in DI water for Chemical 307 may be at least 10 times higher than that for Chemical 305. In at least one example, the HF concentration in DI water for Chemical 307 is about 1% or more, while the HF concentration in DI water for Chemical 305 is about 0.1% or less. Dilute hydrofluoric acid at a concentration of 1% or more reacts well with the metal-containing layer 300. However, it also etches the dielectric layer 240. To avoid excessive loss of the dielectric layer 240, the HF concentration in DI water for the chemical 307 is, in some embodiments, intended to be approximately 1% to 2%. In these examples, the metal component 308 contains a metal fluoride.For example, if the metal-containing layer 300 contains titanium, the metal component 308 contains titanium fluoride (e.g. TiF3).

[0027] In another example, both chemicals 305 and 307 may be dilute hydrochloric acid (HCl), but chemical 307 has a higher HCl concentration in DI water than chemical 305. For example, the HCl concentration in DI water for chemical 307 may be at least 10 times higher than that for chemical 305. In at least one example, the HCl concentration in DI water for chemical 307 is about 1% or more (such as 1% to 2%), while the HCl concentration in DI water for chemical 305 is about 0.1% or less. In these examples, metal component 308 contains a metal chloride. For example, if metal-containing layer 300 contains titanium, metal component 308 contains titanium fluoride (e.g., TiCl3).

[0028] In another embodiment, the two chemicals 305 and 307 have different components, with chemical 305 being designed to have a higher etch selectivity (higher etch rate) on dielectric layer 240 than on metal-containing layer 300, while chemical 307 is designed to have a higher etch selectivity on metal-containing layer 300 than on dielectric layer 240. For example, chemical 305 may be a dilute HF acid at a low concentration, such as 0.1% or lower, and chemical 307 may be a dilute HCl acid at a higher concentration, such as 1% or higher (such as approximately 1% or 2%). In this example, chemical 305 does not react well with metal-containing layer 300, but still effectively etches dielectric layer 240.At the same time, chemical 307 reacts well with metal-containing layer 300, but still slightly etches dielectric layer 240. In this example, metal component 308 contains a metal chloride. For example, if metal-containing layer 300 contains titanium, metal component 308 contains titanium fluoride (e.g., TiCl3).

[0029] Fig. 2I illustrates a partial top view of the device 100 in its fabrication stage. As shown, the metal component 308 surrounds the metal-containing layer 304. Both the metal component 308 and the metal-containing layer 304 have a generally rounded shape in this example. However, in various embodiments, they may have other shapes, such as a generally rectangular shape or an irregular shape. The metal component 308 is chemically very stable and does not react with oxygen. The top surface of the dielectric layer 240 is substantially free of any reactive metal elements, such as transition metals or transition metal nitrides. Accordingly, by performing operations 24 and 26 after the CMP process at operation 22, the method 10 effectively removes any reactive metal elements from the top surface of the dielectric layer 240, thereby preventing the metal distribution defects discussed above.Furthermore, the structure including the metal-containing layers 300 and 304 and the metal component 308 becomes a source / drain contact (or contact plug) 310. As shown in . Fig. As shown in Figure 2H, a lower portion of the source / drain contact 310 includes a lower portion of the metal-containing layer 304 surrounded by the metal-containing layer 300, and an upper portion of the source / drain contact 310 includes an upper portion of the metal-containing layer 304 surrounded by the metal component 308. The upper portion of the source / drain contact 310 extends above the top surface of the dielectric layer 240. The source / drain contact 310 is disposed directly on the silicide 302 disposed above the source / drain feature 160.

[0030] The method 10 may continue the construction of the interconnect structure on the device 100. For example, the method 10 may create via structures disposed over the source / drain contacts 310 by using the Fig. 1B and Fig. 1C. Many aspects of operations 28 to 40 are similar to operations 12 to 26 discussed above. Thus, operations 28 to 40 are discussed below in conjunction with the Fig. 3A to 3H briefly discussed.

[0031] In operation 28, the procedure 10 ( Fig. 1B) another dielectric layer over the dielectric layer 240 and the source / drain contacts 310. The resulting structure 100 is shown in Fig. 3A. The dielectric layer 400 may comprise the same or similar materials as the dielectric layer 240. In one embodiment, the dielectric layer 400 may include silicon oxide, silicon oxynitride, TEOS oxide, undoped silicate glass or doped silicon oxide, such as BPSG, FSG, PSG, other low-k dielectric materials, and / or other suitable dielectric materials. The dielectric layer 400 may be formed by PECVD, FCVD, or other suitable methods. The device structure 100 may include a contact etch stop layer (CESL layer) between the dielectric layer 400 and the dielectric layer 240 and the source / drain contacts 310. The dielectric layer 400 may be referred to as an ILD-2 layer in some embodiments.

[0032] At operation 30, the procedure etches 10 ( Fig. 1B) Via holes 402 in the dielectric layer 400 to expose some of the conductive features underneath, such as the source / drain contacts 310 and / or the gate structures 120. The resulting structure 100 is shown in Fig. 3B. Referring to Fig. 3B, the via holes 402 expose the source / drain contacts 310 for forming source / drain contact vias. Although not shown, some via holes 402 may be etched directly above the gate structures 120 to form gate vias. Operation 30 is similar to operation 14 discussed above. For example, operation 30 may include a photolithography process for forming an etch mask and an etching process for etching the dielectric layer 400 through the etch mask.

[0033] In operation 32, the procedure 10 ( Fig. 1B) a metal-containing layer 404 in the via holes 402. The resulting structure 100 is Fig. 3C. With reference to Fig. 3C, the metal-containing layer 404 is also formed on the bottom surface and sidewalls of the via holes 402, as well as on the top surface of the dielectric layer 400. The metal-containing layer 404 may be formed using CVD, PVD, ALD, or other suitable techniques and may be formed to have a substantially uniform thickness (i.e., surface-facing) in some embodiments or a non-uniform thickness in alternative embodiments. The metal-containing layer 404 may include a metal layer, a metal nitride layer, or a combination thereof. In one embodiment, the metal-containing layer 404 includes a transition metal, a transition metal nitride, or a combination thereof. For example, the metal-containing layer 404 may include tantalum (Ta), tantalum nitride (TaN), or a combination thereof. Aspects of operation 32 are similar to those of operation 16.

[0034] In operation 34, the procedure 10 ( Fig. 1C) a metal-containing layer 406 to fill the remaining space of the via holes 402. With reference to Fig. 3D, the metal-containing layers 406 are deposited over the metal-containing layer 404. The metal-containing layers 406 may contain copper or other metal, such as W, Co, or Ru, and may be formed by CVD, PVD, plating, and / or other suitable processes. Aspects of operation 34 are similar to those of operation 20.

[0035] At operation 36, procedure 10 ( Fig. 1C) performs a CMP process to partially remove (or thin) the metal-containing layer 406 and expose the dielectric layer 400. The dielectric layer 400 may also be partially removed by the CMP process. The resulting structure 100 is shown in Fig. 3E. Aspects of operation 36 are similar to that of operation 22. At this manufacturing stage, the top surface of the structure 100 is substantially planar. However, some metal residues (or particles) may appear on top of the dielectric layer 400. Since these metal residues may contain transition metal(s) that are highly reactive with oxygen, if they are not removed, they could react with oxygen elements in the dielectric layer 400 or layers deposited on top of the layers 400 and 406 to cause manufacturing defects.

[0036] In operation 38, the procedure 10 ( Fig. 1C) a third chemical 405 for thinning the dielectric layer 400. As a result, an upper portion of the metal-containing layer 404 and an upper portion of the metal-containing layer 406 extend above the dielectric layer 400, as in Fig. 3F. Aspects of operation 38 are similar to those of operation 24. Chemical 405 may be intended to be the same or similar to chemical 305 discussed above. For example, chemical 405 may contain dilute hydrofluoric acid or dilute hydrochloric acid at a low concentration (such as approximately 0.1% or lower).

[0037] In operation 40, the procedure 10 ( Fig. 1C) deposits a fourth chemical 407 onto the exposed upper portion of the metal-containing layer 404 and converts it into a metal component 408. The resulting structure 100 is shown in Figures 3G and 3H. Aspects of operation 40 are similar to that of operation 26. The chemical 407 may be intended to be the same or similar to the chemical 307 discussed above. For example, the chemical 407 may include dilute hydrofluoric acid or dilute hydrochloric acid at a comparatively high concentration (such as approximately 1% or higher, or approximately 1% to 2%). The metal component 408 may include a metal fluoride or a metal chloride. For example, if the metal-containing layer 404 includes tantalum, the metal component 408 may include tantalum fluoride (e.g., TaCl3) or tantalum chloride (e.g., TaCl3).

[0038] In one embodiment, chemical 405 may be a dilute HF acid at a low concentration, such as 0.1% or lower, and chemical 407 may be a dilute HCl acid at a higher concentration, such as 1% or higher (such as approximately 1% or 2%). In this example, chemical 405 does not react well with metal-containing layer 404, but still effectively etches dielectric layer 400. At the same time, chemical 407 reacts well with metal-containing layer 404, but still somewhat etches dielectric layer 400. In this example, metal component 408 contains a metal chloride, such as tantalum chloride (e.g., TaCl3).

[0039] Fig. 3H illustrates a partial top view of the device 100 in its fabrication stage. As shown, the metal component 408 surrounds the metal-containing layer 406. Both the metal component 408 and the metal-containing layer 406 have a generally rounded shape in this example. However, in various embodiments, they may have other shapes, such as a generally rectangular shape or an irregular shape. The metal component 408 is chemically very stable and does not react with oxygen. The top surface of the dielectric layer 400 is substantially free of any reactive metal elements, such as transition metals or transition metal nitrides. Accordingly, by performing operations 38 and 40 after the CMP process at operation 36, the method 10 effectively removes any reactive metal elements from the surface of the dielectric layer 400, thereby preventing the metal distribution defects discussed above.Furthermore, the structure including the metal-containing layers 404 and 406 and the metal component 408 will include a source / drain contact via 410. As shown in . Fig. 3G, a lower portion of the source / drain contact via 410 includes a lower portion of the metal-containing layer 406 surrounded by the metal-containing layer 404, and an upper portion of the source / drain contact via 410 includes an upper portion of the metal-containing layer 406 surrounded by the metal component 408. The upper portion of the source / drain contact via 410 extends above the upper surface of the dielectric layer 400. Although not shown, the device structure 100 may include gate vias disposed over and electrically connected to the gate structures 120, where the gate vias have a similar structure to the source / drain contact vias 410.

[0040] At operation 42, procedure 10 ( Fig. 1C) performs further processes to complete the fabrication of the device 100. For example, the method 10 may form wires connecting the source / drain contact vias 410 and the gate vias and repeat the above operations to form interconnect structures at a higher level.

[0041] Although not intended to be limiting, one or more embodiments of this disclosure provide many advantages of a semiconductor device and its formation. For example, embodiments of this disclosure provide methods for removing metal residues from dielectric layers through a two-step cleaning (or etching) process. The cleaning process converts reactive metal residues into stable metal devices to prevent metal distribution manufacturing defects. Other embodiments of this disclosure may be readily incorporated into existing semiconductor manufacturing processes.

[0042] In one aspect, this disclosure is directed to a method. The method includes receiving a structure having a substrate, a conductive feature over the substrate, and a dielectric layer over the conductive feature and the substrate.The method further includes forming a hole in the dielectric layer, the hole exposing the conductive feature; forming a first metal-containing layer on at least sidewalls of the hole; forming a second metal-containing layer in the hole surrounded by the first metal-containing layer, the first and second metal-containing layers containing different materials; applying a first chemical to thin the dielectric layer, resulting in an upper portion of the first metal-containing layer and an upper portion of the second metal-containing layer protruding above the dielectric layer; and applying a second chemical comprising fluorine or chlorine to the upper portion of the first metal-containing layer to convert the upper portion of the first metal-containing layer to a metal fluoride or a metal chloride.

[0043] In some embodiments, the first chemical contains dilute hydrofluoric acid (HF acid), and the second chemical contains dilute hydrochloric acid (HCl acid). In another embodiment, the dilute hydrofluoric acid has an HF concentration in deionized water of approximately 0.1% or less, and the dilute hydrochloric acid has an HCl concentration in deionized water of approximately 1% or more.

[0044] In one embodiment, the first metal-containing layer contains a transition metal, a transition metal nitride, or a combination thereof. In another embodiment, the transition metal or transition metal nitride contains either Ti, Co, Ni, Nb, Ru, Rh, W, or Re.

[0045] In another embodiment, forming the second metal-containing layer includes depositing the second metal-containing layer over the dielectric layer. The method further includes applying a chemical mechanical planarization (CMP) process to the second metal-containing layer to expose the dielectric layer.

[0046] In one embodiment of the process, the first chemical comprises a dilute hydrofluoric acid (HF acid) with a first HF concentration in deionized water of approximately 0.1% or less, and the second chemical comprises another dilute HF acid with a second HF concentration in deionized water, and the second concentration is at least 10 times higher than the first concentration. In another embodiment, the second concentration is approximately 1% to 2%.

[0047] In one embodiment, the dielectric layer includes silicon oxide. In an embodiment where the conductive feature includes a doped semiconductor, the method further includes, after forming the first metal-containing layer, annealing the first metal-containing layer and the conductive feature to result in a metal silicide between the first metal-containing layer and the conductive feature.

[0048] In another aspect, this disclosure is directed to a method. The method includes receiving a structure having a substrate, a conductive feature over the substrate, and a dielectric layer over the conductive feature and the substrate, wherein the dielectric layer comprises silicon oxide. The method further includes etching a hole in the dielectric layer, the hole exposing the conductive feature; depositing a first metal-containing layer on the bottom and sidewalls of the hole, the first metal-containing layer comprising a transition metal or a transition metal nitride; depositing a second metal-containing layer in the hole, over the first metal-containing layer, and over the dielectric layer, the first and second metal-containing layers comprising different materials;performing a chemical mechanical planarization (CMP) process on the second metal-containing layer to expose the dielectric layer; applying a first chemical to recess the dielectric layer, resulting in an upper portion of the first metal-containing layer and an upper portion of the second metal-containing layer protruding above the dielectric layer; and applying a second chemical comprising fluorine or chlorine to the upper portion of the first metal-containing layer to convert the upper portion of the first metal-containing layer to a transition metal fluoride or a transition metal chloride.

[0049] In one embodiment of the process, the first chemical comprises a dilute hydrofluoric acid (HF acid), and the second chemical comprises a dilute hydrochloric acid (HCl acid). In another embodiment, the dilute HF acid has an HF concentration in deionized water of approximately 0.1% or lower, and the dilute HCl acid has an HCl concentration in deionized water of approximately 1% to 2%.

[0050] In another embodiment of the method, the first chemical comprises a dilute hydrofluoric acid (HF acid) with a first HF concentration in deionized water of approximately 0.1% or lower, and the second chemical comprises another dilute HF acid with a second HF concentration in deionized water of approximately 1% to 2%. In yet another embodiment, the first metal-containing layer comprises either Ti, TiN, Ta, or TaN.

[0051] In yet another aspect, this disclosure is directed to a semiconductor structure. The semiconductor structure includes a substrate, a conductive feature over the substrate; a dielectric layer over the conductive feature and the substrate; and a structure disposed over the conductive feature and at least partially surrounded by the dielectric layer. The structure includes a first metal-containing layer and a second metal-containing layer surrounded by the first metal-containing layer. The first and second metal-containing layers contain different materials. A lower portion of the first metal-containing layer contains a transition metal or a transition metal nitride, and an upper portion of the first metal-containing layer contains a transition metal fluoride or a transition metal chloride.

[0052] In one embodiment of the semiconductor structure, the lower portion of the first metal-containing layer contains titanium or titanium nitride, and the upper portion of the first metal-containing layer contains titanium fluoride or titanium chloride. In another embodiment of the semiconductor structure, the lower portion of the first metal-containing layer contains tantalum or tantalum nitride, and the upper portion of the first metal-containing layer contains tantalum fluoride or tantalum chloride.

[0053] In one embodiment, the first metal-containing layer contains Ti or Ta, and the second metal-containing layer contains W, Co, Ru, or Cu. In one embodiment, the semiconductor structure further includes a metal silicide between the conductive feature and the first metal-containing layer.

Claims

[1] Procedure comprising: Receiving a structure comprising a substrate (110), a conductive feature (160) over the substrate (110), and a dielectric layer (240) over the conductive feature (160) and the substrate (110). Forming a hole (242) in the dielectric layer (240), the hole (242) exposing the conductive feature (160); Forming a first metal-containing layer (300) at least on sidewalls of the hole (242); Forming a second metal-containing layer (304) in the hole (242) surrounded by the first metal-containing layer (300), wherein the first metal-containing layer (300) and the second metal-containing layer (304) contain different materials; Applying a first chemical (305) to recess the dielectric layer (240), thereby resulting in an upper portion of the first metal-containing layer (300) and an upper portion of the second metal-containing layer (304) projecting beyond the dielectric layer (240); and Applying a second chemical (307) containing fluorine or chlorine to the upper portion of the first metal-containing layer (300) to convert the upper portion of the first metal-containing layer (300) into a metal fluoride or a metal chloride, wherein the first chemical (305) comprises dilute hydrochloric acid. [2] The method of claim 1, wherein the second chemical (307) comprises dilute hydrochloric acid, HCl. [3] The method of claim 2, wherein the dilute hydrochloric acid of the first chemical (305) has an HCl concentration in deionized water of about 0.1% or less, and wherein the dilute hydrochloric acid of the second chemical (307) has an HCl concentration in deionized water of about 1% or more. [4] A method according to any one of the preceding claims, wherein the first metal-containing layer (300) contains a transition metal, a transition metal nitride or a combination thereof. [5] The method of claim 4, wherein the transition metal or transition metal nitride contains one of Ti, Co, Ni, Nb, Ru, Rh, W or Re. [6] The method of any preceding claim, wherein forming the second metal-containing layer (304) comprises depositing the second metal-containing layer (304) over the dielectric layer (240), and the method further comprises: Performing a chemical mechanical planarization process, CMP process, on the second metal-containing layer (304) to expose the dielectric layer (240). [7] A method according to any one of the preceding claims, wherein the dielectric layer (240) contains silicon oxide. [8] The method of any preceding claim, wherein the conductive feature (160) includes a doped semiconductor, the method further comprising: after forming the first metal-containing layer (300), annealing the first metal-containing layer (300) and the conductive feature (160) to obtain a metal silicide between the first metal-containing layer (300) and the conductive feature (160). [9] Procedure comprising: Receiving a structure comprising a substrate (110), a conductive feature (160) over the substrate (110), and a dielectric layer (240) over the conductive feature (160) and the substrate (110), the dielectric layer (240) comprising silicon oxide; Etching a hole (242) into the dielectric layer (240), the hole (242) exposing the conductive feature (160); Depositing a first metal-containing layer (300) on the bottom and sidewalls of the hole (242), wherein the first metal-containing layer (300) comprises a transition metal or a transition metal nitride; Depositing a second metal-containing layer (304) in the hole (242) over the first metal-containing layer (300) and over the dielectric layer (240), wherein the first metal-containing layer (300) and the second metal-containing layer (304) contain different materials from each other; performing a chemical mechanical planarization process, CMP, on the second metal-containing layer (304) to expose the dielectric layer (240); Applying a first chemical (305) to recess the dielectric layer (240), thereby resulting in an upper portion of the first metal-containing layer (300) and an upper portion of the second metal-containing layer (304) projecting beyond the dielectric layer (240); and Applying a second chemical (307) containing fluorine or chlorine to the upper portion of the first metal-containing layer (300) to convert the upper portion of the first metal-containing layer (300) into a transition metal fluoride or a transition metal chloride, wherein the first chemical (305) comprises dilute hydrochloric acid. [10] The method of claim 9, wherein the second chemical (307) comprises dilute hydrochloric acid, HCl. [11] The method of claim 10, wherein the dilute hydrochloric acid of the first chemical (305) has an HCl concentration in deionized water of about 0.1% or less, and wherein the dilute hydrochloric acid of the second chemical (307) has an HCl concentration in deionized water of about 1% or more. [12] Method according to one of the preceding claims 9 to 11, wherein the first metal-containing layer (300) contains Ti, TiN, Ta or TaN.

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