MEMORY DEVICE AND MTJ MEMORY DEVICE USING A DIELECTRIC ETCH STOP LAYER AND METHOD FOR FORMING THE SAME

Abstract

Storage device comprising: an array of memory cells (101) overlying a substrate (9) and arranged in a memory array region (100), each of the memory cells (101) comprising a vertical stack comprising a lower electrode (126), a memory element and an upper electrode (160); a logic area (200) arranged outside the memory array area (100) and free of memory cells (101); a dielectric etch stop layer (170) comprising: a horizontally extending portion extending continuously through the memory array region (100) and the logic region (200), and an array of vertically projecting portions laterally surrounding each of the memory cells (101) in the array of memory cells (101), each of the vertically projecting portions having an opening in an uppermost region and a corresponding annular uppermost surface, which is arranged within a horizontal plane comprising the upper surfaces of the upper electrodes (160); and Metal cell contact structures (188) contacting a respective subset of the upper electrodes (160) and a respective subset of the vertically projecting portions of the dielectric etch stop layer (170).

Description

GENERAL STATE OF THE ART

[0001] The present disclosure is directed to semiconductor devices, and more particularly to a semiconductor memory device using an etch stop hard mask layer for contact via structures and methods of forming the same.

[0002] Semiconductor memory devices are widely used in modern electronic devices. Some semiconductor memory devices employ memory cells comprising a respective vertical stack of a bottom electrode, a memory element, and a top electrode. A magnetic tunnel junction memory device, for example, may employ such a vertical stack in which the memory element comprises a magnetic tunnel junction. Electrical contact with the top electrodes may be provided using contact via structures.

[0003] From the publication DE 10 2018 122 524 A1, a memory device with memory cells arranged above a substrate is known. The memory cells each have an upper electrode on which a dielectric layer is formed. Electrode vias, which contact a relatively narrow section of the upper electrode, extend through the dielectric layer.

[0004] The document US 2019 / 0 165 041 A1 describes a semiconductor structure comprising magnetic tunnel junctions (MTJs) and a spacer layer, wherein the MTJs are laterally surrounded by the spacer layer and the spacer layer extends only through a memory array region of the semiconductor device, but not through a logic region.

[0005] From the publication US 2019 / 0 164 584 A1, an MRAM structure is known that comprises an array region and a logic region. MTJs are formed in the array region. The MTJs are laterally surrounded by an oxide layer that extends through the array region and the logic region. An uppermost region of the oxide layer lies above a horizontal plane in which the upper surfaces of the upper electrodes of the MTJs lie.

[0006] Further storage devices are known from the documents US 2017 / 0 194 557 A1, US 2020 / 0 006 638 A1, US 10 199 566 B2 and US 2018 / 0 374 901 A1.

[0007] The task is to improve corresponding storage devices. SUMMARY OF THE INVENTION

[0008] The object is achieved by a memory device according to claim 1, a magnetic tunnel junction memory device, MTJ memory device, according to claim 11 and a method for forming a memory device according to claim 15. Advantageous embodiments of the invention are specified in the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Aspects of the present disclosure can best be understood by reference to the following detailed description when taken in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not drawn to scale. Indeed, the dimensions of various features may be arbitrarily exaggerated or reduced for the sake of clarity of illustration. Fig. 1 is a vertical cross-sectional view of an exemplary structure after formation of complementary metal oxide semiconductor (CMOS) transistors and metal interconnect structures formed in layers of dielectric material according to an embodiment of the present disclosure. Fig. 2 is a vertical cross-sectional view of the exemplary structure after formation of a dielectric cap layer and a dielectric via level structure according to an embodiment of the present disclosure. Fig. 3 is a vertical cross-sectional view of the exemplary structure after formation of contact via cavities for bottom electrodes according to an embodiment of the present disclosure. Fig. 4 is a vertical cross-sectional view of the exemplary structure after formation of a continuous metallic barrier layer and portions of metallic via fill material according to an embodiment of the present disclosure. Fig. 5 is a vertical cross-sectional view of the exemplary structure after formation of a continuous bottom electrode material layer, a continuous non-magnetic metallic buffer layer, a continuous selector material layer, a continuous synthetic antiferromagnetic layer, a continuous non-magnetic tunnel barrier layer, a continuous free magnetization layer, at least one continuous cap layer, and a continuous top electrode material layer according to an embodiment of the present disclosure. Fig. 6 is a vertical cross-sectional view of the exemplary structure after forming an array of individual vertical stacks, each comprising a selector element, a synthetic antiferromagnetic structure, a non-magnetic tunnel barrier layer, a free magnetization layer, at least one cap layer, and a top electrode, according to an embodiment of the present disclosure. Fig. 7 is a vertical cross-sectional view of the exemplary structure after formation of an array of dielectric spacers according to an embodiment of the present disclosure. Fig. 8 is a vertical cross-sectional view of the exemplary structure after formation of non-magnetic metallic buffer layers, bottom electrodes, and via structures for connecting bottom electrodes according to an embodiment of the present disclosure. Fig. 9 is a vertical cross-sectional view of the exemplary structure after formation of a dielectric etch stop layer and a silicon oxide liner layer according to an embodiment of the present disclosure. Fig. 10 is a vertical cross-sectional view of the exemplary structure after formation of a first dielectric matrix layer and a planarization stop sacrificial material layer according to an embodiment of the present disclosure. Fig. 11 is a vertical cross-sectional view of the exemplary structure after a chemical mechanical planarization process using portions of the dielectric etch stop layer in a memory array region and portions of the planarization stop sacrificial material layer in a logic region as stop structures according to an embodiment of the present disclosure. Fig. 12 is a vertical cross-sectional view of the exemplary structure after a corrective planarization process that removes portions of the dielectric etch stop layer in the memory array region and portions of the planarization stop sacrificial material layer in the logic region, according to an embodiment of the present disclosure. Fig. 13 is a vertical cross-sectional view of the exemplary structure after formation of a second dielectric matrix layer according to an embodiment of the present disclosure. Fig. 14 is a vertical cross-sectional view of the exemplary structure after formation of via cavities in the logic region according to an embodiment of the present disclosure. Fig. 15 is a vertical cross-sectional view of the exemplary structure after formation of integrated line and via cavities in the logic region and cell contact cavities in the memory array region according to an embodiment of the present disclosure. Fig. 16 is a vertical cross-sectional view of the exemplary structure after formation of integrated line and via cavities in the logic region and metal cell contact structures in the memory array region according to an embodiment of the present disclosure. Fig. 17 is a vertical cross-sectional view of an exemplary structure after formation of additional metal interconnect structures formed in additional dielectric material layers according to an embodiment of the present disclosure. Fig. 18 is a flowchart illustrating the general processing steps of the methods of the present disclosure. DETAILED DESCRIPTION

[0010] The following disclosure presents many different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, only examples and are not to be construed as limiting. For example, the formation of a first feature over or on top of a second feature in the following description may include embodiments in which the first feature and the second feature are formed in direct contact with each other, and may also include embodiments in which additional features may be formed between the first feature and the second feature such that the first feature and the second feature may not be in direct contact with each other. Furthermore, the present disclosure may repeat reference numbers and / or characters in the various examples.This repetition is for the purpose of simplicity and clarity, and does not in itself prescribe any relationship between the various embodiments and / or configurations discussed.

[0011] Furthermore, terms of spatial relationships such as "below," "beneath," "lower," "above," "upper," and the like may be used herein for the purpose of more easily describing the relationship of one element or feature depicted in the figures to another element or feature. The terms of spatial relationships are intended to encompass various orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be oriented differently (rotated 90 degrees or in other orientations), and the terms of spatial relationships used herein may thus be interpreted accordingly.

[0012] In general, the structures and methods of the present disclosure can be used for memory devices comprising an array of memory cells overlying a substrate and arranged in a memory array region, and a logic region arranged outside the memory array region and free of memory cells. Each of the memory cells may comprise a vertical stack including a bottom electrode, a memory element, and a top electrode. The vertical stacks may be arranged as a one-dimensional array or as a two-dimensional array with a high density sufficient to provide a topographical average height difference for a dielectric matrix layer to be subsequently formed. However, increasing the density of memory cells introduces additional manufacturing challenges.As the lateral dimensions of memory cells decrease, the process window for forming contact via structures also shrinks. Differences in the height of dielectric matrix layers can lead to overetching or underetching of the dielectric matrix layer. For example, overetching during the formation of via cavities for forming the contact via structures can cause electrical shorts (i.e., an electrical connection) to underlying material layers. Underetching during the formation of the via cavities for forming the contact via structures can cause electrical circuit breaks between the top electrodes and the contact via structures.

[0013] A dielectric etch stop layer may be formed in conjunction with the array of memory cells prior to the formation of the dielectric matrix layer. The dielectric etch stop layer may be used as a planarization stop material layer during the planarization of the dielectric matrix layer. The dielectric etch stop layer may subsequently also be used as an etch stop layer during an anisotropic etch process that forms cell contact cavities for forming contacts to the top electrodes. The memory element within each of the memory cells may be any type of memory cell having a planar layer structure.While the present disclosure is described using an embodiment in which each memory element includes a magnetic tunnel junction providing magnetoresistance, embodiments in which the magnetic tunnel junction is replaced by any layer or layer stack capable of providing at least two different resistance states between the bottom electrode and the top electrode are expressly contemplated herein. Therefore, the claims of the present disclosure are to be interpreted to encompass all such variations, unless otherwise limited to magnetoresistive memory devices including a corresponding magnetic tunnel junction.

[0014] It is further understood that the memory devices according to embodiments of the present disclosure may comprise a single discrete memory cell, a one-dimensional array of memory cells, or a two-dimensional array of memory cells. It is also further understood that a one-dimensional array of memory cells of the present disclosure may be implemented as a periodic one-dimensional array of memory cells, and that a two-dimensional array of memory cells of the present disclosure may be implemented as a periodic two-dimensional array of memory cells.Further, while the present disclosure is described using an embodiment in which a two-dimensional array of memory cells is formed within fifth metal interconnect levels, generally referred to as a fifth line-and-via level (M5 + V4), embodiments in which the two-dimensional array of memory cells is formed within different metal interconnect levels are expressly contemplated herein.

[0015] Referring to Fig. 1 illustrates an exemplary structure according to an embodiment of the present disclosure. The exemplary structure includes a substrate 9, which may be a semiconductor substrate, such as a commercially available silicon substrate. Trench isolation structures 720 comprising a dielectric material, such as silicon oxide, may be formed in an upper portion of the substrate 9. Suitable doped semiconductor wells, such as p-wells and n-wells, may be formed within each of the regions laterally enclosed by a continuous portion of the trench isolation structures 720. Field-effect transistors may be formed over the upper surface of the substrate 9.For example, each of the field-effect transistors may include a source region 732, a drain region 738, a semiconductor channel 735 comprising a surface portion of the substrate 9 extending between the source region 732 and the drain region 738, and a gate structure 750. Each of the gate structures 750 may include a gate dielectric 752, a gate electrode 754, a gate cap dielectric 758, and a gate spacer dielectric 756. A source-side metal-semiconductor alloy region 742 may be formed at each of the source regions 732, and a drain-side metal-semiconductor alloy region 748 may be formed at each of the drain regions 738.

[0016] The exemplary structure may include a memory array region 100, in which an array of memory cells is subsequently formed, and a logic region 200, in which logic devices that support the operation of the array of memory elements are formed. In one embodiment, devices (such as field-effect transistors) in the memory array region 100 may include bottom electrode access transistors that provide access to bottom electrodes of memory cells to be subsequently formed. Top electrode access transistors that provide access to top electrodes of memory cells to be subsequently formed may be formed in the logic region 200 in this processing step.Devices (such as field-effect transistors) in logic region 200 may provide functions required to operate the array of memory cells to be subsequently formed. In particular, devices / components in the logic region may be configured to control the programming operation, the erasing operation, and the reading operation of the array of memory cells. For example, the devices in the logic region may include a sensing circuit and / or a top electrode bias circuit. The devices formed on the top surface of substrate 9 may include complementary metal-oxide-semiconductor (CMOS) transistors and optionally additional semiconductor devices (such as resistors, diodes, capacitors, etc.), and are collectively referred to as CMOS circuitry 700.

[0017] Various metal interconnect structures formed in dielectric material layers may subsequently be formed over the substrate 9 and the devices (such as the field-effect transistors). The dielectric material layers may include, for example, a contact level dielectric material layer 601, a first metal line level dielectric material layer 610, a second line and via level dielectric material layer 620, a third line and via level dielectric material layer 630, and a fourth line and via level dielectric material layer 640. The metal interconnect structures may include device contact via structures 612 formed in the contact level dielectric material layer 601 and contacting a respective component of the CMOS circuit 700, first metal line structures 618,which are formed in the first metal line-level dielectric material layer 610, first metal via structures 622 which are formed in a lower portion of the second line-and-via-level dielectric material layer 620, second metal via structures 628 which are formed in an upper portion of the second line-and-via-level dielectric material layer 620, second metal via structures 632 which are formed in a lower portion of the third line-and-via-level dielectric material layer 630, third metal via structures 638 which are formed in an upper portion of the third line-and-via-level dielectric material layer 630, third metal via structures 642 which are formed in a lower portion of the fourth line-and-via-level dielectric material layer 640,and fourth metal line structures 648 formed in an upper portion of the fourth line-and-via-level dielectric material layer 640. In one embodiment, the second metal line structures 648 may include source lines connected to a source-side power supply for an array of memory elements. The voltage provided by the source lines may be applied to the lower electrodes by the access transistors provided in the memory array region 100.

[0018] Each of the dielectric material layers (601, 610, 620, 630, 640) may include a dielectric material, such as undoped silicate glass, doped silicate glass, organosilicate glass, amorphous fluorinated carbon, porous variants thereof, or combinations thereof. Each of the metal interconnect structures (612, 618, 622, 628, 632, 638, 642, 648) may include at least one conductive material, which may be a combination of a metal liner layer (such as a metal nitride or a metal carbide) and a metal fill material. Each of the metal conductive layers may include TiN, TaN, WN, TiC, TaC, and WC, and each of the metal fill material portions may include W, Cu, Al, Co, Ru, Mo, Ta, Ti, alloys thereof, and / or combinations thereof. Other suitable materials may also be used.In one embodiment, the first metal via structures 622 and the second metal line structures 628 may be formed as integrated line and via structures by a double damascene process, the second metal via structures 632 and the third metal line structures 638 may be formed as integrated line and via structures, and / or the third metal via structures 642 and the fourth metal line structures 648 may be formed as integrated line and via structures.While the present disclosure is described using an embodiment in which an array of memory cells is formed over the fourth line and via level material layer 640, embodiments in which the array of memory cells may be formed in different metal interconnect levels are also expressly contemplated herein.

[0019] Referring to Fig. 2, a dielectric cap layer 108 and a dielectric via level layer 110 may be formed sequentially over the metal interconnect structures and the dielectric material layers. For example, the dielectric cap layer 108 may be formed on the upper surfaces of the fourth metal line structures 648 and on the upper surface of the fourth line-and-via dielectric material layer 640. The dielectric cap layer 108 includes a dielectric cap material that may protect underlying metal interconnect structures, such as the fourth metal line structures 648. In one embodiment, the dielectric cap layer 108 may include a material that may provide high etch resistance, i.e.a dielectric material, and which may also serve as an etch stop material during a subsequent anisotropic etch process that etches the via level dielectric layer 110. For example, the dielectric cap layer 108 may include silicon carbide or silicon nitride, and may have a thickness in a range of 5 nm to 30 nm, although thinner and thicker thicknesses may also be used.

[0020] The via level dielectric layer 110 may include any material that can be used for the dielectric material layers (601, 610, 620, 630, 640). For example, the via level dielectric layer 110 may comprise undoped silicate glass or a doped silicate glass deposited by decomposition of tetraethyl orthosilicate (TEOS). The thickness of the via level dielectric layer 110 may range from 50 nm to 200 nm, although thinner and thicker thicknesses may also be used. The cap dielectric layer 108 and the via level dielectric layer 110 may be formed as planar (unpatterned) cap layers having a corresponding planar top surface and a corresponding planar bottom surface that extends throughout the memory array region 100 and the logic region 200.

[0021] Referring to Fig. 3, via cavities may be formed through the via level dielectric layer 110 and the cap dielectric layer 108. For example, a photoresist layer (not shown) may be applied over the via level dielectric layer 110 and may be patterned to form an opening within portions of the memory array region 100 that overlie a respective one of the fourth metal line structures 648. An anisotropic etch may be performed to transfer the pattern in the photoresist layer through the via level dielectric layer 110 and the cap dielectric layer 108.The via cavities formed by the anisotropic etching process are referred to herein as bottom electrode contact via cavities 121 because bottom electrode connection via structures are subsequently formed in the bottom electrode contact via cavities 121. The bottom electrode contact via cavities 121 may have tapered sidewalls having a taper angle (with respect to a vertical direction) in a range of 1 degree to 10 degrees. A top surface of a fourth metal line structure 648 may be physically exposed at the bottom of each bottom electrode contact via cavity 121. The photoresist layer may subsequently be removed, for example, by ashing.

[0022] Referring to Fig. 4, a continuous metal barrier layer 122L may be formed as a continuous material layer. The continuous metal barrier layer 122L may cover physically exposed upper surfaces of the fourth metal line structures 648, tapered sidewalls of the lower electrode contact via cavities 121, and the upper surface of the dielectric via level layer 110 without any hole therethrough. The continuous metal barrier layer 122L may include a conductive metal nitride, such as TiN, TaN, and / or WN. Other suitable materials may also be used. The thickness of the continuous metal barrier layer 122L may range from 3 nm to 20 nm, although thinner and thicker thicknesses may also be used.

[0023] A metal fill material, such as tungsten or copper, may be deposited in remaining volumes of the lower electrode contact via layers 121. Portions of the metal fill material that lie above the horizontal plane comprising the top surface of the continuous metal barrier layer 122L may be removed by a planarization process, such as chemical mechanical planarization, to form metal via fill material portions 124. Each of the metal via fill material portions 124 may have a top surface that is coplanar with the top surface of the continuous metal barrier layer 122L.

[0024] Referring to Fig. 5, a layer stack comprising a continuous lower electrode material layer 126L, a continuous non-magnetic metal buffer layer 128L, a continuous selector material layer 130L, a continuous synthetic antiferromagnetic layer 140L, a continuous non-magnetic tunnel barrier layer 146L, a continuous free magnetization layer 148L, at least one continuous cap layer 158L, and a continuous upper electrode material layer 160L may be formed over the continuous metal barrier layer 122L and the metal via fill material portions 124. The layers within the layer stack may be deposited by a respective chemical vapor deposition process or a respective physical vapor deposition process. Each of the layers within the layer stack may be deposited as a planar cap material layer each having a continuous uniform thickness.

[0025] The continuous bottom electrode material layer 126L includes at least one metallic material, such as TiN, TaN, WN, W, Cu, Al, Ti, Ta, Ru, Co, Mo, Pt, an alloy thereof, and / or a combination thereof. Other suitable materials may also be used. For example, the continuous bottom electrode material layer 126L may include and / or be formed essentially of tungsten (W). The thickness of the continuous bottom electrode material layer 126L may range from 10 nm to 100 nm, although thinner and thicker thicknesses may also be used.

[0026] The continuous non-magnetic metal buffer layer 128L includes a non-magnetic material that can serve as a seed layer. In particular, the continuous non-magnetic metal buffer layer 128L can provide a crystalline template structure that aligns polycrystalline grains of the materials of the continuous synthetic antiferromagnetic layer 140L along directions that maximize the magnetization of a reference layer within the continuous synthetic antiferromagnetic layer 140L. The continuous non-magnetic metal buffer layer 128L can include Ti, a CoFeB alloy, a NiFe alloy, ruthenium, or a combination thereof. The thickness of the continuous non-magnetic metal barrier layer 128L can range from 3 nm to 30 nm, although thinner and thicker thicknesses can also be used.

[0027] The continuous selector material layer 130L comprises a selector material, i.e., a material exhibiting a voltage-dependent switching characteristic. The continuous selector material layer 130L may include an oxygen vacancy-modulated selector material, such as hafnium oxide or zirconium oxide, an ovonic threshold switching material, such as zinc telluride, or a vertical diode layer stack comprising a p-doped semiconductor layer and an n-doped semiconductor layer with a horizontal pn junction between them. Alternatively, other materials that turn on at a high bias and turn off at a low bias may be used for the continuous selector material layer 130L.

[0028] The continuous synthetic antiferromagnetic layer (SAF layer) 140L may comprise a layer stack of a ferromagnetic hard layer 141, an antiferromagnetic coupling layer 142, and a reference magnetization layer 143. Both the ferromagnetic hard layer 141 and the reference magnetization layer 143 may each have a fixed magnetization direction. The antiferromagnetic coupling layer 142 provides an antiferromagnetic coupling between the magnetization of the ferromagnetic hard layer 141 and the magnetization of the reference magnetization layer 143, such that the magnetization direction of the ferromagnetic hard layer 141 and the magnetization direction of the reference magnetization layer 143 remain fixed during operation of the memory cells to be subsequently formed. The ferromagnetic hard layer 141 may contain a hard ferromagnetic material such as PtMn, IrMn, RhMn, FeMn, OsMn, etc.The reference magnetization layer 143 may contain a hard ferromagnetic material, such as Co, CoFe, CoFeB, CoFeTa, NiFe, CoPt, CoFeNi, etc. Other suitable materials may also be used. The antiferromagnetic coupling layer 142 may contain ruthenium or iridium. The thickness of the antiferromagnetic coupling layer 142 may be selected such that the exchange interaction induced by the antiferromagnetic coupling layer 142 stabilizes the relative magnetization directions of the hard ferromagnetic layer 141 and the reference magnetization layer 143 in opposite directions, i.e., in an antiparallel orientation. In one embodiment, the net magnetization of the continuous SAF layer 140L is adjusted by matching the magnetization magnitude of the hard ferromagnetic layer 141 to the magnetization magnitude of the reference magnetization layer 143.The thickness of the continuous SAF layer 140L can range from 5 nm to 30 nm, although thinner and thicker thicknesses can also be used.

[0029] The continuous non-magnetic tunnel barrier layer 146L may include a tunnel barrier material, which may be an electrically insulating material having a thickness that enables electron tunneling effects. For example, the continuous non-magnetic tunnel barrier layer 146L may include magnesium oxide (MgO), aluminum oxide (Al2O3), aluminum nitride (AlN), aluminum oxynitride (AlON), hafnium oxide (HfO2), or zirconium oxide (ZrO2). Other suitable materials may also be used. The thickness of the continuous non-magnetic tunnel barrier layer 146L may range from 0.7 nm to 1.3 nm, although thinner and thicker thicknesses may also be used.

[0030] The continuous free magnetization layer 148L contains a ferromagnetic material having two stable magnetization directions that are parallel or antiparallel to the magnetization direction of the reference magnetization layer 143. The continuous free magnetization layer 148L contains a hard ferromagnetic material, such as Co, CoFe, CoFeB, CoFeTa, NiFe, CoPt, CoFeNi, etc. Other suitable materials may also be used. The thickness of the continuous free magnetization layer 148L can range from 1 nm to 6 nm, although thinner and thicker thicknesses may also be used.

[0031] The at least one continuous cap layer 158L includes at least one cap material. Example cap materials that may be used for the at least one continuous cap layer 158L include, but are not limited to, a metallic material such as Be, Mg, Al, Ti, Ta, W, Ge, Pt, Ru, Cu, an alloy thereof, and a layer stack thereof. Other suitable materials may also be used. Additionally or alternatively, the at least one continuous cap layer 158L may include a conductive metal nitride and / or a conductive metal nitride. The total thickness of the at least one continuous cap layer 158L may range from 0.5 nm to 5 nm, although thinner and thicker thicknesses may also be used.

[0032] The continuous upper electrode material layer 160L includes at least one metallic material, such as TiN, TaN, WN, W, Cu, Al, Ti, Ta, Ru, Co, Mo, Pt, an alloy thereof, and / or a combination thereof. Other suitable materials may also be used. For example, the continuous upper electrode material layer 160L may include and / or be formed essentially of tungsten (W). The thickness of the continuous upper electrode material layer 160L may range from 10 nm to 100 nm, although thinner and thicker thicknesses may also be used.

[0033] Referring to Fig. 6, a photoresist layer may be applied over the continuous top electrode material layer 160L and lithographically patterned to form an array of individual photoresist material sections. Each individual photoresist material section in the array of individual photoresist material sections may overlie a respective one of the metal via fill material sections 124. In one embodiment, the metal via fill material section 124 may be configured as a two-dimensional periodic array having a first pitch along a first horizontal direction and a second pitch along a second horizontal direction. The individual photoresist material sections may be configured as a two-dimensional periodic array having the same periodicity as the two-dimensional periodic array of the metal via fill material sections 124.

[0034] An anisotropic etching process may be performed to etch unmasked portions of the continuous top electrode material layer 160L, the at least one continuous cap layer 158L, the continuous free magnetization layer 148L, the continuous non-magnetic tunnel barrier layer 146L, the continuous SAF layer 140L, and the continuous selector material layer 130L.The chemistry of the anisotropic etch process may be selected such that patterned portions of the continuous top electrode material layer 160L, the at least one continuous cap layer 158L, the continuous free magnetization layer 148L, the continuous non-magnetic tunnel barrier layer 146L, the continuous SAF layer 140L, and the continuous selector material layer 130L have tapered sidewalls having a taper angle in a range of 1 degree to 20 degrees, for example, from 3 degrees to 10 degrees, with respect to the vertical direction. In one embodiment, the continuous non-magnetic metal buffer layer 128L may be used as an etch stop layer for the anisotropic etch process.

[0035] The patterned portions of the continuous top electrode material layer 160L, the at least one continuous cap layer 158L, the continuous free magnetization layer 148L, the continuous non-magnetic tunnel barrier layer 146L, the continuous SAF layer 140L, and the continuous selector material layer 130L may represent an arrangement of individual vertical stacks. From bottom to top, each individual vertical stack may include a selector element 130, a synthetic antiferromagnetic (SAF) structure 140, a non-magnetic tunnel barrier layer 146, a free magnetization layer 148, at least one cap layer 158, and a top electrode 160. Each selector element 130 is a patterned portion of the continuous selector material layer 130L. Each SAF structure 140 is a patterned portion of the continuous SAF layer 140L.Each non-magnetic tunnel barrier layer 146 is a patterned portion of the continuous non-magnetic tunnel barrier layer 146L. Each free magnetization layer 148 is a patterned portion of the continuous free magnetization layer 148L. Each cap layer 158 is a patterned portion of the at least one continuous cap layer 158L. Each top electrode 160 is a patterned portion of the continuous top electrode material layer 160L.

[0036] The array of individual vertical stacks (130, 140, 146, 148, 158, 160) can be formed over the substrate 9 in the memory array region 100. Each SAF structure 140 comprises a layer stack consisting of a ferromagnetic hard layer 141, an antiferromagnetic coupling layer 142, and a reference magnetization layer 143. A group of a reference magnetization layer 143, a non-magnetic tunnel barrier layer 146, and a free magnetization layer 148 within a single vertical stack (130, 140, 146, 148, 158, 160) represents a magnetic tunnel junction (MTJ), which serves as a magnetoresistive memory element. The magnetization of the free magnetization layer 148 and the magnetization of the reference magnetization layer 143 within each individual vertical stack (130, 140, 146, 148, 158, 160) may have two stable orientations, including a parallel orientation and an antiparallel orientation.The bistable magnetic coupling between the ferromagnetic material of the free magnetization layer 148 and the ferromagnetic material of the reference magnetization layer 143 within each of the magnetic tunnel junctions provides a magnetoresistance, i.e., a change in resistance between the free magnetization layer 148 and the reference magnetization layer 143, which depends on the alignment of the magnetization directions of the free magnetization layer 148 and the reference magnetization layer 143. Sidewalls of each element within individual vertical stacks (130, 140, 146, 148, 158, 160) may be physically exposed after the anisotropic etching process. The photoresist layer may subsequently be removed, for example, by ashing.

[0037] While the present disclosure is described using an embodiment in which the continuous metal barrier layer 122L, the continuous bottom electrode material layer 126L, and the continuous non-magnetic metal buffer layer 128L are not patterned in this processing step, embodiments in which the continuous metal barrier layer 122L, the continuous bottom electrode material layer 126L, and the continuous non-magnetic metal buffer layer 128L are patterned in this processing step are expressly contemplated herein.

[0038] Referring to Fig. 7, at least one dielectric spacer material layer may be conformally deposited over the array of individual vertical stacks (130, 140, 146, 148, 158, 160) and on the physically exposed portions of the upper surface of the continuous non-magnetic metal buffer layer 128L. For example, a first dielectric spacer material layer comprising a first dielectric spacer material and a second dielectric spacer material layer comprising a second dielectric spacer material may be sequentially deposited using a corresponding conformal deposition process (such as a chemical vapor deposition process).For example, the first dielectric spacer material may include silicon nitride or a dielectric metal oxide (such as aluminum oxide), and the second dielectric spacer material may include silicon oxide (such as TEOS oxide). The thickness of the first dielectric spacer material layer may range from 3 nm to 10 nm, and the thickness of the second dielectric spacer material layer may range from 30 nm to 100 nm, although thinner and thicker thicknesses may be used for both the first dielectric spacer material layer and the second dielectric spacer material layer.

[0039] An anisotropic etch process may be performed to remove horizontal portions of the at least one dielectric spacer material layer. The anisotropic etch process, which etches the first dielectric spacer material and the second dielectric spacer material, may be selective for the materials of the continuous non-magnetic metal buffer layer 128L and the top electrodes 160. Each remaining portion of the first dielectric spacer material layer represents a first dielectric spacer 162, and each remaining portion of the second dielectric spacer material layer represents a second dielectric spacer 164. In general, an array of dielectric spacers (162, 164) may be formed around, and on, a respective individual vertical stack (130, 140, 146, 148, 158, 160) in the array of individual vertical stacks (130, 140, 146, 148, 158, 160).In one embodiment, each individual vertical stack (130, 140, 146, 148, 158, 160) may be laterally surrounded by a first dielectric spacer 162 and a second dielectric spacer 164. In another embodiment, the first dielectric spacers 162 may be omitted. In some embodiments, each individual vertical stack (130, 140, 146, 148, 158, 160) may be laterally surrounded by a single dielectric spacer, i.e., a second dielectric spacer 164.

[0040] Referring to Fig. 8, an etching process may be performed to pattern the continuous non-magnetic metal buffer layer 128L, the continuous bottom electrode material layer 126L, and the continuous metal barrier layer 122L by performing an anisotropic etching process. In such embodiments, portions of the continuous metal barrier layer 122L, the continuous bottom electrode material layer 126L, and the continuous non-magnetic metal buffer layer 128L that are not masked by the arrangement of dielectric spacers (162, 164) and the top electrodes 160 may be removed by the etching process. The etching process may be selective for material of the via level dielectric layer 110. The etching process may include an anisotropic etching process (such as a reactive ion etching process) and / or an isotropic etching process (such as a wet etching process).If the top electrodes 160 include a different material than the materials of the continuous metal barrier layer 122L, the continuous bottom electrode material layer 126L, and the continuous non-magnetic metal buffer layer 128L, the etching process may be selective for the material of the top electrodes 160 (i.e., it does not significantly etch the material of the top electrodes 160).

[0041] Each patterned portion of the continuous non-magnetic metal buffer layer 128L represents a non-magnetic metal buffer layer 128. Each patterned portion of the continuous bottom electrode material layer 126L represents a bottom electrode 126. Each patterned portion of the continuous metal barrier layer 122L represents a metal barrier layer 122. Each vertical stack of a non-magnetic metal buffer layer 128, a bottom electrode 126, and a metal barrier layer 122 may have vertically matching sidewalls arranged within a same vertical plane. Each continuous combination of a single vertical stack (130, 140, 146, 148, 158, 160), a non-magnetic metal buffer layer 128 (which is an optional component), and a bottom electrode 126 represents a memory cell 101, which is a magnetoresistive memory cell.Each combination of a metal barrier layer 122 and a metal via fill material portion 124 represents a bottom electrode interconnect via structure (122, 124) that provides electrical connection between a respective bottom electrode 126 and a respective fourth metal line structure 648.

[0042] In general, an array of bottom electrode interconnect via structures (122, 124) may be formed on a respective underlying one of the metal interconnect structures. An array of memory cells 101 may be formed on the array of bottom electrode interconnect via structures (122, 124). The array of memory cells 101 may be formed above the substrate 9 in the memory array region 100. Each of the memory cells 101 may have a vertical stack including a bottom electrode 126, a memory element (such as a magnetic tunnel junction (143, 146, 148)), and a top electrode 160. Each magnetic tunnel junction (143, 146, 148) may include a vertical stack of a reference magnetization layer 143, a non-magnetic tunnel barrier layer 146, and a free magnetization layer 148.In one embodiment, each of the memory cells 101 may include a selector element 130 disposed on a respective magnetic tunnel contact (143, 146, 148). The selector element 130 may be located above or below the respective magnetic tunnel contact (143, 146, 148).

[0043] In an alternative embodiment, the patterning of the continuous non-magnetic metal buffer layer 128L, the continuous bottom electrode material layer 126L, and the continuous metal barrier layer 122L may be performed after forming the array of individual vertical stacks (130, 140, 146, 148, 158, 160) and before forming the array of dielectric spacers (162, 164). In this case, the anisotropic etching process may be performed during the processing steps of Fig. 6 may be continued until the continuous non-magnetic metal buffer layer 128L, the continuous lower electrode material layer 126L, and the continuous metal barrier layer 122L are patterned. In this case, the dielectric spacers (162, 164) may be formed on the sidewalls of the non-magnetic metal buffer layers 128, the lower electrodes 126, and the metal barrier layers 122.

[0044] Referring to Fig. 9, a dielectric etch stop layer 170 and an optional silicon oxide liner layer 172 may be sequentially formed by a respective deposition process. The dielectric etch stop layer 170 comprises a dielectric material that may be used as a planarization stop material during a chemical mechanical planarization process and which may subsequently be used as an etch stop material during an anisotropic etch process. The dielectric etch stop layer 170 includes a non-reactive dielectric hard mask material. For example, the dielectric etch stop layer 170 may include and / or consist essentially of silicon nitride (Si3N4), silicon oxynitride (SiON), silicon carbide (SiC), silicon carbide nitride (SiCN), silicon oxycarbide (SiOC), or a nitrogen-free anti-reflection layer (NFARL) comprising a nitrogen-free inorganic polymer material.Other suitable materials may also be used. The dielectric etch stop layer 170 may be deposited by plasma-enhanced chemical vapor deposition (PECVD), high-density plasma chemical vapor deposition (HDP-CVD), or atmospheric pressure chemical vapor deposition (APCVD). The dielectric etch stop layer 170 may be deposited conformally or non-conformally.

[0045] The dielectric etch stop layer 170 may be formed over and on the array of dielectric spacers (162, 164) and over the array of memory cells 101. The dielectric etch stop layer 170 includes a horizontally extending portion extending continuously through the memory array region 100 and into the logic region 200, and an array of vertically projecting portions laterally surrounding each of the memory cells 101 in the array of memory cells 101. The thickness of a horizontally extending portion of the dielectric etch stop layer 170 in the logic region 200 or over the upper surfaces of the top electrodes 160 may range from 5 nm to 50 nm, although lower and higher densities may be used.

[0046] The optional silicon oxide liner layer 172, if present, may include a non-porous silicon oxide material, such as a TEOS oxide material formed by plasma-enhanced chemical vapor deposition (PECVD). The silicon oxide liner layer 172 may include undoped silicate glass or a doped silicate glass. The silicon oxide liner layer 172 may be formed by a conformal or non-conformal deposition process. The thickness of the horizontally extending portions of the silicon oxide liner layer 172 in the logic region 200 or over the top surfaces of the top electrodes 160 may range from 5 nm to 50 nm, although lower and higher densities may also be used.

[0047] Referring to Fig. 10, a first dielectric matrix layer 176 may be formed over the silicon oxide liner layer 172 and the etch stop dielectric layer 170. The first dielectric matrix layer 176 may be formed by a chemical vapor deposition process. In one embodiment, the first dielectric matrix layer 176 comprises a low-k dielectric material having a dielectric constant less than the dielectric constant of thermal silicon oxide (i.e., 3.9). In one embodiment, the dielectric matrix layer 176 includes an ultra-low-k (ELK) dielectric material having a dielectric constant of less than 2.5. In one embodiment, the first dielectric matrix layer 176 includes a porous silicon oxide-based dielectric material having a dielectric constant of less than 2.5.In this case, the porous silicon oxide-based dielectric material may include a porogen-doped SiCO-based material having a porous structure. The porous structure may be formed by introducing a pore-forming material (a porogen) into a carbon-doped oxide using a chemical vapor deposition process. The chemical vapor deposition process may include a plasma-enhanced chemical vapor deposition (PECVD) process or a thermal chemical vapor deposition process. The refractive index of the ELK dielectric material in the first dielectric matrix layer 176 may be in a range of 1.0 to 1.4 at the wavelength of 632.8 nm (which is the wavelength of commercially available HeNe laser measurement instruments).

[0048] A first portion of an upper surface of the first dielectric matrix layer 176, which is arranged in the memory array region 100, may have a greater vertical separation distance from the substrate 9 than a second portion of the upper surface of the first dielectric matrix layer 176, which is formed in the logic region 200. In other words, the upper surface of the first dielectric matrix layer 176 may be higher in the memory array region 100 than in the logic region 200. The first portion of the upper surface of the first dielectric matrix layer 176 may comprise the uppermost portion of the upper surface of the first dielectric matrix layer 176.The height difference between the first portion of an upper surface of the first dielectric matrix layer 176, which is arranged in the memory array region 100, and the second portion of the upper surface of the first dielectric matrix layer 176, which is arranged in the logic region 200, exists due to the presence of the array of memory cells 101 and the array of dielectric spacers (162, 164) in the memory array region 100.

[0049] The contour of the upper surface of the first dielectric matrix layer 176 initially follows the contour of the physically exposed areas of the array of memory cells 101 and the array of dielectric spacers (162, 164) in the memory array region 100 during the deposition of the first dielectric matrix layer 176. As material portions of the first dielectric matrix layer 176 are joined midway between each adjacent pair of dielectric spacers (162, 164), the contour of the upper surface of the first dielectric matrix layer 176 gradually flattens and increases with the progressive accumulation of dielectric material until the completion of the deposition process for the first dielectric matrix layer 176.In one embodiment, the duration of the deposition process that deposits the first dielectric matrix layer 176 may be selected such that the upper surface of the portion of the first dielectric matrix layer 176 in the logic region 200 is disposed within the same horizontal plane as the upper surfaces of the upper electrodes 160. In other words, the duration of the deposition process that deposits the first dielectric matrix layer 176 may be selected such that the thickness of the first dielectric matrix layer 176 in the logic region 200 is equal to the distance obtained by adding the height of a memory cell 101 and the thickness of a metal barrier layer 122, then subtracting the thickness of the silicon oxide liner layer 172 in the logic region 200, and then subtracting the thickness of the dielectric etch stop layer 170 in the logic region 200.

[0050] The height difference between the first portion of a top surface of the first dielectric matrix layer 176 disposed in the memory array region 100 and the second portion of the top surface of the first dielectric matrix layer 176 formed in the logic region 200 may be in a range of 40% to 100%, for example, 70% to 90%, of the vertical distance between the horizontal plane including the top surface of the via level dielectric layer 110 and the horizontal plane including the top surfaces of the top electrodes 160. In one embodiment, the first dielectric matrix layer 176 may have a vertical undulation of height in the memory array region 100.In one embodiment, the height difference between the first portion of a top surface of the first dielectric matrix layer 176 disposed in the memory array region 100 and the second portion of the top surface of the first dielectric matrix layer 176 formed in the logic region 200 may be in a range of 40 nm to 400 nm, for example, 80 nm to 200 nm, although smaller and larger height differences may also be used.

[0051] A planarization stop sacrificial material layer 180 may be formed over the first dielectric matrix layer 176. The planarization stop sacrificial material layer 180 includes a non-reactive dielectric hard mask material. For example, the planarization stop sacrificial material layer 180 may include and / or consist essentially of silicon nitride (Si3N4), silicon oxynitride (SiON), silicon carbide (SiC), silicon carbide nitride (SiCN), silicon oxycarbide (SiOC), or a nitrogen-free anti-reflective layer (NFARL) comprising a nitrogen-free inorganic polymer material. The planarization stop sacrificial material layer 180 may be deposited by plasma-enhanced chemical vapor deposition (PECVD), high-density plasma chemical vapor deposition (HDP-CVD), or atmospheric pressure chemical vapor deposition (APCVD). The planarization stop sacrificial material layer 180 may be deposited conformally or non-conformally.The thickness of the planarization stop sacrificial material layer 180 in the logic region 200 may range from 5 nm to 50 nm, although thinner and thicker thicknesses may also be used. In one embodiment, the planarization stop sacrificial material layer 180 may have the same material composition and thickness as the dielectric etch stop layer 170.

[0052] Referring to Fig. 11, the first dielectric matrix layer 176 may be planarized by performing a chemical-mechanical planarization process. Portions of the first dielectric matrix layer 176 that lie above the horizontal plane comprising the top surface of the planarization stop sacrificial material layer 180 in the logic region 200 may be removed from the memory array region 100 by the chemical-mechanical planarization process. The top surface of the portion of the first dielectric matrix layer 176 in the logic region 200 may be coplanar with the top surfaces of the top electrodes 160, and the thickness of the planarization stop sacrificial material layer 180 in the logic region 200 may be the same as the thickness of the horizontal portions of the etch stop dielectric layer 170 that lie above the top electrodes 160.In such embodiments, the upper surface of the planarization stop sacrificial material layer 180 in the logic region 200 may be arranged in the same, or approximately the same, horizontal plane as the horizontal plane comprising the upper surfaces of the portions of the dielectric etch stop layer 170 that overlie the upper electrodes 160. The planarization stop sacrificial material layer 180 in the logic region 200 and the portions of the dielectric etch stop layer 170 that overlie the upper electrodes 160 may be used together as planarization stop structures during the chemical-mechanical planarization process.In other words, the chemical-mechanical planarization process may use upper portions of the dielectric etch stop layer 170 overlying the array of memory cells 101 as planarization stop structures, and may use a portion of the planarization stop sacrificial material layer 180 in the logic region 200 as an additional planarization stop structure. Thus, the upper surface of the remaining portion of the first dielectric matrix layer 176 may be disposed within the same horizontal plane as the upper surface of the planarization stop sacrificial material layer 180 in the logic region 200 and the upper surfaces of the portions of the dielectric etch stop layer 170 overlying the top electrodes 160.

[0053] Referring to Fig. 12, a corrective planarization process may be performed to remove portions of the dielectric etch stop layer 170 overlying the top electrodes 160 in the memory array region 100 and to remove remaining portions of the planarization stop sacrificial material layer 180 in the logic region 200. The corrective planarization process may use a dry etch process, which may include an anisotropic dry etch process (such as a reactive dry etch process) or an isotropic dry etch process (such as a chemical dry etch process). In this case, the etch chemistry of the dry etch process may be selected to remove the materials of the dielectric etch stop layer 170 and the planarization stop sacrificial material layer 180 selectively for the material of the first dielectric matrix layer 176 or at the same etch rate as for the material of the first dielectric matrix layer 176.Alternatively, the corrective planarization process may use a chemical-mechanical corrective planarization process. In this case, the chemical-mechanical planarization process, which removes portions of the first dielectric matrix layer 176 in the memory array region 100, may continue until the portions of the dielectric etch stop layer 170 overlying the top electrodes 160 in the memory array region 100 and the remaining portions of the planarization stop sacrificial material layer 180 in the logic array 200 have been removed.

[0054] Thus, portions of the dielectric etch stop layer 170 overlying the array of memory cells 101 (each comprising a vertical stack of a bottom electrode 126, a memory element, and a top electrode 160) may be removed concurrently with the removal of the portion of the planarization stop sacrificial material layer 180 disposed in the logic region 200. Optionally, portions of the first dielectric matrix layer 176 overlying the horizontal plane including the top surfaces of the top electrodes 160 may be additionally removed during the corrective planarization process. Generally, top surfaces of the top electrodes 160 may be physically exposed during, or after, the chemical-mechanical planarization process that planarizes the first dielectric matrix layer 176.

[0055] Referring to Fig. 13, a second dielectric matrix layer 178 may be applied over, and directly on, the physically exposed horizontal surface of the remaining portion of the first dielectric matrix layer 176. The second dielectric matrix layer 178 may have the same material composition as the material composition of the first dielectric matrix layer 176, or may have a different material composition. In one embodiment, the second dielectric matrix layer 178 may comprise a low dielectric constant (low-k) dielectric material, such as an ELK dielectric material having a dielectric constant of less than 2.5. In one embodiment, the second dielectric matrix layer 178 includes a porous silicon oxide-based dielectric material having a dielectric constant of less than 2.5.The thickness of the second dielectric matrix layer 178 may be equal to the desired height of metal cell contact structures to be formed on the upper surfaces of the upper electrodes 160. For example, the second dielectric matrix layer 178 may have a thickness in a range of 20 nm to 160 nm, for example, 40 nm to 80 nm, although thinner and thicker thicknesses may also be used. In one embodiment, the entire upper surface of the second dielectric matrix layer 178 may be disposed within a first horizontal plane, and the entire lower surface of the second dielectric matrix layer 178 may be disposed within a second horizontal plane. Thus, the entirety of the second dielectric matrix layer 178 may have a uniform thickness throughout.

[0056] Referring to Fig. 14, a first photoresist layer (not shown) may be deposited over the second dielectric matrix layer 178 and lithographically patterned to form an array of openings in the logic region 200. The pattern of the openings in the photoresist layer may be transferred through the second dielectric matrix layer 178, the first dielectric matrix layer 176, the silicon oxide liner layer 172, and the dielectric etch stop layer 170. In one embodiment, the dielectric etch stop layer 170 may be used as an etch stop layer for a first etch step that etches the materials of the second dielectric matrix layer 178, the first dielectric matrix layer 176, and the silicon oxide liner layer 172, and an etch chemistry that etches the material of the dielectric etch stop layer 170 may be used during a second etch step of the anisotropic etch process.Via cavities 181 are formed beneath each of the openings in the photoresist layer. A top surface of the dielectric via level layer 110 may be physically exposed at the bottom of each via cavity 181. The first photoresist layer may subsequently be removed, for example, by ashing.

[0057] Referring to Fig. 15, a second photoresist layer may be applied over the second dielectric matrix layer 178 and may be lithographically patterned to form conductive structures. The conductive structure portions in the photoresist layer may include all portions of the via cavities 181. Thus, during development of the second photoresist layer, the second photoresist layer may be removed from the inside of the via cavities 181. An anisotropic etch process may be performed to transfer the conductive structures in the second photoresist layer into underlying material portions. Each of the via cavities 181 extends vertically through the via level dielectric layer 110 and through the dielectric cap layer 108, such that a top surface of a respective one of the fourth metal conductive structures 648 may be physically exposed beneath each of the via cavities 181.Furthermore, portions of the second dielectric matrix layer 178 that are not masked by the patterned second photoresist layer may be etched through to form conductive cavities. Integrated conductive and via cavities 183 are formed in the logic region 200. Each of the integrated conductive and via cavities 183 may include a respective conductive cavity and at least one via cavity adjacent to a bottom surface of the respective conductive cavity. Cell contact cavities 187, each overlying one of the top electrodes 160, are formed in the memory array region 100.

[0058] According to one aspect of the present disclosure, the anisotropic etch process that forms the cell contact cavities 187 and the integrated line and via cavities 183 may be selective for the material of the dielectric etch stop layer 170. The cell contact cavities 187 may be formed through the second dielectric matrix layer 178 by performing the anisotropic etch process that etches the material of the second dielectric matrix layer 178 and is selective for the material of the dielectric etch stop layer 170. In one embodiment, the lateral extent of a cell contact cavity 187 selected from the array of cell contact cavities 187 (referred to herein as the first cell contact cavity) may be larger than the lateral extent of a respective underlying upper electrode 160, i.e., larger than the lateral extent of the upper electrode underlying the first cell contact cavity.In one embodiment, a plurality of cell contact cavities 187 may each have a lateral extent that is greater than the lateral extent of a respective underlying upper electrode 160. In one embodiment, each of the cell contact cavities 187 may have a corresponding lateral extent that is greater than the lateral extent of a respective underlying upper electrode 160.In this case, each of the cell contact cavities 187 (such as the first cell contact cavity) having a greater lateral extent than the lateral extent of a respective underlying upper electrode 160 may extend into an upper portion of the first dielectric matrix layer 176, and thus may have a downwardly projecting portion extending below the horizontal plane comprising the upper surfaces of the upper electrode 160 and overlying a tapered portion of the dielectric etch stop layer 170.

[0059] In one embodiment, the top surfaces of the line trenches within the integrated line and via cavities 183 may be formed below the horizontal interface between the first dielectric matrix layer 176 and the second dielectric matrix layer 178. Vertically projecting portions of the dielectric etch stop layer 170, which laterally surround the memory cells 101, serve as etch stop material portions, while the bottom surfaces of the line trenches are recessed vertically below the horizontal interface between the first dielectric matrix layer 176 and the second dielectric matrix layer 178. Thus, the cell contact cavities 187 do not extend through the dielectric etch stop layer 170 and do not contact any of the underlying dielectric spacers (162, 164).Consequently, sidewalls of the various layers within each memory cell 101 remain covered by a respective one of the dielectric spacers (162, 164).

[0060] Referring to Fig. 16, at least one conductive material may be deposited in the line and via cavities 183 and in the cell contact cavities 187. The at least one conductive material may include, for example, a metal liner material, such as TiN, TaN, or WN, and a metal filler material, such as W, Cu, Co, Ru, Mo, Al, alloys thereof, and / or a layer stack thereof. Other suitable materials may also be used. Excess portions of the at least one conductive material that lie above the horizontal plane comprising the top surface of the second dielectric matrix layer 178 may be removed by a planarization process, such as a chemical mechanical polishing process.Each remaining portion of the at least one conductive material filling an integrated line and via cavity 183 represents an integrated line and via structure 184. Each remaining portion of the at least one conductive material filling a cell contact cavity 187 represents a metal cell contact structure 188. The integrated line and via structure 184, the metal cell contact structure 188, and the bottom electrode connection via structure (122, 124) together represent memory cell level metal interconnect structures (122, 124, 184, 188), i.e.Metal interconnect structures arranged in the memory cell plane, which comprises the volume between the horizontal plane comprising the upper surfaces of the fourth metal line structures 648 and the horizontal plane comprising the upper surfaces of the integrated line and via structure 184 and the metal cell contact structure 188.

[0061] Referring to Fig. 17, additional dielectric material layers and additional metal interconnect structures may subsequently be formed as needed. The combination of the dielectric cap layer 108, the via level dielectric layer 110, the etch stop dielectric layer 170, the silicon oxide liner layer 172, the first dielectric matrix layer 176, and the second dielectric matrix layer 178 collectively serves as a fifth line-and-via level dielectric material layer. A sixth line-and-via level dielectric material layer 660 may be formed over the second dielectric matrix layer 178.Fifth metal via structures 662 may be formed in a lower portion of the sixth dielectric line and via level material layer 660, and sixth metal line structures 668 may be formed in an upper portion of the sixth dielectric line and via level material layer 640. Contact pads (not shown) may be formed over the additional metal interconnect structures.

[0062] Referring to Fig.18, a general method of forming a memory device is provided according to an embodiment of the present disclosure. Referring to step 1810, an array of memory cells 101 may be formed over a substrate 9 in a memory array region 100. Each of the memory cells 101 has a vertical stack including a bottom electrode 126, a memory element (such as a magnetic tunnel contact (143, 146, 148)), and a top electrode 160. Referring to step 1820, a dielectric etch stop layer 170 may be formed over the array of memory cells 101. The dielectric etch stop layer 170 has a horizontally extending portion extending continuously through the memory array region 100 and extending into a logic region 200.Referring to step 1830, a first dielectric matrix layer 176 may be formed over the dielectric etch stop layer 170. A first portion of an upper surface of the first dielectric matrix layer 176 in the memory array region 100 has a greater vertical separation distance from the substrate 9 than a second portion of the upper surface of the first dielectric matrix layer 176 formed in the logic region 200. Referring to step 1840, the first dielectric matrix layer 176 may be planarized by performing a chemical mechanical planarization process by using upper portions of the dielectric etch stop layer 170 overlying the array of memory cells 101 as planarization stop structures. Referring to step 1850, a second dielectric matrix layer 178 may be formed over the first dielectric matrix layer 176.Referring to step 1860, metal cell contact structures 188 may be formed through the second dielectric matrix layer 178 on a respective subset of the top electrodes 160 over vertically projecting portions of the dielectric etch stop layer 170 laterally surrounding the array of memory cells 101.

[0063] Referring to all the drawings and according to the various embodiments of the present disclosure, a memory device is provided using a dielectric etch stop layer 170. The dielectric etch stop layer 170 has a horizontally extending portion extending continuously through the memory array region 100 and the logic region 200, and further includes an array of vertically protruding portions laterally surrounding each of the memory cells 101 in the array of memory cells 101. Each of the vertically protruding portions has a corresponding opening in an uppermost region and a corresponding uppermost annular surface disposed within a horizontal plane including upper surfaces of the top electrodes 160.

[0064] The first dielectric matrix layer 176 overlies the horizontally extending portion of the dielectric etch stop layer 170 and laterally surrounds the array of laterally extending portions of the dielectric etch stop layer 170. The second dielectric matrix layer 178 overlies the first dielectric matrix layer 176. The second dielectric matrix layer 178 may have a bottom surface disposed within the horizontal plane including the top surfaces of the top electrodes 160. Furthermore, the second dielectric matrix layer 178 may have a top surface disposed within a horizontal plane including the top surfaces of the metal cell contact structures 188.

[0065] In one embodiment, each of the annular uppermost surfaces of the vertically protruding portions of the dielectric etch stop layer 170 may have an inner perimeter that coincides with a perimeter of one of the upper surfaces of the upper electrodes 160. In one embodiment, an outer perimeter of each of the annular uppermost surfaces of the vertically protruding portions of the dielectric etch stop layer 170 may be laterally offset from the inner perimeter by a uniform lateral offset distance. Due to the tapering of the vertically protruding portions of the dielectric etch stop layer 170 above the dielectric spacers (162, 164), the uniform lateral offset distance may be greater than the thickness of the vertically protruding portions of the dielectric etch stop layer 170.In one embodiment, the outer peripheries and the inner peripheries of the annular uppermost surfaces of the vertically protruding portions of the dielectric etch stop layer 170 may be disposed within the horizontal plane including the upper surfaces of the upper electrodes 160.

[0066] The metal cell contact structures 188 extend through the second dielectric matrix layer 178 and are formed on a respective subset of the top electrodes 160. In one embodiment, each of the metal cell contact structures 188 may contact a row of top electrodes 160 or a column of top electrodes 160 within a two-dimensional array of memory cells 101. Alternatively, each of the metal cell contact structures 188 may contact a respective single top electrode 160 within a two-dimensional array of memory cells 101. In this case, metal interconnect structures subsequently formed over the metal cell contact structures 188 may be used to electrically connect a row of metal cell contact structures 188 or a column of metal cell contact structures 188.

[0067] The metal cell contact structures 188 are formed over the vertically protruding portions of the dielectric etch stop layer 170 that laterally surround the array of memory cells 101. The metal cell contact structures 188 may contact a respective subset of the vertically protruding portions of the dielectric etch stop layer 170. At least one metal cell contact structure 188 (such as a first metal cell contact structure formed in the first cell contact cavity) may include a downwardly protruding portion that contacts a tapered portion of the dielectric etch stop layer 170, i.e., a tapered convex segment of an outer sidewall of a laterally protruding portion of the dielectric etch stop layer 170.

[0068] In one embodiment, at least one of the metal cell contact structures 188 may have a planar lower surface contacting a planar upper surface of a corresponding one of the upper electrodes 160 and a tapered, downwardly projecting portion extending downwardly below the horizontal plane encompassing the upper surfaces of the upper electrodes 160 and contacting a tapered outer sidewall of a corresponding one of the vertically projecting portions of the dielectric etch stop layer 170.

[0069] Each of the integrated line and via structures 188 may include a line portion and at least one via portion. Each line portion may include a planar top surface disposed within a horizontal plane including top surfaces of the metal cell contact structures 188 and a planar bottom surface disposed below a horizontal plane including top surfaces of the top electrodes 160. Each via portion may extend through the horizontally extending portion of the dielectric etch stop layer 170 and contact a top surface of a corresponding one of the fourth metal line structures 648.

[0070] In one embodiment, metal interconnect structures (612, 618, 622, 628, 632, 638, 642, 648) formed in dielectric material layers (601, 610, 620, 630, 640) may be disposed between the dielectric etch stop layer 170 and the substrate 9. In one embodiment, memory cell-level metal interconnect structures (such as the integrated line and via structures 188) may be disposed in the logic area 200. Such memory cell-level metal interconnect structures may extend through the horizontally extending portion of the dielectric etch stop layer 170 and may have upper surfaces within a horizontal plane that includes upper surfaces of the metal cell contact structures 184.In one embodiment, at least one of the memory cell level metal interconnect structures may include an integrated line and via structure 184 having a line portion having a planar bottom surface disposed below the horizontal plane including the top surfaces of the top electrodes 160 and a via portion extending through the horizontally extending portion of the dielectric etch stop layer 170.

[0071] In one embodiment, an array of bottom electrode connection via structures (122, 124) may be provided, which may contact a corresponding one of the bottom electrodes 126 of the array of memory cells 101 and a corresponding one of the metal interconnect structures (such as a fourth metal line structure 648) formed in the dielectric material layers.

[0072] In one embodiment, each of the lower electrodes 126 may have a corresponding sidewall contacting the dielectric etch stop layer 170, and an array of dielectric spacers (162, 164) may laterally surround and contact a respective memory cell 101 in the array of memory cells 101. Each of the dielectric spacers (162, 164) in the array of dielectric spacers (162, 164) may be laterally surrounded by and contacted by a respective sidewall of the dielectric etch stop layer 170.

[0073] In one embodiment, each of the memory cells 101 may include a vertical stack including a bottom electrode 126, a memory element (such as a magnetic tunnel junction (143, 146, 148)), and a top electrode 160. In one embodiment, each of the magnetic tunnel junctions includes a vertical stack of a reference magnetization layer 143, a non-magnetic tunnel barrier layer 146, and a free magnetization layer 148. In one embodiment, each of the memory cells 101 may include a selector element 130 disposed at a respective magnetic tunnel junction (143, 146, 148).

[0074] By providing a dielectric etch stop layer 170, the thickness of a first dielectric matrix layer 176 can be more precisely controlled after a chemical-mechanical planarization process. Subsequent deposition of a second dielectric matrix layer 178 overlying the first dielectric matrix layer 176 can then form a more uniform layer having a desired thickness. Thus, the thickness range of the dielectric matrix layer has been improved. By ensuring that the chemical-mechanical planarization process removes a precise amount of the first dielectric matrix layer 176, subsequent etch processes can prevent defects due to over-etching or under-etching. Thus, undesirable problems due to short circuits and open circuits can be prevented.As a result, devices formed using the various process embodiments can reduce the failure rate due to electrical shorts and open circuits that devices are subject to using conventional processes. Furthermore, the metal trench landing window can be increased.

[0075] According to one aspect of the present disclosure, horizontal portions of the dielectric etch stop layer 170 overlying the memory cells 101 extend the planarization stop sacrificial material layer 180 as planarization stop structures in the memory array region 100 during the planarization of the first dielectric matrix layer 176. Thus, both the memory array region 100 and the logic region 200 have planarization stop structures with sufficiently high area coverage, and crowning of the first dielectric matrix layer 176 in the memory array region 100 can be prevented. Thus, erosion of the top electrodes 160 can be avoided or minimized by using the dielectric etch stop layer 170.The removal of the horizontal portions of the dielectric etch stop layer 170 may be performed selectively for the top electrodes 160 using a controlled removal process, allowing physical exposure of the top surfaces of the top electrodes 160 and the deposition of the second dielectric matrix layer 178 directly on the top surfaces of the top electrodes 160.

[0076] Furthermore, the remaining portions of the dielectric etch stop layer 170 may have annular horizontal surfaces having inner perimeters that coincide with perimeters of the top electrodes 160. Thus, after the top surfaces of the top electrodes 160 have been physically exposed following the corrective planarization process, the underlying dielectric spacers (162, 164) may be covered by the dielectric etch stop layer 170 without any gap between the top electrodes 160 and the remaining portions of the dielectric etch stop layer 170. The dielectric etch stop layer 170 may subsequently be used as an etch stop structure during the formation of the cell contact cavities. Thus, the cell contact cavities 187 and the metal cell contact structures 188 do not extend through the dielectric spacers (162, 164) and therefore do not contact the sidewalls of the memory cells 101.In other words, the dielectric etch stop layer 170 ensures that the metal cell contact structures 188 of all structural components of the memory cells 101 only contact upper surfaces of the upper electrodes 160.

[0077] Therefore, the dielectric etch stop layer 170 provides the dual function of a planarization stop structure during a chemical-mechanical planarization process and an etch stop structure during a subsequent anisotropic etch process that forms the cell contact cavities 187. The dielectric etch stop layer 170 provides the benefit of a self-aligned contact configuration between each vertically adjacent pair of a top electrode 160 and a metal cell contact structure 188. The contact area between each underlying top electrode 160 and an overlying metal cell contact structure 188 may be the same as the surface area of ​​the upper surface of the underlying top electrode 160 for each of the memory cells 101.Furthermore, the dielectric etch stop layer 170 ensures that none of the downwardly projecting portions of the metal cell contact structures 188 extend into the dielectric spacers (162, 164) and contact any of the sidewalls of the vertical layer stack comprising the magnetic tunnel contact (140, 146, 148). The self-aligned contact configuration between the top electrodes 160 and the metal cell contact structures 188 enables the scaling of lateral dimensions of the top electrodes 160 even below a critical dimension, i.e., a minimum dimension that can be printed using a single lithographic exposure and development process.

[0078] The dielectric etch stop layer 170 may increase the process window for the chemical mechanical planarization process that planarizes the first dielectric matrix layer 176, thereby improving the thickness uniformity of the first dielectric matrix layer 176. In other words, the thickness range of the combination of the dielectric etch stop layer 170, the silicon oxide liner layer 172, the first dielectric matrix layer 176, and the second dielectric matrix layer 178 has smaller thickness variations than would otherwise be possible without the use of the dielectric etch stop layer 170. In one non-limiting illustrative example, the height variation of the top surface of the second dielectric matrix layer 178 in the memory array region 100 may be less than 10 nm.

[0079] Furthermore, the dielectric etch stop layer 170 can increase the process window for forming the cell contact cavities 187, thereby reducing electrical short circuits between the metal cell contact structures 188 and components of the memory cell 101 underlying the top electrode 160 (such as the magnetic tunnel junction (143, 146, 148) and the bottom electrode 126), as well as electrical circuit interruptions between the metal cell contact structures 188 and the top electrodes 160. The improvement in the process window results in part from improving the thickness uniformity of the combination of the first dielectric matrix layer 176 and the second dielectric matrix layer 178, and in part from the presence of the dielectric etch stop layer 170 as an etch stop structure during the formation of the cell contact via cavities 187.

[0080] Portions of the first dielectric matrix layer 176 overlying the upper surfaces of the top electrodes 160 are completely removed from the memory array region 100, and the height of the metal cell contact structures 188 is determined by the thickness of the second dielectric matrix layer 178.

Claims

[1] Storage device comprising: an array of memory cells (101) overlying a substrate (9) and arranged in a memory array region (100), each of the memory cells (101) comprising a vertical stack comprising a lower electrode (126), a memory element and an upper electrode (160); a logic area (200) arranged outside the memory array area (100) and free of memory cells (101); a dielectric etch stop layer (170) comprising: a horizontally extending portion extending continuously through the memory array region (100) and the logic region (200), and an array of vertically projecting portions laterally surrounding each of the memory cells (101) in the array of memory cells (101), each of the vertically projecting portions having an opening in an uppermost region and a corresponding annular uppermost surface, which is arranged within a horizontal plane comprising the upper surfaces of the upper electrodes (160); and Metal cell contact structures (188) contacting a respective subset of the upper electrodes (160) and a respective subset of the vertically projecting portions of the dielectric etch stop layer (170). [2] The storage device of claim 1, further comprising: a first dielectric matrix layer (176) disposed over the horizontally extending portion of the dielectric etch stop layer (170) and laterally surrounding the array of vertically projecting portions of the dielectric etch stop layer (170); and a second dielectric matrix layer (178) disposed over the first dielectric matrix layer (176) and having: a lower surface lying in the horizontal plane containing the upper surfaces of the upper electrodes (160), and an upper surface lying in a horizontal plane containing upper surfaces of the metal cell contact structures (188). [3] The memory device according to claim 1 or 2, wherein each of the annular uppermost surfaces of the vertically projecting portions of the dielectric etching stop layer (170) has an inner periphery that coincides with a periphery of one of the upper surfaces of the upper electrodes (160). [4] A storage device according to claim 3, wherein: an outer periphery of each of the annular uppermost surfaces of the vertically projecting portions of the dielectric etch stop layer (170) is laterally offset from the inner periphery by a uniform lateral offset distance; and the outer peripheries and the inner peripheries of the annular uppermost surfaces of the vertically projecting portions of the dielectric etch stop layer (170) lie in the horizontal plane in which the upper surfaces of the upper electrodes (160) are contained. [5] A memory device according to any preceding claim, further comprising metal interconnect structures (612, 618, 622, 628, 632, 638, 642, 648) formed in dielectric material layers (601, 610, 620, 630, 640) and disposed between the dielectric etch stop layer (170) and the substrate (9). [6] The memory device of claim 5, further comprising memory cell level metal interconnect structures (184) disposed in the logic region (200) that extend through the horizontally extending portion of the dielectric etch stop layer (170) and have upper surfaces within a horizontal plane in which upper surfaces of the metal cell contact structures (188) are included. [7] The memory device of claim 6, wherein at least one of the memory cell level metal interconnect structures (184) comprises an integrated line and via structure having a line portion having a planar bottom surface underlying the horizontal plane in which the top surfaces of the top electrodes (160) are contained, and a via portion extending through the horizontally extending portion of the dielectric etch stop layer (170). [8] The memory device of claim 5, further comprising an array of bottom electrode interconnect via structures (124) each contacting one of the bottom electrodes (126) of the array of memory cells (101) and each contacting one of the metal interconnect structures (648) formed in the dielectric material layers (640). [9] A storage device according to any one of the preceding claims, wherein: each of the lower electrodes (126) has a respective sidewall in contact with the dielectric etch stop layer (170); and the memory device further comprises an array of dielectric spacers (164) each laterally surrounding and contacting a memory cell in the array of memory cells (101), wherein each of the dielectric spacers (164) in the array of dielectric spacers (164) is laterally surrounded and contacted by a respective sidewall of the dielectric etch stop layer (170). [10] A memory device according to any preceding claim, wherein at least one of the metal cell contact structures (188) comprises: a planar lower surface contacting a planar upper surface of each of the upper electrodes (160), and a tapered, downwardly projecting portion extending downwardly below the horizontal plane in which the upper surfaces of the upper electrodes (160) are contained, and a tapered outer sidewall contacting each of the vertically projecting portions of the dielectric etch stop layer (170). [11] Magnetic tunnel junction memory device, MTJ memory device, comprising: an array of memory cells (101) overlying a substrate (9) and arranged in a memory array region (100), each of the memory cells (101) having a vertical stack comprising a lower electrode (126), a memory element comprising a magnetic tunnel contact, and an upper electrode (160); a logic area (200) arranged outside the memory array area (100) and free of memory cells (101); a dielectric etch stop layer (170) laterally surrounding each of the memory cells (101) in the array of memory cells (101) and extending into the logic region (200), wherein vertically projecting portions of the dielectric etch stop layer (170) each have an annular uppermost surface having an inner periphery and an outer periphery lying in a horizontal plane in which upper surfaces of the upper electrodes (160) are included; and Metal cell contact structures (188) contacting a respective subset of the upper electrodes (160) and a respective subset of the vertically projecting portions of the dielectric etch stop layer (170). [12] The MTJ memory device of claim 11, further comprising: a first dielectric matrix layer (176) overlying the horizontally extending portion of the dielectric etch stop layer (170) and laterally surrounding the array of vertically projecting portions of the dielectric etch stop layer (170); and a second dielectric matrix layer (178) overlying the first dielectric matrix layer (176) and having a lower surface lying in the horizontal plane containing the upper surfaces of the upper electrodes (160) and an upper surface lying in a horizontal plane containing upper surfaces of the metal cell contact structures (188). [13] The MTJ memory device of claim 11 or 12, wherein at least one of the metal cell contact structures (188) comprises: a planar bottom surface contacting a planar top surface of each of the top electrodes (160), and a tapered, downwardly projecting portion extending downwardly below the horizontal plane in which the top surfaces of the top electrodes (160) are contained, and a tapered outer sidewall contacting each of the vertically projecting portions of the dielectric etch stop layer (170). [14] MTJ memory device according to one of the preceding claims 11 to 13, wherein: each of the magnetic tunnel contacts comprises a vertical stack of a reference magnetization layer, a non-magnetic tunnel barrier layer and a free magnetization layer; and each of the memory cells (101) comprises a selector element (130) arranged on a respective magnetic tunnel contact. [15] A method of forming a memory device comprising: Forming an array of memory cells (101) over a substrate (9) in a memory array region (100), each of the memory cells (101) having a vertical stack comprising a lower electrode (126), a memory element, and an upper electrode (160); Forming a dielectric etch stop layer (170) over the array of memory cells (101), the dielectric etch stop layer (170) comprising a horizontally extending portion extending continuously through the memory array region (100) and extending into a logic region (200); Forming a first dielectric matrix layer (176) over the dielectric etch stop layer (170), wherein a first portion of an upper surface of the first dielectric matrix layer (176) formed in the memory array region (100) has a greater vertical separation distance from the substrate (9) than a second portion of the upper surface of the first dielectric matrix layer (176) formed in the logic region (200); Planarizing the first dielectric matrix layer (176) by performing a chemical-mechanical planarization process using upper portions of the dielectric etch stop layer (170) overlying the array of memory cells (101) as planarization stop structures; Forming a second dielectric matrix layer (178) over the first dielectric matrix layer (176); and Forming metal cell contact structures (188) through the second dielectric matrix layer (178) on a respective subset of the upper electrodes (160) over vertically projecting portions of the dielectric etch stop layer (170) laterally surrounding the array of memory cells (101). [16] The method of claim 15, further comprising: physically exposing upper surfaces of the upper electrodes (160) during the chemical-mechanical planarization process or after the chemical-mechanical planarization process and before formation of the second dielectric matrix layer (178); and forming cell contact cavities (187) through the second dielectric matrix layer (178) by performing an anisotropic etch process that etches a material of the second dielectric matrix layer (178) and is selective for the material of the dielectric etch stop layer (170), wherein the metal cell contact structures (188) are formed in the cell contact cavities (187). [17] The method of claim 16, wherein: a lateral extent of a first cell contact cavity selected from among the cell contact cavities (187) is greater than a lateral extent of one of the upper electrodes (160) located below the first cell contact cavity; the first cell contact cavity has a downwardly projecting portion extending below a horizontal plane containing the upper surfaces of the upper electrodes (160) and disposed above a tapered portion of the dielectric etch stop layer (170); and a first metal cell contact structure (188) formed in the first cell contact cavity includes a downwardly projecting portion contacting the tapered portion of the dielectric etch stop layer (170). [18] A method according to any one of claims 15 to 17, further comprising: Forming a planarization stop sacrificial material layer (180) over the first dielectric matrix layer (176), wherein the chemical-mechanical planarization process uses a portion of the planarization stop sacrificial material layer (180) in the logic region (200) as an additional planarization stop structure; and Removing portions of the dielectric etch stop layer (170) overlying the array of memory cells (101) and simultaneously removing the portion of the planarization stop sacrificial material layer (180) in the logic region (200), wherein the second dielectric matrix layer (178) is formed on an upper surface of a remaining portion of the first dielectric matrix layer (176). [19] A method according to any one of claims 15 to 18, further comprising: Forming metal interconnect structures (612, 618, 622, 628, 632, 638, 642, 648) in dielectric material layers (601, 610, 620, 630, 640) above the substrate (9); Forming an array of lower electrode interconnect via structures (124) each on one of the metal interconnect structures (648), wherein the array of memory cells (101) is formed on the array of lower electrode interconnect via structures (124); and Forming an array of dielectric spacers (164), wherein each of the dielectric spacers (164) in the array of dielectric spacers (164) laterally surrounds a memory cell (101) in the array of memory cells (101), and wherein the dielectric etch stop layer (170) is formed over and on the array of dielectric spacers (164). [20] The method of any one of the preceding claims 15 to 19, further comprising: forming an integrated line and via structure (184) in the logic region (200), the integrated line and via structure (184) comprising: a line portion having a planar upper surface lying in a horizontal plane containing upper surfaces of the metal cell contact structure (188) and a planar lower surface lying below a horizontal plane containing upper surfaces of the upper electrodes (160), and a via portion extending through the horizontally extending portion of the dielectric etch stop layer (170).

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