Chip package structure with deflection control and method for manufacturing the same

Abstract

Package structure with: a package substrate (102); an interposer substrate (110) disposed over the package substrate (102); a first semiconductor device (124) and a second semiconductor device (128) disposed over the interposer substrate (110), wherein the first semiconductor device (124) and the second semiconductor device (128) are different types of electrical devices; and a protective layer (134) formed over the interposer substrate (110) to enclose the first semiconductor device (124) and the second semiconductor device (128), the second semiconductor device (128) being free from the protective layer (134, 506) and the first semiconductor device (124) not being free from the protective layer (134, 506), the protective layer (134, 506) having a cover portion (134C) covering a top surface (124A) of the first semiconductor device (124) and an opening (134B) exposing a top surface (128A) of the second semiconductor device (128).

Description

background

[0001] The IC (semiconductor integrated circuit) industry has experienced rapid growth. Continuous advances in semiconductor manufacturing processes have led to semiconductor devices with finer features and / or higher levels of integration. Functional density (i.e., the number of interconnected devices per chip area) has generally increased, while feature size (i.e., the smallest component that can be produced using a manufacturing process) has decreased. This process of downsizing generally offers advantages by increasing production output and reducing associated costs.

[0002] A chip package not only protects semiconductor components against environmental contamination but also provides a connection interface for the semiconductor components encapsulated within it. Smaller package structures have been developed for encapsulating semiconductor components, requiring less space or having a lower height.

[0003] Although existing packaging processes have so far been largely suitable for their intended purpose, they are not yet satisfactory in every respect.

[0004] US 2018 / 0 138 101 A1 discloses a method for forming a package structure. US 2013 / 0 241 044 A1 discloses a semiconductor package, a first semiconductor chip on a first substrate, a protective layer directly on the first semiconductor chip, and an encapsulation covering a top surface of the first substrate. Short description of the drawings

[0005] Aspects of the present invention can best be understood from the following detailed description when taken in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various elements are not drawn to scale. Rather, for the sake of clarity of discussion, the dimensions of various elements may be exaggerated or reduced as desired.

[0006] The Fig. 1A to 1E are cross-sectional views of various stages of a method of manufacturing a package structure according to some embodiments.

[0007] The Fig. 2A to 2C are cross-sectional views of various stages of a method of manufacturing a package structure according to some embodiments. Fig. 3 is a cross-sectional view of a package structure according to some embodiments. Fig. 4 is a cross-sectional view of a package structure according to some embodiments. Fig. 5 is a cross-sectional view of a package module according to some embodiments. Detailed description

[0008] The invention is defined by the independent claims. Embodiments of the invention are provided in the dependent claims, the description, and the figures. The following description provides many different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present invention. For example, the fabrication of a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are fabricated in direct contact, and may also include embodiments in which additional elements may be fabricated between the first and second elements such that the first and second elements are not in direct contact.Furthermore, reference numerals and / or letters may be repeated in the various examples throughout the present invention. This repetition is for simplicity and clarity and does not, in itself, dictate any relationship between the various embodiments and / or configurations discussed.

[0009] Furthermore, spatially relative terms such as "beneath," "under," "lower," "above," "upper," and the like may be used herein to conveniently describe the relationship of one element or structure to one or more other elements or structures illustrated in the figures. The spatially relative terms are intended to encompass other orientations of the device in use or operation, in addition to the orientation illustrated in the figures. The device may be oriented differently (rotated 90 degrees or in a different orientation), and the spatially relative descriptors used herein may be interpreted accordingly.

[0010] The term "substantially" as used in the description, such as in the phrase "substantially planar" or "substantially coplanar," etc., will be understood by a person skilled in the art. In some embodiments, the adverb "substantially" may be omitted. Where appropriate, the term "substantially" may also encompass embodiments with "completely," "all," etc. Where appropriate, the term "substantially" may also refer to 90% or more, such as 95% or more, in particular 99% or more, e.g., 100%. Furthermore, terms such as "substantially parallel" or "substantially perpendicular" are to be construed as terms that do not exclude insignificant deviation from the specified arrangement and may, for example, include deviations of up to 10°. The term "substantially" does not exclude "completely," for example, a composition that is "substantially free" of Y may be completely free of Y.

[0011] Terms such as "approximately" in connection with a specific distance or size are to be interpreted as terms that do not exclude insignificant deviations from the specified distance or size and may, for example, include deviations of up to 10%. The term "approximately" in connection with a numerical value x may mean x ± 5% or x ± 10%.

[0012] Some embodiments of the invention are described. Additional steps may be provided before, during, and / or after the steps described in these embodiments. Some of the described steps may be replaced or omitted in other embodiments. Other elements may be used for the semiconductor device structure. Some of the elements described below may be replaced or omitted in other embodiments. While some embodiments are discussed with steps performed in a particular order, these steps may also be performed in a different logical order.

[0013] Embodiments of the invention may relate to 3D packaging or 3D IC devices. Other elements or methods may also be used. For example, test structures may be used to assist in verification testing of the 3D packaging or 3D IC devices. The test structures may include, for example, test pads fabricated in a redistribution layer or on a substrate that enable testing of the 3D packaging or 3D IC devices, the use of probes and / or probe cards, and the like. Verification testing may be performed on intermediate structures as well as final structures. Furthermore, the structures and methods described herein may be used in conjunction with test methodologies that include intermediate verification of proven good die to increase yield and reduce costs.

[0014] The Fig. 1A to 1E are cross-sectional views of various stages of a method for manufacturing a package structure according to some embodiments. As shown in Fig. 1A, in some embodiments, a package substrate 102 is fabricated over a carrier substrate 100. The carrier substrate 100 may be a glass substrate, a semiconductor substrate, or another suitable substrate. The package substrate 102 may be used to establish an electrical connection between semiconductor devices (described later) in the package structure and an external electronic component after the carrier substrate 100 is fabricated in a later step described in Fig. 1E has been removed.

[0015] The package substrate 102 can be used for routing. In some embodiments, the package substrate 102 is a redistribution substrate. In some alternative embodiments, the package substrate 102 is a build-up substrate having a core and build-up layers on opposite sides of the core. In the following discussion of embodiments of the present invention, although a build-up substrate is explained as an example of the package substrate 102, the principles demonstrated according to the exemplary embodiments readily apply to build-up substrates as well. The redistribution substrate 102 includes a plurality of multi-layer insulating layers 104 and a plurality of conductive features 106 enclosed by the insulating layers 104, as shown in Fig. 1A. The conductive features 106 may be conductive lines, conductive vias, and / or conductive pads. In some embodiments, some of the conductive vias are stacked on top of each other. The upper conductive via is substantially aligned with the lower conductive via. In some embodiments, some of the conductive vias are staggered vias. The upper conductive via is offset from the lower conductive via.

[0016] The insulating layers 104 can be made of one or more polymer materials. The polymer materials can be polybenzoxazole (PBO), polyimide (PI), epoxy-based resins, one or more other suitable polymer materials, or a combination thereof. In some embodiments, the polymer material is light-sensitive. Therefore, a photolithographic process can be used to create openings with desired structures in the insulating layers 104.

[0017] In some other embodiments, some or all of the insulating layers 104 are made of or include dielectric materials other than polymer materials. The dielectric materials may be silicon oxide, silicon carbide, silicon nitride, silicon oxynitride, one or more other suitable materials, or a combination thereof.

[0018] The conductive features 106 may include conductive lines that establish electrical connections in horizontal directions and conductive vias that establish electrical connections in vertical directions. The conductive features 106 may be made of copper, aluminum, gold, cobalt, titanium, nickel, silver, graphene, one or more other suitable conductive materials, or a combination thereof. In some embodiments, the conductive features 106 include multiple sublayers. For example, each of the conductive features 106 includes multiple sublayers, such as Ti / Cu, Ti / Ni / Cu, Ti / Cu / Ti, Al / Ti / Ni / Ag, other suitable sublayers, or a combination thereof.

[0019] The fabrication of the redistribution substrate 102 may include multiple deposition or coating processes, multiple patterning processes, and / or multiple planarization processes.

[0020] The deposition or coating processes can be used to produce insulating layers and / or conductive layers. The deposition or coating processes can include spin coating, electroplating, electroless plating, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), one or more other suitable processes, or a combination thereof.

[0021] The patterning processes can be used to pattern the fabricated insulating layers and / or the fabricated conductive layers. The patterning processes can include a photolithographic process, an energy beam drilling process (such as a laser beam drilling process, an ion beam drilling process, or an electron beam drilling process), an etching process, a mechanical drilling process, one or more other suitable processes, or a combination thereof.

[0022] The planarization processes can impart planar top surfaces to the fabricated insulating layers and / or the fabricated conductive layers to facilitate subsequent processing. The planarization processes can include a mechanical grinding process, a chemical mechanical polishing (CMP) process, one or more other suitable processes, or a combination thereof.

[0023] As in Fig. 1A, in some embodiments, the redistribution substrate 102 further includes conductive elements 108 fabricated thereon. Each conductive element 108 may be exposed at or protrude from the uppermost surface of the insulating layers 104 and may be electrically connected to one of the conductive structural elements 106. The conductive elements 108 may be used to hold or contain conductive structural elements, such as conductive pillars and / or conductive spheres.

[0024] The conductive elements 108 may be made of or comprise copper, aluminum, gold, cobalt, titanium, tin, one or more other suitable materials, or a combination thereof. The conductive elements 108 may be formed by electroplating, electroless plating, placement, printing, PVD, CVD, one or more other suitable processes, or a combination thereof.

[0025] As in Fig. 1B, in some embodiments, an interposer substrate 110 is fabricated over the redistribution substrate 102. In some embodiments, the interposer substrate 110 is bonded to the conductive elements 108 through conductive structures 116. The conductive structures 116 may include solder bumps, solder balls, conductive pillars, other suitable conductive elements, or a combination thereof.

[0026] In some embodiments, the interposer substrate 110 includes a plate 112 and conductive features 114. The conductive features 114 may be made of or comprise copper, aluminum, cobalt, nickel, gold, silver, tungsten, one or more other suitable materials, or a combination thereof. The plate 112 may be made of or comprise a polymeric material, a ceramic material, a metallic material, a semiconductor material, one or more other suitable materials, or a combination thereof. For example, the plate 112 includes resin, prepreg, glass, and / or ceramic. In the event that the plate 112 is made of a metallic material or a semiconductor material (such as silicon), dielectric layers may be formed between the plate 112 and the conductive features 114 to prevent shorting.

[0027] In the case where the plate 112 is made of or comprises a polymer material, the plate 112 may further comprise fillers dispersed throughout the polymer material. The polymer material may be made of or comprise an epoxy-based resin, a polyimide-based resin, one or more other suitable polymer materials, or a combination thereof. Examples of the fillers include fibers (such as silica fibers and / or carbonaceous fibers), particles (such as silica particles and / or carbonaceous particles), or a combination thereof.

[0028] In some embodiments, the interposer substrate 110 contains more fillers than the redistribution substrate 102. In some embodiments, the plate 112 has a higher mass fraction of fillers than the insulating layers 104 of the redistribution substrate 102. In some embodiments, the insulating layers 104 of the redistribution substrate 102 are made of or include a polymeric material. In some embodiments, the insulating layers 104 of the redistribution substrate 102 do not contain any fillers. In this case, the redistribution substrate 102 does not contain any fillers.

[0029] In some embodiments, the interposer substrate 110 and the carrier substrate 100 are pressed against each other at an elevated temperature. This bonds the interposer substrate 110 to the redistribution substrate 102 via the conductive structures 116. In some embodiments, the aforementioned bonding process is performed by thermal compression.

[0030] Subsequently, in some embodiments, an underfill element 118 is fabricated to enclose and protect the conductive structures 116, as shown in Fig. 1B. The underfill member 118 may be made of or include an insulating material, such as an underfill material. The underfill material may be an epoxy, a resin, a filler material, a stress reliever (SRA), an adhesion promoter, another suitable material, or a combination thereof. In some embodiments, an underfill material is dispensed in a liquid state into a gap between the interposer substrate 110 and the redistribution substrate 102 to increase the strength of the conductive structures 116 and thus the overall package structure. After dispensing, the underfill material is cured to fabricate the underfill member 118. The underfill member 118 may also provide a heat dissipation path for the package structure. In some other embodiments, the underfill member 118 is not fabricated.

[0031] As in Fig. 1B, in some embodiments, the interposer substrate 110 further includes conductive elements 120 and 122 fabricated thereon. The conductive elements 120 and 122 may each be exposed at or protrude from the uppermost surface of the plate 112 and may be electrically connected to one of the conductive structural elements 114. The conductive elements 120 and the conductive elements 122 may be used to hold or contain conductive structural elements, such as conductive pillars and / or conductive spheres. The materials and fabrication process for the conductive elements 120 and 122 may be similar to those for the Fig. 1A are the same or similar to the conductive elements 108.

[0032] As in Fig. 1C, in some embodiments, semiconductor devices 124 and semiconductor devices 128 are stacked on top of the interposer substrate 110 (for simplicity, only one semiconductor device 124 and only one semiconductor device 128 are shown). In some embodiments, the semiconductor devices 124 and / or the semiconductor devices 128 comprise one or more semiconductor dies or chips, which may be any type of integrated circuit, such as a processor, logic circuit, memory, analog circuit, digital circuit, mixed circuit, or the like. In some embodiments, the semiconductor devices 124 and / or the semiconductor devices 128 comprise one or more active devices, such as transistors, diodes, photodiodes, or other suitable active devices.Alternatively, the semiconductor devices 124 and / or the semiconductor devices 128 include one or more passive components, such as resistors, capacitors, inductors, or other suitable passive components.

[0033] In some embodiments, semiconductor devices 124 and semiconductor devices 128 are different types of electronic devices that provide different functions. For example, semiconductor devices 124 are memory devices, and semiconductor devices 128 are processor devices. However, other combinations of semiconductor devices 124 and semiconductor devices 128 may also be used.

[0034] In some embodiments, the semiconductor devices 124 and the semiconductor devices 128 have different sizes. For example, a height H1 of the semiconductor device 124 in a direction D1 that is substantially perpendicular to a top surface 110A of the interposer substrate 110 is smaller than a height H2 of the semiconductor device 128 in the direction D1, as shown in Fig. 1C is shown.

[0035] In some embodiments, each semiconductor device 124 is bonded to the conductive elements 120 via conductive structures 126, and each semiconductor device 128 is bonded to the conductive elements 122 via conductive structures 130. Therefore, various semiconductor devices 124 and 128 can be interconnected via the interposer substrate 110. This improves the signal transmission speed. The conductive structures 126 and / or the conductive structures 130 can comprise conductive pillars, solder bumps, solder balls, one or more other suitable conductive elements, or a combination thereof. The materials and the manufacturing process for the conductive structures 126 and the conductive structures 130 can be similar to those for the Fig. 1B. In some embodiments, an underfill element 132 is fabricated to enclose and protect the conductive structures 126 and 130. The materials and fabrication method for the underfill element 132 may be similar to those for the conductive structures 126 and 130 shown in Fig. 1B are the same or similar to the underfill element 118 shown.

[0036] In some embodiments not discussed, the conductive elements 120 and / or the conductive elements 122 are omitted, and the semiconductor devices 124 and / or the semiconductor devices 128 are bonded to pad regions (formed by some of the conductive features 114) of the interposer substrate 110 by solder bumps, solder balls, conductive pillars, one or more other suitable conductive elements, or a combination thereof.

[0037] As in Fig. 1D, in some embodiments, a protective layer 134 is formed to enclose and protect the semiconductor devices 124 and 128. In some embodiments, the protective layer 134 is separated from the conductive structures 126 beneath the semiconductor device 124 and the conductive structures 130 beneath the semiconductor device 128 by the underfill element 132. However, embodiments of the invention are not so limited. Numerous variations and / or modifications may be made to embodiments of the invention. In some further embodiments, the underfill element 132 is not formed. In these cases, the protective layer 134 may be in direct contact with the conductive structures 126 beneath the semiconductor device 124 and the conductive structures 130 beneath the semiconductor device 128.

[0038] In some embodiments, the protective layer 134 is made of or includes an insulating material, such as a molding material. The molding material may be a polymeric material, such as an epoxy-based resin, in which fillers are dispersed. In some embodiments, a molding material (such as a liquid molding material) is dispersed on the top surface 110A of the interposer substrate 110 and / or over the semiconductor devices 124 and 128. In some embodiments, a thermal process is then used to cure the liquid molding material and convert it into the protective layer 134.

[0039] In some embodiments, a planarization process is performed on the protective layer 134 to partially remove the protective layer 134. This exposes a top surface 128A of each semiconductor device 128, while leaving a top surface 124A of each semiconductor device 124 unexposed, as shown in Fig. 1D. In some embodiments, after the planarization process, the top surface 128A of each semiconductor device 128 is substantially flush with a top surface 134A of the protective layer 134, and the top surface 124A of each semiconductor device 124 is spaced a distance G from the top surface 134A of the protective layer 134. A grinding process, a CMP process, an etching process, a dry polishing process, one or more other suitable processes, or a combination thereof may be used for the planarization process.

[0040] Subsequently, in some embodiments, the carrier substrate 100 is removed to expose a surface of the package substrate 102, as shown in Fig. 1E. In some embodiments, prior to fabricating the package substrate 102, a release layer (not shown) is formed over the carrier substrate 100. The release layer is a temporary bonding material that facilitates separation between the carrier substrate 100 and the package substrate 102.

[0041] In some embodiments, conductive bumps 136 are subsequently formed over the surface of the package substrate 102 that was originally covered by the carrier substrate 100, as shown in Fig. 1E. Each bump 136 may be electrically connected to one of the conductive features 106 of the package substrate 102. The conductive bumps 136 enable electrical connection between the package structure and an external device (not shown). The conductive bumps 136 may be or include solder bumps, such as tin-containing solder bumps. The tin-containing solder bumps may also include copper, silver, gold, aluminum, lead, one or more other suitable materials, or a combination thereof. In some embodiments, the tin-containing solder bumps are lead-free.

[0042] In some embodiments, after the removal of the carrier substrate 100, solder balls (or solder elements) are present on the exposed conductive features 106. A reflow process is then performed to melt the solder balls into the conductive bumps 136. In some embodiments, UBM (under bump metallization) elements are formed over the exposed conductive features 106 before the solder balls are placed. In some other embodiments, solder elements are electroplated onto the exposed conductive features 106. A reflow process is then performed to melt the solder element into the conductive bumps 136.

[0043] In some embodiments, a separation process is then performed. This creates several separate package structures. In Fig. 1E shows only one of the package structures. The protective layer 134 has an opening 134B that exposes the top surface 128A of each semiconductor device 128. In cases where a large amount of heat may be generated during operation of the semiconductor device 128 (such as a processor device), the opening 134B in the protective layer 134 facilitates rapid heat dissipation from the semiconductor device 128 and prevents overheating.

[0044] In addition, the protective layer 134 further includes a cover portion 134C covering the top surface 124A of each semiconductor device 124, as shown in Fig. 1E. In some embodiments, the cover portion 134C covers substantially the entire top surface 124A of the semiconductor device 124. In some embodiments, the cover portion 134C is disposed directly on the top surface 124A of the semiconductor device 124. As a result, the cover portion 134C of the protective layer 134 may reduce deflection of the semiconductor device 124, as will be explained below. In some embodiments, the semiconductor device 124 is susceptible to deflection or buckling caused by the elevated temperatures used in the reflow or thermal processes discussed above, and the deflection of the semiconductor device 124 may result in irregular joints and / or cracks in the underlying conductive structures 126. By covering and pressing with the cover portion 134C, the deflection of the semiconductor device 124 may be reduced.

[0045] This improves the performance and reliability of the semiconductor components in the package structure. Consequently, the overall performance (which includes electrical and mechanical performance) and reliability of the package structure are also improved.

[0046] Numerous variations and / or modifications may be made to embodiments of the invention. Fig. 2A to 2C are cross-sectional views of various stages of a method of manufacturing a package structure according to some embodiments.

[0047] As in Fig. 2A, a structure is provided or obtained which is similar to that shown in Fig. 1C. Subsequently, in some embodiments, a cap layer 200 is formed over each of the semiconductor devices 124. In some embodiments, the cap layer 200 is disposed directly on (i.e., in direct contact with) the top surface 124A of the semiconductor device 124. In some embodiments, the cap layer 200 covers substantially the entire top surface 124A of the semiconductor device 124. In some embodiments, a sum H1 + H3 of the height H1 of the semiconductor device 124 and a height H3 of the cap layer 200 in the direction D1, which is substantially perpendicular to the top surface 110A of the interposer substrate 110, is smaller than the height H2 of the semiconductor device 128 in the direction D1, as shown in Fig. 2A is shown.

[0048] In some embodiments, the cap layer 200 comprises an organic polymer material (e.g., epoxy, a resin, or the like) either with or without a hardener, fillers (e.g., silica filler, glass filler, alumina, silicon oxide, or the like), adhesion promoters, a combination thereof, or the like. Alternatively, the cap layer 200 comprises copper, aluminum, gold, titanium, another suitable metallic material, alloys thereof, or a combination thereof. The cap layer 200 may be formed using a placement process, a printing process, a PVD process, a CVD process, one or more other suitable processes, or a combination thereof.

[0049] As in Fig. 2B, a protective layer 134 is formed in some embodiments to enclose and protect the semiconductor devices 124, the cap layer 200, and the semiconductor devices 128. The materials and the manufacturing process for the protective layer 134 may be similar to those for the Fig. 1D. In some embodiments, the cover layer 200 comprises a different material than the protective layer 134. For example, the protective layer 134 comprises a molding material described above, and the cover layer 200 comprises an organic polymer material or a metallic material described above. In some embodiments, the hardness of the cover layer 200 is greater than that of the protective layer 134.

[0050] In some embodiments, a planarization process is performed on the protective layer 134 to partially remove it. This exposes the top surface 128A of each semiconductor device 128, while leaving a top surface 200A of each cap layer 200 above the respective semiconductor device 124 unexposed, as shown in Fig. 2B. In some embodiments, after the planarization process, the top surface 128A of each semiconductor device 128 is substantially flush with the top surface 134A of the protective layer 134, and the top surface 200A of each cap layer 200 is spaced a distance G' from the top surface 134A of the protective layer 134. A grinding process, a CMP process, an etching process, a dry polishing process, one or more other suitable processes, or a combination thereof may be used for the planarization process.

[0051] Subsequently, in some embodiments, the carrier substrate 100 is removed to expose a surface of the package substrate 102, as shown in Fig. 2C. In some embodiments, conductive bumps 136 are subsequently formed over the surface of the package substrate 102 that was originally covered by the carrier substrate 100, as shown in Fig. 1E. The materials and the manufacturing process for the conductive bumps 136 may be similar to those shown in Fig. 1E are the same as or similar to the conductive bumps 136 shown.

[0052] In some embodiments, a separation process is then performed. This creates several separate package structures. In Fig. 2C shows only one of the package structures. Similar to the one shown in Fig. In the package structure shown in Figure 1E, the protective layer 134 has an opening 134B that exposes the top surface 128A of each semiconductor device 128. This facilitates rapid heat dissipation from the semiconductor device 128 and prevents overheating.

[0053] In addition, the protective layer 134 further comprises a cover part 134C covering the top side 200A of each cover layer 200, so that the cover layer 200 is arranged between the cover part 134C and the top side 124A of the respective semiconductor device 124, as shown in Fig. 2C. By covering and pressing with the cover part 134C and the cover layer 200, the deflection of the semiconductor component 124 can be reduced. Due to its rigidity, the cover layer 200 also withstands the deflection of the semiconductor component 124.

[0054] This improves the performance and reliability of the semiconductor components in the package structure. Consequently, the overall performance (which includes electrical and mechanical performance) and reliability of the package structure are also improved.

[0055] Numerous variations and / or modifications may be made to embodiments of the invention. Fig. 3 is a cross-sectional view of a package structure according to some embodiments. In Fig. 3, the cover layer 200 is fabricated to cover only a portion of the top surface 124A of the semiconductor device 124 instead of the entire top surface 124A, while the other parts of the package structure are the same as those of the Fig. 2C. In some embodiments, the cap layer 200 may cover about 90% to about 95% of the top surface 124A of the semiconductor device 124. It has been found that by using this amount of coverage of the semiconductor device 124, the deflection experienced by the semiconductor device 124 may be effectively reduced. However, embodiments of the invention are not limited thereto. A different coverage level for the cap layer 200 over the semiconductor device 124 may also be used, as long as the deflection of the semiconductor device 124 can be reduced.

[0056] Numerous variations and / or modifications may be made to embodiments of the invention. Fig. 4 is a cross-sectional view of a package structure according to some embodiments. In Fig. 4, the protective layer 134 not only has an opening 134B exposing the top surface 128A of each semiconductor device 128, but it also has an opening 134D exposing the top surface 200A of each cap layer 200 above the respective semiconductor device 124, while the other parts of the package structure are the same as those in Fig. 2C shown package structure.

[0057] In some embodiments, the capping layer 200 is formed such that a sum H1 + H3 of the height H1 of the semiconductor device 124 and the height H3 of the capping layer 200 in the direction D1, which is substantially perpendicular to the top side 110A of the interposer substrate 110, is equal to the height H2 of the semiconductor device 128 in the direction D1, as shown in Fig. 4. Therefore, after the planarization process on the protective layer 134 to partially remove the protective layer 134, the top surface 134A of the protective layer 134 is substantially flush with the top surface 200A of the cap layer 200 and the top surface 128A of the semiconductor device 128. This facilitates rapid heat dissipation from the semiconductor device 128 and the semiconductor device 124 via the opening 134B and the opening 134D and prevents overheating. In some embodiments where the cap layer 200 comprises a metallic material, this further assists in dissipating heat from the semiconductor device 124.

[0058] Fig. Although Figure 4 shows that the capping layer 200 covers the entire top side 124A of the semiconductor device 124, the capping layer 200 may cover only a portion of the top side 124A of the semiconductor device 124 in other embodiments not explained. Similar to the embodiments of Fig. 2C and Fig. 3, the cover layer 200 also withstands the deflection of the semiconductor component 124 due to its rigidity.

[0059] Numerous variations and / or modifications may be made to embodiments of the invention. For example, the semiconductor devices 124 and / or the semiconductor devices 128 may be incorporated in the package structures shown in the Fig. 1 to 4, may also be or comprise one or more package modules (as shown for example in Fig. 5 is shown).

[0060] As in Fig. 5, in some embodiments, a package module includes an interconnect structure 500 and one or more semiconductor dies 502 and 504 fabricated on the interconnect structure 500. In various embodiments, the semiconductor dies 502 and 504 may be any type of semiconductor die described above. The semiconductor dies 502 and 504 may be bonded to the interconnect structure 500 by flip-chip bonding, wire bonding, and / or other suitable bonding techniques. In some embodiments, the interconnect structure 500 is an interposer substrate that supports the semiconductor dies 502 and 504 and provides an electrical connection between the semiconductor dies 502 and 504 and the interposer substrate 110 (see Fig. 1 to 4). In these cases, the connection structure 500 has a structure similar to that of the interposer substrate 110. As in Fig. 5, in some embodiments, the package module further includes a protective layer 506 formed over the interposer substrate 110 to enclose and protect the semiconductor dies 502 and 504. The materials and fabrication process for the protective layer 506 may be similar to those for the Fig. 1D shown protective layer 134.

[0061] Although only two types of semiconductor devices are shown in the package structures of the above embodiments, more types of semiconductor devices may be used in other embodiments.

[0062] In embodiments of the invention, a package structure is fabricated including a package substrate, an interposer substrate over the package substrate, and a plurality of semiconductor devices over the interposer substrate. A protective layer is fabricated to enclose and protect the semiconductor devices. Some semiconductor devices are exposed through openings in the protective layer so that the generated heat can be quickly dissipated. Some other semiconductor devices are embedded in the protective layer and / or covered with additional capping layers so that deflection of the semiconductor devices can be reduced. The performance and reliability of the semiconductor devices in the package structure are improved. This also improves the overall performance (which includes electrical and mechanical performance) and reliability of the package structure.

[0063] According to some embodiments, a package structure is provided. The package structure includes a package substrate, an interposer substrate, a first semiconductor device, a second semiconductor device, and a protective layer. The interposer substrate is disposed over the package substrate, wherein the first semiconductor device and the second semiconductor device are different types of electronic devices. The protective layer is formed over the interposer substrate to enclose the first semiconductor device and the second semiconductor device. The second semiconductor device is free of the protective layer, while the first semiconductor device is not free of the protective layer.

[0064] According to some embodiments, a package structure is provided. The package structure includes a package substrate, an interposer substrate, a first semiconductor device, a second semiconductor device, a cap layer, and a protection layer. The interposer substrate is disposed over the package substrate. The first semiconductor device and the second semiconductor device are disposed over the interposer substrate. The cap layer is formed on a top surface of the first semiconductor device. The protection layer is formed over the interposer substrate to enclose the first semiconductor device, the cap layer, and the second semiconductor device. The second semiconductor device is free of the protection layer, while the first semiconductor device is not free of the protection layer.

[0065] According to some embodiments, a method for manufacturing a package structure is provided. The method includes stacking an interposer substrate to be disposed over the package substrate. The method further includes disposing a first semiconductor device and a second semiconductor device over the interposer substrate. The method further includes forming a protective layer over the interposer substrate to enclose the first semiconductor device and the second semiconductor device. Furthermore, the method includes removing a portion of the protective layer such that the second semiconductor device is exposed from the protective layer and the first semiconductor device is not exposed from the protective layer.

Claims

[1] Package structure with: a package substrate (102); an interposer substrate (110) disposed over the package substrate (102); a first semiconductor device (124) and a second semiconductor device (128) disposed over the interposer substrate (110), wherein the first semiconductor device (124) and the second semiconductor device (128) are different types of electrical devices; and a protective layer (134) formed over the interposer substrate (110) to enclose the first semiconductor device (124) and the second semiconductor device (128), the second semiconductor device (128) being free from the protective layer (134, 506) and the first semiconductor device (124) not being free from the protective layer (134, 506), the protective layer (134, 506) having a cover portion (134C) covering a top surface (124A) of the first semiconductor device (124) and an opening (134B) exposing a top surface (128A) of the second semiconductor device (128). [2] The package structure of claim 1, wherein the protective layer (134) is made of a polymer material. [3] The package structure according to claim 1 or 2, wherein the cover part (134C) is arranged directly on the top surface (124A) of the first semiconductor device (124). [4] The package structure according to claim 2 or 3, further comprising a cap layer (200) formed between the cap part (134C) and the top surface (124A) of the first semiconductor device (124), the cap layer (200) comprising a different material than the protective layer (134, 506). [5] The package structure of claim 4, wherein the cap layer (200) is disposed directly on the top surface (124A) of the first semiconductor device (124). [6] The package structure according to claim 4 or 5, wherein the cap layer (200) covers a part of the top surface (124A) of the first semiconductor device (124). [7] Package structure according to one of claims 4 to 6, wherein the cover layer (200) has a greater hardness than the protective layer (134). [8] Package structure with: a package substrate (102); an interposer substrate (110) disposed over the package substrate (102); a first semiconductor device (124) and a second semiconductor device (128) disposed over the interposer substrate (110); a cap layer (200) formed on a top surface (124A) of the first semiconductor device (124); and a protective layer (134) formed over the interposer substrate (110) to enclose the first semiconductor device (124), the cap layer (200), and the second semiconductor device (128), wherein the second semiconductor device (128) is free of the protective layer (134) and the first semiconductor device (124) is not free of the protective layer (134), the cap layer (200) being disposed directly on top (124A) of the first semiconductor device (124). [9] The package structure of claim 8, wherein the protective layer (134) has a first opening (134D) exposing a top surface (200A) of the cap layer (200) and a second opening (134B) exposing a top surface (128A) of the second semiconductor device (128). [10] The package structure of claim 9, wherein a top surface (134A) of the protective layer (134) is level with the top surface (200A) of the cap layer (200) and the top surface (128A) of the second semiconductor device (128). [11] Package structure according to one of claims 8 to 10, wherein the cover layer (200) comprises an organic polymer material or a metallic material. [12] The package structure according to any one of claims 8 to 11, wherein the cap layer (200) covers a part of the top surface (124A) of the first semiconductor device (124). [13] The package structure according to any one of claims 8 to 12, wherein the cap layer (200) covers the entire top surface (124A) of the first semiconductor device (124). [14] Package structure according to one of claims 8 to 13, wherein the cover layer (200) comprises a different material than the protective layer (134). [15] Package structure according to one of claims 8 to 14, wherein the cover layer (200) has a greater hardness than the protective layer (134). [16] Method for producing a package structure comprising the following steps: Stacking an interposer substrate (110) so that it is arranged over a package substrate (102); Arranging a first semiconductor device (124) and a second semiconductor device (128) over the interposer substrate (110); Forming a protective layer (134) over the interposer substrate (110) so as to enclose the first semiconductor device (124) and the second semiconductor device (128); and Removing a portion of the protective layer (134) such that the second semiconductor device (128) is freed from the protective layer (134) and the first semiconductor device (124) is not freed from the protective layer (134), wherein after removing the portion of the protective layer (134), the protective layer (134) has a portion remaining on a top surface (124A) of the first semiconductor device (124) and an opening (134B) exposing a top surface of the second semiconductor device (128). [17] The method of claim 16, wherein the method further comprises forming a cap layer (200) over the first semiconductor device (124) prior to forming the protective layer (134), wherein after removing the portion of the protective layer (134), the cap layer (200) is located between a cap portion (134C) and the top surface (124A) of the first semiconductor device (124). [18] The method of claim 17, wherein the cover layer (200) has a greater hardness than the protective layer (134). [19] The method of claim 17 or 18, wherein the cap layer (200) is in direct contact with the top surface (124A) of the first semiconductor device (124). [20] The method of claim 17 or 18 or 19, wherein the cap layer (200) is formed to cover a portion of the top surface (124A) of the first semiconductor device (124).

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