SPACING PLAN AND PROCEDURES FOR MRAM

Abstract

IC (100), comprising: a substrate (202); a resistive random access memory cell (107) formed over the substrate (202), the resistive random access memory cell (107) having a bottom electrode (125), a resistive switching layer (142), and a top electrode (103), the resistive switching layer (142) having a side surface (104) between the bottom electrode (125) and the top electrode (103), at least one of the top electrode (103) and the bottom electrode (125) comprising an electrode metal; and a side wall spacer (113, 115) formed over the side surface (104); wherein an amount of the electrode metal sufficient to form a thin layer (105) is distributed over the side surface (104) within a first layer (117, 251, 301) between the side surface (104) and the sidewall spacer (113, 115); and the first layer (117, 251, 301) contains an oxide, a carbide, an oxycarbide, an oxynitride, a carbonitride or an oxycarbonitride; wherein the electrode metal is intermittently distributed within the first layer (117, 251, 301) over the side surface (104) and is covered by the oxide, carbide, oxycarbide, oxynitride, carbonitride or oxycarbonitride also present within the first layer (117, 251, 301).

Description

BACKGROUND

[0001] This disclosure generally relates to volatile and non-volatile memory for use in standalone memory chips and memory arrays integrated on logic chips. More specifically, this disclosure relates to resistive random access memory devices for integrated circuits. Types of resistive random access memory include resistive random access memory (ReRAM), phase-change random access memory (PCRAM), and magnetoresistive random access memory (MRAM). ReRAM may include a dielectric through which conductive bridges can be reversibly formed by applying voltage. PCRAM relies on "phase-change" materials that transition from highly amorphous to crystalline arrays when heated as a programming mechanism. MRAM stores information according to the direction of magnetic moments on magnetic film layers within magnetic tunnel junction (MTJ) devices.US 2019 / 0036014 A1 describes a semiconductor memory with a variable resistance element, wherein an initial sidewall spacer formed on sidewalls of the variable resistance element during an etching process is predominantly composed of etching by-products of the etched layers. BRIEF DESCRIPTION OF THE DRAWINGS

[0002] Aspects of the present disclosure can best be understood by reference to the following detailed description when taken in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not drawn to scale. Indeed, the dimensions of various features may be arbitrarily exaggerated or reduced for clarity of illustration. Fig. 1 illustrates a cross-sectional view of an integrated circuit (IC) with RRAM cells according to some aspects of this teaching. Fig. Figure 2 illustrates a cross-sectional view of an integrated circuit (IC) with RRAM cells according to some other aspects of this teaching. Fig. Figure 3 illustrates a cross-sectional view of an integrated circuit (IC) with RRAM cells according to some other aspects of this teaching. Fig. Figure 3A is an enlarged view of area 3A of Fig. 3 ready. Fig. 4 to 17 illustrate a series of cross-sectional views of an IC according to some aspects of this teaching undergoing a manufacturing process according to some aspects of this teaching. Fig. 18 to 20 illustrate a series of cross-sectional views of an IC according to some other aspects of this teaching undergoing a manufacturing process according to some aspects of this teaching. Fig. 21 to 23 illustrate a series of cross-sectional views of an IC according to some other aspects of this teaching undergoing a manufacturing process according to some other aspects of this teaching. Fig. 24 shows a flow diagram of a manufacturing process according to some aspects of this teaching. DETAILED DESCRIPTION

[0003] This disclosure provides many different embodiments or examples for implementing various features of this disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, only examples and are not intended to be limiting. For example, in the following description, forming a first feature or a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features need not be in direct contact.

[0004] Resistive-switched random access memory (RRAM) includes a bottom electrode, a top electrode, and a resistive switching structure such as an MTJ between them. During patterning of RRAM cells, it is possible for a metal, such as tantalum (Ta), to be re-sputtered from the top electrode or bottom electrode onto the sides of the MTJ or other resistive switching structure. When a silicon nitride (SiN) spacer is subsequently deposited over the RRAM cell, the re-sputtered electrode metal can react to form a metal nitride layer. Current can bypass the resistive switching structure by conduction through the metal nitride layer. The bypass current can be sufficiently large to disrupt the operation of the RRAM cell.

[0005] According to some aspects of this teaching, the electrode metal that has been resputtered onto a side is either encapsulated or converted into a high-resistivity compound. Encapsulation may be sufficient if the resputtered electrode metal does not form a continuous layer, for example, if the resputtered material is intermittently distributed across the side. Encapsulation may be with an oxide, a carbide, an oxycarbide, an oxynitride, a carbonitride, an oxycarbonitride, or another compound that either does not react with the electrode metal or that reacts with the electrode metal to form a high-resistivity compound of the electrode metal. A high-resistivity compound of the electrode metal may be an oxide, a carbide, an oxycarbide, an oxynitride, a carbonitride, or an oxycarbonitride. In some of these teachings, the electrode metal is tantalum (Ta).

[0006] In some of these teachings, the newly sputtered electrode metal is converted into a high-resistivity compound by reaction with a flux gas. The flux gas may be oxygen-rich and contain O 2 , O 3 or the like at a partial pressure in the range of 5 to 20 Torr. The reaction temperature may be in the range of 100 °C to 500 °C. In some of these teachings, the newly deposited electrode metal is converted into a high-resistivity compound by reaction with a plasma. In some of these teachings, the plasma source comprises O 2 , O 3 , N 2 O or the like, forming an oxide of the electrode metal. In some of these teachings, the plasma source comprises CO, forming an oxycarbide of the electrode metal.

[0007] In some of these teachings, the newly sputtered electrode metal is coated with a thin layer that either encapsulates the newly sputtered electrode metal without reacting with the newly sputtered electrode metal or converts the newly sputtered electrode metal into a high-resistivity compound. In some of these teachings, the thin layer is an oxide. The oxide can oxidize the newly sputtered electrode metal. In some of these teachings, the oxide is a SiO x , HfO x , ZrO x , TiO x or WHERE x In some of these teachings, the thin film has a thickness in the range of 3 Å to 30 Å. The thin film can be formed by PVD, CVD, or ALD.

[0008] In some of these teachings, the thin film is a high-resistivity compound of the electrode metal. A high-resistivity compound can be an oxide, a carbide, an oxycarbide, an oxynitride, a carbonitride, or an oxycarbonitride of the electrode metal. The high-resistivity compound can provide good coverage of the newly sputtered electrode metal, and the process of depositing the high-resistivity compound can either encapsulate the newly sputtered electrode metal or convert the newly sputtered electrode metal into a high-resistivity form. In some of these teachings, the thin film is formed in a spacer by anisotropic etching. The thin film formed in the spacer can have a thickness that decreases along the direction from the bottom electrode to the top electrode, with the thin film adjacent to the bottom electrode being thinner than adjacent to the top electrode.

[0009] In some of these teachings, the newly sputtered electrode metal is converted to a form having a lower conductivity than an insulating material comprising a resistive layer of an MTJ, such as MgO or the like. In some of these teachings, the newly sputtered electrode metal is tantalum (Ta) and is converted to a form having a lower conductivity than hexagonal Ta. 5 N 6 or a similar phase of tantalum nitride. In some of these teachings, the protective layer comprising the newly sputtered electrode metal has a thickness in the range of 3 Å to 30 Å.

[0010] In some of these teachings, the newly sputtered electrode metal is converted or encapsulated into a high-resistance interconnect while the substrate is under vacuum, and a layer of silicon nitride (SiN) or the like is formed over the high-resistance interconnect while the IC device remains under vacuum. The SiN layer may be etched to form a SiN spacer. In some of these teachings, a second spacer is formed over the SiN spacer. The second spacer may be silicon nitride, silicon oxide, silicon carbide, silicon carbonitride, silicon oxycarbide, silicon oxycarbonitride, or the like. In some of these teachings, the spaces between adjacent RRAM cells are subsequently filled with silicon nitride (SiN), silicon carbide (SiC), silicon carbonitride (SiCN), silicon oxycarbide (SIOC), silicon oxycarbonitride (SiOCN), or the like.

[0011] Regardless of whether the newly sputtered electrode metal is encapsulated and thereby prevented from forming a continuous metal nitride layer or is converted into a high-resistance interconnect, the result is that a bypass current through the newly sputtered electrode metal is prevented from becoming significant compared to a current through the RRAM cell. The RRAM cell has a high-resistance state and a low-resistance state. In some embodiments, the bypass current is 20 times a current through the RRAM cell or less when the RRAM cell is in the low-resistance state. In some embodiments, the bypass current is 100 times a current through the RRAM cell or less when the RRAM cell is in the low-resistance state. In some embodiments, the bypass current is 1000 times a current through the RRAM cell or less when the RRAM cell is in the low-resistance state.

[0012] Fig. 1 illustrates a cross-sectional view of a portion of an integrated circuit device 100 including memory cells 107 according to some aspects of this teaching. Each memory cell 107 includes a bottom electrode 125, a metal tunnel junction (MTJ) 142, and a top electrode 103. The MTJ 142 includes a first ferromagnet 123, an insulator 121, and a second ferromagnet 119. An electrode metal found in either the bottom electrode 125 or the top electrode 103 is also found within a thin layer 105 on a side surface 104 of the MTJ 142.

[0013] In some embodiments, thin layer 105 forms at least one atomic layer of electrode metal compounds over side surface 104. In some embodiments, electrode metal compounds in thin layer 105 form a layer having a thickness of 3 Å or more. In some embodiments, the electrode metal compounds in thin layer 105 are oxides, carbides, oxycarbides, oxynitrides, carbonitrides, or oxycarbonitrides of the electrode metal. In some embodiments, the electrode metal compounds in thin layer 105 are oxides of the electrode metal.

[0014] In some embodiments, the thin layer 105 includes the electrode metal in a metallic form, but the metallic form does not form a continuous path between the top electrode 103 and the bottom electrode 125. In some embodiments, the electrode metal in the thin layer 105 is present in compounds that are an oxide, a carbide, an oxycarbide, an oxynitride, a carbonitride, or an oxycarbonitride.

[0015] The thin layer 105 is covered by or integrated with a protective layer 117. In some embodiments, the protective layer 117 has a thickness in the range of 2 Å to 60 Å. In some embodiments, the protective layer has a thickness in the range of 3 Å to 30 Å. The protective layer 117 comprises one or more layers of oxide, carbide, oxycarbide, oxynitride, carbonitride, or oxycarbonitride. In some embodiments, the protective layer comprises an oxide selected from the group consisting of SiO x , HfO x, ZrO x , TiO x and where x was selected. In some embodiments, the protective layer comprises an oxide, a carbide, an oxycarbide, an oxynitride, a carbonitride, or an oxycarbonitride of the electrode metal.

[0016] A first spacer 115 is formed around the RRAM cell 107 and is separated from the MTJ 142 by the thin layer 105 and the protective layer 117. In some embodiments, the first spacer 115 is silicon nitride (SiN). In some embodiments, the electrode metal is contained within the thin layer 105, and the protective layer 117 separates the thin layer 105 from the first spacer 115. In some embodiments, the protective layer 117 contains the electrode metal in the form of high-resistance interconnects of the electrode metal. In some embodiments, the protective layer 117 and the thin layer 105 are combined into a single layer.

[0017] Neither the thin layer 105 nor the protective layer 117, nor these two layers together, provide a conductive path between the top electrode 103 and the bottom electrode 125 with a conductivity comparable to that of the MTJ 142 or a similar resistive switching structure. In some embodiments, neither the material of the thin layer 105 nor the material of the protective layer 117 has as high a conductivity as the insulating material forming the insulator 121 of the resistive switching structure. In some embodiments, the insulator 121 is MgO.

[0018] A second spacer 113 may be formed over the first spacer 115. In some embodiments, the second spacer 113 is silicon nitride (SiN), silicon carbide (SiC), silicon carbonitride (SiCN), silicon oxycarbide (SIOC), silicon oxycarbonitride (SiOCN), or the like. The spaces between adjacent MRAM cells 107 may be filled with a dielectric fill layer 109. In some embodiments, the dielectric fill layer 109 is silicon nitride (SiN), silicon carbide (SiC), silicon carbonitride (SiCN), silicon oxycarbide (SIOC), silicon oxycarbonitride (SiOCN), or the like. An etch stop layer 143 may be formed over MRAM cells 107 and the dielectric fill layer 109.

[0019] Top electrodes 103 are coupled to metal features 147 in metal interconnect 149 through top electrode vias 101. Metal features 147 and top electrode vias 101 are surrounded by an interlayer dielectric layer 145. In some of these teachings, the interlayer dielectric layer 145 is a low-kappa dielectric layer. In some of these teachings, the interlayer dielectric layer 145 is an ultra-low-kappa dielectric layer. Top electrode vias 101 pass through the interlayer dielectric layer 145 and the etch stop layer 143 before terminating at the top electrodes 103. Bottom electrodes 125 are coupled to metal features 141 in metal interconnect layer 135 through bottom electrode vias 127. Lower electrode vias 127 may be formed within the etch stop layer 137, interface layer 139, and oxide layer 140.The metal feature 141 is surrounded by a matrix of the interlayer dielectric layer 133.

[0020] Metal interconnect layer 135 and metal interconnect layer 149 are part of a metal interconnect structure 218 disposed over a substrate 202. Metal interconnect layer 135 may be the third metal interconnect layer over substrate 202, and metal interconnect layer 149 may be the fourth. Metal interconnect structure 218 also includes a first metal interconnect layer 108, a second metal interconnect layer 118, and may include additional interconnect layers above those illustrated. In some of these teachings, memory cells 107 are located between the third metal interconnect layer 135 and the fourth metal interconnect layer 149 as shown in the illustrations. In some of these teachings, memory cells 107 are located between a fourth metal interconnect layer 149 and a fifth fourth metal interconnect layer. Generally, memory cells 107 may be located between any pair of metal interconnect layers.

[0021] The substrate 202 may be, for example, a bulk substrate (e.g., a bulk silicon substrate) or a silicon-on-insulator (SOI) substrate, or the like. One or more shallow trench isolation (STI) regions 204 or oxide-filled trenches may be disposed in or on the substrate 202. A pair of wordline transistors 206 may be located between STI regions 204. Wordline transistors 206 may include gates 210 that function as wordlines. Gates 210 are separated from the substrate 202 by wordline dielectric layers 212. Source / drain regions 214, 216 for wordline transistors 206 may be formed in or on the substrate 202. A metal feature 217 in the second metal interconnect layer 118 or elsewhere in the metal interconnect structure 218 may be coupled to the source / drain region 216 and function as a source line.Lower electrodes 125 can be coupled to source / drain regions 214 via vias 203. Metal features 147 in a fourth metal interconnect layer 149 or another metal interconnect layer over memory cells 107 can function as bitlines. The illustrated control structure for memory cells 107 in the IC device 100 is one of many possible control structures that can be used to connect and operate the memory cells 107. IC devices according to this teaching are not limited with respect to the control structure.

[0022] The metal interconnect structure 218 is the product of back-end-of-line (BEOL) processing. Metal features 147, 141, 217 of metal interconnect layers 108, 118, 135, 149 and vias 101, 127, 203 may be formed from metals such as copper, aluminum, gold, tungsten, titanium nitride, and the like. Interlayer dielectric layers 133, 145 may be low-κ dielectrics or ultra-low-κ dielectrics. A low-κ dielectric is a material that has a smaller dielectric constant than SiO. 2 SiO 2has a dielectric constant of approximately 3.9. Examples of low-κ dielectrics include organosilicate glasses (OSG) such as carbon-doped silicon dioxide, fluorine-doped silicon dioxide (also referred to as fluorinated fused silica (FSG), low-κ organic polymer dielectrics, and porous silica glass. An ultra-low-κ dielectric is a material that has a dielectric constant of approximately 2.1 or less. An ultra-low-κ dielectric is generally a low-κ dielectric formed in a porous structure. Porosity reduces the effective dielectric constant.

[0023] The bottom electrode via 127 may be titanium nitride or the like, or another suitable conductive material. A diffusion barrier layer 129 may separate the bottom electrode via 127 from the metal feature 141. The diffusion barrier layer 129 may be, for example, tantalum nitride or the like. In some examples, the thickness of the diffusion barrier layer 129 ranges from about 50 Å to about 100 Å. The combined thickness of the diffusion barrier layer 129 and the via 127 may range from 150 to 600 Å. In some embodiments, the combined thickness of the diffusion barrier layer 129 and the via 127 ranges from 250 to 500 Å.

[0024] Each of the layers in the memory cells 107 may include multiple layers having different compositions. The bottom electrode 125 may include one or more layers of metal or metal compounds, such as tantalum nitride, titanium nitride, tantalum, titanium, platinum, gold, iridium, tungsten, nickel, ruthenium, copper, tungsten silicide, a combination thereof, or the like. In some of these teachings, the thickness of the bottom electrode 125 ranges from about 30 Å to about 500 Å. In some of these teachings, the thickness of the bottom electrode 125 ranges from about 50 Å to about 300 Å.

[0025] The first ferromagnet 123 and the second ferromagnet 119 of the MTJ 142 are materials with ferromagnetism. Materials with ferromagnetism include cobalt iron boron (CxFeB), cobalt iron (CoFe), and nickel iron (NiFe), cobalt (Co), iron (Fe), nickel (Ni), iron boron (FeB), iron platinum (FePt), and the like. The first ferromagnet 123 and the second ferromagnet 119 may be made of different materials. In some embodiments, the first ferromagnet 123 and the second ferromagnet 119 are Co x Fe y B z However, the atomic ratios (x, y, z) between the first ferromagnet 123 and the second ferromagnet 119 may differ. The first ferromagnet 123 and the second ferromagnet 119 may be formed by any suitable process. Examples of suitable processes may include electroplating, electroless plating, sputtering, chemical vapor deposition (CVD), or other suitable processes, or the like.

[0026] The insulator 121 is a dielectric layer. Examples of materials that may be suitable for the insulator 121 include magnesium oxide (MgO), aluminum oxides (Al x O y ), titanium oxides (TiO x ) and the like. In some embodiments, the insulator 121 is a magnesium oxide (MgO). The insulator 121 may be formed by any suitable process. A suitable process may be chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), spin-on coating, or the like. In some of these teachings, the thickness of the MTJ 142 is in the range of about 50 Å to about 700 Å. In some of these teachings, the thickness of the MTJ 142 is in the range of about 100 Å to about 500 Å.

[0027] The top electrode 103 is disposed over the MTJ 142. The top electrode 103 may include a liner made of tungsten or the like. The top electrode 103 may include one or more layers of metal or metal compounds, such as tantalum nitride, titanium nitride, tantalum, titanium, platinum, gold, iridium, tungsten, nickel, ruthenium, copper, tungsten silicide, a combination thereof, or the like. In some of these teachings, the thickness of the top electrode 103 is in the range of about 30 Å to about 500 Å. In some of these teachings, the thickness of the top electrode 103 is in the range of about 50 Å to about 300 Å.

[0028] During operation of a memory cell 107, voltages are applied between the upper electrode 103 and the lower electrode 125. Depending on the applied voltages, the voltages can be used to judge whether the memory cell 107 is in a low resistance state or a high resistance state, or to place the memory cell 107 in a high resistance state or a low resistance state.

[0029] MTJ 142 is a type of resistive switching structure associated with a type of resistive switching random access memory. Memory cells 107 can be any type of resistive switching random access memory, and any type of resistive switching structure can replace MTJ 142. Examples of resistive switching random access memory include, without limitation, oxygen displacement memory (OxRAM), conductive bridge random access memory (CBRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), carbon nanotube random access memory (NRAM), and the like. Various layers of different thicknesses and compositions can replace MTJ 142 in memory cells 107 to provide resistive switching structures associated with these various types of resistive switching random access memory.For example, instead of MTJ 142, the memory cells 107 may comprise an amorphous oxide layer that forms reversibly conductive bridges and may further comprise an active metal layer that alternately donates and receives ions to the amorphous oxide layer.

[0030] Fig. 2 illustrates a cross-sectional view of a portion of an integrated circuit (IC) device 200. The description for IC device 100 applies to IC device 200, except that in IC device 200, thin layer 105 and protective layer 117 take the form of a single protective layer 251. In some embodiments, protective layer 251 has a thickness in the range of 2 Å to 60 Å. In some embodiments, protective layer 251 has a thickness in the range of 3 Å to 30 Å. Protective layer 251 comprises the newly sputtered electrode metal in a high-resistivity interconnect. In some embodiments, the high-resistivity interconnect is an oxide, a carbide, an oxycarbide, an oxynitride, a carbonitride, or an oxycarbonitride of the electrode metal.

[0031] In some embodiments, the protective layer 251 is a single layer of uniform composition. In other embodiments, the protective layer 251 comprises multiple layers of different compositions. In some embodiments, the electrode metal is uniformly distributed within the protective layer 251. In other embodiments, the electrode metal is concentrated within the protective layer 251 adjacent to the side surface 104.

[0032] Fig. 3 illustrates a cross-sectional view of a portion of an integrated circuit (IC) device 300. The description of IC device 200 also applies to IC device 300, except that IC device 300 includes a protective layer 301 instead of protective layer 251. The composition of protective layer 301 may be the same as that of protective layer 251. Protective layer 301 may include an inner layer having the composition of thin layer 105 and an outer layer having the composition of protective layer 117.

[0033] As in Fig. 3A, which shows an expanded view of area 3A from Fig. 3, the protective layer 301 has a thickness that increases with increasing distance from the substrate 202. The thickness 305 of the protective layer 301 adjacent to the upper electrode 103 is less than the thickness 303 of the protective layer 301 adjacent to the lower electrode 125. The maximum thickness of the protective layer 301 adjacent to the upper electrode 103 is less than the minimum thickness of the protective layer 301 adjacent to the lower electrode 125. This variation in thickness facilitates the process of filling the space between adjacent MRAM cells 107 without creating voids.

[0034] Fig. 4 to 17 provide a series of cross-sectional views 400 to 1700 illustrating an integrated circuit device according to these teachings at various stages of manufacture according to a process of these teachings. Although Fig. 4 to 17 with reference to a series of acts, it will be appreciated that the order of the acts may be changed in some cases and that this series of acts applies to structures other than those illustrated. In some embodiments, some of these acts may be omitted in whole or in part. Furthermore, it will be appreciated that the structures illustrated in Fig. 4 to 17 are not limited to one method of manufacture, but instead may stand alone as structures separate from the process.

[0035] As shown in cross-sectional view 400 of Fig. 4, an etch stop layer 137, an interface layer 139, and an oxide layer 140 may be formed over the third metal interconnect 135. The third metal interconnect 135 may be formed by a suitable process. Examples of suitable processes include damascene and double damascene processes. The etch stop layer 137 may be, for example, silicon carbide (SiC) or the like. The interface layer 139 is optional and may be, for example, silicon dioxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiON), silicon oxycarbide (SiOC), or the like. The oxide layer 140 may be silicon dioxide (SiO 2 ) or the like and may be made of tetraethylorthosilicate (Si(OH) 4 or TEOS) or another suitable precursor. The etch stop layer 137, interface layer 139, and oxide layer 140 may be formed by any suitable processes or combinations of processes.

[0036] As shown by the cross-sectional view 500 of Fig. 5, a mask 503 may be formed over the oxide layer 140 and used to form openings 501 through the oxide layer 140, interface layer 139, and etch stop layer 137. The openings 501 are placed over metal features 141 of the metal interconnect 135. The mask 503 may be a photoresist mask patterned using photolithography. Openings 501 may be formed using any suitable etching process, such as dry etching such as plasma etching.

[0037] As shown by the cross-sectional view 600 of Fig. 6, the mask 503 may be stripped, followed by the formation of a diffusion barrier layer 129 and a layer of conductive material 601. The conductive material 601 is deposited or built up in sufficient quantity to fill openings 501. As illustrated by the cross-sectional view 700 of Fig. As illustrated in Figure 7, the layer of conductive material 601 may be planarized to form the vias 127. The diffusion barrier layer 129 and the layer of conductive material 601 may be formed by any suitable growth or deposition process. The planarization process may be chemical mechanical polishing (CMP) or any other suitable planarization process.

[0038] As shown in cross-sectional view 800 of Fig. 8, an MRAM cell stack 815 may be formed over the area of ​​the structure represented by the cross-sectional view 700 of Fig. 7. In this example, the MRAM cell stack 815 includes the bottom electrode layer 801, MTJ layer 810, and the top electrode layer 811. The MTJ layer 810 includes a first ferromagnetic layer 803, an insulation layer 805, and a second ferromagnetic layer 809. The bottom electrode layer 801, the various layers of the MTJ layer 810, and the top electrode 811 may be formed by any suitable process or combination of processes.

[0039] As shown in cross-sectional view 800 of Fig. 8, a mask 813 may be formed over the MRAM cell stack 815 and used to isolate MRAM cells 107 from the MRAM cell stack 815 as illustrated by the cross-sectional view 900 of Fig. 9 illustrates the structuring process. The structuring forms lower electrodes 125 from the lower electrode layer 801, first ferromagnets 123 from the first ferromagnetic layer 803, insulators 121 from the insulating layer 805, second ferromagnets 119 from the second ferromagnetic layer 809, and upper electrodes 103 from the lower electrode layer 811. The structuring process may use any suitable etching process, such as plasma etching or the like.

[0040] As shown in cross-sectional view 900 of Fig. As illustrated in Figure 9, during the patterning process, a thin layer 105 forms on the sides 104 of the MTJs 142. The thin layer 105 includes a small amount of metal, which may come from the top electrode layer 811, or more likely from the bottom electrode layer 801. The bottom electrode layer 801 and the top electrode layer 811 may have been formed by sputtering, and the process by which metal from either of these layers deposits on the sides 104 of the MTJs 142 is similar to sputtering. Accordingly, the electrode metal in the thin layer 105 may be described as newly sputtered electrode metal.

[0041] The thin layer 105 may be only a few angstroms thick. While the amount of newly sputtered electrode metal in the thin layer 105 may not form a continuous path between the top electrode 103 and the bottom electrode 125, it is sufficient to form a single layer over the sides 104. Even if the thin layer 105 does not form a continuous layer of newly sputtered electrode metal, the newly sputtered electrode metal is sufficiently well-distributed that reaction with ammonium or similar chemicals used to form silicon nitride spacers converts the newly sputtered electrode metal into a continuous layer of nitride of the newly sputtered electrode metal over the sides 104.

[0042] As shown in the cross-sectional view 1000 from Fig. 10, a protective layer 117 is formed over the thin layer 105. The protective layer 117 is a high-resistivity layer formed with a chemistry that does not convert the thin layer 105 into a continuous, high-conductivity layer. The protective layer 117 encapsulates the thin layer 105. In some embodiments, the process of forming the protective layer 117 converts the newly sputtered electrode metal in the thin layer 105 into a high-resistivity compound of the electrode metal, such as an oxide, a carbide, an oxycarbide, an oxynitride, a carbonitride, or an oxycarbonitride of the electrode metal.

[0043] According to some aspects of this teaching, the protective layer 117 is formed by an oxide deposition process. Depending on the composition of the protective layer 117, an interface between the protective layer 117 and the oxide layer 140 may or may not be visible. In some embodiments, the protective layer 117 is deposited to a thickness in the range of 2 Å to 60 Å. In some embodiments, the protective layer 117 is deposited to a thickness in the range of 3 Å to 30 Å. In some of these teachings, the protective layer 117 is formed of tetraethylorthosilicate (TEOS). In some of these teachings, the protective layer 117 is formed of SiH 4 or the like. In some of these teachings, the protective layer 117 is formed from precursors of HfO x , ZrO x , TiO x or WHERE xformed. In some of these teachings, the protective layer 117 is formed from a metal oxide precursor, such as M-OR, where "M" is a metal and "OR" is an organic material. For example, M-OR may be Ta(OCH 2 CH 3 ) 5 In some of these teachings, the deposition takes place under oxygen-rich conditions, such as by including O 2 , O 3 or the like in a process gas flow.

[0044] In some embodiments, the protective layer 117 is formed by chemical vapor deposition (CVD) at a pressure in the range of 0.5 Torr to 20 Torr. In some embodiments, the pressure is in the range of 1 Torr to 5 Torr, such as 1.5 Torr. In some embodiments, the protective layer 117 is formed by CVD at a temperature in the range of 100°C to 500°C. In some embodiments, the temperature is in the range of 200°C to 400°C, such as 300°C.

[0045] CVD can be enhanced by generating a plasma from the reacting gases. For example, the plasma can be generated by a radio frequency (RF) discharge. In some embodiments, the power is in the range of 10 W to 1 kW. In some embodiments, the power is in the range of 50 W to 500 W, such as 100 W.

[0046] In some embodiments, the protective layer 117 is formed by atomic layer deposition (ALD). In some embodiments, the ALD occurs at a pressure in the range of 0.5 Torr to 10 Torr. In some embodiments, the ALD occurs at a pressure in the range of 1 Torr to 5 Torr. In some embodiments, the protective layer 117 is formed by ALD at a temperature in the range of 100°C to 400°C. In some embodiments, the temperature is in the range of 200°C to 350°C.

[0047] As shown in cross-sectional view 1100 of Fig. 11, a spacer material 1101 may be disposed over the protective layer 117 and the remainder of the structure shown by the cross-sectional view 1000 of Fig. 10. Spacer material 1101 may comprise any suitable spacer material. In some embodiments, the spacer material is silicon nitride (SiN) or the like.

[0048] Spacer material 1101 may be deposited by any suitable process or processes. A suitable process may be chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or the like. In some of these teachings, the protective layer 117 is formed at reduced pressure, and the spacer material 1101 is deposited without exposing the protective layer 117 to the atmosphere or atmospheric pressure. In some of these teachings, the spacer material 1101 is deposited using the same tool used to form the protective layer 117.

[0049] As shown in cross-sectional view 1200 Fig. As illustrated in Figure 12, the spacer material 1101 may be etched to form first sidewall spacers 115. The etching process may include plasma etching or any other etching process that selectively removes the spacer material where it is thinnest with respect to a downward direction. In some embodiments, first sidewall spacers 115 have a thickness in the range of 20 Å to 300 Å. In some embodiments, first sidewall spacers 115 have a thickness in the range of 30 Å to 200 Å.

[0050] As shown in cross-sectional view 1300 of Fig. 13, a second spacer material layer 1301 may be formed over the structure shown by the cross-sectional view 1200 of Fig. 12. The second spacer material layer 1301 may be one or more layers of one or more suitable dielectrics. Materials that may be suitable for the second spacer material layer 1301 include, without limitation, silicon nitride (SiN), silicon dioxide (SiO 2 ), silicon carbide (SiC), silicon carbonitride (SiCN), silicon oxycarbide (SIOC), silicon oxycarbonitride (SiOCN), or the like. The material can be deposited by any suitable process. A suitable process may be chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or the like.

[0051] As shown in cross-sectional view 1400 Fig. As illustrated in Figure 14, the second spacer material 1301 may be etched to form second sidewall spacers 113. The etching process may include plasma etching or any other etching process that selectively removes the spacer material where it is thinnest with respect to a downward direction. In some embodiments, second sidewall spacers 113 have a thickness in the range of 20 Å to 300 Å. In some embodiments, second sidewall spacers 113 have a thickness in the range of 30 Å to 200 Å.

[0052] As shown by the cross-sectional view 1500 of Fig. 15, a dielectric fill layer 109 and a bottom anti-reflective coating (BARC) 1501 may be formed over the structure shown by the cross-sectional view 1400 of Fig. 14. The dielectric filling layer 109 may be a dielectric such as silicon dioxide (SiO 2), silicon nitride (SiN), silicon carbide (SiC), silicon carbonitride (SiCN), silicon oxycarbide (SIOC), silicon oxycarbonitride (SiOCN), or the like. The dielectric fill layer 109 is sufficiently thick to fill the space between MRAM cells 107. The dielectric fill layer 109 may be deposited by any suitable process, such as CVD, ALD, or the like. BARC 1501 may be an organic material consumed by a spin-on process to form a planar surface.

[0053] As shown in the cross-sectional view 1600 Fig. 16, one or more processes may be performed to modify the structure of the surface represented by the cross-sectional view 1500 of Fig. As illustrated in FIG. 15, it is etched sufficiently to expose the upper electrodes 103 while obtaining a substantially planar upper surface. The processes may include a non-selective etch-back process and / or a chemical-mechanical polishing (CMP) or a non-selective etch-back process followed by CMP.

[0054] As shown by the cross-sectional view 1700 of Fig. 17, an etch stop layer 143 may be formed over the structure shown by the cross-sectional view 1600 of Fig. 16. The etch stop layer 143 may be any suitable dielectric. Examples of the dielectric that may be suitable for the etch stop layer 143 include silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbide (SiOC), and the like. In some of these teachings, the etch stop layer 143 is silicon nitride (SiN). The etch stop layer 143 may be formed by any suitable process or processes. A suitable process may be chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or the like.

[0055] As further shown by the cross-sectional view 1700 of Fig. 17, a protective layer 145 may be formed over the etch stop layer 143. The interlayer dielectric layer 145 may be a low-κ or ultra-low-κ dielectric formed by any suitable process. Openings may be etched through the interlayer dielectric layer 145 and filled with metal to form vias 101 and metal features 147 of the interconnect layer 149. The process of forming the vias 101 and the metal features 147 may include damascene or double damascene processing. The resulting structure may resemble that of the IC 100 of Fig. 1 correspond.

[0056] The cross-sectional views 1800 to 2000 from Fig. 18 to 20 second an alternative processing that can be used at the location of the processing indicated by the cross-sectional views 1000 to 1200 of Fig. 10 to 12. As shown by the cross-sectional view 1800 of Fig. As shown in Figure 18, the formation of the protective layer 251 may be limited to areas where the thin layer 105 was present, and the material of the thin layer 105 may be incorporated into the protective layer 251. In some embodiments, the protective layer 251 has a thickness in the range of 2 Å to 60 Å. In some embodiments, the protective layer 251 has a thickness in the range of 3 Å to 30 Å.

[0057] In one embodiment, the protective layer 251 is the product of a chemical reaction with the material of the thin layer 105 shown in the cross-sectional view 900 of Fig. 9. In some embodiments, the protective layer 251 is a high-resistivity compound of the newly sputtered electrode metal. In some embodiments, the protective layer 251 is formed by oxidizing the newly sputtered electrode metal. Oxygen may be removed by O 2 , O 3 , N 2O or the like. The oxygen source can be combined with one or more other gases, and the reagents can be formed into a plasma. Other gases can be Ar, He, H 2 or the like. Reactions other than oxidation may be used to convert the newly sputtered electrode metal into a high-resistivity compound. In one embodiment, the reaction gas comprises CO 2 and the protective layer 251 is an oxycarbide of the electrode metal

[0058] As shown by the cross-sectional view from 1900 by Fig. 19, a layer of spacer material 1101 may be formed over the structure shown by the cross-sectional view 1800 of Fig. 18. The spacer material 1101 may be silicon nitride. The compounds of the newly sputtered electrode metal in the protective layer 251 may be sufficiently stable that the newly sputtered electrode metal does not further react to form nitrides of the electrode metal during the process of forming the layer of spacer material 1101. The layer of spacer material 1101 may be etched to form spacers 115, as illustrated by the cross-sectional view 2000 of FIG. Fig. 20. The resulting structure can be further processed to produce a structure similar to that of the IC device 200 of Fig. 2 can correspond.

[0059] The cross-sectional views 2100 to 2300 from Fig. 21 to 23 show an alternative process sequence corresponding to the cross-sectional view 1000 of Fig. 10 or the cross-sectional view 1800 Fig. 18. As can be seen from the cross-sectional view 2100 of Fig. As shown in Figure 21, an anisotropic etching may be used to form the protective layer 301, which has the shape of a spacer, from the protective layer 251 or the combination of the thin layer 105 and the protective layer 117. A thickness of the protective layer 301 decreases from the lower electrode cones to the upper electrode 103. The etching process may be a dry etching of a type used to form spacers.

[0060] As shown in cross-sectional view 2200 Fig. 22 and the cross-sectional view 2300 from Fig. 23, the formation of the protective layer 301 may be followed by the deposition of the spacer material 1101 and the etching of the spacer material 1101 to form spacers 115. The resulting structure may be further processed to produce a structure similar to that of the IC 300 of Fig. 3. Although not clearly apparent from these illustrations, the etching that provides the protective layer 301 with a tapered thickness may increase the pitch of the spacers 115 and ultimately improve the filling between the MRAM cells 107.

[0061] Fig. 24 illustrates a flow diagram of a process 2400 according to some aspects of these teachings. The process 2400 may be used to create integrated circuit devices according to these teachings. While the process 2400 is described herein as a series of acts or events, it is to be understood that the illustrated ordering of such acts or events is not intended to be limiting. For example, some acts may occur in different orders and / or concurrently with other acts or events that are different from those illustrated and / or described herein. Furthermore, not all of the illustrated acts may be required to practice one or more aspects or embodiments of the description herein. Further, one or more of the acts depicted herein may be performed in one or more separate acts and / or phases.

[0062] Process 2400 begins with act 2401, front-end-of-line (FEOL) processing and formation of some first metal interconnect layers 108, 118, 135, and act 2403, deposition of etch stop layer 137, interface layer 139 and oxide layer 140, to create a structure such as that shown by cross-sectional view 400 of Fig. 4 is illustrated.

[0063] Process 2400 continues with act 2405, forming and patterning a mask 503, and act 2407, etching to form openings 501 in the etch stop layer 137, interface layer 139, and oxide layer 140, as shown by cross-sectional view 500 of Fig. 5. Action 2409 is the deposition of a layer of material 601 for filling openings 501 as illustrated by the cross-sectional view 600 of Fig. 6. Act 2411 is planarizing to remove the material layer 601 that lies outside the openings 501, and thereby forming the vias 127 as illustrated by the cross-sectional view 700 of Fig. 7. Material 601 and other metal layers may be formed by any suitable process. Suitable processes may include electroplating, electroless plating, sputtering, chemical vapor deposition (CVD), or the like.

[0064] Action 2413 is forming the MRAM cell stack 801 as shown by the cross-sectional view 800 of Fig. 8. The MRAM cell stack 815 may include a bottom electrode layer 801, a resistive switching layer 810, and a top electrode layer 811. The resistive switching layer 810 may be a metal tunnel junction layer. A metal tunnel junction layer may include the first ferromagnetic layer 803, the insulator layer 805, and the second ferromagnetic layer 809. Act 2415 is forming the photoresist mask 813.

[0065] Action 2417 is using the photoresist mask 813 to pattern the MRAM cell stack 815 to form the MRAM cells 107 as in Fig. 9. Patterning the MRAM cell stack 815 to form the MRAM cells 107 also forms the thin layer 105. The thin layer 105 includes metal from the bottom electrode layer 801 and / or the top electrode layer 811. Plasma used to etch the MRAM cell stack 815 may cause atoms of the metal to sputter and deposit on the sides 104 of the MRAM cells 107.

[0066] Action 2419 is the formation of the protective layer 117 as in Fig. 10, or the protective layer 251 as shown in Fig. 18. In some embodiments, act 2419 includes forming the protective layer 117 over the thin layer 105 to encapsulate the thin layer 105. In some embodiments, act 2419 includes converting the electrode metal within the thin layer 105 into a high-resistance compound of the electrode metal. In some embodiments, act 2419 forms the thin layer 105 into the protective layer 251.

[0067] Act 2421 is an optional step of performing a spacer etching on the protective layer 117, 251 to form a spacer-shaped protective layer 301 as in Fig. 21. The etching process may be an anisotropic dry etching, which may be a plasma etching.

[0068] Action 2423 is forming first sidewall spacers 115 as in Fig. 11 and Fig. 12, or alternatively as shown in Fig. 19 and Fig. 20, or as shown in Fig. 22 and Fig. 23. In some embodiments, the first sidewall spacers 115 are SiN, but in any case, the process of forming the protective layer 117, 251, 301 ensures that the newly sputtered electrode metal is not converted into nitrides of the electrode metal.

[0069] Act 2425 is forming second sidewall spacers 113. This may include depositing a layer of spacer material 1301, as in Fig. 13, followed by a spacer etching to form second sidewall spacers 113 as in Fig. 14 shown.

[0070] Action 2429 is the deposition of the dielectric filler layer 109 for filling the space between MRAM cells 107 as in Fig. 15. Act 2431 is the deposition of BARC 1501 over the dielectric filler layer 109 to form a planar top surface as in Fig. 15. Action 2433 is a non-selective etch-back process that covers the area as shown in Fig. 15. The non-selective etch-back process of Act 2433 can remove various material from the top of the device while leaving the surface nearly planar.

[0071] Act 2435 is a CMP process that again exposes the top electrodes 103 of the MRAM cells 107, as in Fig. 16. The CMP process may have low selectivity for the material of the upper electrodes 103.

[0072] Act 2439 is forming the etch stop layer 143 over the surface created by the CMP process of act 2435. Act 2441 is depositing the interlayer dielectric 145 over the etch stop layer 143. Act 2443 is depositing the metal interconnect layer 149 and vias 101 within the interlayer dielectric 145 as in Fig.17. Act 2445 is further additional processing to complete the BEOL processing and the formation of a device such as the IC device 100.

[0073] Some aspects of these teachings relate to an integrated circuit (IC) comprising a substrate and a resistive random access memory cell formed over the substrate. The resistive random access memory cell comprises a bottom electrode, a resistive switching layer, and a top electrode. The resistive switching layer has a side surface between the bottom electrode and the top electrode. One of the top electrode and the bottom electrode comprises an electrode metal. A spacer is formed over the side surface. According to these teachings, an amount of the electrode metal sufficient to form a thin layer is distributed over the side surface within a first layer between the side surface and the spacer. The first layer comprises an oxide, a carbide, an oxycarbide, an oxynitride, a carbonitride, or an oxycarbonitride.

[0074] Some aspects of this teaching relate to an integrated circuit (IC) comprising a substrate and an MRAM cell formed over the substrate. The MRAM cell includes a bottom electrode, a metal tunnel junction, and a top electrode. The metal tunnel junction has a side surface between the bottom electrode and the top electrode. A metal, which is also found in one of the top electrode or the bottom electrode, is found within a thin layer at the side surface. The thin layer has a lower conductivity than the metal tunnel junction.

[0075] Some aspects of this teaching relate to a method of manufacturing an integrated circuit (IC) device. The method includes forming a metallization layer over a semiconductor and forming an MRAM cell stack over the metallization layer. The MRAM cell stack includes a bottom electrode layer, a metal tunnel junction layer, and a top electrode layer. Either the bottom electrode layer or the top electrode layer includes an electrode metal. The MRAM cell stack is patterned to form an MRAM cell including a bottom electrode, a metal tunnel junction, and a top electrode. During the patterning process, a portion of the electrode metal is deposited on one side of the metal tunnel junction. A protective layer is formed over the side of the metal tunnel junction.The process of forming the protective layer leaves the electrode metal on the side surface in a form that offers lower conductivity than the metal tunnel junction. A spacer is formed over the protective layer.

Claims

[1] IC (100), comprising: a substrate (202); a resistive random access memory cell (107) formed over the substrate (202), the resistive random access memory cell (107) having a bottom electrode (125), a resistive switching layer (142), and an top electrode (103), the resistive switching layer (142) having a side surface (104) between the bottom electrode (125) and the top electrode (103), at least one of the top electrode (103) and the bottom electrode (125) comprising an electrode metal; and a side wall spacer (113, 115) formed over the side surface (104); wherein an amount of the electrode metal sufficient to form a thin layer (105) is distributed over the side surface (104) within a first layer (117, 251, 301) between the side surface (104) and the sidewall spacer (113, 115); and the first layer (117, 251, 301) contains an oxide, a carbide, an oxycarbide, an oxynitride, a carbonitride or an oxycarbonitride; wherein the electrode metal is distributed intermittently within the first layer (117, 251, 301) over the side surface (104) and is covered by the oxide, the carbide, the oxycarbide, the oxynitride, the carbonitride or the oxycarbonitride which is also present within the first layer (117, 251, 301). [2] The IC (100) of claim 1, wherein the electrode metal within the first layer (117, 251, 301) is present in compounds that are oxides, carbides, oxycarbides, oxynitrides, carbonitrides, or oxycarbonitrides of the electrode metal. [3] IC (100) according to one of the preceding claims, wherein the first layer (117, 251, 301) is thicker at the lower electrode (125) than at the upper electrode (103). [4] The IC (100) of any preceding claim, wherein the first layer (117, 251, 301) comprises an oxide of a different material than the electrode metal. [5] IC (100) according to one of the preceding claims, wherein the electrode metal is Ta and the first layer (117, 251, 301) comprises an oxide selected from the group consisting of SiO x , HfO x , ZrO x , TiO x and where x is selected. [6] The IC (100) of any preceding claim, wherein the sidewall spacer (113, 115) is silicon nitride. [7] The IC (100) of claim 6, further comprising a second spacer (113) formed over the sidewall spacer (113, 115). [8] IC (100) comprising: a substrate (202); an MRAM cell (107) formed over the substrate (202), the MRAM cell (107) comprising a bottom electrode (125), a metal tunnel junction (142), and a top electrode (103), the metal tunnel junction (142) having a side surface (104) between the bottom electrode (125) and the top electrode (103), one of the top electrode (103) and the bottom electrode (125) comprising an electrode metal; a thin layer (105) having one or more connections of the electrode metal on the side surface (104), the thin layer (105) having a lower conductivity than the metal tunnel junction (142); an oxide layer (117, 251, 301) between the side surface (104) and a sidewall spacer (113, 115) formed above the side surface (104); wherein the electrode metal is distributed intermittently within the oxide layer (117, 251, 301) over the side surface (104) and is covered by an oxide, a carbide, an oxycarbide, an oxynitride, a carbonitride or an oxycarbonitride which is also present within the oxide layer (117, 251, 301). [9] The IC (100) of claim 8, wherein the electrode metal in the thin layer (105) is present in compounds that are oxides, carbides, oxycarbides, oxynitrides, carbonitrides, or oxycarbonitrides of the electrode metal. [10] IC (100) according to claim 8 or 9, wherein: the metal tunnel junction (142) has a first ferromagnetic layer (803) and a second ferromagnetic layer (809) separated by a layer of the insulating material (805), and the one or more compounds of the electrode metal have a lower conductivity than the insulating material (805). [11] IC (100) according to one of the preceding claims 8 to 10, wherein the thin layer (105) is covered by the oxide layer (117, 251, 301). [12] IC (100) according to claim 11, wherein the oxide layer (117, 251, 301) is SiO x , HfO x , ZrO x , TiO x or WHERE x includes. [13] The IC (100) of any one of the preceding claims 8 to 12, wherein the thin layer (105) has a thickness that decreases along a direction from a bottom surface of the MRAM cell (107) to a top surface of the MRAM cell (107). [14] The IC (100) of any one of the preceding claims 8 to 13, further comprising a silicon nitride spacer (115) around the MRAM cell (107). [15] IC (100) according to one of the preceding claims 8 to 14, wherein: the MRAM cell (107) has a high resistance state and a low resistance state, and a bypass current through the thin layer (105) is 100 times or less of a current through the MRAM cell (107) when the MRAM cell (107) is in the low resistance state. [16] A method of manufacturing an integrated circuit device (100), comprising: Forming a metallization layer (135) over a semiconductor substrate (202); Forming an MRAM cell stack (815) over the metallization layer (135), the MRAM cell stack (815) comprising a bottom electrode layer (801), a metal tunnel junction layer (142), and a top electrode layer (811), at least one of the bottom electrode layer (801) and the top electrode layer (811) comprising an electrode metal; Structuring the MRAM cell stack (815) to form an MRAM cell (107) having a lower electrode (125), a metal tunnel junction (142), and an upper electrode (103), wherein a portion of the electrode metal is deposited on one side (104) of the metal tunnel junction (142) during the structuring of the MRAM cell stack (815); Forming a protective layer (117, 251, 301) over the side (104) of the metal tunnel junction (142), wherein a process of forming the protective layer (117, 251, 301) leaves the electrode metal on the side (104) of the metal tunnel junction (142) in a form that has a lower conductivity than the metal tunnel junction (142), wherein the electrode metal is intermittently distributed within the protective layer (117, 251, 301) over the side surface (104) and is covered by an oxide, a carbide, an oxycarbide, an oxynitride, a carbonitride, or an oxycarbonitride that is also present within the protective layer (117, 251, 301); and Forming a spacer (115) over the protective layer (117, 251, 301). [17] The method of claim 16, wherein forming the protective layer (117, 251, 301) comprises providing a reagent that reacts with the electrode metal in the layer of electrode metal to form the oxide, carbide, oxycarbide, oxynitride, carbonitride, or oxycarbonitride of the electrode metal. [18] The method of claim 16 or 17, wherein forming the protective layer (117, 251, 301) comprises depositing an oxide over the electrode metal on the side (104). [19] The method of any one of the preceding claims 16 to 18, wherein forming the protective layer (117, 251, 301) comprises depositing a compound of the electrode metal over the electrode metal on the side (104) of the metal tunnel junction (142). [20] The method of claim 19, further comprising: Performing an anisotropic etching to form a first spacer (115) from the protective layer (117, 251, 301); and Forming a second spacer (113) over the first spacer (115).

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