Method for the self-addressing of a bidirectional two-wire bus

Abstract

Procedure for assigning valid bus node addresses to bus nodes (SL1 to SLn) of a two-wire data bus system wherein the two-wire data bus system has a bus master (BM) and where the two-wire data bus system has n bus nodes (SL1 to SLn) with n being a positive integer greater than 1 and wherein the two-wire data bus has a first one-wire data bus (KMH, K1H, K2H to KnH, KTH) and wherein the two-wire data bus has a second one-wire data bus (KML, K1L, K2L to KnL, KTL) and where the bus master (BM) is a bus master high-side driver (I MH , T XMH , T XENMH ) exhibits and where the bus master (BM) is a bus master low-side driver (I ML , T XML , T XENML ) exhibits and wherein the bus master high-side driver (I MH , T XMH , T XENMH) can inject an electric current into the first single-wire data bus (KMH, K1H, K2H to KnH, KTH) at a first end (KMH) of the first single-wire data bus (KMH, K1H, K2H to KnH, KTH) and where the bus master low-side driver (I MH , T XMH , T XENMH ) can extract an electrical current from the second single-wire data bus (KML, K1L, K2L to KnL, KTL) at a first end (KML) of the second single-wire data bus (KML, K1L, K2L to KnL, KTL) and wherein the second end (KTH) of the first single-wire data bus (KMH, K1H, K2H to KnH, KTH) is terminated via a termination resistor (R TR ) is electrically connected to the second end (KTL) of the second single-wire data bus (KML, K1L, K2L to KnL, KTL) and where the two-wire data bus is subdivided into n+2 two-wire bus segments ([KMH, KML]; [K1H, K1L]; [K2H, K2L] to [KnH, KnL]; [KTH, KTL]) by the n bus nodes (SL1 to SLn) and wherein each two-wire data bus segment ([KjH, KjL] with j as an integer or j=“M” or j=“T”) of the two-wire data bus segments ([KMH, KML]; [K1H, K1L]; [K2H, K2L] to [KnH, KnL] ; [KTH, KTL]) comprises an associated first single-wire data bus segment (KjH) and an associated second single-wire data bus segment (KjL) and wherein the first single-wire data bus segments (KMH, K1H to KnH, KTH) form the first single-wire data bus (KMH, K1H, K2H to KnH, KTH) and wherein the second single-wire data bus segments (KML, K1L to KnL, KTL) form the second single-wire data bus (KML, K1L, K2L to KnL, KTL) and which divides the first single-wire data bus into n+2 sections (KHM, K1H to KnH, KTH) among others by the n bus nodes (SL1 to SLn) and which divides the second single-wire data bus into n+2 sections (KLM, K1L to KnL, KTL) among others by the n bus nodes (SL1 to SLn) and where each bus node (SLj) of the (n-1) bus nodes is upstream of a bus node following the master ((SL1) to [SL(n-1)]) up to the nth bus node (SLn) in the two-wire data bus, where here the index j stands for an integer between 1 and (n-1) inclusive, and where the bus master (BM) is positioned upstream of the first bus node (SL1) and where the nth bus node (SLn) is connected to the termination resistor (R) TR ) is upstream, characterized by, that each of the bus nodes (SLj) involved in the addressing procedure has means (RPCB_L_j) for recording the current from the second single-wire data bus section (K(j+1)L or KTL) downstream of this bus node and / or in the second single-wire data bus section (KjL or KML) upstream of this bus node and for determining an associated current measurement value and that each of the bus nodes (SLj) involved in the addressing procedure has means to detect a bus collision when it attempts to transmit simultaneously with a higher-priority bus node and that the bus protocol is designed in such a way, - that in the event of a bus collision, the date of exactly one of the bus junctions prevails and - that a bus node whose data has not been adopted detects this bus collision and aborts the transmission of its data, the procedure comprises the following steps: Step 1: The bus master (BM) begins an addressing cycle by signaling to all bus nodes (SL1 to SLn) that an addressing cycle is now taking place; Step 2: The bus nodes (SL1 to SLn) receive the signal from the bus master (BM) indicating that an addressing cycle is now taking place; Step 3: Using the high-side driver (I MH , T XMH , TXMENH ) of the bus master (BM) for injecting an addressing current, whose addressing current value lies within a specified addressing current interval, into the first single-wire data bus line (KMH, K1H to KnH, KTH); Step 4: Using the low-side driver (I ML , T XML , T XMENL ) of the bus master (BM) for extracting the addressing current from the second single-wire data bus line; Step 5: Extraction of a local bus node addressing stream from the second single-wire data bus line (KML, K1L to KnL, KTL) by each bus node participating in the addressing procedure and which does not have a valid bus node address, hereinafter referred to as the bus node in question; Step 6: Detection of the respective current value of the electric current through the second single-wire data bus (KLM, K1L to KnL, KTL) at the location of each relevant bus node (SLj) without a valid bus node address by the respective means (RPCB_L_j) of the relevant bus node (SLj) for detecting the current from the second single-wire data bus section (K(j+1)L) downstream of this relevant bus node (SLj) and / or in the second single-wire data bus section (KjL) upstream of this bus node (SU); Step 7: Generation of a respective provisional bus node address for each relevant bus node based on the respective current value determined by the respective relevant bus node (SLj) by a linear mapping of the current measurement value to the set of possible and / or allowed bus node addresses; Step 8: Transmission of a message comprising the provisional bus node address and the current measurement value to the bus master (BM) by each relevant bus node participating in the addressing procedure, each relevant bus node attempting to send its respective message in the event of bus collisions until it has been able to send its respective message to the bus master (BM) without bus collision or until another termination condition is met; Step 9: Analysis of the current values ​​received by the relevant bus nodes (SL1 to SLn) from the bus master (BM) in this way by the bus master (BM) and calculation of the sequence of the bus nodes (SL1 to SLn) along the two-wire data bus of the relevant bus nodes participating in the addressing procedure; Step 10: Assigning a valid bus node address to each relevant bus node participating in the addressing procedure, depending on the provisional bus node address; Step 11: Signaling to all relevant bus nodes (SL1 to SLn) that the assigned bus node address should be used and that the addressing procedure is complete, and termination of the addressing procedure by the bus nodes (SI1 to SLN) and the bus master (BM).

Description

Field of invention

[0001] The invention relates to a method for assigning valid bus node addresses to bus nodes (SL1 to SLn) of a two-wire data bus system. General Introduction

[0002] A method for assigning bus node addresses is known from DE 10 2018 104 852 A1. This method addresses the bus nodes of a serial, bidirectional, differential two-wire communication bus, comprising a bus master, a serial, bidirectional, differential two-wire communication bus radiating from the bus master, and several addressable bus nodes. The bus nodes are connected to the serial, bidirectional, differential two-wire communication bus. The serial, bidirectional, differential two-wire communication bus consists of a first single-wire bus and a second single-wire bus. In this method, each unaddressed bus node injects an addressing stream into at least one of the single-wire buses, hereinafter referred to as the addressing single-wire bus, for identification purposes.All other unaddressed bus nodes also feed an addressing current into the addressing single-wire bus. All addressing currents flow through the serial, bidirectional, differential two-wire communication bus towards the bus master (ECU). Each unaddressed bus node detects the current flowing through the addressing single-wire bus of the serial, bidirectional, differential two-wire communication bus. Only those unaddressed bus nodes that detect no current or only a current less than a predefined initial threshold are identified as unaddressed. An address is then assigned to the identified bus node as a valid bus node address. The aforementioned steps are performed without the most recently addressed bus node until all unaddressed bus nodes have been addressed.

[0003] One disadvantage of the method is that resistors have to be inserted into the single-wire data bus lines.

[0004] The main disadvantage, however, is that, according to the technical teaching of DE 10 2018 104 852 A1, special addressing current sources are required. This increases the costs. Furthermore, an analog-to-digital converter is necessary, which occupies a considerable amount of chip area.

[0005] German patent application DE 10 2016 125 290 A1 describes a method for initializing a two-wire data bus between a first sub-device, the bus master (BM), and at least two further sub-devices, the bus nodes (BS1, BS2, BS3). The two-wire data bus (b1, b2, b3) is divided into at least two two-wire data bus sections (b1, b2, b3) by the at least two bus nodes (BS1, BS2, BS3). The method begins with the bus master (BM) determining a new bus node address. This can be done, for example, by simply incrementing an internal value of the bus master (BM). The second step involves the bus master (BM) storing this bus node address in a bus node address register (BKADRn) of the respective bus node (BSn).The bus master (BM) and the relevant bus node (BSn) are connected to each other via one or more two-wire data bus sections (b1, b2, b3).

[0006] The publication DE 601 06 929 T2 refers to buses that use a wired AND protocol, and more precisely to methods and devices for connecting facilities or devices in a bus system with multiple bus masters.

[0007] The publication DE 10 2018 116 540 A1 discloses a signal-up transceiver for coupling with a signal-up connection of a bus of a communication system; and circuit technology for coupling with the signal-up connection of the bus and with a local power supply, wherein the circuit technology serves to switch from providing the local power supply to supply the slave device with power to providing bus power supplied by the signal-up connection of the bus to supply the slave device with power. Task

[0008] The proposal is therefore based on the task of creating a solution that does not have the above disadvantages of the prior art and offers further advantages.

[0009] This problem is solved by the methods according to claims 1 and 3. Solution to the task

[0010] The invention relates to a first method for assigning valid bus node addresses to bus nodes (SL1 to SLn) of a two-wire data bus system. The two-wire data bus system comprises a bus master (BM), n bus nodes (SL1 to SLn) where n is a positive integer greater than 1, a first single-wire data bus (KMH, K1H, K2H to KnH, KTH), and a second single-wire data bus (KML, K1L, K2L to KnL, KTL). The bus master (BM) comprises a bus master high-side driver (I MH , T XMH , T XENMH ) and a bus master low-side driver (I ML , T XML , T XENML The bus master high-side driver (I MH , T XMH , T XENMH ) can inject an electrical addressing current into the first single-wire data bus (KMH, K1H, K2H to KnH, KTH) at a first end (KMH) of the first single-wire data bus (KMH, K1H, K2H to KnH, KTH). Similarly, the bus master low-side driver (I) can MH , T XMH , T XENMH) draw an electrical current from the second single-wire data bus (KML, K1L, K2L to KnL, KTL) at a first end (KML) of the second single-wire data bus (KML, K1L, K2L to KnL, KTL). The second end (KTH) of the first single-wire data bus (KMH, K1H, K2H to KnH, KTH) is connected via a termination resistor (R). TRThe second end (KTL) of the second single-wire data bus (KML, K1L, K2L to KnL, KTL) is electrically connected. The two-wire data bus is subdivided into n+2 two-wire bus segments ([KMH, KML]; [K1H, K1L]; [K2H, K2L] to [KnH, KnL]; [KTH, KTL]) by the n bus nodes (SL1 to SLn). Each two-wire data bus segment ([KjH, KjL] where j is an integer or j="M" or j="T") of the two-wire data bus segments ([KMH, KML]; [K1H, K1L]; [K2H, K2L] to [KnH, KnL]; [KTH, KTL]) comprises an associated first single-wire data bus segment (KjH) and an associated second single-wire data bus segment (KjL). The first single-wire data bus segments (KMH, K1H to KnH, KTH) form the first single-wire data bus (KMH, K1H, K2H to KnH, KTH). The second single-wire data bus segments (KML, K1L to KnL, KTL) form the second single-wire data bus (KML, K1L, K2L to KnL, KTL). The first single-wire data bus is subdivided into n+2 segments (KHM, K1H to KnH, KTH) by, among other things, the n bus nodes (SL1 to SLn).The second single-wire data bus is divided into n+2 segments (KLM, K1L to KnL, KTL) by the n bus nodes (SL1 to SLn). Each bus node (SLj), which is the (n-1) bus node following the master ((SL1) to [SL(n-1)]), is, with the exception of the nth bus node (SLn), upstream of a subsequent bus node (SL(j+1)) in the two-wire data bus. Here, the index j represents an integer between 1 and (n-1) inclusive. The bus master (BM) is upstream of the first bus node (SL1). The nth bus node (SLn) is connected to the termination resistor (R). TR ) upstream.

[0011] The first method proposed here is characterized by the fact that each bus node (SLj) involved in the addressing procedure has means (RPCB_L_j) for detecting the current from the second single-wire data bus segment (K(j+1)L or KTL) downstream of this bus node and / or in the second single-wire data bus segment (KjL or KML) upstream of this bus node, and for determining a corresponding current measurement. Furthermore, each bus node (SLj) involved in the addressing procedure has means for detecting a bus collision if it attempts to transmit simultaneously with a higher-priority bus node. At the same time, the bus protocol is designed such that, in the event of a bus collision, the data of exactly one of the bus nodes prevails, and thus the message of this prevailing bus node reaches the bus master, while all other colliding bus nodes abort their transmission.A bus node whose data has not been adopted detects this bus collision and then aborts the transmission of its data. The procedure comprises the following steps: • Step 1: Start of an addressing cycle by signaling the bus master (BM) to all bus nodes (SL1 to SLn) that an addressing cycle is now taking place; • Step 2: The bus nodes (SL1 to SLn) receive the signal from the bus master (BM) indicating that an addressing cycle is now taking place; • Step 3: Using the high-side driver (I MH , T XMH , T XMENH ) of the bus master (BM) for injecting an addressing current, whose addressing current value lies within a specified addressing current interval, into the first single-wire data bus line (KMH, K1H to KnH, KTH); • Step 4: Using the low-side driver (I ML , T XML , T XMENL) of the bus master (BM) for extracting the addressing current from the second single-wire data bus line; • Step 5: Extraction of a local bus node addressing stream from the second single-wire data bus line (KML, K1L to KnL, KTL) by each bus node participating in the addressing procedure and which does not have a valid bus node address, hereinafter referred to as the bus node in question; • Step 6: Detection of the respective current value of the electric current through the second single-wire data bus (KLM, K1L to KnL, KTL) at the location of each relevant bus node (SLj) without a valid bus node address by the respective means (RPCB_L_j) of the relevant bus node (SLj) for detecting the current from the second single-wire data bus segment (K(j+1)L) downstream of this relevant bus node (SLj) and / or in the second single-wire data bus segment (KjL) upstream of this bus node (SLJ); • Step 7: Generation of a respective provisional bus node address of a respective relevant bus node based on the respective current value determined by the respective relevant bus node (SLj) by a linear mapping of the current measurement value to the set of possible and / or allowed bus node addresses; • Step 8: Transmission of a message comprising the provisional bus node address and the current measurement value to the bus master (BM) by each relevant bus node participating in the addressing procedure, each relevant bus node attempting to send its respective message in the event of bus collisions until it can send its respective message to the bus master (BM) without bus collision or until another termination condition is met; • Step 9: Analysis of the current values ​​received by the relevant bus nodes (SL1 to SLn) from the bus master (BM) in this way by the bus master (BM) and calculation of the sequence of the bus nodes (SL1 to SLn) along the two-wire data bus of the relevant bus nodes participating in the addressing procedure; • Step 10: Assignment of a valid bus node address to each relevant bus node participating in the addressing procedure, depending on the provisional bus node address; • Step 11: Signaling to all relevant bus nodes (SL1 to SLn) that the assigned bus node address should be used and that the addressing procedure is complete, and termination of the addressing procedure by the bus nodes (SL1 to SLn) and the bus master (BM).

[0012] The method according to the invention can be supplemented by preparatory steps. It is then a method with the following steps preceding step 1: • Step A: Signaling by the bus master to all or at least some of the bus nodes involved in the addressing procedure that their bus node addresses are invalid; • Step B: Marking the bus node address associated with the respective bus node as invalid by all bus nodes participating in the addressing procedure.

[0013] The invention also relates to a second method for assigning valid bus node addresses to the bus nodes (SL1 to SLn) of a two-wire data bus system. Here too, the two-wire data bus system comprises a bus master (BM), n bus nodes (SL1 to SLn) where n is a positive integer greater than 1, a first single-wire data bus (KMH, K1H to KnH, KTH), and a second single-wire data bus (KML, K1L to KnL, KTL). The bus master (BM) includes a bus master high-side driver (I). MH , T XMH , T XENMH ) and a bus master low-side driver (I ML , T XML , T XENML The bus master high-side driver (I MH , T XMH , T XENMH ) can inject an electrical current into the first single-wire data bus (KMH, K1H to KnH, KTH) at a first end (KMH) of the first single-wire data bus (KMH, K1H to KnH, KTH). The bus master low-side driver (I MH , T XMH , T XENMHThe second single-wire data bus (KML, K1L to KnL, KTL) can draw an electrical current from its first end (KML). The second end (KTH) of the first single-wire data bus (KMH, K1H to KnH, KTH) is typically terminated via a termination resistor (R). TRThe second end (KTL) of the second single-wire data bus (KML, K1L to KnL, KTL) is electrically connected. The two-wire data bus is subdivided into n+2 two-wire bus segments ([KMH, KML]; [K1H, K1L]; [K2H, K2L] to [KnH, KnL]; [KTH, KTL]) by the n bus nodes (SL1 to SLn). Each two-wire data bus segment ([KjH, KjL] where j is an integer or j="M" or j="T") of the two-wire data bus segments ([KMH, KML]; [K1H, K1L]; [K2H, K2L] to [KnH, KnL]; [KTH, KTL]) comprises an associated first single-wire data bus segment (KjH) and an associated second single-wire data bus segment (KjL). The first single-wire data bus segments (KMH, K1H to KnH, KTH) form the first single-wire data bus (KMH, K1H, K2H to KnH, KTH). The second single-wire data bus segments (KML, K1L to KnL, KTL) form the second single-wire data bus (KML, K1L, K2L to KnL, KTL). The first single-wire data bus is subdivided into n+2 segments (KHM, K1H to KnH, KTH) by, among other things, the n bus nodes (SL1 to SLn).The second single-wire data bus is divided into n+2 segments (KLM, K1L to KnL, KTL) by the n bus nodes (SL1 to SLn). Each bus node (SLj) of the bus nodes ((SL1) to [SL(n-1)]) following a bus node from the master (n-1) is, with the exception of the nth bus node (SLn), upstream of a subsequent bus node (SL(j+1)) in the two-wire data bus, where the index j represents an integer between 1 and (n-1) inclusive. The bus master is upstream of the first bus node (SL1). The nth bus node (SLn) is connected to the termination resistor (R). TR) upstream. This second method according to the invention is characterized in that each bus node (SLj) participating in the addressing method has means (RPCB_L_j) for detecting the current from the second single-wire data bus segment (K(j+1)L or KTL) downstream of this bus node and / or in the further single-wire data bus segment (KjL or KML) upstream of this bus node and for determining a corresponding current measurement value. Each bus node (SLj) participating in the addressing method according to the invention has means for detecting a bus collision if it attempts to transmit simultaneously with a higher-priority bus node. The bus protocol according to the invention is designed such that, in the event of a bus collision, the data of exactly one of the bus nodes prevails. A bus node whose data has not prevailed detects this bus collision and then terminates the transmission of its data.The second method according to the invention comprises the following steps: • Step 1: Start of an addressing cycle by signaling the bus master (BM) to all bus nodes (SL1 to SLn) that an addressing cycle is now taking place; • Step 2: The bus nodes (SL1 to SLn) receive the signal from the bus master (BM) indicating that an addressing cycle is now taking place; • Step 3: Using the high-side driver (I MH , T XMH , T XMENH ) of the bus master (BM) for injecting an addressing current, whose addressing current value lies within a specified addressing current interval, into the first single-wire data bus line (KMH, K1H to KnH, KTH); • Step 4: Using the low-side driver (I ML , T XML , T XMENL ) of the bus master (BM) for taking the addressing current from the second single-wire data bus line (KML, K1L to KnL, KTL); • Step 5: Extraction of a local bus node addressing stream from the second single-wire data bus line (KML, K1L to KnL, KTL) by each bus node participating in the addressing procedure and which does not have a valid bus node address, hereinafter referred to as the bus node in question; • Step 6: Detection of the respective current value of the electric current through the second single-wire data bus (KLM, K1L to KnL, KTL) at the location of each relevant bus node (SLj) without a valid bus node address by the respective means (RPCB_L_j) of the relevant bus node (SLj) for detecting the current from the second single-wire data bus segment (K(j+1)L) downstream of this relevant bus node (SLj) and / or in the second single-wire data bus segment (KjL) upstream of this bus node (SLJ); • Step 7: Comparison of the respective recorded current value of a respective relevant bus node (SLj) with a threshold value in each relevant bus node (SLj) participating in the addressing procedure and identification of the relevant bus node whose current value is above the threshold value as the last unaddressed bus node, hereinafter referred to as the last unaddressed bus node; • Step 8: Termination of power injections and withdrawals by the bus master (BM) and the bus nodes (SL1 to SLn); • Step 9: Transmission of a valid bus node address to be assigned to the last unaddressed bus node by the bus master (BM); • Step 10: The bus nodes concerned, which are not the last unaddressed bus node, do not accept the bus node address transmitted to the last unaddressed bus node, and the last unaddressed bus node accepts the bus node address transmitted to the last unaddressed bus node, thereby having a valid bus node address and no longer being a relevant bus node and thus no longer participating in further addressing cycles until further notice, thereby ending the addressing cycle; • Step 11: Start of the next addressing cycle and repeat steps 1 to 10 until all unaddressed bus nodes participating in the addressing procedure have received a valid bus node address or another termination condition has been met.

[0014] Here too, preparatory steps according to the invention are useful. The inventive method then typically comprises those steps according to the invention that precede step 1: • Step A: Signaling by the bus master to all or at least some of the bus nodes involved in the addressing procedure that their bus node addresses are invalid; • Step B: Marking the bus node address associated with the respective bus node as invalid by all bus nodes participating in the addressing procedure. Advantage

[0015] In the present proposal, the high-side and low-side switches already present in the bus system are supplemented by power sources that are already provided for safety reasons (I). MH , I ML , I SL1 , I SL2 , I SLN). This means that, unlike the technical teaching of DE 10 2018 104 852 A1, no additional effort is required. Furthermore, a fixed threshold exists because the current is limited by the external termination (R). TL , R TR ) is determined. In the technical teaching of DE 10 2018 104 852 A1, an analog-to-digital converter is necessary to correctly detect the bus current. This is not necessary here. The only remaining question to be clarified by the respective bus node is whether the termination current is flowing or whether one and a half times the prescribed termination current is flowing. During the development of the proposal, it became apparent that the parasitic resistances of single-wire data bus sections standardized within the data bus system are entirely sufficient for detecting the bus current. Description of the figures: Figure 1

[0016] Fig. Figure 1 shows the proposed, state-of-the-art data bus system with the components important for carrying out the addressing procedure. For example, it could be a CAN data bus system or another suitable two-wire data bus.

[0017] The data bus is intended to be used in the example of the Fig. 1. Can assume a dominant and a recessive data bus state according to the CAN standard.

[0018] For this purpose, the bus master (BM) has a high-side driver (I). MH , T XMH , T XMENH ), which can pull the first single-wire data bus to generate a dominant data bus state by injecting a current in the direction of the positive supply voltage. The high-side driver of the bus master (BM) has a high-side data transmit current source (I MH), which can limit the current into the first single-wire data bus. This current can only be injected if the high-side data transmission enable transistor (T) is switched on. XMENH ) of the high-side driver of the bus master (BM) is switched on, i.e., conducting, and if at the same time a dominant data bit is to be sent to the first single-wire data bus by the high-side data transmit transistor (T XMH The high-side driver of the bus master (BM) is also switched through, i.e., conducting. This high-side driver is already present in the example bus master CAN interface.

[0019] Furthermore, the busmaster (BM) has a low-side driver (I ML , T XML , T XMENL), which can pull the second single-wire data bus to generate a dominant data bus state by drawing current towards the negative supply voltage. The low-side driver of the bus master (BM) has a low-side data transmit current source (I ML ), which can limit the current drawn from the second single-wire data bus. This current can only be drawn if the low-side data transmission enable transistor (T) is switched on. XMENL ) of the low-side driver of the bus master (BM) is switched on, i.e., conducting, and if at the same time a dominant data bit is to be sent to the second single-wire data bus by the low-side data transmit transistor (T XML The low-side driver of the bus master (BM) is also switched on, i.e., conducting. This low-side driver is already present in the example bus master CAN interface.

[0020] The two-wire data bus is terminated by the termination resistors (R TL , RTR ), the bus master termination resistor (R TL ) and the termination resistance (R TR ) is brought into the recessive bus state when the transistors are off.

[0021] The first single-wire data bus exhibits a parasitic line resistance. This is due to the parasitic line resistances (R). PCB_H_M , R PCB_H_2 , R pCB_H_2 to R PCB_H_n ) shown.

[0022] The second single-wire data bus exhibits parasitic line resistance. This is due to the parasitic line resistances (R). PCB_L_M , R PCB_L_2 , R pCB_L_2 to R PCB_L_n ) shown.

[0023] The bus nodes (SL1, SL2 to SLn) also have an interface similar to that of the bus master (BM). The high-side drivers of the bus nodes (SL1, SL2 to SLn) are not shown for clarity.

[0024] The first bus node (SL1) has a low-side driver (I SL1, T XS1L , TX S1ENL ), which can pull the second single-wire data bus to generate a dominant data bus state by drawing a current towards the negative supply voltage. The low-side driver of the first bus node (SL1) has a low-side data transmit current source (I SL1 ), which can limit the current drawn from the second single-wire data bus. This current can only be drawn if the low-side data transmission enable transistor (T) is switched on. XS1ENL ) of the low-side driver of the first bus node (SL1) is switched on, i.e., conducting, and if at the same time a dominant data bit is to be sent to the second single-wire data bus by the low-side data transmit transistor (T XSlL The low-side driver of the first bus node (SL1) is also switched on, i.e., conducting. This low-side driver is already present in the example bus node CAN interface of the first bus node (SL1).

[0025] The second bus node (SL2) has a low-side driver (I SL2 , T XS2L , T XS2ENL ), which can pull the second one-wire data bus to generate a dominant data bus state by drawing a current towards the negative supply voltage. The low-side driver of the second bus node (SL2) has a low-side data transmit current source (I SL2 ), which can limit the current drawn from the second single-wire data bus. This current can only be drawn if the low-side data transmission enable transistor (T) is switched on. XS2ENL ) of the low-side driver of the second bus node (SL2) is switched on, i.e., conducting, and if at the same time a dominant data bit is to be sent to the second single-wire data bus by switching off the low-side data transmit transistor (T XS2LThe low-side driver of the second bus node (SL2) is also switched through, i.e., conducting. This low-side driver is already present in the example bus node CAN interface of the second bus node (SL2).

[0026] The nth bus node (SLn) has a low-side driver (I SLn , T XSnL , T XSnENL ), which can pull the second one-wire data bus to generate a dominant data bus state by drawing a current in the direction of the negative supply voltage. The low-side driver of the nth bus node (SLn) has a low-side data transmit current source (I). SLn ), which can limit the current drawn from the second single-wire data bus. This current can only be drawn if the low-side data transmission enable transistor (T) is switched on. XSnENL) of the low-side driver of the nth bus node (SLn) is switched on, i.e., conducting, and if at the same time a dominant data bit is to be sent to the second single-wire data bus by switching off the low-side data transmit transistor (T XSnL The low-side driver of the nth bus node (SLn) is also switched on, i.e., conducting. This low-side driver is already present in the example bus node CAN interface of the nth bus node (SLn). Figure 2

[0027] The Fig. 2 corresponds to the Fig. 1 with the difference that it is assumed an addressing cycle is being performed. After the bus master (BM) has signaled the execution of an addressing cycle, the bus master feeds its high-side driver (I) MH , T XMH , T XMENH ) introduces the addressing current into the first one-wire data bus. The resistance value of the bus master termination resistor (R) is preferred. TL) as close as possible to the resistance value of the termination resistor (R) TR ) selected. Therefore, the current value of the in Fig. The two indicated addressing streams are approximately half the magnitude of the high-side data transmit stream source (I). MH ). The magnitude of the current of the high-side data transmit current source (I MH The current of the bus master (BM) is significantly larger for addressing than the current of the low-side data transmit current source (I). ML ) of the bus master (BM). The other portion of this current is the high-side data transmit current source (I). MH The current of the bus master (BM) does not flow through the first and second single-wire data buses, but through the bus master termination resistor (R). TL The current in this configuration is determined by the magnitude of the current from the low-side data transmit current source (I). ML ) of the bus master (BM). Figures 3 to 5

[0028] The addressing process based on the second method is carried out using the Fig. Illustrated in 3 to 5. Figure 3

[0029] At the start of the process, all bus nodes (SL1 to SLn) activate their addressing mode based on a broadcast message from the bus master (BM) (message from the bus master (BM) to all bus nodes (SL1 to SLn) or a subset of the bus nodes). This occurs primarily because the bus nodes (SL1 to SLn) switch off their high-side drivers, so that these drivers essentially do not affect the state of the two-wire data bus and thus the first and second single-wire data buses. Furthermore, the bus nodes (SL1 to SLn) activate their low-side drivers. To do this, they switch on their respective low-side data transmission enable transistors (TL). XS1ENL , T XS2ENL , are XSnENL ). They also switch on their respective low-side data transmit transistor (T). xS1L , T xS2L , are XSnL) one. Each of these bus nodes (SL1 to SLn) regulates the current it draws from the second single-wire data bus via its respective low-side data transmit current source (I). SL1 , I SL2 , until I SLn ) to a typically predefined addressing stream value.

[0030] It is obvious that through the parasitic resistance (R) PCB_L_n ) the largest electric current flows at the nth bus node (SLn), while through the parasitic resistance (R) PCB_L_1 ) at the first bus node (SL1) the smallest electrical current flows in relation to the bus nodes (SL1 to SLN).

[0031] In the proposed method, each bus node (SL1 to SLn) is measured, for example, by measuring the voltage drop across a parasitic bus shunt resistor (R). PCB_L_1 , R PCB_L_2 to R PCB_L_n ) the bus flow towards the bus master.

[0032] Each bus node receives a voltage or current measurement that increases with increasing distance from the bus master (BM). Thus, the first bus node (SL1) receives a first voltage or current measurement that is smaller in magnitude than the second voltage or current measurement received by the second bus node (SL2). The second bus node (SL2) receives a second voltage or current measurement that is smaller in magnitude than the third voltage or current measurement received by the third bus node [SL3], which is not shown. This continues until the nth bus node, which receives an nth voltage or current measurement that is larger in magnitude than the (n-1)th voltage or current measurement received by the preceding (n-1)th bus node [SL(n-1)], which is not shown.

[0033] As proposed, there are now two possibilities for evaluating this information and for using this information to assign a valid bus node address to the bus nodes (SL1 to SLn).

[0034] The first method uses the recorded voltage and thus current measurements to decentralize the generation of individual and unique provisional bus node addresses, which allow initial unambiguous communication between each bus node and the bus master (BM).

[0035] In the second method, each bus node compares its voltage or current measurement with a threshold value and decides whether it is located at a predetermined end of the chain of unaddressed bus nodes. If so, it accepts a valid bus node address offered by the bus master via broadcast message. If not, it does not accept the valid bus node address offered by the bus master via broadcast message, but ignores it.

[0036] The first method will be explained first.

[0037] The voltage and current measurements are the same with the same dimensioning of the parasitic bus shunt resistors (R). PCB_L_1 , R PCB_L_2 to R PCB_L_n) in different voltage measurement intervals or different current measurement intervals, wherein these voltage measurement intervals or current measurement intervals preferably have the same absolute distance with respect to their interval boundaries. These voltage measurement intervals or current measurement intervals preferably do not overlap or only overlap minimally in order to ensure a unique assignment of exactly one voltage or current measurement value to exactly one of these intervals.

[0038] Each voltage measurement interval or current measurement interval can be assigned an individual index.

[0039] By using a bijective calculation rule common to all bus nodes, the indices of these voltage or current measurement intervals can now be mapped to the set of available bus node addresses.

[0040] This occurs at each bus node. As a result, each bus node receives an individual temporary bus node address, which differs from the temporary bus node addresses of the other bus nodes because different voltage or current values ​​were measured at those other bus nodes. The bus nodes then report their temporary bus node address to the bus master. Typically, this happens at the request of the bus master (BM). The bus master preferably sends this request as a broadcast message. Since all bus nodes (SL1 to SLn) then transmit simultaneously, bus collisions occur. It is therefore advantageous if the protocol of the two-wire data bus system begins a data message with a potentially identical preamble, followed directly by the bus address of the sender.When the bus nodes (SL1 to SLn) access the two-wire data bus with their provisional bus node addresses, a bus collision manifests itself for a bus node attempting to send data with a recessive bit value. This manifests as the node expecting a recessive data value on the two-wire data bus and observing a dominant bit value. The affected bus node then recognizes that it is not the highest-priority bus node with respect to its provisional bus node address and stops sending its message to the bus master, disabling its data bus drivers. Once the other bus node has completed sending its message to the bus master, the affected bus node attempts to send its message again until no further collisions occur and the message is successfully transmitted. The bus node then typically waits for a response from the bus master at its provisional bus node address.The bus master can declare the temporary address of the bus node valid, thereby making the temporary bus node address a valid bus node address, or transmit another valid bus node address to the bus node, which then replaces the temporary bus node address.

[0041] In this way, the bus master can then assign a valid bus node address to all bus nodes, which correlates with the physical position in the chain of bus nodes. Second procedure

[0042] In the second method, all bus nodes (SL1 to SLn) compare the magnitude of their voltage or current measurements with a threshold value. If the number of bus nodes is known, for example, after transmission to all bus nodes by the bus master via a broadcast message, then, given the addressing currents of the bus nodes and the bus master, the bus node can determine the magnitude of the bus current through the parasitic resistance of the bus node furthest from the bus master and thus calculate a threshold value that lies below this magnitude of the bus current and above the magnitude of the bus current through the parasitic resistance of the second-furthest bus node from the bus master.

[0043] If the bus node detected by the bus node is above this threshold, then the bus node is the last bus node in the chain without a valid bus node address, as seen by the bus master. After identifying itself as this bus node, it adopts a bus node address, which the bus master sends as a broadcast message after a predetermined time, as its valid bus node address. It then switches off its low-side driver and no longer draws any current from the second single-wire data bus. It remains in this state, for example, until the bus master signals the end of the addressing process to all bus nodes. The bus node then transitions to normal data bus operation with its valid bus node address.

[0044] However, if the bus node detected by the bus node is below this threshold, then the bus node is not the last bus node in the chain without a valid bus node address. After identifying itself as a bus node not at the end of this chain, it does not accept a bus node address that the bus master sends as a broadcast message after a fixed time as its valid bus node address and preferentially ignores this address. It preferentially participates in subsequent addressing cycles until it, too, has received a valid bus node address.

[0045] In Fig. Figure 4 shows that the nth bus node (SLn) has already received a valid bus node address. The second bus node (SL2) and the first bus node (SL1) have not yet received a valid bus node address.

[0046] In Fig. Figure 5 shows that the bus nodes from the second bus node (SL2) to the nth bus node (SLn) have already received a valid bus node address. The first bus node (SL1) has not yet received a valid bus node address. After the first bus node (SL1) has been addressed, i.e., when it has received a valid bus node address according to the procedure described above, the situation is again as follows. Fig. 2 one.

[0047] One variant of the procedure can be such that the allocation of bus node addresses does not go towards the bus master, but away from the bus master.

[0048] In this variant of the second method, all bus nodes (SL1 to SLn) also compare the magnitude of their voltage or current measurements with a threshold value. Given the addressing currents of the bus nodes and the bus master, the bus node can then calculate the magnitude of the bus current through the parasitic resistance of the bus node closest to the bus master, and thus a threshold value that lies above this magnitude of the bus current and below the magnitude of the bus current through the parasitic resistance of the second-closest bus node to the bus master.

[0049] If the bus node detected by the bus node is below this threshold, the bus node is the first in the chain of bus nodes without a valid address from the bus master's perspective. After identifying itself as this bus node, it adopts a bus node address, which the bus master sends as a broadcast message after a predetermined time, as its valid bus node address. It then switches off its low-side driver and no longer draws any power from the second single-wire data bus. This makes the bus node that was previously second closest to the bus master the bus node closest to the bus master. The bus node that was just addressed remains in this state with its drivers switched off, for example, until the bus master signals the end of the addressing process to all bus nodes. The bus node then transitions to normal data bus operation with its valid bus node address.

[0050] However, if the bus node detected by the bus node is above this threshold, then the bus node is not the nearest bus node to the bus master in the chain of bus nodes without a valid bus node address, as seen from the bus master's perspective. After identifying itself as a bus node not at the beginning of this chain, it does not accept a bus node address that the bus master sends as a broadcast message, for example, after a fixed time, as its valid bus node address and preferentially ignores this address. It preferentially participates in subsequent addressing cycles until it, too, has received a valid bus node address. Figure 6

[0051] Fig. 6 shows in addition to Fig. 1. Devices for detecting the bus current in the bus nodes (SL1 to SLn). Each bus node has a means, here by way of example an operational amplifier (ML1 to MLn), that detects the voltage drop across the aforementioned parasitic bus shunt resistance, which is preferably the conductor resistance of a section of the second single-wire data bus that is configured as uniformly as possible from bus node to bus node. Not shown is the processing with a preferably used analog-to-digital converter of the respective bus node, which digitizes the output signal (VL1 to VLn) of the respective operational amplifier (ML1 to MLn) and makes it available to a computer system of the respective bus node (not shown). There, for example, the threshold calculation and the comparison described above, or the calculation of the provisional bus node addresses, can then be performed. Figure 7

[0052] Fig. Figure 7 shows the wiring of a single j-th bus node (SLj) with j as an integer and 1 <j<n, wobei n die Zahl der Busknoten im Zweidrahtdatenbussystem ist. Die Zeichnung soll die Verschaltung für beliebige Busknoten (SLj) veranschaulichen. Dem j-ten Busknoten (SLj) ist ein (j-1)-ter Busknoten (SL(j-1)) auf der Bus-Master-Seite vorgeschaltet. Dem j-ten Busknoten (SLj) ist ein (j+1)-ter Busknoten (SL(j+1)) auf der Terminationswiderstandsseite nachgeschaltet.

[0053] Fig. Figure 7 shows an example section of three consecutive proposed bus nodes (SL(j-1) to SL(j+1)) from an example two-wire data bus system with n bus nodes (SL1 to SLn) and one bus master (BM). Here, n>2 is chosen for illustrative purposes to clarify the system. The bus master (BM) and the termination resistor (R) TRThe nodes (SL1) and (SL2) are not shown for clarity. Similarly, the other n-3 bus nodes (SL1 to SL2) are not shown for clarity. The reader is expected to imagine them. This proposal is not limited to bus systems with n > 2. To the j-th bus junction (SLj):

[0054] The j-th bus node (SLj) is connected to the (j-1)-th bus node (SL(j-1)) via the j-th single-wire data bus section (KjH) of the first single-wire data bus.

[0055] The j-th bus node (SLj) is connected to the (j-1)-th bus node (SL(j-1)) via the j-th single-wire data bus section (KjL) of the second single-wire data bus.

[0056] The j-th bus node again has a low-side driver (I SLj , T XSjL , T XSjENL ). The low-side driver (I SLj , T XSjL , T XSjENL ) of the j-th bus node (SLj) again preferably includes the associated low-side data transmit current source (I SLj) of the j-th bus node (SLj) and the low-side data transmission enable transistor (T XSjENL ) and the low-side data transmit transistor (T XSjL ). If the low-side data transmission enable transistor (T XSjENL ) and the low-side data transmission transistor (T XSjL ) are switched on, the low-side driver (I SLj , T XSjL , T XSjENL ) of the j-th bus node (SLj) the through the low-side data transmit current source (I SLjThe j-th bus node (SLj) is defined as the current from the second single-wire data bus, provided that a high-side driver of a bus node (SL1 to SLn) and / or the high-side driver of the bus master (BM) is switched on. The j-th bus node (SLj) here also includes, by way of example, a measuring device to detect the bus current in the second single-wire data bus in the vicinity of the j-th bus node (SLj), so that the address assignment procedure described above can be carried out with the involvement of this j-th bus node (SLj). This measuring device includes the parasitic j-th data bus resistance (R). pCB_L_j) in the second single-wire data bus between the j-th single-wire data bus section (KjL) of the second single-wire data bus at the j-th bus node (SLj) and the (j+1)-th single-wire data bus section (K(j+1)L) of the second single-wire data bus, which is still located at the j-th bus node (SLj). For the sake of simplicity, the parasitic data bus resistances in the first and second single-wire data buses between the bus nodes have been omitted from the figure, as they are not evaluated. This parasitic j-th data bus resistance (R) PCB_L_j ) in the second single-wire data bus, this is preferably a conductor track section in the area of ​​the j-th bus node, which is preferably manufactured in the same way in all bus nodes (SL1 to SLn), so that the voltage drops across these parasitic data bus resistances (R) PCB_L_1 to R PCB_L_n ) are essentially the same in the second single-wire data bus with the same current supply. In the example of the Fig. 7. A j-th operational amplifier (MLj) determines a j-th measurement result in the form of the j-th output signal (VLj) of the j-th operational amplifier (MLj). This measurement result can be used for the bus node address assignment procedure described above. Finally, the j-th bus node here includes the parasitic j-th data bus resistance (R). PCB_H_j ) in the first single-wire data bus between the j-th single-wire data bus section (KjH) of the first single-wire data bus in the j-th bus node (SLj) and the (j+1)-th single-wire data bus section (K(j+1)H) of the first single-wire data bus, which here is still located in the j-th bus node (SLj). Preferably, this is also configured in the same analogous way as the parasitic j-th data bus resistance (R). PCB_L_j) in the second single-wire data bus between the j-th single-wire data bus section (KjL) of the second single-wire data bus in the j-th bus node (SLj) and the (j+1)-th single-wire data bus section (K(j+1)L) of the second single-wire data bus is implemented as an identically constructed conductor track, resulting in a symmetry.

[0057] To the (j+1)th bus junction (SL(j+1)):

[0058] The (j+1)th bus node (SL(j+1)) is connected to the j-th bus node (SLj) via the (j+1)th single-wire data bus section (K(j+1)H) of the first single-wire data bus.

[0059] The (j+1)th bus node (SL(j+1)) is connected to the j-th bus node (SLj) via the (j+1)th single-wire data bus section (K(j+1)L) of the second single-wire data bus.

[0060] The (j+1)th bus node again has a low-side driver (I SL(j+1) , T XS(j+1)L , T XS(j+1)ENL ). The low-side driver (I SL(j+1) , T XS(j+1)L , T XS(j+1)ENL) of the (j+1)th bus node (SL(j+1)) again preferably includes the associated low-side data transmit current source (I SL(j+1) ) of the (j+1)th bus node (SL(j+1)) and the low-side data transmission enable transistor (T XS(j+1)ENL ) and the low-side data transmit transistor (T XS(j+1)L ). If the low-side data transmission enable transistor (T XS(j+1)ENL ) and the low-side data transmission transistor (T XS(j+1)L ) are switched on, the low-side driver (I SL(j+1) , T XS(j+1)L , T XS(j+1)ENL ) of the (j+1)th bus node (SL(j+1)) the through the low-side data transmit current source (l SL(j+1)The (j+1)th bus node (SL(j+1)) is defined as the current from the second single-wire data bus, provided that a high-side driver of a bus node (SL1 to SLn) and / or the high-side driver of the bus master (BM) is switched on. The (j+1)th bus node (SL(j+1)) here also includes, by way of example, a measuring device to detect the bus current in the second single-wire data bus in the vicinity of the (j+1)th bus node (SL(j+1)), so that the address assignment procedure described above can be carried out with the involvement of this (j+1)th bus node (SL(j+1)). This measuring device includes the parasitic (j+1)th data bus resistance (R). PCB_L_(j+1)) in the second single-wire data bus between the (j+1)th single-wire data bus section (K(j+1)L) of the second single-wire data bus at the (j+1)th bus node (SL(j+1)) and the (j+2)th single-wire data bus section (K(j+2)L) of the second single-wire data bus, which here is still located at the (j+1)th bus node (SL(j+1)). In the figure, the parasitic data bus resistances in the first single-wire data bus and in the second single-wire data bus between the bus nodes are omitted for the sake of simplicity, as they are not evaluated. This parasitic (j+1)th data bus resistance (R) PCB_L_(j+1) ) in the second single-wire data bus, this is preferably a conductor track section in the region of the (j+1)th bus node, which is preferably manufactured in the same way in all bus nodes (SL1 to SLn), so that the voltage drops across these parasitic data bus resistances (R) PCB_L_1 to R PCB_L_n ) are essentially the same in the second single-wire data bus with the same current supply. In the example of the Fig. 7. A (j+1)th operational amplifier (ML(j+1)) determines a (j+1)th measurement result in the form of the (j+1)th output signal (VL(j+1)) of the (j+1)th operational amplifier (ML(j+1)). This measurement result can be used for the procedure described above for assigning bus node addresses.

[0061] Finally, the (j+1)th bus node (SL(j+1)) here includes the parasitic (j+1)th data bus resistor (R) PCB_H_(j+1) ) in the first single-wire data bus between the (j+1)th single-wire data bus section (K(j+1)H) of the first single-wire data bus in the (j+1)th bus node (SL(j+1)) and the (j+2)th single-wire data bus section (K(j+2)H) of the first single-wire data bus, which here is still located in the (j+1)th bus node (SL(j+1)). This is also preferably implemented in the same analogous manner as the parasitic (j+1)th data bus resistance (R). PCB_L_(j+1)) in the second single-wire data bus between the (j+1)th single-wire data bus section (K(j+1)L) of the second single-wire data bus at the (j+1)th bus node (SL(j+1)) and the (j+2)th single-wire data bus section (K(j+2)L) of the second single-wire data bus is implemented as an identically constructed conductor segment, resulting in symmetry. The (j+1)th bus node is followed by a (j+2)th bus node [SL(j+2)] (not shown) or, for j=n, by the termination resistor (R). TR ) after. To the (j-1)th bus junction (SL(j-1)):

[0062] The (j-1)th bus node (SL(j-1)) is connected via the (j-1)th single-wire data bus section (K(j-1)H) of the first single-wire data bus to the (j-2)th bus node [SL(j-2)], which is no longer shown, or in the case of j=2 to the bus master (BM).

[0063] The (j-1)th bus node (SL(j-1)) is connected via the (j-1)th single-wire data bus section (K(j-1)L) of the second single-wire data bus to the (j-2)th bus node [SL(j-2)], which is no longer shown, or in the case of j=2 to the bus master (BM).

[0064] The (j-1)th bus node again has a low-side driver (I SL(j-1) , T XS(j-1)L , T XS(j-1)ENL ). The low-side driver (I SL(j-1) , T XS(j-1)L , T XS(j-1)ENL ) of the (j-1)th bus node (SL(j-1)) again preferably includes the associated low-side data transmit current source (I SL(j-1) ) of the (j-1)th bus node (SL(j-1)) and the low-side data transmission enable transistor (T XS(j-1)ENL ) and the low-side data transmit transistor (T XS(j-1)L ). If the low-side data transmission enable transistor (T XS(j-1)ENL ) and the low-side data transmission transistor (T XS(j-1)L ) are switched on, the low-side driver (I SL(j-1) , T XS(j-1)L , T XS(j-1)ENL) of the (j-1)th bus node (SL(j-1)) the through the low-side data transmit current source (I SL(j-1) The (j-1)th bus node (SL(j-1)) is defined as the current from the second single-wire data bus, provided that a high-side driver of a bus node (SL1 to SLn) and / or the high-side driver of the bus master (BM) is switched on. The (j-1)th bus node (SL(j-1)) here also includes, by way of example, a measuring device to detect the bus current in the second single-wire data bus in the vicinity of the (j-1)th bus node (SL(j-1)), so that the address assignment procedure described above can be carried out with the involvement of this (j-1)th bus node (SL(j-1)). This measuring device includes the parasitic (j-1)th data bus resistance (R). PCB_L_(j-1)) in the second single-wire data bus between the j-th single-wire data bus section (KjL) of the second single-wire data bus at the (j-1)-th bus node (SL(j-1)) and the j-th single-wire data bus section (KjL) of the second single-wire data bus, which here is still located at the (j-1)-th bus node (SL(j-1)). In the figure, the parasitic data bus resistances in the first single-wire data bus and in the second single-wire data bus between the bus nodes are omitted for the sake of simplicity, as they are not evaluated. This parasitic (j-1)-th data bus resistance (R) PCB_L_(j-1) ) in the second single-wire data bus, it is preferably a conductor track section in the region of the (j-1)th bus node, which is preferably manufactured in the same way in all bus nodes (SL1 to SLn), so that the voltage drops across these parasitic data bus resistances (R) PCB_L_1 to R PCB_L_n ) are essentially the same in the second single-wire data bus with the same current supply. In the example of the Fig.7. A (j-1)th operational amplifier (ML(j-1)) determines a (j-1)th measurement result in the form of the (j-1)th output signal (VL(j-1)) of the (j-1)th operational amplifier (ML(j-1)). This measurement result can be used for the bus node address assignment procedure described above. Finally, the (j-1)th bus node (SL(j-1)) here includes the parasitic (j-1)th data bus resistance (R). PCB_H_(j-1) ) in the first single-wire data bus between the (j-1)th single-wire data bus section (K(j-1)H) of the first single-wire data bus in the (j-1)th bus node (SL(j-1)) and the jth single-wire data bus section (KjH) of the first single-wire data bus, which here is still located in the (j-1)th bus node (SL(j-1)). Preferably, this is also configured in the same analogous manner as the parasitic (j-1)th data bus resistance (R). PCB_L_(j-1)In the second single-wire data bus, the connection between the (j-1)th single-wire data bus section (K(j-1)L) of the second single-wire data bus at the (j-1)th bus node (SL(j-1)) and the jth single-wire data bus section (KjL) of the second single-wire data bus is implemented as an identically constructed conductor track, resulting in symmetry. The (j-1)th bus node is preceded by a (j-2)th bus node [SL(j-2)] (not shown) or, for j=2, by the bus master (BM). Reference symbol list

[0065] Note: Labels in square brackets are not reference symbols in the sense that they would be found in the drawings. They are only there for better understanding. BM Bus-Master; I MHThe high-side data transmit current source of the bus master's (BM) high-side driver. In the dominant bus state, this current source limits the current that can be drawn from the bus master's (BM) high-side driver via the first single-wire data bus. This data transmit current source is proposed to be used to generate the addressing current. I ML Low-side data transmit current source of the bus master's (BM) low-side driver. In the dominant bus state, this current source limits the current that can be fed into the bus master's (BM) low-side driver via the second single-wire data bus. This data transmit current source is proposed for drawing the addressing current. I SL1Low-side data transmit current source of the low-side driver of the first bus node (SL1). In the dominant bus state, this current source limits the current that can be fed from the second single-wire data bus into the low-side driver of the first bus node (SL1). This data transmit current source is proposed to be used to divert portions of the addressing current to ground (GND) through the first bus node (SL1) when this first bus node (SL1) does not have a valid bus node address during the addressing process. I SL2Low-side data transmit current source of the low-side driver of the second bus node (SL2). In the dominant bus state, this current source limits the current that can be fed from the second single-wire data bus into the low-side driver of the second bus node (SL2). This data transmit current source is proposed to be used to divert portions of the addressing current to ground (GND) through the second bus node (SL2) when this second bus node (SL2) does not have a valid bus node address during the addressing process. I SL(j+1)Low-side data transmit current source of the low-side driver of the (j+1)th bus node (SL(j+1)). In the dominant bus state, this current source limits the current that can be injected from the second single-wire data bus into the low-side driver of the (j+1)th bus node (SL(j+1)). Proposedly, this data transmit current source is used to divert portions of the addressing current to ground (GND) through the (j+1)th bus node (SL(j+1)) when this (j+1)th bus node (SL(j+1)) does not have a valid bus node address during the addressing process. I SLjLow-side data transmit current source of the low-side driver of the j-th bus node (SLj). In the dominant bus state, this current source limits the current that can be fed from the second single-wire data bus into the low-side driver of the j-th bus node (SLj). Proposedly, this data transmit current source is used to divert portions of the addressing current to ground (GND) through the j-th bus node (SLj) when this j-th bus node (SLj) does not have a valid bus node address during the addressing process. I SL(j+1)Low-side data transmit current source of the low-side driver of the (j+1)th bus node (SL(j+1)). In the dominant bus state, this current source limits the current that can be injected from the second single-wire data bus into the low-side driver of the (j+1)th bus node (SL(j+1)). Proposedly, this data transmit current source is used to divert portions of the addressing current to ground (GND) through the (j+1)th bus node (SL(j+1)) when this (j+1)th bus node (SL(j+1)) does not have a valid bus node address during the addressing process. I SLnLow-side data transmit current source of the low-side driver of the nth bus node (SLn). In the dominant bus state, this current source limits the current that can be fed from the second single-wire data bus into the low-side driver of the nth bus node (SLn). Proposedly, this data transmit current source is used to divert portions of the addressing current to ground (GND) through the nth bus node (SL1) when this nth bus node (SLn) does not have a valid bus node address during the addressing process. I MSL Low-side data transmit current source of the bus master's (BM) low-side driver. In the dominant bus state, this current source limits the current that can be fed into the low-side driver from the second single-wire data bus. This data transmit current source is proposed to be used for deriving the addressing current against ground (GND). K1H first single-wire data bus section of the first single-wire data bus between the bus master (BM) and the first bus node (SL1); K1L is the first single-wire data bus section of the second single-wire data bus between the bus master (BM) and the first bus node (SL1); K2H second single-wire data bus section of the first single-wire data bus between the first bus node (SL1) and the second bus node (SL2); K2L second single-wire data bus section of the second single-wire data bus between the first bus node (SL1) and the second bus node (SL2); K3H third single-wire data bus section of the first single-wire data bus between the second bus node (SL2) and the third bus node [SL3] (not shown); K3L third single-wire data bus section of the second single-wire data bus between the second bus node (SL2) and the third bus node [SL3] (not shown); K(j-1)H (j-1)th single-wire data bus section of the first single-wire data bus between the (j-2)th bus node [SL(j-2)] not shown or the bus master (BM) in the case of j=1 and the (j-1)th bus node (SL(j-1)); K(j-1)L (j-1)th single-wire data bus section of the second single-wire data bus between the (j-2)th bus node [SL(j-2)] not shown or the bus master (BM) in the case of j=1 and the (j-1)th bus node (SL(j-1)); KjH j-th single-wire data bus section of the first single-wire data bus between the (j-1)-th bus node (SL(j-1)) and the j-th bus node (SLj); KjL j-th single-wire data bus section of the second single-wire data bus between the (j-1)-th bus node (SL(j-1)) and the j-th bus node (SLj); K(j+1)H (j+1)th single-wire data bus section of the first single-wire data bus between the j-th bus node (SLj) and the (j+1)-th bus node (SL(j+1)); K(j+1)L (j+1)th single-wire data bus section of the second single-wire data bus between the j-th bus node (SLj) and the (j+1)-th bus node (SL(j+1)); KnH nth single-wire data bus section of the first single-wire data bus between the not drawn (n-1)th bus node [SL(n-1)] and the nth bus node (SLn); KnL nth single-wire data bus section of the second single-wire data bus between the not drawn (n-1)th bus node [SL(n-1)] and the nth bus node (SLn); KMH is the first end of the first single-wire data bus of the two-wire data bus. This first end is typically located in the bus master (BM). KML is the first end of the second single-wire data bus of the two-wire data bus. This first end is typically located in the bus master (BM). KTH is the second end of the first single-wire data bus of the two-wire data bus. This first end is typically located at the end of the chain of bus nodes opposite the bus master (BM). The second end of the first single-wire data bus is preferably used to connect a first terminal of the termination resistor (R). TR ) used; KTL is the second end of the second single-wire data bus of the two-wire data bus. This first end is typically located at the end of the chain of bus nodes opposite the bus master (BM). The second end of the second single-wire data bus is preferably used to connect a second terminal of the termination resistor (R). TR ) used; ML1 first operational amplifier of the first bus node (SL1); ML2 second operational amplifier of the second bus node (SL2); ML(j-1) (j-1)th operational amplifier of the (j-1)th bus node (SL(j-1)); MLj j-th operational amplifier of the j-th bus node (SLj); ML(j+1) (j+1)th operational amplifier of the (j+1)th bus node (SL(j+1)); MLn nth operational amplifier of the nth bus node (SLn); n Number of bus nodes (SL1 to SLn) of the two-wire data bus system; RPCB_L_1 parasitic data bus resistance in the second single-wire data bus between the single-wire data bus section (K1L) of the second single-wire data bus in the first bus node (SL1) and the first single-wire data bus section (K2L) of the second single-wire data bus in the second bus node (SL2); RPCB_L_2 parasitic data bus resistance in the second single-wire data bus between the single-wire data bus section (K1L) of the second single-wire data bus in the second bus node (SL2) and the single-wire data bus section (K2L) of the second single-wire data bus in the third bus node [SL3] (not shown); R PCB_L_nparasitic data bus resistance in the second single-wire data bus between the single-wire data bus section (KnL) of the second single-wire data bus in the nth bus node (SLn) and the single-wire data bus section (KTL) of the second single-wire data bus at the second terminal (KTL) of the termination resistor (R) TR ); R PCB_L_(j-1) parasitic data bus resistance in the second single-wire data bus between the single-wire data bus section (K(j-1)L) of the second single-wire data bus in the (j-1)th bus node (SL(j-1)) and the j-th single-wire data bus section (KjL) of the second single-wire data bus in the j-th bus node (SLj); R PCB_L_j parasitic data bus resistance in the second single-wire data bus between the j-th single-wire data bus section (KjL) of the second single-wire data bus in the j-th bus node (SLj) and the (j+1)-th single-wire data bus section (K(j+1)L) of the second single-wire data bus in the (j+1)-th bus node (SL(j+1)); R PCB_L_(j+1)parasitic data bus resistance in the second single-wire data bus between the (j+1)th single-wire data bus section (K(j+1)L) of the second single-wire data bus in the (j+1)th bus node (SL(j+1)) and the (j+2)th single-wire data bus section (Kj(j+2)L) of the second single-wire data bus in the (j+2)th bus node [SL(j+2)] not shown; R PCB_L_M parasitic data bus resistance in the second single-wire data bus between the single-wire data bus section (KML) of the second single-wire data bus in the bus master and the first single-wire data bus section (K1L) of the second single-wire data bus in the first bus node (SL1); R PCB_H_1 parasitic data bus resistance in the first single-wire data bus between the single-wire data bus section (K1H) of the first single-wire data bus in the first bus node (SL1) and the first single-wire data bus section (K2H) of the first single-wire data bus in the second bus node (SL2); R PCB_H_2parasitic data bus resistance in the first single-wire data bus between the single-wire data bus section (K1H) of the first single-wire data bus in the second bus node (SL2) and the single-wire data bus section (K2H) of the first single-wire data bus in the third bus node [SL3] (no longer shown); R PCB_H_n parasitic data bus resistance in the first single-wire data bus between the single-wire data bus section (KnH) of the first single-wire data bus in the nth bus node (SLn) and the single-wire data bus section (KTH) of the first single-wire data bus at the first terminal (KTH) of the termination resistor (R) TR ); R PCB_H_M parasitic data bus resistance in the first single-wire data bus between the single-wire data bus section (KMH) of the first single-wire data bus in the bus master and the first single-wire data bus section (K1L) of the first single-wire data bus in the first bus node (SL1); R TL bus mater termination resistor; R TRTermination resistance; SL1 first bus junction; SL2 second bus junction; SL3 is the third bus junction, no longer shown in the drawings; SL(j-2) is the (j-2)th bus junction no longer shown in the drawings; SL(j-1) (j-1)-th bus junction; SLj j-ter bus junction; SL(j+1) (j+1)-th bus node; SL(j+2) is the (j+2)th bus junction no longer shown in the drawings; SL(n-1) is the (n-1)th bus junction no longer shown in the drawings; SLn nth bus junction; T XENH High-side data transmission enable transistor of the high-side driver of the bus master (BM). If this transistor is off, no data transmission is possible via the first single-wire data line in the dominant bus state. T XENLLow-side data transmission enable transistor of the low-side driver of the bus master (BM). If this transistor is off, no data transmission is possible via the second single-wire data line in the dominant bus state. T XMH High-side data transmit transistor of the high-side driver of the bus master (BM). In a CAN bus, the high-side driver pulls the first single-wire data bus to a high potential in the dominant bus state. T XML Low-side data transmit transistor of the bus master's (BM) low-side driver. In a CAN bus, the low-side driver pulls the second single-wire data bus to a low potential when the bus is dominant. T XS1L Low-side data transmit transistor of the low-side driver of the first bus node (SL1). In a CAN bus, the low-side driver can pull the second single-wire data bus to a low potential when the bus is dominant. T XS1ENLLow-side data transmission enable transistor of the low-side driver of the first bus node (SL1). If this transistor is off, data transmission via the second single-wire data line is not possible in the dominant bus state for the first bus node (SL1). T XS2L Low-side data transmit transistor of the low-side driver of the second bus node (SL2). In a CAN bus, the low-side driver can pull the second single-wire data bus to a low potential when the bus is dominant. T XS2ENL Low-side data transmission enable transistor of the low-side driver of the second bus node (SL2). If this transistor is off, data transmission via the second single-wire data line is not possible in the dominant bus state for the second bus node (SL2). T XS(j-1)LLow-side data transmit transistor of the low-side driver of the (j-1)th bus node (SL(j-1)). In a CAN bus, the low-side driver can pull the second single-wire data bus to a low potential in the dominant bus state. T XS(j-1)ENL Low-side data transmission enable transistor of the low-side driver of the (j-1)th bus node (SL(j-1)). If this transistor is off, data transmission over the second single-wire data line is not possible in the dominant bus state for the (j-1)th bus node (SL(j-1)). T XSjL Low-side data transmit transistor of the low-side driver of the j-th bus node (SLj). In a CAN bus, the low-side driver can pull the second single-wire data bus to a low potential in the dominant bus state. T XSjENLLow-side data transmission enable transistor of the low-side driver of the j-th bus node (SLj). If this transistor is off, data transmission via the second single-wire data line is not possible in the dominant bus state for the j-th bus node (SLj). T XS(j+1)L Low-side data transmit transistor of the low-side driver of the (j+1)th bus node (SL(j+1)). In a CAN bus, the low-side driver can pull the second single-wire data bus to a low potential in the dominant bus state. T XS(j+1)ENL Low-side data transmission enable transistor of the low-side driver of the (j+1)th bus node (SL(j+1)). If this transistor is off, data transmission via the second single-wire data line is not possible in the dominant bus state for the (j+1)th bus node (SL(j+1)). T XSnLLow-side data transmit transistor of the low-side driver of the nth bus node (SLn). In a CAN bus, the low-side driver can pull the second single-wire data bus to a low potential in the dominant bus state. T XSnENL Low-side data transmission enable transistor of the low-side driver of the nth bus node (SLn). If this transistor is off, data transmission via the second single-wire data line is not possible in the dominant bus state for the nth bus node (SLn). VL1 first output signal of the first operational amplifier (ML1) of the first bus node (SL1); VL2 second output signal of the second operational amplifier (ML2) of the second bus node (SL2); VL(j-1) (j-1)th output signal of the (j-1)th operational amplifier (ML(j-1)) of the (j-1)th bus node (SL(J-1)); VLj j-th output signal of the j-th operational amplifier (MLj) of the j-th bus node (SLj); VL(j+1) (j+1)th output signal of the (j+1)th operational amplifier (ML(j+1)) of the (j+1)th bus node (SL(j+1)); VLn nth output signal of the nth operational amplifier (MLn) of the nth bus node (SLn); List of cited works

[0066] DE 10 2018 104 852 A1, DE 10 2016 125 290 A1, DE 601 06 929 T2, DE 10 2018 116 540 A1

Claims

[1] Method for assigning valid bus node addresses to bus nodes (SL1 to SLn) of a two-wire data bus system wherein the two-wire data bus system has a bus master (BM) and where the two-wire data bus system has n bus nodes (SL1 to SLn) with n being a positive integer greater than 1 and wherein the two-wire data bus has a first one-wire data bus (KMH, K1H, K2H to KnH, KTH) and wherein the two-wire data bus has a second one-wire data bus (KML, K1L, K2L to KnL, KTL) and where the bus master (BM) is a bus master high-side driver (I MH , T XMH , T XENMH ) exhibits and where the bus master (BM) is a bus master low-side driver (I ML , T XML , T XENML ) exhibits and wherein the bus master high-side driver (I MH , T XMH , T XENMH) can inject an electric current into the first single-wire data bus (KMH, K1H, K2H to KnH, KTH) at a first end (KMH) of the first single-wire data bus (KMH, K1H, K2H to KnH, KTH) and where the bus master low-side driver (I MH , T XMH , T XENMH ) can extract an electrical current from the second single-wire data bus (KML, K1L, K2L to KnL, KTL) at a first end (KML) of the second single-wire data bus (KML, K1L, K2L to KnL, KTL) and wherein the second end (KTH) of the first single-wire data bus (KMH, K1H, K2H to KnH, KTH) is terminated via a termination resistor (R TR ) is electrically connected to the second end (KTL) of the second single-wire data bus (KML, K1L, K2L to KnL, KTL) and where the two-wire data bus is subdivided into n+2 two-wire bus segments ([KMH, KML]; [K1H, K1L]; [K2H, K2L] to [KnH, KnL]; [KTH, KTL]) by the n bus nodes (SL1 to SLn) and wherein each two-wire data bus segment ([KjH, KjL] with j as an integer or j=“M” or j=“T”) of the two-wire data bus segments ([KMH, KML]; [K1H, K1L]; [K2H, K2L] to [KnH, KnL] ; [KTH, KTL]) comprises an associated first single-wire data bus segment (KjH) and an associated second single-wire data bus segment (KjL) and wherein the first single-wire data bus segments (KMH, K1H to KnH, KTH) form the first single-wire data bus (KMH, K1H, K2H to KnH, KTH) and wherein the second single-wire data bus segments (KML, K1L to KnL, KTL) form the second single-wire data bus (KML, K1L, K2L to KnL, KTL) and which divides the first single-wire data bus into n+2 sections (KHM, K1H to KnH, KTH) among others by the n bus nodes (SL1 to SLn) and which divides the second single-wire data bus into n+2 sections (KLM, K1L to KnL, KTL) among others by the n bus nodes (SL1 to SLn) and where each bus node (SLj) of the (n-1) bus nodes is upstream of a bus node following the master ((SL1) to [SL(n-1)]) up to the nth bus node (SLn) in the two-wire data bus, where here the index j stands for an integer between 1 and (n-1) inclusive, and where the bus master (BM) is positioned upstream of the first bus node (SL1) and where the nth bus node (SLn) is connected to the termination resistor (R) TR ) is upstream, characterized by, that each of the bus nodes (SLj) involved in the addressing procedure has means (RPCB_L_j) for recording the current from the second single-wire data bus section (K(j+1)L or KTL) downstream of this bus node and / or in the second single-wire data bus section (KjL or KML) upstream of this bus node and for determining an associated current measurement value and that each of the bus nodes (SLj) involved in the addressing procedure has means to detect a bus collision when it attempts to transmit simultaneously with a higher-priority bus node and that the bus protocol is designed in such a way, - that in the event of a bus collision, the date of exactly one of the bus junctions prevails and - that a bus node whose data has not been adopted detects this bus collision and aborts the transmission of its data, the procedure comprises the following steps: Step 1: The bus master (BM) begins an addressing cycle by signaling to all bus nodes (SL1 to SLn) that an addressing cycle is now taking place; Step 2: The bus nodes (SL1 to SLn) receive the signal from the bus master (BM) indicating that an addressing cycle is now taking place; Step 3: Using the high-side driver (I MH , T XMH , T XMENH) of the bus master (BM) for injecting an addressing current, whose addressing current value lies within a specified addressing current interval, into the first single-wire data bus line (KMH, K1H to KnH, KTH); Step 4: Using the low-side driver (I ML , T XML , T XMENL ) of the bus master (BM) for extracting the addressing current from the second single-wire data bus line; Step 5: Extraction of a local bus node addressing stream from the second single-wire data bus line (KML, K1L to KnL, KTL) by each bus node participating in the addressing procedure and which does not have a valid bus node address, hereinafter referred to as the bus node in question; Step 6: Detection of the respective current value of the electric current through the second single-wire data bus (KLM, K1L to KnL, KTL) at the location of each relevant bus node (SLj) without a valid bus node address by the respective means (RPCB_L_j) of the relevant bus node (SLj) for detecting the current from the second single-wire data bus section (K(j+1)L) downstream of this relevant bus node (SLj) and / or in the second single-wire data bus section (KjL) upstream of this bus node (SU); Step 7: Generation of a respective provisional bus node address for each relevant bus node based on the respective current value determined by the respective relevant bus node (SLj) by a linear mapping of the current measurement value to the set of possible and / or allowed bus node addresses; Step 8: Transmission of a message comprising the provisional bus node address and the current measurement value to the bus master (BM) by each relevant bus node participating in the addressing procedure, each relevant bus node attempting to send its respective message in the event of bus collisions until it has been able to send its respective message to the bus master (BM) without bus collision or until another termination condition is met; Step 9: Analysis of the current values ​​received by the relevant bus nodes (SL1 to SLn) from the bus master (BM) in this way by the bus master (BM) and calculation of the sequence of the bus nodes (SL1 to SLn) along the two-wire data bus of the relevant bus nodes participating in the addressing procedure; Step 10: Assigning a valid bus node address to each relevant bus node participating in the addressing procedure, depending on the provisional bus node address; Step 11: Signaling to all relevant bus nodes (SL1 to SLn) that the assigned bus node address should be used and that the addressing procedure is complete, and termination of the addressing procedure by the bus nodes (SI1 to SLN) and the bus master (BM). [2] Method according to claim 1 comprising the steps preceding step 1: Step A: Signaling by the bus master to all or at least some of the bus nodes involved in the addressing procedure that their bus node addresses are invalid; Step B: Marking the bus node address associated with the respective bus node as invalid by all bus nodes participating in the addressing procedure. [3] Method for assigning valid bus node addresses to the bus nodes (SL1 to SLn) of a two-wire data bus system wherein the two-wire data bus system has a bus master (BM) and where the two-wire data bus system has n bus nodes (SL1 to SLn) with n being a positive integer greater than 1 and wherein the two-wire data bus has a first one-wire data bus (KMH, K1H to KnH, KTH) and wherein the two-wire data bus has a second one-wire data bus (KML, K1L to KnL, KTL) and where the bus master (BM) is a bus master high-side driver (I MH , T XMH , T XENMH ) exhibits and where the bus master (BM) is a bus master low-side driver (I ML , T XML , T XENML ) exhibits and where the bus master high-side driver (I MH , T XMH , T XENMH ) can inject an electric current into the first single-wire data bus (KMH, K1H to KnH, KTH) at a first end (KMH) of the first single-wire data bus (KMH, K1H to KnH, KTH) and where the bus master low-side driver (I MH , T XMH , T XENMH) can extract an electrical current from the second single-wire data bus (KML, K1L to KnL, KTL) at a first end (KML) of the second single-wire data bus (KML, K1L to KnL, KTL) and wherein the second end (KTH) of the first single-wire data bus (KMH, K1H to KnH, KTH) is terminated via a termination resistor (R TR ) is electrically connected to the second end (KTL) of the second single-wire data bus (KML, K1L to KnL, KTL) and where the two-wire data bus is subdivided into n+2 two-wire bus segments ([KMH, KML]; [K1H, K1L]; [K2H, K2L] to [KnH, KnL]; [KTH, KTL]) by the n bus nodes (SL1 to SLn) and wherein each two-wire data bus segment ([KjH, KjL] with j as an integer or j=“M” or j=“T”) of the two-wire data bus segments ([KMH, KML]; [K1H, K1L]; [K2H, K2L] to [KnH, KnL]; [KTH, KTL]) comprises an associated first single-wire data bus segment (KjH) and an associated second single-wire data bus segment (KjL) and wherein the first single-wire data bus segments (KMH, K1H to KnH, KTH) form the first single-wire data bus (KMH, K1H, K2H to KnH, KTH) and wherein the first single-wire data bus segments (KML, K1L to KnL, KTL) form the second single-wire data bus (KML, K1L, K2L to KnL, KTL) and which divides the first single-wire data bus into n+2 sections (KHM, K1H to KnH, KTH) among others by the n bus nodes (SL1 to SLn) and which divides the second single-wire data bus into n+2 sections (KLM, K1L to KnL, KTL) among others by the n bus nodes (SL1 to SLn) and where each bus node (SLj) of the (n-1) following a bus node from the master ((SL1) to [SL(n-1)]) upstream of a subsequent bus node (SL(j+1)) in the two-wire data bus, except for the nth bus node (SLn), is upstream of a downstream bus node (SL(j+1)), where here the index j stands for an integer between 1 and (n-1) inclusive, and where the bus master is positioned upstream of the first bus node (SL1) and where the nth bus node (SLn) is connected to the termination resistor (R) TR ) is upstream, characterized by, that each of the bus nodes (SLj) involved in the addressing procedure has means (RPCB_L_j) for recording the current from the second single-wire data bus section (K(j+1)L or KTL) downstream of this bus node and / or in the second single-wire data bus section (KjL or KML) upstream of this bus node and for determining an associated current measurement value and that each of the bus nodes (SLj) involved in the addressing procedure has means to detect a bus collision when it attempts to transmit simultaneously with a higher-priority bus node and that the bus protocol is designed in such a way, - that in the event of a bus collision, the date of exactly one of the bus junctions prevails and - that a bus node whose data has not been adopted detects this bus collision and aborts the transmission of its data, the procedure comprises the following steps: Step 1: The bus master (BM) begins an addressing cycle by signaling to all bus nodes (SL1 to SLn) that an addressing cycle is now taking place; Step 2: The bus nodes (SL1 to SLn) receive the signal from the bus master (BM) indicating that an addressing cycle is now taking place; Step 3: Using the high-side driver (I MH , T XMH , T XMENH ) of the bus master (BM) for injecting an addressing current, whose addressing current value lies within a specified addressing current interval, into the first single-wire data bus line (KMH, K1H to KnH, KTH); Step 4: Using the low-side driver (I ML , T XML , T XMENL) of the bus master (BM) for taking the addressing current from the second single-wire data bus line (KML, K1L to KnL, KTL); Step 5: Extraction of a local bus node addressing stream from the second single-wire data bus line (KML, K1L to KnL, KTL) by each bus node participating in the addressing procedure and which does not have a valid bus node address, hereinafter referred to as the bus node in question; Step 6: Detection of the respective current value of the electrical current through the second single-wire data bus (KLM, K1L to KnL, KTL) at the location of each relevant bus node (SLj) without a valid bus node address by the respective means (RPCB_L_j) of the relevant bus node (SLj) for detecting the current from the second single-wire data bus segment (K(j+1)L) downstream of this relevant bus node (SLj) and / or in the second single-wire data bus segment (KjL) upstream of this bus node (SU); Step 7: Comparison of the respective detected current value of a respective relevant bus node (SLj) with a threshold value in each relevant bus node (SLj) participating in the addressing procedure and identification of the relevant bus node whose current value is above the threshold value as the last unaddressed bus node, hereinafter referred to as the last unaddressed bus node; Step 8: Termination of power injections and withdrawals by the bus master (BM) and the bus nodes (SL1 to SLn); Step 9: Transmission of a valid bus node address to be assigned to the last unaddressed bus node by the bus master (BM); Step 10: The bus nodes concerned, which are not the last unaddressed bus node, do not accept the bus node address transmitted to the last unaddressed bus node, and the last unaddressed bus node accepts the bus node address transmitted to the last unaddressed bus node, thereby having a valid bus node address and no longer being a relevant bus node and thus no longer participating in further addressing cycles until further notice, thereby ending the addressing cycle; Step 11: Start of the next addressing cycle and repeat steps 1 to 10 until all unaddressed bus nodes participating in the addressing process have received a valid bus node address or another termination condition has been met. [4] Method according to claim 3 comprising the steps preceding step 1: Step A: Signaling by the bus master to all or at least some of the bus nodes involved in the addressing procedure that their bus node addresses are invalid; Step B: Marking the bus node address associated with the respective bus node as invalid by all bus nodes participating in the addressing procedure.

Images