METHOD FOR MANUFACTURING AN IMAGE SENSOR DEVICE

Abstract

Procedure with the following steps: Forming a dielectric layer (408) over a first surface of a semiconductor layer (202), the dielectric layer (408) having a conductive structure (412); Creating an opening (600) extending from a second surface of the semiconductor layer (202) to the first surface of the semiconductor layer to expose a portion of the dielectric layer (408), the second surface of the semiconductor layer being opposite the first surface of the semiconductor layer; forming a buffer oxide layer (700) to cover the opening (600), a portion of a first surface of the buffer oxide layer contacting the exposed portion of the dielectric layer (408); Creating, according to a structurable layer (800), one or more recesses (900) in the buffer oxide layer (700) extending from a second surface of the buffer oxide layer partially through the buffer oxide layer, the second surface of the buffer oxide layer being opposite the first surface of the buffer oxide layer; Removing the structurable layer (800); Enlarging the one or more recesses (900) through the buffer oxide layer (700) and a portion of the dielectric layer (408) based on the one or more recesses (900) to expose respective portions of the conductive structure (412); and Filling the one or more recesses (900) with a conductive material to form one or more pad structures (1200) configured to make an electrical connection with the conductive structure (412).

Description

BackgroundThe present invention relates generally to image sensor devices and, more particularly, to methods of making the same.Semiconductor image sensors are used for sensing incident visible or non-visible radiation, such as visible light, infrared light, and the like. CMOS (Complementary Metal Oxide Semiconductor) and CCD (Charge Coupled Device) image sensors are used in various applications, such as digital photographs, mobile phones, tablets, glasses, etc. These devices use an array of pixels that absorb (e.g., sample) the incident radiation and convert it into electrical signals. A backlighted (BSI) image sensor device is an example of image sensor devices. These BSI image sensor devices are operable to detect light from their back side.With regard to the prior art, reference is made to DE 10 2019 116 605 A1, DE 10 2019 114 944 A1, U.S. Pat. No. 2017 / 0 207 182 A1 and U.S. Pat. No. 2016 / 0 365 378 A1.The invention provides methods according to claims 1, 12 and 20. Embodiments are set forth in the dependent claims.Brief Description of the DrawingsAspects of the present invention can best be understood from the following detailed description taken in conjunction with the accompanying drawings. It should be noted that, in accordance with common practice in the industry, various elements are not drawn to scale. Rather, for clarity of discussion, the dimensions of the various elements may be arbitrarily increased or decreased.FIGS. 1A and 1B show a flow diagram of an example method of manufacturing an image sensor device, in accordance with some embodiments.FIGS. 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, and 14 show cross-sectional views of an example image sensor device at various stages of manufacturing the method of FIGS. 1A and 1B, in accordance with some embodiments. FIG. 15 is a top view of the example image sensor device shown in FIGS. 2-14, in accordance with some embodiments.Detailed DescriptionThe following description provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements will be described below to simplify the present invention. For example, the formation of a first element over or on a second element in the description below may include embodiments in which the first and second elements are formed in direct contact, and may also include embodiments in which additional elements may be formed between the first and second elements such that the first and second elements are not in direct contact. Moreover, in the present invention, reference numerals and / or letters may be repeated in the various examples. This repetition is for convenience and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.Moreover, spatially relative terms such as "lower", "lower", "lower(r)" / "lower", "higher", "upper(r)" / "upper" and the like may be used herein to easily describe the relationship of an element or structure to one or more other elements or structures depicted in the figures. The spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or in another orientation) and the spatially relative descriptors used herein may also be interpreted accordingly.The terms "about" and "substantially" may indicate a value of a given quantity that varies within 5% of the value (e.g., by ±1%, ±2%, ±3%, ±4%, ±5% of the value).Generally, a backside illuminated (BSI) image sensor device includes a semiconductor substrate (e.g., a silicon substrate) having pixels or radiation sensor regions fabricated therein. The terms "radiation sensor regions" and "pixels" used herein may be used interchangeably. A BSI image sensor device may include a pixel array disposed in the semiconductor substrate. The pixel array is vertically arranged with respect to a multilevel metallization layer (e.g., one or more interconnect structures) formed on a first surface of the semiconductor substrate. The first surface of the semiconductor substrate is referred to herein as a "front side" or "front surface" of the semiconductor substrate. The pixel array extends into the semiconductor substrate and is configured to receive radiation from a second surface of the semiconductor substrate that is opposite the front side of the semiconductor substrate. This second surface of the semiconductor substrate that receives the radiation (and that faces the front side of the semiconductor substrate) is referred to herein as a "back side" or "back surface" of the semiconductor substrate.The pixels in the semiconductor substrate are electrically insulated with isolation structures such as deep trench isolation (DTI) structures. Respective grating structures that enable optical isolation between adjacent pixels are aligned with the aforementioned isolation structures (and fabricated on the back side of the semiconductor substrate). Adjacent lattice structures together form cells. In addition, the cells together form a composite grid structure configured to receive color filter material. Based on the above description, the compound lattice structure is formed on the back surface of the semiconductor substrate.The color filter material may be disposed between adjacent grid structures to produce color filters. The color filter material may be selected such that light having a desired wavelength passes through the color filter material while light having other wavelengths is absorbed by the color filter material. For example, a green light filter material that receives unfiltered natural light would transmit the green light portion (wavelengths from about 495 nm to about 570 nm) through the filter, but it would absorb all other wavelengths. The color filters are aligned with respective pixels to provide filtered light to corresponding pixels.Components of the image sensor device (e.g., pixels, transistors, capacitors, memory structures, other chips attached to the image sensor device, etc.) may be electrically connected to external devices (e.g., an external circuit) via line connectors attached to pad structures fabricated on the back side of the semiconductor substrate. To achieve this, the pad structures of a BSI image sensor device physically extend from the back side of the semiconductor substrate to its front side and electrically connect to the multilevel metallization layer of the image sensor. Therefore, the multilevel metallization layer of the BSI image sensor device that establishes an electrical signal connection with the BSI image sensor device may be electrically connected to an external device or circuit via the pad structures. The pad structures may be disposed at the periphery of the BSI image sensor device around the pixels or the radiation sensor areas.In existing technologies for forming the pad structure in a BSI image sensor device, an opening extending at least from the back side to the front side of its semiconductor substrate has to be created, and subsequently a relatively thick patternable layer, e.g. a photoresist (PR) layer, is filled into the opening to define a structure of the pad structure. In certain applications of the BSI image sensor, a thickness of the semiconductor substrate should be kept relatively large. For example, in the case where the BSI image sensor is configured to absorb near infrared radiation, the semiconductor substrate typically has a thickness of about 2 μm to about 8 μm. And to ensure that no undesired charges are stored in certain areas of the BSI image sensor device, one or more high-k dielectric layers are normally formed on the back side of the semiconductor substrate. Accordingly, a thickness of the structureable layer may be significantly increased, e.g. up to 10 μm.However, such a thick structureable layer may cause various problems during subsequent processes. For example, unwanted polymers (or PR residues) may remain along sidewalls of the opening after the structureable layer is removed. For efficiently removing the patternable layer, an etching process using an oxygen-based plasma may be used. Although the structureable layer may be thoroughly removed, such an oxygen-based plasma etching process may damage the underlying metallization layers. For example, during the removal of the structureable layer using the oxygen-based plasma, one of the metallization layers (e.g. the lowermost metallization layer) may be exposed. The oxygen-based plasma may react with a barrier layer (e.g., a TaN layer) enclosing the metallization layer, such that air bubbles may form on a surface of the metallization layer. These air bubbles may disadvantageously facilitate penetration of etchants and / or acids into a connection structure of the metallization layer in a later process, so that the connection structure may be damaged. Therefore, the existing technologies for manufacturing a BSI image sensor device are not yet fully satisfactory.The present invention provides various embodiments for methods of manufacturing a BSI image sensor device to avoid these problems. For example, various embodiments of the method disclosed herein include using a 1E2P (1E2P) process to first partially etch a buffer oxide layer using a patterned layer to create one or more recesses and then etch through the one or more recesses to expose an underlying metallization layer. Prior to exposing the metallization layer, the patternable layer defining the recesses (and later the pad structures to be connected to the metallization layer) has been removed. In other words, the metallization layer is protected, for example, by the buffer oxide layer against damage during the removal of the structureable layer. Therefore, the compromise which the existing technologies enter into can be advantageously eliminated, so that the structureable layer can be removed thoroughly and no (potential) damage occurs to the metallization layer.FIGS. 1A and 1B collectively illustrate a flowchart of a method 100 of manufacturing a BSI image sensor device, in accordance with one or more embodiments of the present invention. It should be appreciated that method 100 is merely an example and is not intended to limit the present invention. Accordingly, it should be appreciated that additional steps may be provided before, during, and after the method 100 of FIGS. 1A and 1B, and that some additional steps may only be briefly described herein. In some embodiments, steps of the method 100 may be associated with cross-sectional views of a BSI image sensor device at various fabrication stages shown in FIGS. 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, respectively, and discussed in further detail below.In a brief overview, the method 100 begins with a step 102 of manufacturing a number of pixels (or radiation sensor areas) over a front side of a semiconductor substrate. The method 100 proceeds to a step 104 of forming one or more isolation regions over the front side. The method 100 proceeds with a step 106 of forming a device layer and one or more metallization layers over the front side. The method 100 proceeds to a step 108 for turning over the semiconductor substrate. The method 100 proceeds to a step 110 of creating an opening from a back side of the semiconductor substrate. The method 100 proceeds to a step 112 of forming a buffer oxide layer. The method 100 proceeds with a step 114 for producing a structureable layer. The method 100 proceeds to a step 116 of creating one or more recesses. The method 100 proceeds to a step 118 for removing the structureable layer. The method 100 proceeds to a step 120 of enlarging the one or more recesses. The method 100 proceeds with a step 122 of depositing a conductive material to form one or more pad structures. The method 100 proceeds with a step 124 of depositing a dielectric layer over the one or more pad structures. The method 100 proceeds to a step 126 of exposing respective portions of the one or more pad structures.As set forth above, FIGS. 2-14 each show, in cross-sectional view, a portion of a BSI image sensor device 200 at various stages of manufacture of the method 100 of FIG. 1. FIGS. 2-14 are simplified for a better understanding of the principles of the present invention. Although FIGS. 2-14 show the BSI image sensor device 200, it should be understood that the BSI image sensor device 200 may include a number of other components, such as inductors, fuses, capacitors, inductors, etc., which are not shown in these figures for clarity of illustration.Corresponding to step 102 of FIG. 1A, FIG. 2 shows a cross-sectional view of a BSI image sensor device 200 having a number of pixels 204A, 204B, and 204C formed over a front side 202F of a semiconductor substrate (or layer) 202 at one of the various fabrication stages. Opposite the front side 202F (e.g. along the z-axis), the semiconductor substrate 202 has a back side 202B from which the BSI image sensor device 200 receives incident radiation.The semiconductor substrate 202 may be a solid semiconductor wafer or an upper layer of a semiconductor-on-insulator (SOI) wafer having a thickness of greater than about 6 μm (e.g., about 6.15 μm, about 6.30 μm, about 6.50 μm, or about 6.70 μm). The semiconductor substrate 202 may include, for example, a semiconductor material such as silicon or germanium, a compound semiconductor, an alloy semiconductor, another suitable semiconductor material, and / or a combination thereof. In addition, the semiconductor substrate 202 may be an epitaxial material that is strained to improve performance and / or doped with n-type dopants, p-type dopants, or a combination thereof. In various embodiments, the semiconductor substrate 202 may include combinations of p- and n-doped regions.The pixels 204A to 204C are formed in a portion of the semiconductor substrate 202, referred to herein as a pixel region 203A. Although three pixels 204A- 204C are shown in FIG. 3 and subsequent cross-sectional views, it should be appreciated that the BSI image sensor device 200 may have any desired number of pixels, which is within the scope of the present invention. In some embodiments, the pixel region 203A is a central region of the semiconductor substrate 202. The pixel region 203A may correspond to a region where a pixel array is generated in the BSI image sensor device 200, for example, as shown in the plan view of FIG. 15.Pixels 204A- 204C are each configured to scan electromagnetic radiation, such as near infrared light. By way of example, and not limitation, pixels 204A- 204C each include a pinned layer photodiode, a photogate, a reset transistor, a source follower transistor, a transfer transistor, another suitable structure, and / or combinations thereof. In addition, pixels 204A- 204C may be occasionally referred to as "radiation detection devices" or "light sensors.". In some embodiments, pixels 204A- 204C are formed by doping semiconductor substrate 202 from front side 202F. The doping process may include doping the semiconductor substrate 202 with, for example, a p-dopant such as boron or an n-dopant such as phosphorus or arsenic. In some embodiments, pixels 204A- 204C are formed using a dopant diffusion process and / or an ion implantation process.In some embodiments, the semiconductor substrate 202 includes a pad region 203B adjacent to the pixel region 203A. In the pad region 203B, one or more pad structures may be formed. The pad structures may be disposed at a periphery of the semiconductor substrate 202 so as to enclose the pixel region 203A. For example, the pad region 203B corresponds to a region where one or more pad arrays are formed in the BSI image sensor device 200, as shown in the plan view of FIG. 15.Corresponding to step 104 of FIG. 1A, FIG. 3 shows a cross-sectional view of a BSI image sensor device 200 having one or more isolation regions 302 and 304 formed over the front side 202F at one of the various fabrication stages. In some embodiments, the isolation region 302 formed in the pad region 203B of the semiconductor substrate 202 may facilitate the formation of the one or more pad structures. In some embodiments, one or more isolation regions 304 may be formed in the pixel region 203A before, simultaneously with, or after forming the isolation region 302 in the pad region 203B. These isolation regions 304 may separate pixels 204A- 204C from each other. By way of example, and not limitation, isolation regions 302 and 304 may be formed over respective portions of front side 202F.In some embodiments, the isolation regions 302 and 304 may be formed by performing at least some of the following processes: forming a patternable layer, e.g., a photoresist (PR) layer having a structure defining respective positions of the isolation regions 302 and 304 in the semiconductor substrate 202; etching (e.g., dry etching) the semiconductor substrate 202 using the patternable layer as an etch mask to form recesses; removing (e.g., wet etching) the patternable layer; depositing one or more layers including, but not limited to, silicon oxide, undoped silicate glass (USG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), polyethyloxazoline (PEOX), fluorosilicate glass (FSG), a low-k dielectric material (e.g., having a k value less than about 3.9), or combinations thereof as a protective layer to fill the recesses; and planarizing, e.g., chemical mechanical polishing (CMP), the protective layer.Corresponding to step 106 of FIG. 1A, FIG. 4 shows a cross-sectional view of a BSI image sensor device 200 having a device layer 400 and one or more metallization layers 410 at one of the various fabrication stages. The device layer 400 and the metallization layers 410 may be sequentially formed on the front side 202F of the semiconductor substrate 202, in some embodiments. The device layer 400 may be in contact with a certain portion of the front side 202F, for example.The device layer 400 may include one or more semiconductor devices 404 (e.g. field effect transistors) formed according to a chip layout on the front side 202F of the semiconductor substrate 202. The device layer 400 may also include other elements or structures, such as doped regions, dummy regions, epitaxial layers, capacitor structures, resistors, etc. These other elements or structures of the device layer 400 are not shown in FIG. 4 for simplicity. In some embodiments, the BSI image sensor device 200 includes vertical conductive structures 406 (e.g., vias) that electrically connect the semiconductor devices 404 and other elements of the device layer 400 to upper metallization layers. The conductive structures 406 may form part of a MOL (middle of the line) wiring network. An etch stop layer (ESL) 402, the semiconductor devices 404 and the conductive structures 406 may be embedded in or covered by a corresponding dielectric layer 408. In some embodiments, device layer 400 further includes a nitride layer 402, which is used as an etch stop layer in a later etch step during the formation of the pad structures. In some embodiments, the ESL 402 is fabricated around the semiconductor devices 404 but not between the semiconductor devices 404 and the semiconductor substrate 202.Metallization layers 410 may include one or more metallization layers, such as metallization layers 410A, 410B, 410C, and 410D, as shown in FIG. 4. It should be appreciated that the BSI image sensor device 200 may include any desired number of metallization layers, which is within the scope of the present invention. In some embodiments, metallization layer 410A is a first metallization layer (sometimes referred to as an M1 layer) and metallization layer 410D is an upper metallization layer (sometimes referred to as an upper metal (TM) layer. The metallization layers 410 may form part of a Back End of Line (BEOL) wiring network. Metallization layers 410 (e.g., 410A- 410D) may each include one or more lateral conductive structures 412 (e.g., lines) embedded in a corresponding dielectric layer 414. In some embodiments, the corresponding dielectric layer and the lines embedded therein may be collectively referred to as a metallization layer. Across different metallization layers 410, one or more vertical conductive structures 416 (e.g., vias) may be extended by a corresponding dielectric layer 418 to electrically connect adjacent metallization layers along the z-axis. The lines 412 and the vias 416 made of, for example, copper may sometimes be referred to as copper interconnect structures. In some embodiments, the copper lines 412 and the copper vias 416 may each be surrounded by a (diffusion) barrier layer. The barrier layer may comprise a material selected from the group consisting of tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), titanium tungsten (TiW), and titanium (Ti). In some embodiments, this barrier layer may occasionally be referred to as a portion of the corresponding metallization layer.The dielectric layers 408, 414, and 418 may electrically separate the elements and / or structures therein. In some embodiments, each of the dielectric layers 408, 414, and 418 is an ILD (Inter-Layer Dielectric) or an IMD (Inter-Metal Dielectric) layer. Such an ILD or IMD layer includes, for example, silicon oxide, USG, BPSG, a low-k dielectric (e.g., having a dielectric constant of less than 3.9), or a stack of dielectrics, such as a low-k dielectric and another dielectric, namely (I) a low-k dielectric (e.g., carbon-doped silicon oxide) and nitrogen-doped silicon carbide; (II) a low-k dielectric (e.g., carbon-doped silicon oxide) and oxygen-doped silicon carbide; (III) a low-k dielectric (e.g., carbon-doped silicon oxide) with silicon nitride; or (IV) a low-k dielectric (e.g. carbon-doped silicon oxide) with silicon oxide.In some further embodiments, the device layer 400 and / or metallization layers 410 may be formed on a separate semiconductor substrate (e.g., different from the semiconductor substrate 202) and subsequently attached to the front side 202F of the semiconductor substrate 202.In certain applications of the BSI image sensor device 200, an application specific integrated circuit (ASIC) and / or a silicon-on-chip (SoC) 420 may be attached to the upper metallization layer 410D. This structure may be sometimes referred to as a three-dimensional (3D) stack or a 3D integrated circuit. Here, one or more bonding structures 422 may be used for electrically and mechanically bonding the ASIC / SoC 420 to the upper metallization layer 410D. The ASIC / SoC 420 may provide functionality to the BSI image sensor device 200 or may control functions of the BSI image sensor device 200. In some embodiments, the ASIC / SoC 420 includes metallization layers, semiconductor devices, or memory devices, or may be a stack of chips, such as memory chips, CPU (main processor) chips, other functional chips (e.g., RF chips), or combinations thereof.In some embodiments, the fabrication of the BSI image sensor device 200 may proceed with fabricating further structures in or on the semiconductor substrate 202 from the back side 202B. For this reason, the partially-fabricated BSI image sensor device 200 may be rotated (turned) 180° about the x-axis, as shown in FIG. 6, which also corresponds to step 108 of FIG. 1A.After turning the semiconductor substrate 202, one or more isolation regions 504 are formed in alignment with the isolation regions 304 to further isolate the pixels 204A- 204C in the pixel region 203A. The isolation regions 504 may include one or more dielectric materials and form, for example, deep trench isolation (DTI) structures. The isolation regions 504 may be formed by etching the semiconductor substrate 202 to create respective trenches between pixels 204A- 204C. The trenches may then be filled with one or more dielectric materials. Although not shown in FIG. 5, after forming the isolation regions 504, one or more high-k dielectric layers (having a dielectric constant of more than 3.9) may optionally be formed over the isolation regions 504. The high-k dielectric layers may each include, for example, a material selected from the group consisting of Ta 2 O 5, HfO 2 and Al 2 O 3 and combinations thereof. These high-k dielectric layers may be configured to scatter the charges stored in the BSI image sensor device 200.In some embodiments, the dielectric layers (e.g., comprising the dielectric layers forming the isolation regions 504, and the one or more optional high-k dielectric layers) may cover the pixel region 203A and the pad region 203B of the semiconductor substrate 202. Prior to forming the isolation regions 504 on the back side 202B, the semiconductor substrate 202 may be thinned to a desired thickness T 1. By way of example, and not limitation, the thickness T 1 may be about 2 μm to about 6 μm, depending on the use of the BSI image sensor device 200. Thinning the semiconductor substrate 202 may be performed using a planarization process (e.g., a CMP process), an etch back process (e.g., a dry etch process), another thinning process (e.g., grinding), or a combination thereof. Thinning the semiconductor substrate 202 may facilitate forming the isolation regions 504 and later forming the one or more pad structures.After forming the isolation regions 504 (and optional high-k dielectric layers) on the backside 202B, a passivation layer 506 may be deposited over the backside 202B, as shown in FIG. 5. The passivation layer 506 may be a dielectric layer, such as silicon oxide, silicon nitride, or a combination thereof. In some embodiments, the passivation layer 506 is a protective layer or a hard mask (HM) layer that is grown or deposited on the pixel region 203A and the pad region 203B.Corresponding to step 110 of FIG. 1A, FIG. 6 shows a cross-sectional view of a BSI image sensor device 200 having an opening 600 at one of the various stages of fabrication. The opening 600 is formed in the pad region 203B to expose a portion of the dielectric layer 408. As shown, the opening 600 may extend through at least the passivation layer 506, the one or more dielectric layers of the isolation regions 504, the semiconductor substrate 202, the isolation region 302, and the ESL 402. In the example where the thinned semiconductor substrate 202 has a thickness T 1 of about 6 μm, the opening 600 may be characterized by a depth T 2 substantially greater than 6 μm.The opening 600 may be formed by performing at least some of the following processes: forming a patternable layer (e.g., a photoresist layer) 602 over the passivation layer 506; patterning the patternable layer 602 in the pixel region 203A to expose a portion of the passivation layer 506 that is aligned with the isolation region 302; etching (e.g., with one or more dry etching processes) the passivation layer 506, the one or more dielectric layers of the isolation regions 504, the semiconductor substrate 202, the isolation region 302, and the ESL 402 to expose a portion of the dielectric layer 408; and removing the patternable layer 602. In particular, one or more different etching gases can be used for the dry etching processes. For example, the material (e.g., silicon) of the semiconductor substrate 202 may be etched with a first dry etching process using a gas mixture of chlorine (Cl 2) and HBr terminating on the isolation region 302. In some embodiments, in this first dry etching process, about 200 Å to 300 Å of material is etched away from the isolation region 302 before the etching process is terminated. Next, a second dry etch process, e.g., using tetrafluoromethane (CF 4)- gas, removes the isolation region 302, ending the second dry etch process on the ESL 402. Then, with a third dry over etch process, e.g., using octafluorocyclobutane (C 4 F 8)- gas, the ESL 402 is removed to expose the dielectric layer 408 of the device layer 400, as shown in FIG. 6. In other words, the one or more etching processes may be terminated when at least a portion of the dielectric layer 408 of the device layer 400 in the pad region 203B has been exposed through the opening 600.Corresponding to step 112 of FIG. 1A, FIG. 7 shows a cross-sectional view of a BSI image sensor device 200 having a buffer oxide layer 700 at one of the various fabrication stages. After removing the structureable layer 602 (FIG. 6 ), the buffer oxide layer 700 may be conformally deposited to occupy the opening 600 (e.g., to extend across a bottom and sidewalls of the opening 600) and to cover the exposed surface of the dielectric layer 408 and the passivation layer 506, as shown in FIG. 7. In some embodiments, the buffer oxide layer 700 is a silicon oxide dielectric, such as PEOX, having a thickness of about 100 nm to about 700 nm. In some other embodiments, the buffer oxide layer 700 comprises a material selected from the group consisting of USG, PSG, BPSG, FSG, low-k dielectric material, and combinations thereof.Corresponding to step 114 of FIG. 1A, FIG. 8 shows a cross-sectional view of a BSI image sensor device 200 having a patternable layer (e.g., a photoresist layer) 800 having a pattern 802 in the opening 600 at one of the various fabrication stages. In some embodiments, the structure 802 may be used to form one or more structures in the opening 600, which will be discussed in more detail below. The patternable layer 800 may be formed as follows: depositing (e.g., by spin coating) a photoresist protection layer over the buffer oxide layer 700; and patterning the photoresist protection layer to create the pattern (one or more openings) 802 in the opening 600 exposing one or more portions of a surface 700A of the buffer oxide layer 700. In order to fill the opening 600 characterized by a relatively large depth T 2( e.g. of more than 6 μm), in some embodiments at least the portion of the photoresist protection layer in the opening 600 has to be formed with a thickness substantially greater than 6 μm and e.g. about 8 μm to 10 μm. Therefore, the structure 802 may be characterized by a thickness T 3 that is about 8 μm to 10 μm.Corresponding to step 116 of FIG. 1A, FIG. 9 shows a cross-sectional view of a BSI image sensor device 200 having one or more recesses 900 at one of the various stages of fabrication. In some embodiments, the recesses 900 are formed by performing one or more dry etching processes (e.g., using CF 4- gas) to remove top portions of the buffer oxide layer 700 in the opening 600, using the structureable layer 800 as an etch mask. In other words, the buffer oxide layer 700 is partially etched to create the recesses 900 that are aligned with the structure 802. Because only the upper portions of the buffer oxide layer 700 exposed by the structure 802 are removed in the opening 600, the surface 700A in the opening 600 may be characterized as a non-coplanar surface.Corresponding to step 118 of FIG. 1A, FIG. 10 shows a cross-sectional view of a BSI image sensor device 200 in which the structureable layer 800 is removed at one of the various fabrication stages. Since, in some embodiments, the structurable layer 800 is characterized by a relatively large thickness, the structurable layer 800 may be removed by performing a peeling process 1000 using an oxygen-based plasma, wherein the oxygen plasma is generated using an oxygen source in a plasma system. It should be appreciated that various other stripping processes (e.g., using other gas sources) may also be used, which is within the scope of the present invention. In some embodiments, the removal of the structureable layer 800 (step 118) may be in situ with the formation of the one or more recesses 900 (step 116). Therefore, the BSI image sensor device 200 can be placed in the same chamber for steps 116 and 118. In some other embodiments, the removal of the structureable layer 800 (step 118) may be ex situwith the formation of the one or more recesses 900 (step 116). Therefore, the BSI image sensor device 200 can be placed in different chambers, respectively, for steps 116 and 118.In the existing technologies, the metallization layer to be connected to pad structures to be subsequently produced has normally been exposed before removing a corresponding structureable layer. Thus, during removal of the structureable layer (e.g., using an oxygen-based plasma lift-off process), a barrier layer (e.g., a TaN layer) enclosing the metallization layer may react with the oxygen to oxidize the barrier layer, thereby creating air bubbles over a surface of the barrier layer. These air bubbles are reacted with etching gases (e.g., fluoride-based gases) used in later processes, where the etching gases may disadvantageously permeate the barrier layer, exposing the metallization layer in some of the subsequent processes. As a result, the metallization layer located thereunder may be damaged, as a result of which the probability of electromigration in such a damaged metallization layer and / or in corresponding connection interfaces significantly increases. In contrast, despite the removal of the structureable layer 800 using the oxygen plasma, the metallization layers 410 (e.g., in particular the line 412 in the metallization layer 410A to be connected to pad structures to be subsequently formed) are not exposed. Rather, the metallization layers 410 are protected against the oxygen plasma at least by the buffer oxide layer 700. Thus, with the fabrication method disclosed herein (e.g., 100), the relatively thick structurable layer used to form pad structures may be thoroughly removed while the underlying metallization layer remains intact.Corresponding to step 120 of FIG. 1B, FIG. 11 shows a cross-sectional view of a BSI image sensor device 200 in which the recesses 900 are further enlarged at one of the various stages of fabrication. In some embodiments, due to the partially etched recesses 900 (FIG. 10 ), one or more dry etching processes may be performed on the buffer oxide layer 700, the ESL 402, and the dielectric layer 408 to enlarge the recesses 900 to expose respective portions of the line 412 of the metallization layer 410A. For example, with a first dry etching process, e.g., using CF 4- gas, the portions of the buffer oxide layer 700 directly below the recesses 900 are removed, the first dry etching process ending on the ESL 402. Then, with a second dry over etch process, e.g., using C 4 F 8- gas, the ESL 402 is removed to expose the dielectric layer 408 of the device layer 400. A third dry etching process, e.g., using CF 4- gas, removes the portions of the dielectric layer 408 that have been exposed from the recesses 900, and the third dry etching process ends on the line 412.Corresponding to step 122 of FIG. 1BA, FIG. 12 shows a cross-sectional view of a BSI image sensor device 200 having one or more pad structures 1200 at one of the various stages of fabrication. In some embodiments, a metal layer may be deposited in the opening 600 and subsequently patterned to form the pad structure 1200. The structuring of the metal layer can be effected, for example, with one or more lithographic processes followed by one or more etching processes. In some embodiments, the pad structure 1200 includes a metal alloy, for example aluminum-copper (AlCu). However, this is not limiting, and other suitable metals or metal alloys may also be used to form the pad structure 1200.Corresponding to step 124 of FIG. 1B, FIG. 13 shows a cross-sectional view of a BSI image sensor device 200 having a dielectric layer 1300 at one of the various stages of fabrication. In some embodiments, the dielectric layer 1300 (e.g., a USG layer or other oxide) is deposited on the pad structure 1200. A top surface of the dielectric layer 1300 may be inwardly curved ("dished") with a CMP process, in which deposited amounts of the dielectric layer 1300 on the buffer oxide layer 700 are polished and removed.Corresponding to step 126 of FIG. 1B, FIG. 14 shows a cross-sectional view of a BSI image sensor device 200 having an opening 1400 extending through the dielectric layer 1300 at one of the various stages of fabrication. In some embodiments, the dielectric layer 1300 is patterned to form the opening 1400 to expose a portion of the pad structure 1200. By way of example and not limitation, a lead connector, solder ball, and / or bump, not shown in FIG. 14, may be fabricated in opening 1400. In some embodiments, such a connector structure electrically connects the line 412 of the metallization layer 410A to one or more external components via the pad structure 1200.In FIG. 15, a plan view of the BSI image sensor device 200 viewed from the back surface 202B of the semiconductor substrate 202 is shown. FIGS. 2 to 14 correspond to sectional views of the BSI image sensor device 200 taken along the line A-A'. As shown, the BSI image sensor device 200 may include other pixels and pad structures substantially similar to pixels 204A- 204C and pad structure 1200, respectively. In various embodiments, these pixels may form a pixel array 1502 laterally surrounded by one or more pad arrays 1504 each having one or more of the pad structures 1200.In one aspect of the present invention, a method of manufacturing an image sensor device is disclosed. The method includes forming a dielectric layer over a first surface of a semiconductor layer. The dielectric layer has a conductive structure. The method further includes creating an opening extending from a second surface of the semiconductor layer to the first surface to expose a portion of the dielectric layer. The second surface of the semiconductor layer is opposite to the first surface of the semiconductor layer. The method further includes forming a buffer oxide layer occupying the opening, wherein a portion of a first surface of the buffer oxide layer contacts the exposed portion of the dielectric layer. The method further comprises creating, corresponding to a structureable layer, one or more recesses in the buffer oxide layer extending partially therethrough from a second surface of the buffer oxide layer. The second surface of the buffer oxide layer is opposite to the first surface of the buffer oxide layer. The method further comprises removing the structureable layer. The method further includes enlarging the one or more recesses through the buffer oxide layer and a portion of the dielectric layer to expose respective portions of the conductive structure. The method further includes filling the one or more recesses with a conductive material to form one or more pad structures configured to electrically connect to the conductive structure.In another aspect of the present invention, a method of manufacturing an image sensor device is disclosed. The method includes forming a plurality of radiation sensor regions over a first surface of a semiconductor layer. The method further includes forming, over the first surface of the semiconductor layer, a sacrificial isolation region enclosing the plurality of radiation sensor regions. The method further comprises forming a dielectric layer over the first surface of the semiconductor layer, the dielectric layer having a conductive structure. The method further includes etching a second surface of the semiconductor layer to create an opening exposing a bottom surface of the isolation region, the second surface of the semiconductor layer opposing the first surface of the semiconductor layer. The method further includes removing at least a portion of the isolation region to expose the dielectric layer; and forming a buffer oxide layer to occupy the opening. The method further comprises forming a structureable layer having a structure in the opening. The method further comprises creating, according to the structure of the structureable layer, one or more recesses in the buffer oxide layer extending partially therethrough from a second surface of the buffer oxide layer, the second surface of the buffer oxide layer opposing a first surface of the buffer oxide layer contacting the dielectric layer; and removing the structureable layer. The method further includes etching, due to the one or more recesses, the buffer oxide layer and a portion of the dielectric layer to expose respective portions of the conductive structure. The method further includes filling the one or more recesses with a conductive material to form one or more pad structures configured to electrically connect to the conductive structure.In yet another aspect of the present invention, a method of manufacturing an image sensor device is disclosed. The method includes forming a plurality of pixels over a first surface of a semiconductor layer configured to absorb near infrared radiation from a second surface of the semiconductor layer, the second surface of the semiconductor layer opposing the first surface of the semiconductor layer. The method further comprises forming a dielectric layer over the first surface of the semiconductor layer, the dielectric layer having a conductive structure. The method further comprises etching the second surface of the semiconductor layer to create an opening, the opening being adjacent to the plurality of pixels. The method further comprises: occupying the opening with a buffer oxide layer; forming a structureable layer having a structure in the opening; and creating, corresponding to the structure of the structureable layer, one or more recesses in the buffer oxide layer that extend partially therethrough from a second surface of the buffer oxide layer, the second surface of the buffer oxide layer opposing a first surface of the buffer oxide layer that directly contacts the dielectric layer. The method further comprises: removing the structureable layer using an oxygen-based plasma, wherein the conductive structure remains covered by at least the buffer oxide layer; and etching, due to the one or more recesses, the buffer oxide layer and a portion of the dielectric layer to expose respective portions of the conductive structure. The method further includes filling the one or more recesses with a conductive material to form one or more pad structures configured to electrically connect to the conductive structure.

Claims

A method comprising: forming a dielectric layer (408) over a first surface of a semiconductor layer (202), the dielectric layer (408) comprising a conductive structure (412); forming an opening (600) extending from a second surface of the semiconductor layer (202) to the first surface of the semiconductor layer to expose a portion of the dielectric layer (408), the second surface of the semiconductor layer being opposite the first surface of the semiconductor layer; forming a buffer oxide layer (700) to occupy the opening (600), a portion of a first surface of the buffer oxide layer contacting the exposed portion of the dielectric layer (408); Forming, according to a structureable layer (800), one or more recesses (900) in the buffer oxide layer (700) extending partially therethrough from a second surface of the buffer oxide layer, the second surface of the buffer oxide layer being opposite the first surface of the buffer oxide layer; removing the structureable layer (800); enlarging the one or more recesses (900) through the buffer oxide layer (700) and a portion of the dielectric layer (408) based on the one or more recesses (900) to expose respective portions of the conductive structure (412); and filling the one or more recesses (900) with a conductive material to form one or more pad structures (1200) configured to electrically connect to the conductive structure (412).The method of claim 1, wherein at least a portion of the structureable layer (800) has a thickness of at least about 8 μm.The method of claim 1 or 2, wherein the semiconductor layer (202) has a thickness of about 3 μm to 6 μm.The method of any preceding claim, wherein the buffer oxide layer (700) comprises a material selected from the group consisting of silicon oxide, undoped silicate glass (USG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), and combinations thereof.The method of any preceding claim, wherein the buffer oxide layer (700) comprises polyethyloxazoline (PEOX).The method of any preceding claim, wherein removing the structureable layer (800) further comprises ashing the structureable layer using an oxygen-based plasma.The method of any preceding claim, wherein the removing of the structureable layer (800) is performed in situ or ex situ with the creating of the one or more recesses (900) in the buffer oxide layer (700).The method of any preceding claim, wherein enlarging the one or more recesses (900) through the buffer oxide layer (700) and a portion of the dielectric layer (408) further comprises etching the buffer oxide layer and the first dielectric layer using a fluoride-based etching gas.The method of any preceding claim, wherein the conductive structure (412) comprises a lateral copper interconnect structure and a nitride-based conductive layer enclosing the lateral copper interconnect structure.The method of any preceding claim, further comprising forming one or more radiation sensor regions (204) in the semiconductor layer (202), wherein the one or more radiation sensor regions are surrounded by the one or more pad structures (1200).The method of any preceding claim, further comprising: forming one or more semiconductor devices over the first surface of the semiconductor layer (202); depositing a nitride layer (402) on the first surface of the semiconductor layer (202), the nitride layer enclosing the one or more semiconductor devices; depositing the dielectric layer (408); and forming one or more vertical conductive structures (412) in the dielectric layer (408) to electrically connect the one or more semiconductor devices to the conductive structure (412).A method comprising: forming a plurality of radiation sensor regions (204) over a first surface of a semiconductor layer (202); forming, over the first surface of the semiconductor layer (202), a sacrificial isolation region (302) to enclose the plurality of radiation sensor regions (204); forming a dielectric layer (408) over the first surface of the semiconductor layer (202), the dielectric layer (408) including a conductive structure (412); etching a second surface of the semiconductor layer (202) to create an opening (600) exposing a bottom surface of the isolation region (302), the second surface of the semiconductor layer being opposite the first surface of the semiconductor layer; removing at least a portion of the isolation region (302) to expose the dielectric layer (408); forming a buffer oxide layer (700) to occupy the opening (600); forming a structureable layer (800) having a structure (802) in the opening (600); forming, corresponding to the structure (802) of the structureable layer (800), one or more recesses (900) in the buffer oxide layer (700) extending partially therethrough from a second surface of the buffer oxide layer, the second surface of the buffer oxide layer being opposite a first surface of the buffer oxide layer contacting the dielectric layer (408); removing the structureable layer (800); etching, based on the one or more recesses (900), the buffer oxide layer (700), and a portion of the dielectric layer (408), to expose respective portions of the conductive structure (412); and filling the one or more recesses (900) with a conductive material to form one or more pad structures (1200) configured to electrically connect to the conductive structure (412).The method of claim 12, wherein the removing of the structureable layer (800) is performed in situ or ex situ with creating the one or more recesses (900) in the buffer oxide layer (700).The method of claim 12 or 13, wherein removing the structureable layer (800) further comprises ashing the structureable layer using an oxygen-based plasma.The method of any of claims 12 to 14, wherein the conductive structure (412) comprises a lateral copper interconnect structure and a nitride-based conductive layer enclosing the lateral copper interconnect structure.The method of any of claims 12 to 15, further comprising: forming one or more semiconductor devices over the first surface of the semiconductor layer (202); depositing a nitride layer (402) on the first surface of the semiconductor layer (202), the nitride layer enclosing the one or more semiconductor devices; depositing the dielectric layer (408); and forming one or more vertical conductive structures (412) in the dielectric layer (408) to electrically connect the one or more semiconductor devices to the conductive structure (412).The method of any of claims 12 to 16, wherein the structure (802) of the structureable layer (800) has a thickness of at least about 8 μm.The method of any of claims 12 to 17, wherein the semiconductor layer (202) has a thickness of about 3 μm to 6 μm.The method of any of claims 12 to 18, wherein each of the plurality of radiation sensor regions (204) is configured to absorb near infrared radiation from the second surface of the semiconductor layer (202).A method comprising: forming, over a first surface of a semiconductor layer (202), a plurality of pixels configured to absorb near infrared radiation from a second surface of the semiconductor layer, the second surface of the semiconductor layer being opposite the first surface of the semiconductor layer; forming a dielectric layer (408) over the first surface of the semiconductor layer (202), the dielectric layer (408) including a conductive structure (412); etching the second surface of the semiconductor layer (202) to create an opening (600), the opening being adjacent the plurality of pixels; lining the opening (600) with a buffer oxide layer (700); forming a structureable layer (800) having a structure (802) in the opening (600); creating, according to the structure (802) of the structureable layer (800), one or more recesses (900) in the buffer oxide layer (700) extending partially therethrough from a second surface of the buffer oxide layer, the second surface of the buffer oxide layer being opposite a first surface of the buffer oxide layer directly contacting the dielectric layer (408); ashing the structureable layer (800) using an oxygen-based plasma, wherein the conductive structure (412) remains at least covered by the buffer oxide layer (700); and etching, based on the one or more recesses (900), the buffer oxide layer (700) and a portion of the dielectric layer (408) to expose respective portions of the conductive structure (802); and filling the one or more recesses (900) with a conductive material to form one or more pad structures (1200) configured to electrically connect to the conductive structure (802).

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