PACKAGE STRUCTURE AND METHOD FOR ITS MANUFACTURING

Abstract

Package structure with: a circuit substrate (300); a semiconductor package (SM) that is arranged on the circuit substrate (300) and electrically connected to it; a cover structure (510) arranged on the circuit substrate (300) such that it covers the semiconductor package (SM), wherein the cover structure (510) is attached to the circuit substrate (300) by an adhesive material (520); a passive device (PDX) arranged on the circuit substrate (300) between the semiconductor package (SM) and the cover structure (510); and a barrier structure (BS) that separates the passive device (PDX) from the cover structure (510) and the adhesive material (520), wherein the barrier structure (BS) is in contact with the adhesive material (520), wherein the barrier structure (BS) has a cover part that covers side surfaces and a top surface of the passive device (PDX).

Description

background

[0001] Semiconductor devices and integrated circuits used in various electronic applications, such as mobile phones and other mobile electronic devices, are typically fabricated on a single semiconductor wafer. The wafer's dies can be processed and packaged with other semiconductor devices or dies at the wafer level, and various technologies have been developed for wafer-level packaging. US 2006 / 0 060 985 A1 discloses an apparatus and method for controlling resin bleedout. US 2016 / 0 163 657 A1 discloses packaging devices and methods for semiconductor devices. US 2005 / 0 082 682 A1 discloses a semiconductor device for preventing contamination on its bond pads during assembly of an electronic component. Short description of the drawings

[0002] Aspects of the present invention can best be understood from the following detailed description when taken in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various elements are not drawn to scale. Rather, for the sake of clarity of discussion, the dimensions of various elements may be exaggerated or reduced as desired. The Fig. 1A to 1G are schematic cross-sectional views of various stages of a semiconductor package manufacturing process according to some example embodiments of the present invention. The Fig. 2A to 2C are schematic cross-sectional views of various stages of a manufacturing process for a package structure according to some exemplary embodiments of the present invention. Fig. 3 is an enlarged sectional view of a package structure according to some example embodiments of the present invention. Fig. 4 is an enlarged sectional view of a package structure according to some further exemplary embodiments of the present invention. Fig. 5 is an enlarged sectional view of a package structure according to some further exemplary embodiments of the present invention. Fig. 6 is an enlarged sectional view of a package structure according to some further exemplary embodiments of the present invention. Fig. 7 is an enlarged sectional view of a package structure according to some further exemplary embodiments of the present invention. Fig. 8 is a top view of a package structure according to some example embodiments of the present invention. Fig. 9 is a top view of a package structure according to some further exemplary embodiments of the present invention. Fig. 10 is a top view of a package structure according to some further exemplary embodiments of the present invention. Fig. 11 is a top view of a package structure according to some further exemplary embodiments of the present invention. Fig. 12 is a top view of a package structure according to some further exemplary embodiments of the present invention. Fig. 13 is a schematic cross-sectional view of a package structure according to some further exemplary embodiments of the present invention. Detailed description

[0003] The invention is defined by claim 1, which defines a package structure, claim 8, which defines a package structure, and claim 14, which defines a method for manufacturing a package structure. Embodiments are provided in the dependent claims, the description, and the drawings. The following description provides many different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present invention.For example, the fabrication of a first element over or on top of a second element in the description below may include embodiments in which the first and second elements are fabricated in direct contact, and may also include embodiments in which additional elements may be fabricated between the first and second elements such that the first and second elements are not in direct contact. Furthermore, throughout the present invention, reference numerals and / or letters may be repeated throughout the various examples. This repetition is for simplicity and clarity and does not, in itself, prescribe any relationship between the various embodiments and / or configurations discussed.

[0004] Furthermore, spatially relative terms such as "beneath," "under," "lower," "above," "upper," and the like may be used herein to conveniently describe the relationship of one element or structure to one or more other elements or structures illustrated in the figures. The spatially relative terms are intended to encompass other orientations of the device in use or operation, in addition to the orientation illustrated in the figures. The device may be oriented differently (rotated 90 degrees or in a different orientation), and the spatially relative descriptors used herein may be interpreted accordingly.

[0005] Other elements and methods may also be used. For example, test structures may be used to assist in the verification testing of a 3D package or 3DIC devices. The test structures may include, for example, test pads fabricated in a redistribution layer or on a substrate that enable testing of the 3D package or 3DIC devices, the use of probes and / or probe cards, and the like. Verification testing may be performed on intermediate structures as well as final structures. Furthermore, the structures and methods described herein may be used in conjunction with test methodologies that include intermediate verification of proven good die to increase yield and reduce costs.

[0006] With the gradual increase in the size of semiconductor packages, such as a chip-on-wafer (CoW) structure on a circuit substrate, an encapsulation width between passive components and an adhesive material of a lid structure is limited. In other words, the space between passive components and the adhesive material decreases, and there is a risk that the adhesive material comes into contact with the passive component. This may cause a functional failure of the passive component. In addition, a tin (Sn) whisker on the passive components may also come into contact with the lid structure, resulting in electrical failure. A package structure according to exemplary embodiments of the present invention includes at least one barrier structure that separates the passive component from the lid structure and the adhesive material.This can prevent leakage or spreading of the adhesive material to the passive component, so that electrical failure and / or functional failure of the passive component can be avoided.

[0007] The Fig. 1A to 1G are schematic sectional views of various stages of a manufacturing method for a semiconductor package according to some exemplary embodiments of the present invention. In Fig. 1A, an interposer structure 100 is provided. In some embodiments, the interposer structure 100 includes a core portion 102 and a plurality of vias 104 and conductive pads 106 formed thereon. In some embodiments, the core portion 102 is a substrate, such as a bulk semiconductor substrate, a silicon-on-insulator (SOI) substrate, or a multilayer semiconductor material substrate. The semiconductor material of the substrate (core portion 102) may be silicon, germanium, silicon germanium, silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or a combination thereof. In some embodiments, the core portion 102 may be doped or undoped.

[0008] In some embodiments, the conductive pads 106 are formed on a first surface 102a of the core portion 102. In some embodiments, the vias 104 are formed in the core portion 102 and are connected to the conductive pads 106. In some embodiments, the vias 104 extend into the core portion 102 to a certain depth. In some embodiments, the vias 104 are substrate vias. In some embodiments, the vias 104 are silicon vias if the core portion 102 is a silicon substrate. In some embodiments, the vias 104 may be formed by creating holes or recesses in the core portion 102, which are then filled with a conductive material. In some embodiments, the recesses may be created, for example, by etching, milling, laser drilling, or the like.In some embodiments, the conductive material may be deposited using an electrochemical plating process, chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD), and may be copper, tungsten, aluminum, silver, gold, or a combination thereof. In some embodiments, the conductive pads 106 connected to the vias 104 may be fabricated as conductive portions of one or more redistribution layers fabricated on the interposer structure 100. In some embodiments, the conductive pads 106 are sub-bump metallizations (UBMs). In certain embodiments, the interposer structure 100 may also include active or passive devices, such as transistors, capacitors, resistors, or diodes, fabricated in the core portion 102.

[0009] As in Fig. 1A, the core part 102 has a plurality of package regions PKR and singulation strips DL that separate the individual package regions PKR from each other. The vias 104 and the conductive pads 106 are formed in the core part 102 in the package regions PKR. In some embodiments, semiconductor dies 21 and semiconductor dies 22 are provided on the interposer structure 100 or on the core part 102 in the package regions PKR. The semiconductor dies 21 and 22 are individual dies that have been separated from a wafer. In some embodiments, the semiconductor dies 21 contain the same circuits, such as devices and metallization structures, or are the same type of die. In some embodiments, the semiconductor dies 22 contain the same circuits or are the same type of die.In certain embodiments, semiconductor dies 21 and 22 have different circuits, or they are different types of dies. In alternative embodiments, semiconductor dies 21 and 22 may have the same circuits.

[0010] In some embodiments, semiconductor dies 21 may be main dies, while semiconductor dies 22 may be slave dies. In some embodiments, the main dies are arranged on the core portion 102 at central positions of each package region PKR, while the slave dies are arranged adjacent to each other and spaced from the main dies. In some embodiments, the slave dies are arranged adjacent to and around the main dies. In one embodiment, four or six slave dies are arranged around one main die per package region PKR.

[0011] In certain embodiments, the semiconductor dies 21 have a surface area that is larger than that of the semiconductor dies 22. Furthermore, in some embodiments, the semiconductor dies 21 and the semiconductor dies 22 may have different sizes, such as different surface areas and / or different thicknesses. In some embodiments, the semiconductor dies 21 may each be a logic die, e.g., a main processor (CPU) die, a graphics processing unit (GPU) die, a system-on-a-chip (SoC) die, a microcontroller, or the like. In some embodiments, the semiconductor dies 21 are each a power management die, e.g., a PMIC (power management integrated circuit) die. In some embodiments, the semiconductor dies 22 may each be a memory die, e.g., a memory card (MRAM). B. a DRAM die (DRAM: dynamic random access memory), an SRAM die (SRAM: static random access memory) or an HBM die (HBM: high bandwidth memory).However, the invention is not limited thereto, and the number, sizes, and types of semiconductor dies arranged on the core part 102 can be adjusted accordingly depending on the product requirements.

[0012] As in Fig. 1A, the semiconductor dies 21 include a body 210 and interconnect pads 212 fabricated on an active surface 211 of the body 210. In certain embodiments, the interconnect pads 212 may in turn include pillar structures for bonding the semiconductor dies 21 to other structures. In some embodiments, the semiconductor dies 22 include a body 220 and interconnect pads 222 fabricated on an active surface 221 of the body 220. In other embodiments, the interconnect pads 222 may in turn include pillar structures for bonding the semiconductor dies 22 to other structures.

[0013] In some embodiments, the semiconductor dies 21 and the semiconductor dies 22 are attached to the first surface 102a of the core portion 102 by means of electrical interconnect elements 110, for example, by flip-chip bonding. The electrical interconnect elements 110 are formed with a reflow process between the connection pads 212 and 222 and the conductive pads 106, thereby electrically and physically connecting the semiconductor dies 21 and 22 to the core portion 102 of the interposer structure 100. In some embodiments, the electrical interconnect elements 110 are disposed between the semiconductor dies 21 and 22 and the interposer structure 100. In certain embodiments, the semiconductor dies 21 and 22 are electrically connected to the vias 104 and the conductive pads 106 via the electrical interconnect elements 110. In one embodiment, the electrical interconnect elements 110 are microbumps, such as microbumps with copper metal pillars.In another embodiment, the electrical connection elements 110 are solder bumps, lead-free solder bumps, or microbumps, such as C4 bumps (C4: controlled collapse chip interconnect) or microbumps containing copper pillars. In some embodiments, the bonding between the semiconductor dies 21 and 22 and the core portion 102 may be a solder bond. In some embodiments, the bonding between the semiconductor dies 21 and 22 and the core portion 102 may be a metal-to-metal direct bond, such as a copper-to-copper bond.

[0014] In Fig. 1B, in a next step, an underfill structure 112 may be formed to cover the plurality of electrical connection elements 110 and fill gaps between the semiconductor dies 21 and 22 and the interposer structure 100. In some embodiments, the underfill structure 112 also covers sidewalls of the semiconductor dies 21 and 22 and is arranged in the package area PKR. Subsequently, an insulating encapsulation material 114 may be deposited over the interposer structure 100 (or over the core portion 102) to cover the underfill structure 112 and enclose the semiconductor dies 21 and 22.

[0015] In some embodiments, the insulating encapsulation material 114 is formed on the first surface 102a of the core part 102 in the package regions PKR and above the singulation strips DL. In some embodiments, the insulating encapsulation material 114 is formed, for example, by compression molding or transfer molding. In one embodiment, a curing process is performed to cure the insulating encapsulation material 114. In some embodiments, the semiconductor dies 21 and 22 and the electrical connection elements 110 are encapsulated with the insulating encapsulation material 114. In some embodiments, a planarization process, such as a grinding or polishing process, may be performed to partially remove the insulating encapsulation material 114 so that backsides 21S and 22S of the semiconductor dies 21 and 22 are exposed.Accordingly, the back surfaces 21S and 22S of the semiconductor dies 21 and 22 are level with a top surface 114a of the insulating encapsulation material 114. The top surface 114a faces a back surface 114b of the insulating encapsulation material 114 and is in contact with the core part 102.

[0016] In some embodiments, the insulating encapsulant material 114 is a polymer (such as an epoxy resin, a phenolic resin, a silicon-containing resin, or other suitable resin), a dielectric material with a low dielectric constant (Dk) and a low-loss tangent (Df), or other suitable material. In an alternative embodiment, the insulating encapsulant material 114 may be any suitable insulating encapsulant material. In some embodiments, the encapsulant material 114 may further include an inorganic filler or compound (e.g., silica, clay, and the like) that may be added to optimize the coefficient of thermal expansion (CTE) of the insulating encapsulant material 114. However, the invention is not so limited.

[0017] In Fig. 1C shows the structure of Fig. 1B and placed on a carrier Cx, so that the carrier Cx directly contacts the backsides 21S and 22S of the semiconductor dies 21 and 22 and the top side 114a of the insulating encapsulation material 114. As shown in Fig. As shown in Figure 1C, at this stage of processing, the interposer structure 100 has not yet been thinned and has a thickness Tx. In other words, the vias 104 are not exposed and are embedded in the core portion 102 of the interposer structure 100.

[0018] In Fig. 1D, a thinning process is performed on the interposer structure 100 to partially remove or thin the core portion 102 of the interposer structure 100 until the vias 104 are exposed and a second surface 102b of the core portion 102 is formed. In some embodiments, the thinning process may be a grind-back process, a polishing process, or an etching process. In some embodiments, after the thinning process, the interposer structure 100 is thinned to a thickness Ty. In some embodiments, a ratio of the thickness Ty to the thickness Tx is about 0.1 to about 0.5.

[0019] In Fig. 1E, a redistribution structure 116 is formed on the second surface 102b of the core portion 102 in the package area PKR and above the singulation stripes DL. The second surface 102b faces the first surface 102a of the core portion 102. In some embodiments, the redistribution structure 116, the core portion 102, the vias 104, and the conductive pads 106 form an interposer structure 100'. In some embodiments, the redistribution structure 116 electrically connects the vias 104 and / or electrically connects the vias 104 to external devices. In certain embodiments, the redistribution structure 116 comprises at least one dielectric layer 116a and metallization structures 116b in the dielectric layer 116a.In some embodiments, the metallization structures 116b may include pads, vias, and / or conductive traces to interconnect the vias 104 and to further connect the vias 104 to one or more external devices. Note that although only one layer of the dielectric layer 116a and only one layer of the metallization structures 116b are shown in FIG. Fig. 1E, the number of layers of the dielectric layer 116a and the metallization structures 116b is not limited thereto and can be adjusted as needed.

[0020] In one embodiment, the material of the dielectric layer 116a is silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or a low-k dielectric material (such as a phosphosilicate glass material, a fluorosilicate glass material, a borophosphosilicate glass material, SiOC, a spin-on glass material, a spin-on polymer, or a silicon carbon material). In some embodiments, the dielectric layer 116a may be formed by spin coating or deposition, such as CVD, plasma-enhanced chemical vapor deposition (PECVD), high-density plasma chemical vapor deposition (HDP-CVD), or the like. In some embodiments, the metallization structures 116b are under-bump metallizations (UBMs).In some embodiments, forming the metallization structures 116b may include patterning the dielectric layer using photolithographic techniques and one or more etching processes, and filling the openings in the patterned dielectric layer with a metallic material. Excess conductive material on the dielectric layer may be removed, for example, using a chemical mechanical polishing process. In some embodiments, the material of the metallization structures 116b is copper, aluminum, tungsten, silver, or a combination thereof.

[0021] As in Fig. 1E, a plurality of conductive terminals 118 are arranged on the metallization structures 116b and are electrically connected to the vias 104. In some embodiments, the conductive terminals 118 are arranged on a top surface 116s of the redistribution structure 116 and are electrically connected to the vias 104 through the metallization structures 116b in the package area PKR. In certain embodiments, the conductive terminals 118 are arranged on and attached to the metallization structures 116b. In some embodiments, the conductive terminals 118 are lead-free solder balls, solder balls, BGA (ball grid array) balls, bumps, C4 bumps, or microbumps. In some embodiments, the conductive terminals 118 may comprise a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or a combination thereof.In some embodiments, the conductive terminals 118 are formed by applying a solder paste to the redistribution structure 116, for example, by evaporation, electroplating, printing, or solder transfer, and then reflowing the solder paste into desired bump shapes. In some embodiments, the conductive terminals 118 are placed on the redistribution structure 116 by ball placement or the like. In other embodiments, the conductive terminals 118 are formed by forming solder-free metal pillars (such as copper pillars) by sputtering, printing, electroless or electroplating, or CVD, and then forming a lead-free capping layer on the metal pillars by plating. The conductive terminals 118 may be used to connect to an external device or another electrical component.In some embodiments, the conductive terminals 118 are used to connect to a circuit substrate, a semiconductor substrate, or a package substrate.

[0022] In Fig. 1F will in a next step the Fig. 1E is severed or singulated along the singulation strips DL to produce a plurality of semiconductor packages SM. For example, the singulation process is performed such that the redistribution structure 116, the core portion 102, and the insulating encapsulation material 114 are severed to remove portions of the redistribution structure 116, the core portion 102, and the insulating encapsulation material 114 along the singulation strips DL. In some embodiments, the singulation process typically includes sawing with a rotating knife or a laser beam. In other words, the singulation process is, for example, a laser cutting process, a mechanical sawing process, or another suitable process. In some embodiments, the singulation process may be performed on a tape (e.g., a singulation tape) held by a frame (not shown).In other words, the carrier Cx can be detached, and the structure is transferred to the singulation belt to perform the singulation process. After the carrier Cx is detached and the singulation process is performed, the structure can be . Fig. 1G shown singulated semiconductor package SM can be obtained.

[0023] The Fig. 2A to 2C are schematic sectional views of various stages of a manufacturing method for a package structure according to some exemplary embodiments of the present invention. In Fig. 2A, in the exemplary embodiment, the Fig. 1G is mounted to a circuit substrate 300 by means of the conductive connections 118. In some embodiments, the circuit substrate 300 comprises contact pads 310, contact pads 320, metallization layers 330, and vias (not shown). In some embodiments, the contact pads 310 and the contact pads 320 are each distributed on two opposite sides of the circuit substrate 300 and are exposed for electrical connection to elements / structural elements to be manufactured later. In some embodiments, the metallization layers 330 and the vias are embedded in the circuit substrate 300 and together provide a routing function for the circuit substrate 300, in which the metallization layers 330 and the vias are electrically connected to the contact pads 310 and the contact pads 320.In other words, at least some of the contact pads 310 are electrically connected to some of the contact pads 320 through the metallization layers 330 and the vias. In some embodiments, the contact pads 310 and the contact pads 320 may be metal pads or metal alloy pads. In some embodiments, the materials for the metallization layers 330 and the vias may be substantially the same as or similar to the material for the contact pads 310 and the contact pads 320.

[0024] Furthermore, in some embodiments, the semiconductor package SM is bonded to the circuit substrate 300 by physically connecting the conductive terminals 118 and the contact pads 310 into a stacked structure. In certain embodiments, the semiconductor package SM is electrically connected to the circuit substrate 300. In some embodiments, the circuit substrate 300 is a flexible organic substrate or a printed circuit board. In these embodiments, the conductive terminals 118 are, for example, chip interconnect elements. In some embodiments, a plurality of conductive balls 340 are fabricated on the circuit substrate 300. As in Fig. As shown in Figure 2A, the conductive balls 340 are connected to the contact pads 320 of the circuit substrate 300. In other words, the conductive balls 340 are electrically connected to the circuit substrate 300 through the contact pads 320. Through the contact pads 310 and the contact pads 320, some of the conductive balls 340 are electrically connected to the semiconductor package SM (e.g., the semiconductor dies 21 and 22 contained therein). In some embodiments, the conductive balls 340 are, for example, solder balls or BGA balls. In some embodiments, the semiconductor package SM is bonded to the circuit substrate 300 by physically connecting the conductive terminals 118 and the contact pads 310 of the circuit substrate 300 using a chip-on-wafer-on-substrate (CoWoS) packaging process. As further described in Fig. As shown in FIG. 2A, passive components PDx (integrated passive components or surface-mount components) can be mounted on the circuit substrate 300. For example, the passive components PDx can be mounted on the contact pads 310 of the circuit substrate 300 using a soldering process. However, the invention is not limited thereto. In certain embodiments, the passive components PDx can be mounted on the circuit substrate such that they enclose the semiconductor package SM.

[0025] As continued in Fig. 2A, in some embodiments, an underfill structure 350 is formed to fill gaps between the circuit substrate 300 and the semiconductor package SM. In certain embodiments, the underfill structure 350 fills the gaps between adjacent conductive pads 118 and covers the conductive pads 118. For example, the underfill structure 350 encloses the plurality of conductive pads 118. In some embodiments, the passive components PDx are freed from the underfill structure 350 and are kept spaced apart from the underfill structure 350. In other words, the underfill structure 350 does not cover the passive components PDx.

[0026] Typically, the semiconductor package SM is also protected with a lid structure that is attached to the circuit substrate 300 with an adhesive. Contact between the adhesive and the passive components PDx should be avoided. Fig. Figures 2B to 13 show blocking or barrier structures that act to prevent the adhesive from adhering to the passive components PDx. As an additional benefit, some of the barrier structures also act to mitigate the growth of tin whiskers from the passive components PDx, which can contact the lid structure and cause component failure due to a short circuit. These structures are shown, for example, in the Fig. 7, Fig. 10 and Fig. 12 shown.

[0027] In Fig. 2B, in a next step, a barrier structure BS (or a first dam portion DP1) is formed on the circuit substrate 300 by inkjet printing or another suitable deposition method. For example, in some embodiments, a polymer ink material IM is distributed on the circuit substrate 300, which is then cured to produce the barrier structure BS (the first dam portion DP1). In certain embodiments, the polymer ink material IM is cured after its distribution by irradiation with UV light. In some embodiments, the polymer ink material IM is distributed on the circuit substrate 300 in a region located between the passive components PDx and a lid structure 510 (which will be provided in a later step) and spaced apart from the passive components PDx and the lid structure 510.In some embodiments, the polymer ink material IM is a polyimide-based polymer material, an epoxy-based polymer material, or another polymer-based material. However, the invention is not limited thereto, and any suitable materials may be used to fabricate the barrier structure BS, as long as they provide sufficient barrier function without compromising the performance of the passive components PDx.

[0028] In Fig. 2C, in some embodiments, the lid structure 510 is attached to the circuit substrate 300 with an adhesive material 520. For example, the lid structure 510 is arranged on the circuit substrate 300 such that it encloses the semiconductor package SM and the passive components PDx. In some embodiments, the adhesive material 520 is a conductive adhesive, but the invention is not limited thereto. In alternative embodiments, the adhesive material 520 may also be another suitable adhesive material, as long as the attachment of the lid structure 510 to the circuit substrate 300 can be realized.

[0029] In some embodiments, the lid structure 510 may be a heat sink used for heat dissipation. In some embodiments, a thermal interface metal 410 is attached to a backside of the semiconductor package SM and is sandwiched between the lid structure 510 and the semiconductor package SM. In certain embodiments, the thermal interface metal 410 fills a gap between the semiconductor package SM and the lid structure 510 to further enhance heat dissipation.

[0030] In an exemplary embodiment, when attaching the lid structure 510 to the circuit substrate 300 with the adhesive material 520, leakage of the adhesive material 520 may occur. The adhesive material 520 may spread to a location where the passive components PDx and the semiconductor package SM are located. Since, in some embodiments, the barrier structure BS (the first dam portion DP1) is arranged between the passive components PDx and the lid structure 510, the spreading or leakage of the adhesive material 520 is blocked by the barrier structure BS (the first dam portion DP1). That is, the barrier structure BS (the first dam portion DP1) separates the passive components PDx from the lid structure 510 and the adhesive material 520, but it remains in contact with the adhesive material 520.In certain embodiments, the barrier structure BS (the first dam portion DP1) is spaced a certain distance from the passive components PDx and the lid structure 510 to prevent overlap of the adhesive material 520. By using the barrier structure BS to prevent the adhesive material 520 from spreading to the passive components PDx, electrical failure and / or functional failure of the passive components PDx can be avoided. The barrier structure BS shown in FIG. Fig. The structure shown in Figure 2C may be considered as a package structure PS in some embodiments of the present invention.

[0031] In the above embodiment, the barrier structure BS is depicted as a dam-like part (first dam part DP1). Various other designs for the barrier structure BS are described in the following sections.

[0032] Fig. 3 is an enlarged sectional view of a package structure according to some exemplary embodiments of the present invention. For example, Fig. 3 an enlarged view of the Fig. 2C, and therefore the same reference numerals are used to designate the same or similar parts, and the detailed description is not repeated here. Fig. 3, the barrier structure BS comprises a first dam part DP1 arranged between the passive component PDx and the lid structure 510. In some embodiments, the first dam part DP1 has a first sidewall S1 and a second sidewall S2 opposite the first sidewall S1, facing the passive component PDx. For example, the first sidewall S1 of the first dam part DP1 is in contact with the adhesive material 520 to stop the adhesive material 520. Furthermore, in some embodiments, the passive component PDx has a first surface SD1 facing the lid structure 510, and a second surface SD2 opposite the first surface SD1, facing the interposer structure 100' (which in Fig. 2C).

[0033] In the exemplary embodiment, a width W1 of the first dam portion DP1 is kept substantially constant from a lower end to an upper end of the first dam portion DP1. In certain embodiments, the width W1 is 5 µm to 3000 µm, which can be adjusted based on design requirements. If the width W1 is less than 5 µm, in some embodiments, undesirable process non-uniformities or insufficient adhesion strength to the circuit substrate 300 arise, such that the first dam portion DP1 breaks due to the stress caused by the adhesive material 520. In some embodiments, a height H1 of the first dam portion DP1 is greater than a height H2 of the passive component PDx.Similar to the above embodiment, since the first dam part DP1 prevents the adhesive material 520 from spreading to the passive component PDx, electrical failure and / or functional failure of the passive component PDx can be avoided.

[0034] Fig. 4 is an enlarged sectional view of a package structure according to some further exemplary embodiments of the present invention. Fig. The embodiment shown in Figure 4 is the one in Fig. 3, which is why the same reference numerals are used to designate the same or similar parts and the detailed description is not repeated here. When configuring Fig. 3, the height H1 of the first dam part DP1 is shown to be greater than the height H2 of the passive component PDx. However, the invention is not limited thereto. Fig. 4, the height H1 of the first dam portion DP1 is smaller than the height H2 of the passive component PDx. When a distance between the first dam portion DP1 and the lid structure 510 is increased, in some embodiments, the height of the first dam portion DP1 may be reduced. When the first dam portion DP1 is arranged farther away from the lid structure 510, the spreading of the adhesive material 520 to the first dam portion DP1 may become less noticeable. In other words, due to the greater distance of the first dam portion DP1 from the lid structure 510, the adhesive material 520 spreads further, resulting in a smaller height of the spreading adhesive material 520. Therefore, the height of the first dam portion DP1 may be reduced due to the limited spreading of the adhesive material 520. In some alternative embodiments, the height of the first dam part DP1 may be substantially equal to the height of the passive component PDx.In some embodiments, the height of the barrier structure BS (or the first dam portion DP1) can be 10 µm to 2000 µm, which can be adjusted according to design requirements. Similar to the previous embodiments, electrical failure and / or functional failure of the passive component PDx can be avoided because the first dam portion DP1 prevents the adhesion material 520 from spreading to the passive component PDx.

[0035] Fig. 5 is an enlarged sectional view of a package structure according to some further exemplary embodiments of the present invention. Fig. The embodiment shown in Figure 5 is the one in Fig. 3, which is why the same reference numerals are used to designate the same or similar parts and the detailed description is not repeated here. As in Fig. 5, the first dam portion DP1 may include a lower portion DP-Bs and an upper portion DP-Ts connected to the lower portion DP-Bs. In the illustrated embodiment, a width of the first dam portion DP1 decreases from the lower portion DP-Bs to the upper portion DP-Ts. For example, in some embodiments, a lower end of the lower portion DP-Bs may have a width W1A, while an upper end of the lower portion DP-Ts may have a width W1B, with the width of the first dam portion DP1 decreasing from W1A to W1B. In some embodiments, the shape or dimensions of the first dam portion DP1 may be adjusted by controlling an amount and duration of spreading and curing the polymer ink material.Similar to the above embodiments, electrical failure and / or functional failure of the passive component PDx can be avoided because the first dam part DP1 prevents the spreading of the adhesive material 520 to the passive component PDx.

[0036] Fig. 6 is an enlarged sectional view of a package structure according to some further exemplary embodiments of the present invention. Fig. The embodiment shown in Figure 6 is the one in Fig. 3, which is why the same reference numerals are used to designate the same or similar parts and the detailed description is not repeated here. As in Fig. 6, the first dam part DP1 may include a lower portion DP-Bs, a middle portion DP-Ms, and an upper portion DP-Ts, which are sequentially assembled, wherein the lower portion DP-Bs, the middle portion DP-Ms, and the upper portion DP-Ts are manufactured together in a single process. In the illustrated embodiment, a width of the first dam part DP1 increases from the lower portion DP-Bs to the middle portion DP-Ms and decreases from the middle portion DP-Ms to the upper portion DP-Ts. For example, in some embodiments, a lower end of the lower portion DP-Bs may have a width W1B, the middle portion DP-Ms may have a maximum width W1C, and an upper end of the upper portion DP-Ts may have a width W1B. In certain embodiments, the width of the first dam portion DP1 increases from W1A to W1C and decreases from W1C to W1B.Similar to the above embodiments, electrical failure and / or functional failure of the passive component PDx can be avoided because the first dam part DP1 prevents the spreading of the adhesive material 520 to the passive component PDx.

[0037] Fig. 7 is an enlarged sectional view of a package structure according to some further exemplary embodiments of the present invention. Fig. The embodiment shown in Figure 7 is the one in Fig. 3, which is why the same reference numerals are used to designate the same or similar parts and the detailed description is not repeated here. As in Fig. 7, the barrier structure BS may include a cover part CP1 covering side surfaces (a first surface SD1 and a second surface SD2) and a top surface PD-Ts of the passive component PDx. In some embodiments, the passive component PDx is covered and enclosed by the cover part CP1 and is in contact with the cover part CP1. In some embodiments, the cover part CP1 may be manufactured in a similar manner as the dam part DP1. For example, a polymer ink material IM (which is described in Fig. 2B) may be distributed on the circuit substrate 300 to enclose the passive component PDx and may then be cured to produce the cover portion CP1. In some embodiments, a height H3 of the cover portion CP1 may be greater than the height H2 of the passive component PDx. In alternative embodiments, the height H3 of the cover portion CP1 may be substantially equal to the height H2 of the passive component PDx. Furthermore, in some embodiments, a width of the cover portion CP1 may be greater than or substantially equal to a width of the passive component PDx to enclose the passive component PDx. Similar to the previous embodiments, electrical failure and / or functional failure of the passive component PDx may be avoided because the cover portion CP1 also prevents the spread of the adhesive material 520 to the passive component PDx.In addition, by protecting the top surface PD-Ts of the passive component PDx with the cover part CP1, the cover part CP1 can act to mitigate the growth of tin whiskers from the passive component PDx, thus preventing component failure due to a short circuit.

[0038] Fig. 8 is a plan view of a package structure according to some exemplary embodiments of the present invention. A package structure PS1 shown in Fig. 8 is shown, the Fig. 2C, the same reference numerals are used to designate the same or similar parts, and the detailed description is not repeated here. As shown in Fig. 8, the package structure PS1 includes a first passive component PDx1 and a second passive component PDx2 arranged adjacent to the semiconductor package SM, with barrier structures BS (first dam portions DP1) provided between the first passive component PDx1 and the lid structure 510 and between the second passive component PDx2 and the lid structure 510. In some embodiments, the first dam portion DP1 arranged adjacent to the first passive component PDx1 has a width WX2 and a length LX2, while the first dam portion DP1 arranged adjacent to the second passive component PDx2 has a width WX1 and a length LX1. In the exemplary embodiment, the width WX1 is greater than the width WX2, and the length LX2 is greater than the length LX1. From the present embodiment, it is apparent that the length and width of the first dam part DP1 can be adjusted accordingly based on design requirements.In some embodiments, a design of the first dam portion DP1 may be adjusted accordingly, as long as the first dam portion DP1 is successful in separating the passive components (PDx1, PDx2) from the adhesive material 520. In the exemplary embodiment, the first dam portion DP1 is arranged on a side surface (the first surface SD1) of the passive components (PDx1, PDx2) to prevent the adhesive material 520 from spreading to the passive components (PDx1, PDx2). In certain embodiments, the first dam portion DP1 is arranged on the surface of the passive components (PDx1, PDx2) that is closest to the lid structure 510.

[0039] Fig. 9 is a top view of a package structure according to some further exemplary embodiments of the present invention. A package structure PS2 shown in Fig. 9 is shown, the Fig. 8, the same reference numerals are used to designate the same or similar parts and the detailed description is not repeated here. Fig. In the configuration shown in Figure 8, the first dam part DP1 is arranged on only one side surface (the first surface SD1) of the passive components (PDx1, PDx2) to protect the passive components (PDx1, PDx2). However, the invention is not limited to this. For example, as shown in Fig. 9, in some embodiments, the first dam portion DP1, which is arranged adjacent to the first passive component PDx1, is manufactured to enclose all side surfaces of the first passive component PDx1. In certain embodiments, the first passive component PDx1 is confined to be arranged in an area enclosed by the first dam portion DP1. Furthermore, in certain embodiments, the first dam portion DP1, which is arranged adjacent to the second passive component PDx2, is manufactured to enclose a first surface SD1, a third surface SD3, and a fourth surface SD4 of the second passive component PDx2, while exposing the second surface SD2. Furthermore, in the above embodiments, the adhesive material 520 is shown contacting a sidewall (e.g., the first sidewall S1) of the first dam portion DP1. However, the invention is not limited thereto.For example, in some embodiments, in some cases, the adhesive material 520 may not spread to contact the first dam portion DP1 when the first dam portion DP1 is spaced a certain distance from the lid structure 510. As shown in FIG. Fig. 9, the first side wall S1 of the first dam part DP1, which is arranged next to the first passive component PDx1, is not in contact with the adhesive material 520.

[0040] Fig. 10 is a top view of a package structure according to some further exemplary embodiments of the present invention. A package structure PS3 shown in Fig. 10 is shown, the Fig. 9, the same reference numerals are used to designate the same or similar parts, and the detailed description is not repeated here. In the above embodiments, the barrier structure BS includes a first dam portion DP1 or a cover portion CP1. However, the invention is not limited thereto, and the barrier structure BS may include both the first dam portion DP1 and the cover portion CP1.

[0041] As in Fig. 10, the package structure PS3 includes, for example, a first passive component PDx1, a second passive component PDx2, a third passive component PDx3, and a fourth passive component PDx4 arranged adjacent to the semiconductor package SM. In some embodiments, barrier structures BS (first dam portions DP1 or a cover portion CP1) are provided between the passive components (PDx1, PDx2, PDx3, PDx4) and the lid structure 510 to separate the passive components (PDx1, PDx2, PDx3, PDx4) from the lid structure 510 and the adhesive material 520. In some embodiments, a first dam portion DP1 encloses all sidewalls of the first passive component PDx1. In some embodiments, a cover portion CP1 covers all side surfaces and a top surface of the third passive component PDx3.Furthermore, in certain embodiments, another first dam portion DP1 may enclose sidewalls of the second passive component PDx2 and the fourth passive component PDx4. In some embodiments, the underfill structure 350 is in contact with the first dam portion DP1 (barrier structure BS), which is arranged adjacent to the second passive component PDx2 and the fourth passive component PDx4. That is, the barrier structure BS may also prevent the underfill structure 350 from propagating to the passive components (PDx1, PDx2, PDx3, PDx4).

[0042] In the exemplary embodiment, four passive components (PDx1, PDx2, PDx3, PDx4) are shown. However, the invention is not limited thereto, and the number of passive components arranged in the package structure can be adjusted based on product requirements. Furthermore, it should be noted that each of the passive components is protected against the propagation of the adhesive material 520 by using one of the various designs of the barrier structures BS described above, or a combination thereof.

[0043] Fig. 11 is a top view of a package structure according to some further exemplary embodiments of the present invention. A package structure PS4 shown in Fig. 11 is shown, the Fig. 10, the same reference numerals are used to designate the same or similar parts, and the detailed description is not repeated here. In the above embodiment, a plurality of barrier structures BS (first dam parts DP1 and / or a cover part CP1) are used to protect the plurality of passive components. However, the invention is not limited thereto. As shown in Fig. 11, for example, only a first dam portion DP1 is provided, which encloses all passive components (PDx1, PDx2, PDx3, PDx4). In some embodiments, the first dam portion DP1 encloses all passive components (PDx1, PDx2, PDx3, PDx4) and the semiconductor package SM. In certain embodiments, the first dam portion DP1 has a first sidewall S1 (outer sidewall) facing the lid structure 510 and a second sidewall S2 (inner sidewall) opposite the first sidewall S1, which faces the passive components (PDx1, PDx2, PDx3, PDx4). In some embodiments, the adhesive material 520 is in contact with the first sidewall S1 (the outer sidewall). In other words, the spreading or leakage of the adhesive material 520 is blocked by the first side wall S1 of the first dam part DP1.

[0044] Fig. 12 is a top view of a package structure according to some further exemplary embodiments of the present invention. A package structure PS5 shown in Fig. 12 is shown, the Fig. 10, the same reference numerals are used to designate the same or similar parts, and the detailed description is not repeated here. As shown in Fig. As shown in Figure 12, the first dam portion DP1, disposed on one side of the first passive component PDx1 and the third passive component PDx3, is in contact with the adhesive material 520 to stop the adhesive material 520. In some embodiments, a second dam portion DP2 encloses the first passive component PDx1 to further protect it. In certain embodiments, a cover portion CP1 is disposed adjacent to the first dam portion DP1 to further protect and cover the third passive component PDx3. Similarly, the first dam portion DP1 and the second dam portion DP2, disposed adjacent to the second passive component PDx2 and the fourth passive component PDx4, are fabricated to enclose three sides of the passive components (PDx2, PDx4).In certain embodiments, the second dam portion DP2 is disposed between the first dam portion DP1 and the passive component PDx1 and is spaced apart from the passive components (PDx2, PDx4) and the first dam portion DP1. In some embodiments, the second dam portion DP2 is fabricated after the first dam portion DP1.

[0045] In the exemplary embodiment, similar to the method for manufacturing the first dam part DP1 and the cover part CP1 already described, the second dam part DP2 can be manufactured by further applying the polymer ink material IM (which has been described with reference to Fig. 2B) is distributed on the circuit substrate 300 in an area located between the first dam portion DP1 and the passive components (PDx1, PDx2, PDx3, PDx4). In certain embodiments, after curing of the polymer ink material IM, a barrier structure BS is formed, which includes a first dam portion DP1, a second dam portion DP2, and a cover portion CP1. In some embodiments, the second dam portion DP2 is separated from the first dam portion DP1 and the cover portion CP1. In certain embodiments, a height of the second dam portion DP2 is different from a height of the first dam portion DP1. However, the invention is not limited thereto, and in the foregoing embodiments, the length, width, height, and design of the dam portions (DP1, DP2) can be adapted. By using the second dam part DP2, the protection of the passive components (PDx1, PDx2, PDx3, PDx4) can be even better achieved.For example, in addition to the first dam part DP1, the second dam part DP2 may act as an additional barrier layer to extend the propagation distance of the adhesive material 520 and prevent the adhesive material 520 from propagating to the passive components (PDx1, PDx2, PDx3, PDx4).

[0046] Fig. 13 is a schematic sectional view of a package structure according to some further exemplary embodiments of the present invention. A package structure PS6 shown in Fig. 13 is shown, the Fig. 2C, the same reference numerals are used to designate the same or similar parts, and the detailed description is not repeated here. As shown in Fig. As shown in Figure 2C, the semiconductor package SM is directed to a chip-on-wafer (CoW) package. In Fig. 13 is used instead of Fig. For example, a semiconductor package SM2 is provided for each of the semiconductor packages SM shown in Figure 2C.

[0047] As in Fig. 13, the semiconductor package SM2 includes: a semiconductor die 602; a dielectric layer 604; an insulating encapsulant material 606; a redistribution layer 608; conductive pads 610; and conductive balls 612. The semiconductor die 602 is disposed on the dielectric layer 604. The insulating encapsulant material 606 is disposed on the dielectric layer 604 to enclose the semiconductor die 602. In some embodiments, the semiconductor die 602 includes: a semiconductor substrate 602A; a plurality of conductive pads 602B; a passivation layer 602C; a post-passivation layer 602D; a plurality of conductive pillars or conductive vias 602E; and a protection layer 602F. As shown in Fig. 13, the plurality of conductive pads 602B are disposed on the semiconductor substrate 602A. The passivation layer 602C is formed over the semiconductor substrate 602A and has openings partially exposing the conductive pads 602B on the semiconductor substrate 602A. The semiconductor substrate 602A may be a bulk silicon substrate or a silicon-on-insulator (SOI) substrate, and in turn, includes active components (e.g., transistors or the like) and optionally passive components (e.g., resistors, capacitors, inductors, or the like) formed therein. The conductive pads 602B may be aluminum pads, copper pads, or other suitable metal pads. The passivation layer 602C may be a protective oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a dielectric layer made of suitable dielectric materials.

[0048] Furthermore, in some embodiments, the post-passivation layer 602D is optionally formed over the passivation layer 602C. The post-passivation layer 602D covers the passivation layer 602C and includes a plurality of contact openings. The conductive pads 602B are partially exposed by the contact openings in the post-passivation layer 602D. The post-passivation layer 602D may be a benzocyclobutene (BCB) layer, a polyimide layer, a polybenzoxazole (PBO) layer, or a dielectric layer made of other suitable polymers. In some embodiments, the conductive pillars or conductive vias 602E are formed by plating on the conductive pads 602B.In some embodiments, the protective layer 602F is formed on the post-passivation layer 602D to cover the conductive pillars or conductive vias 602E to protect the conductive pillars or conductive vias 602E. Note that while only one semiconductor die 602 is illustrated here, the invention is not limited thereto, and the number of semiconductor dies 602 in the semiconductor package SM2 may be more than one.

[0049] As in Fig. 13, a redistribution layer 608 is further formed on the insulating encapsulation material 606, which is electrically connected to the semiconductor die 602. In some embodiments, forming the redistribution layer 608 comprises sequentially forming one or more dielectric layers 608B alternating with one or more metallization layers 608A. In certain embodiments, the metallization layers 608A are sandwiched between the dielectric layers 608B. While only three layers of the metallization layers 608A and four layers of the dielectric layers 608B are illustrated here, the scope of the invention is not limited by the embodiments of the invention. In other embodiments, the number of metallization layers 608A and dielectric layers 608B may be adjusted based on product requirements.In some embodiments, the metallization layers 608A are electrically connected to the conductive pillars 602E of the semiconductor dies 602.

[0050] In some embodiments, a plurality of conductive pads 610 are disposed on an exposed upper surface of the topmost layer of metallization layers 608A for electrically connecting to conductive balls. In certain embodiments, the conductive pads 610 are, for example, UBM structures used for ball mounting. As shown in Fig. As shown in Figure 13, the conductive pads 610 are formed on the redistribution layer 608 and are electrically connected thereto. In some embodiments, materials for the conductive pads 610 may be copper, nickel, titanium, tungsten, or alloys thereof, or the like, and may be formed, for example, by electroplating. The number of conductive pads 610 is not limited in the present invention and may be selected according to the design layout. In some alternative embodiments, the conductive pads 610 may be omitted. In other words, conductive balls 612, which are formed in later steps, may be disposed directly on the redistribution layer 608.

[0051] As in Fig.13, a plurality of conductive balls 612 are disposed on the conductive pads 610 and above the redistribution layer 608. In some embodiments, the conductive balls 612 may be placed on the conductive pads 610 using a ball placement or reflow process. In some embodiments, the conductive balls 612 are, for example, solder balls or BGA balls. In some embodiments, the conductive balls 612 are connected to the redistribution layer 608 via the conductive pads 610. In certain embodiments, some of the conductive balls 612 may be electrically connected to the semiconductor die 602 via the redistribution layer 608. The number of conductive balls 612 is not limited by the invention and may be determined and selected according to the number of conductive pads 610.

[0052] In the exemplary embodiment, the semiconductor package SM2 is arranged on the circuit substrate 300 by flip-chip bonding. In some embodiments, the semiconductor package SM2 is electrically connected to the contact pads 310 of the circuit substrate 300 via the conductive balls 612. In certain embodiments, the conductive balls 612 are in turn protected by the underfill structure 350. Similar to the previous embodiments, electrical failure and / or functional failure of the passive component PDx can be avoided because a barrier structure BS is provided on the circuit substrate 300 to prevent the propagation of the adhesive material 520 to the passive component PDx.

[0053] The package structure includes at least one barrier structure that separates the passive component from the lid structure and the adhesive material. This can prevent leakage or spreading of the adhesive material to the passive component, thus avoiding electrical failure and / or functional failure of the passive component. Furthermore, the barrier structure can act to protect the passive components and prevent tin (Sn) whiskers of the passive components from contacting the lid structure. Furthermore, by using the barrier structure, the encapsulation widths between the passive component and the lid structure can be reduced, allowing a larger semiconductor package to be mounted on the circuit substrate. Overall, a package structure with better reliability and performance can be achieved.

[0054] In some embodiments of the present invention, a package structure is provided including a circuit substrate, a semiconductor package, a lid structure, a passive device, and a barrier structure. The semiconductor package is disposed on the circuit substrate and is electrically connected thereto. The lid structure is disposed on the circuit substrate to cover the semiconductor package, wherein the lid structure is secured to the circuit substrate by an adhesive material. The passive device is disposed on the circuit substrate between the semiconductor package and the lid structure. The barrier structure separates the passive device from the lid structure and the adhesive material, wherein the barrier structure is in contact with the adhesive material.

[0055] In some further embodiments of the present invention, a package structure is provided that includes a circuit substrate, an interposer structure, a plurality of semiconductor dies, a lid structure, a plurality of passive devices, and a plurality of barrier structures. The interposer structure is disposed on the circuit substrate and is electrically connected to the circuit substrate. The plurality of semiconductor dies are disposed on the interposer structure and are electrically connected to the interposer structure. The lid structure is disposed on the circuit substrate and encloses the interposer structure and the plurality of semiconductor dies, wherein the lid structure is attached to the circuit substrate by an adhesive material.The plurality of passive devices is disposed on the circuit substrate between the interposer structure and the lid structure, the plurality of passive devices having a first surface facing the lid structure and a second surface opposite the first surface facing the interposer structure. The plurality of barrier structures is disposed on the circuit substrate between the interposer structure and the lid structure, the plurality of barrier structures separating the first surface of the plurality of passive devices from the lid structure and the adhesive material.

[0056] In yet another embodiment of the present invention, a method for manufacturing a package structure is described. The method comprises the following steps. A semiconductor package is disposed on a circuit substrate. A passive device is disposed on the circuit substrate adjacent to the semiconductor package. A barrier structure is formed on the circuit substrate around the passive device by dispensing a polymer ink material onto the circuit substrate and curing the polymer ink material to create a barrier structure. A lid structure is attached to the circuit substrate by an adhesive material, the barrier structure separating the passive device from the lid structure and the adhesive material, and the lid structure is attached to the circuit substrate such that the adhesive material contacts the barrier structure.

Claims

[1] Package structure with: a circuit substrate (300); a semiconductor package (SM) arranged on the circuit substrate (300) and electrically connected thereto; a lid structure (510) arranged on the circuit substrate (300) so as to cover the semiconductor package (SM), the lid structure (510) being attached to the circuit substrate (300) by an adhesive material (520); a passive device (PDX) arranged on the circuit substrate (300) between the semiconductor package (SM) and the lid structure (510); and a barrier structure (BS) separating the passive device (PDX) from the lid structure (510) and the adhesive material (520), wherein the barrier structure (BS) is in contact with the adhesive material (520), wherein the barrier structure (BS) has a cover portion covering side surfaces and a top surface of the passive device (PDX). [2] The package structure of claim 1, wherein the barrier structure (BS) comprises a first dam portion (PD1) disposed between the passive device (PDX) and the lid structure (510) and spaced apart from the passive device (PDX) and the lid structure (510), and wherein the first dam portion (DP1) has a first sidewall facing the lid structure (510) and a second sidewall opposite the first sidewall facing the passive device (PDX), the first sidewall of the first dam portion (DP1) being in contact with the adhesive material (520). [3] Package structure according to claim 2, wherein the first dam part (DP1) in turn encloses side surfaces of the passive device (PDX). [4] The package structure according to claim 2 or 3, wherein the barrier structure (BS) further comprises a second dam portion (DP2) disposed between the first dam portion (DP1) and the passive device (PDX) and spaced apart from the passive device (PDX) and the first dam portion (DP1). [5] The package structure according to any one of claims 2 to 4, wherein the first dam part (DP1) comprises a lower portion (DP-Bs) and an upper portion (DP-Ts), wherein a width of the first dam part (DP1) decreases from the lower portion (DP-Bs) to the upper portion (DP-Ts). [6] The package structure according to any one of claims 2 to 4, wherein the first dam part (DP1) has a lower portion (DP-Bs), a middle portion (DP-Ms) and an upper portion (DP-Ts), wherein the width of the first dam part (DP1) increases from the lower portion (DP-Bs) to the middle portion (DP-Ms) and the width decreases from the middle portion (DP-Ms) to the upper portion (DP-Ts). [7] Package structure according to claims 1 to 6, wherein the cover part is in contact with the passive device (PDX). [8] Package structure with: a circuit substrate (300); an interposer structure (100, 100') arranged on the circuit substrate (300) and electrically connected to the circuit substrate (300); a plurality of semiconductor dies arranged on the interposer structure (100, 100') and electrically connected to the interposer structure (100, 100'); a lid structure (510) arranged on the circuit substrate (300) and enclosing the interposer structure (100, 100') and the plurality of semiconductor dies, wherein the lid structure (510) is attached to the circuit substrate (300) by an adhesive material (520); a plurality of passive devices (PDX) arranged on the circuit substrate (300) between the interposer structure (100, 100') and the lid structure (510), wherein the plurality of passive devices (PDX) has a first surface (102a) facing the lid structure (510) and a second surface (102b) opposite the first surface (102a) facing the interposer structure (100, 100'); and a plurality of barrier structures (BS) arranged on the circuit substrate (300) between the interposer structure (100, 100') and the lid structure (510), wherein the plurality of barrier structures (BS) separates the first surface (102a) of the plurality of passive devices (PDX) from the lid structure (510) and the adhesive material (520), wherein the plurality of barrier structures (BS) comprises a cover portion covering the first surface (102a), the second surface (102b) and a top surface of the plurality of passive devices (PDX). [9] The package structure of claim 8, wherein the interposer structure (100, 100') is electrically connected to the circuit substrate (300) by a plurality of conductive terminals, and the package structure further comprises an underfill structure (112, 350) enclosing the plurality of conductive terminals, and the plurality of barrier structures (BS) is in contact with the underfill structure (112, 350). [10] The package structure of claim 8 or 9, wherein the plurality of barrier structures (BS) comprises a first dam portion disposed between the plurality of passive devices (PDX) and the lid structure (510) and spaced apart from the plurality of passive devices (PDX) and the lid structure (510), the first dam portion (DP1) having a first sidewall facing the lid structure (510) and a second sidewall opposite the first sidewall facing the plurality of passive devices (PDX), the first sidewall of the first dam portion being in contact with the adhesive material (520). [11] The package structure of claim 10, wherein the plurality of passive devices (PDX) are arranged in an area enclosed by the first dam part (DP1). [12] The package structure according to claim 10 or 11, wherein the first dam part (DP1) comprises a lower portion and an upper portion, wherein a width of the first dam part (DP1) decreases from the lower portion to the upper portion. [13] The package structure according to any one of claims 10 to 12, wherein the plurality of barrier structures (BS) further comprises a second dam portion (DP2) disposed between the first dam portion (DP1) and the plurality of passive devices (PDX) and spaced apart from the plurality of passive devices (PDX) and the first dam portion (DP1), wherein a height of the second dam portion (DP2) is different from a height of the first dam portion (DP1). [14] Method for producing a package structure comprising the following steps: Arranging a semiconductor package (SM) on a circuit substrate (300); Arranging a passive device (PDX) on the circuit substrate (300) adjacent to the semiconductor package (SM); Forming a barrier structure (BS) on the circuit substrate (300) adjacent to the passive device (PDX) by dispensing a polymer ink material onto the circuit substrate (300) and curing the polymer ink material to create a barrier structure (BS); Attaching a lid structure (510) to the circuit substrate (300) by an adhesive material (520), wherein the barrier structure (BS) separates the passive device (PDX) from the lid structure (510) and the adhesive material (520) and the adhesive material (520) contacts the barrier structure (BS), wherein the polymer ink material is distributed on the circuit substrate (300) in an area overlapping the passive device (PDX) so as to cover the passive device (PDX), and after curing of the polymer ink material, the barrier structure (BS) is formed with a cover part covering side surfaces and a top surface of the passive device (PDX). [15] The method of claim 14, wherein the polymer ink material is distributed on the circuit substrate (300) in an area located between the passive device (PDX) and the lid structure (510) and spaced from the passive device (PDX) and the lid structure (510), and after curing of the polymer ink material, the barrier structure (BS) is formed with a first dam portion (DP1), the first dam portion (DP1) having a first sidewall facing the lid structure (510) and a second sidewall opposite the first sidewall facing the passive device (PDX), and the lid structure (510) is attached to the circuit substrate (300) such that the adhesive material (520) contacts the first sidewall. [16] The method of claim 15, wherein the polymer ink material is distributed on the circuit substrate (300) to enclose the passive device (PDX). [17] The method of claim 15 or 16, wherein after forming the first dam portion (DP1), the polymer ink material is further distributed on the circuit substrate (300) in an area located between the first dam portion (DP1) and the passive device (PDX), and after curing the polymer ink material, the barrier structure (BS) is formed with a second dam portion (DP2), the second dam portion (DP2) being separated from the first dam portion (DP1).

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