SENSOR PACKAGE AND PROCESS

Abstract

Device comprising: a sensor die (100) having a detection area on a top side of the sensor die (100); an encapsulation (242) that encapsulates the sensor die (100) at least laterally; a conductive via (116, 216, 258, 260) extending through the encapsulation (242); and a front-side redistribution structure (264) on the encapsulant (242) and on the top surface of the sensor die (100), the front-side redistribution structure (264) being connected to the conductive via (116, 216, 258, 260) and the sensor die (100), an opening (248, 250, 252) in the front-side redistribution structure (264) exposing the sensing area of ​​the sensor die (100), and the front-side redistribution structure (264) comprising a first dielectric layer extending over the encapsulant (242) and the top surface of the sensor die (100), a metallization structure (210, 256) on the first dielectric layer, and a second dielectric layer extending over the metallization structure (210, 256) and the first dielectric layer; wherein a recess (244) is formed in the encapsulation (242) exposing the sensor die (100), and wherein the recess has side walls that are inclined.

Description

BACKGROUNDThe semiconductor industry has experienced rapid growth due to progressive improvements in integration density of a variety of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). The improvement in integration density largely resulted from a repeated reduction in the minimum feature size, allowing more components to be integrated into a particular area. With the increasing demand for shrinking electronic devices, a need has arisen for smaller and more conservative packaging techniques for semiconductor dies. An example of such packaging systems is integrated fan-out (InFO) technology.DE 10 2019, 104 259 A1 discloses a sensor package and a method.BRIEF DESCRIPTION OF THE DRAWINGSAspects of the present disclosure will be best understood from the following detailed description when read with the accompanying drawings. It should be noted that, according to the usual industry practice, various features are not drawn to scale. Indeed, the dimensions of the various features may be increased or decreased as desired for clarity of description.FIGS. 1-4 show cross-sectional views of intermediate steps during a process for forming a sensor die with a sacrificial layer, in accordance with some embodiments.FIGS. 5-18 show cross-sectional views of intermediate steps during a process for forming a sensor package using a dry etching process, in accordance with some embodiments.FIG. 19 shows a cross-sectional view of an intermediate step during a process of forming a sensor device, in accordance with some embodiments.FIGS. 20-27 show cross-sectional views of intermediate steps during a process for forming a sensor package using a wet etching process, in accordance with some embodiments.FIG. 28 shows a cross-sectional view of an intermediate step during a process of forming a sensor device, in accordance with some embodiments.DETAILED DESCRIPTIONThe invention is defined by independent claim 1 defining a device, independent claim 9 defining a package, and independent claim 17 defining a method. Embodiments of the claimed invention are defined by the dependent claims. The following disclosure provides many different embodiments or examples to implement various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, forming a first feature over or on a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first feature and the second feature, such that the first and second features need not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in the various examples. This repetition is for purposes of simplicity and clarity and does not in itself impose any relationship between the various embodiments and / or configurations described.Further, spatially relative terms such as "bottom," "below," "lower," "above," "upper," and the like, may be used herein for convenience of description to describe the relationship of an element or feature with one or more other elements or features as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device being used or operated in addition to the orientation shown in the figures. The device may be otherwise (rotated 90 degrees or oriented in another orientation) oriented and the spatially relative terms used herein may also be interpreted as such.According to some embodiments, a sacrificial layer is formed over a sensor die before the sensor die is packaged as part of a sensor package. The sacrificial layer is removed during the packaging process using a dry etching process or a wet etching process. A redistribution structure may be formed to connect to the sensor die, wherein the sensor package is formed as an integrated fan-out (InFO) package. The sensor package may include openings exposing the sensing areas of the sensor die. Packaging a sensor die in this manner may allow the form factor of the final sensor package to be smaller, may increase the mechanical reliability of the packaged sensor, and may increase manufacturing yield as compared to other packaging schemes (e.g., wire bonding). The sensing areas of the sensor die may also be formed closer to the outside of the sensor package, which may increase the sensitivity and electrical response of the sensing operation.FIGS. 1-4 show cross-sectional views of intermediate steps during a process for forming a sensor die 100 with a sacrificial layer 112, in accordance with some embodiments. FIGS. 5-18 show cross-sectional views of intermediate steps during a process for forming a sensor package 200 using a dry etching process, in accordance with some embodiments. FIG. 19 illustrates a sensor device 300 implementing the sensor package 200 in accordance with some embodiments. FIGS. 20-27 show cross-sectional views of intermediate steps during a process for forming a sensor package 400 using a wet etching process, in accordance with some embodiments. FIG. 28 illustrates a sensor device 500 implementing the sensor package 400 according to some embodiments.FIGS. 1-4 illustrate the formation of a sensor die 100 with a sacrificial layer 112 in accordance with some embodiments. FIG. 1 shows a plurality of sensor dies 100 prior to dicing. As such, the individual sensor dies 100 shown in FIG. 1 are formed on a single substrate 102 and separated by scribe line regions 108.The sensor dies 100 may be formed in the substrate 102 using suitable fabrication processes. The substrate 102 may be, for example, a semiconductor substrate such as silicon, which may be doped or undoped, and which may be a silicon wafer or an active layer of a semiconductor-on-insulator (SOI) substrate, or the like. The semiconductor substrate may include other semiconductor materials such as germanium; a compound semiconductor such as silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates such as multilayer or gradient substrates may also be used. Devices such as transistors, diodes, capacitors, resistors, etc. may be formed in and / or on the active surface of the substrate 102 and may be interconnected by interconnect structures, e.g., formed by metallization structures in one or more dielectric layers on the substrate 102.Each sensor die 100 may include one or more sensors, integrated circuits, logic circuits (e.g., processor units, microcontrollers, etc.), memory (e.g., dynamic random access memory (DRAM), static random access memory (SRAM), etc.), power management circuits (e.g., power management integrated circuits (PMIC)), radio frequency (RF) components, microsystems (MEMS) components, signal processing circuits (e.g., digital signal processing (DSP) circuits), front-end circuits (e.g., analog front-end (AFE) circuits), the like, or a combination thereof.In some embodiments, each sensor die 100 includes a sensor region 110 in which a sensor is formed. The sensor region 110 may include portions formed within the substrate 102 and / or over the substrate 102, and the sensor formed in the sensor region 110 may be spatially and / or electrically connected to integrated circuits, metallization structures, devices, or the like of the associated sensor die 100. The sensor region 110 may include an image sensor, an acoustic sensor, a pressure sensor, a temperature sensor, a MEMS sensor, or the like. The sensor portion 110 may include one or more transducers and may also include one or more features that emit signals for measurement during operation. For example, the sensor portion 110 may include a fingerprint sensor that operates by transmitting ultrasonic acoustic waves and measuring the reflected waves.Each sensor die 100 further includes pads 104, such as aluminum pads, copper pads, or the like, to which external connections are made. The pads 104 are on the active surface of the sensor dies 100. One or more passivation films 106 are on the sensor dies and on portions of the pads 104. Openings extend through the passivation films 106 to expose the pads 104. In some embodiments, an opening in the passivation films 106 exposes the sensor region 110. The opening in the passivation films 106 may have a width W 1 that is between about 5 μm and about 100 μm in some embodiments. In some embodiments, the sensor die 100 is packaged in an InFO package and packaged in a manner that exposes the sensor area 110.In FIG. 2, a sacrificial layer 112 is formed over the substrate 102 to cover the sensor dies 100, in accordance with some embodiments. In some embodiments, sacrificial layer 112 may be cured after being formed over substrate 102. The sacrificial layer 112 may include, for example, a material that may be subsequently removed by an etching process such as a wet etching process and / or a dry etching process. In some embodiments, sacrificial layer 112 includes a material that enables curing and subsequent removal using an etching process of sacrificial layer 112. In some embodiments, sacrificial layer 112 includes a material that can cure sacrificial layer 112 and subsequently planarized, such as using a chemical mechanical polishing (CMP) process or a grinding process. The sacrificial layer 112 may include a polymer such as a polyimide, epoxy, polyolefin, or the like, or a composite material such as a polymer with one or more additives (e.g., stress relief agents, plasticizers, etc.) incorporated to adjust one or more material properties of the polymer. The sacrificial layer 112 may be formed by any suitable deposition process, such as spin coating, laminating, liquid dispensing, the like, or a combination thereof. Sacrificial layer 112 may have a thickness T 1 over substrate 102, which in some embodiments is between about 2 μm and about 50 μm.Referring to FIGS. 3 and 4, a dicing process is performed to dicing individual sensor dies 100, in accordance with some embodiments. The dicing process is performed along the scribe regions 108 and may include sawing, laser drilling, or the like, or a combination thereof. In some embodiments, the dicing process includes forming a groove in the scribe regions 108 using a laser process and then performing a dicing process to completely dicing the sensor dies 100. For example, FIG. 3 shows the substrate 102 after a laser process has been performed. As shown in FIG. 3, the laser process may be performed along the scribe regions 108 to form grooves that extend through the sacrificial layer 112 and into the substrate 102. The laser process may use, for example, a UV laser or the like, which in some embodiments is operated at a power between about 1 W and about 30 W.After the laser process is performed, a dicing process may be performed along the dicing regions 108 to fully dicing the sensor dies 100, as shown in FIG. 4. Using a laser process to remove portions of the sacrificial layer 112 prior to sawing may reduce damage to the sacrificial layer 112 during the dicing process. In some embodiments, sacrificial layer 112 over sensor die 100 may have a convex or rounded top, as shown in FIG. 4. In this way, individual sensor dies 100 are formed that are covered in the sacrificial layer 112.FIGS. 5-26 show intermediate steps in the formation of sensor package 200 (see FIG. 18 ), sensor device 300 (see FIG. 19 ), sensor package 400 (see FIG. 27 ), and sensor device 500 (see FIG. 28 ), in accordance with some embodiments. FIGS. 5-9 illustrate intermediate steps performed prior to removing sacrificial layer 112, in accordance with some embodiments. FIGS. 10-19 show intermediate steps in removing sacrificial layer 112 using a dry etching process to form a sensor package 200 and a sensor device 300 in accordance with some embodiments. FIGS. 20-28 show intermediate steps in removing sacrificial layer 112 using a wet etching process to form a sensor package 400 and a sensor device 500, in accordance with some embodiments.In FIG. 5, a support substrate 202 is provided, and a separation layer 204 is formed on the support substrate 202. The carrier substrate 202 can be, for example, a glass carrier substrate, a ceramic carrier substrate or the like. The carrier substrate 202 may be a wafer such that multiple packages may be formed simultaneously on the carrier substrate 202. The release layer 204 may be formed of a polymer-based material that may be removed, along with the carrier substrate 202, from the overlying structures formed in subsequent steps. In some embodiments, the release layer 204 is an epoxy-based thermal release material that loses its adhesion property when heated, such as a light-heat conversion (LTHC) release coating. In other embodiments, the release layer 204 may be an ultraviolet (UV) adhesive that loses its adhesive property when exposed to UV light. The release layer 204 may be dispensed as a liquid and cured, may be a laminate film laminated to the support substrate 202, or the like. The top surface of the separation layer 204 may be planarized and have a high degree of coplanarity.In FIG. 6, a back redistribution structure 206 and conductive vias 216 are formed on the isolation layer 204, in accordance with some embodiments. In the embodiment shown, the back side redistribution structure 206 includes a dielectric layer 208 and a metallization structure 210 (sometimes referred to as redistribution layers or redistribution lines). The back redistribution structure 206 is optional. In some embodiments, metallization pattern 210 is omitted and only dielectric layer 208 is formed.The dielectric layer 208 is formed on the separation layer 204. The bottom surface of the dielectric layer 208 may be in contact with the top surface of the separation layer 204. In some embodiments, the dielectric layer 208 is formed from a polymer such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or the like. In other embodiments, the dielectric layer 208 is formed of a nitride such as silicon nitride; an oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron doped phosphosilicate glass (BPSG), or the like; or the like. The dielectric layer 208 may be formed by any suitable deposition process, such as spin coating, chemical vapor deposition (CVD), lamination, or the like, or a combination thereof.The metallization pattern 210 is formed on the dielectric layer 208. As an example process for forming metallization pattern 210, a seed layer is formed over dielectric layer 208. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer including a plurality of sub-layers formed from different materials. In some embodiments, the seed layer is comprised of a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, physical vapor deposition (PVD) or the like. A photoresist is then formed and patterned on the seed layer. The photoresist may be formed by spin coating or the like and exposed for patterning. The pattern of the photoresist corresponds to metallization pattern 210. The patterning forms openings through the photoresist that expose the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be formed by plating, for example, electroplating or electroless plating, or the like. The conductive material may be a metal such as copper, titanium, tungsten, aluminum, or the like, or combinations thereof. Then, the photoresist and portions of the seed layer on which the conductive material is not formed are removed. The photoresist may be removed by a suitable ashing or stripping method, for example, using an oxygen plasma or the like. After the photoresist is removed, exposed portions of the seed layer are removed, for example, using a suitable etching process, for example, by wet or dry etching. The remaining portions of the seed layer and the conductive material form the metallization pattern 210.It should be appreciated that the backside redistribution structure 206 may include any number of dielectric layers and metallization structures. Additional dielectric layers and metallization patterns may be formed by repeating the processes for forming the dielectric layer 208 and the metallization pattern 210. The metallization structures may include conductive traces and conductive vias. The conductive vias may be formed during the formation of the metallization pattern by forming the seed layer and the conductive material of the metallization pattern in the opening of the underlying dielectric layer. The conductive vias may therefore interconnect and electrically connect the various conductive traces to one another. In some embodiments, the back side redistribution structure 206 includes a top dielectric or passivation layer covering and protecting the metallization structure 210. In the embodiment shown, the top layer is omitted and the subsequently formed encapsulant 242 is used to protect the metallization pattern 210.Referring to FIG. 6, conductive vias 216 are formed on and extending from dielectric layer 208. As an example process for forming the conductive vias 216, a seed layer is formed over the backside redistribution structure 206, e.g., on the dielectric layer 208 and the metallization structure 210. The seed layer for the conductive vias 216 may be different from the seed layer for the metallization pattern 210 and may be further formed over the metallization pattern 210. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising a plurality of sub-layers formed from different materials. In a particular embodiment, the seed layer is comprised of a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using PVD or the like, for example. A photoresist is formed and patterned on the seed layer. The photoresist may be formed by spin coating or the like and exposed for patterning. The pattern of the photoresist corresponds to the conductive vias. The patterning forms openings through the photoresist that expose the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be formed by plating, for example, electroplating or electroless plating, or the like. The conductive material may be a metal such as copper, titanium, tungsten, aluminum, or the like, or combinations thereof. The photoresist and the portions of the seed layer on which the conductive material is not formed are removed. The photoresist may be removed by a suitable ashing or stripping method, for example, using an oxygen plasma or the like. After the photoresist is removed, exposed portions of the seed layer are removed, for example, using a suitable etching process, for example, by wet or dry etching. The remaining portions of the seed layer and the conductive material form the conductive vias 216. In the embodiment shown, the conductive vias 216 are formed directly on the dielectric layer 208 and connected to the metallization pattern 210 by conductive traces. In further embodiments, the conductive vias 216 are plated out of features of the metallization pattern 210. The conductive vias 216 may be formed to have a height above the back redistribution structure 206 that is greater than the height of an attached sensor die 100, which will be described below.In FIG. 7, a sensor die 100 is attached to the back redistribution structure 206 by an adhesive 228. The adhesive 128 is formed on the back side of the sensor die 100 and adheres the sensor die 100 to the dielectric layer 208 of the back side redistribution structure 206. The adhesive 228 may be any suitable adhesive, epoxy, die attach film (DAF), or the like. The adhesive 228 may be applied to a back side of the sensor die 100, or may be applied over the dielectric layer 208. For example, the adhesive 228 may be applied to the back side of the sensor die 100 prior to dicing to separate the sensor die 100.Although a sensor die 100 is shown bonded to the back redistribution structure 206, it should be appreciated that more than one sensor die 100 may be bonded and present in the final sensor package 200. In such embodiments, the sensor dies 100 may vary in size and type. In some embodiments, the sensor die 100 may be comprised of a die having a large footprint, such as a system on chip (SoC) device. In embodiments where the sensor dies 100 have a large footprint, the space available for the conductive vias 216 may be limited. The use of the back redistribution structure 206 enables an improved interconnect arrangement when the sensor package 200 has only limited space available for the conductive vias 216. In embodiments where a single sensor die 100 is used, logic dies, memory dies, or a combination thereof may also be included in the sensor die 100.In FIG. 8, an encapsulant 242 is formed on the various components, in accordance with some embodiments. After formation, the encapsulant 242 encapsulates the conductive vias 216 and the sensor die 100 at least laterally. The metallization pattern 210 is thus arranged between the encapsulant 242 and the dielectric layer 208. The encapsulant 242 may be a molding compound, an epoxy, a resin, or the like. In some embodiments, the encapsulant 242 includes a fill material, such as particles of silicon oxide or the like. The encapsulant 242 may be applied by compression molding, transfer molding, or the like. The encapsulant 242 may then be cured. Referring to FIG. 9, a planarization process is performed, in accordance with some embodiments. The planarization process may include a CMP process, a grinding process, or the like. The planarization process may expose conductive vias 216 and sacrificial layer 112. In some cases, the surfaces of the conductive vias 216, the sacrificial layer 112, and the encapsulant 242 are planar after the planarization process.FIGS. 10-19 illustrate forming a sensor package 200 and a sensor device 300 in accordance with some embodiments. The sensor package 200 (see FIG. 18 ) is a package including the sensor die 100, and the sensor device 300 (see FIG. 19 ) is a device including the sensor package 200, according to some embodiments. FIGS. 10-19 describe a process flow in which a dry etching process is used to remove sacrificial layer 112. Accordingly, the material of sacrificial layer 112 may be a material selected for removability by a dry etching process.In FIG. 10, a dry etching process is performed to remove the sacrificial layer 112 from the structure shown in FIG. 9, in accordance with some embodiments. As shown in FIG. 10, the dry etching process removes the sacrificial layer 112 over the sensor die 100 and forms a recess 244 in the encapsulant 242 exposing the sensor region 110 and the pads 104 of the sensor die 100. In some cases, the dry etching process also etches portions of the encapsulant 242, which may form a recess 244 with sloped sidewalls, as shown in FIG. 10. In some embodiments, upper portions of the sidewalls of the recess 244 may have an angle A 1 with respect to a lateral direction that is between about 5 degrees and about 60 degrees. In some embodiments, lower portions of the sidewalls of the recess 244 may have an angle A 2 with respect to a vertical direction that is between about 0 degrees and about 15 degrees. In some cases, by forming the recess 244 with sloped sidewalls, subsequently formed layers such as the dielectric layer 246 (described below) may have a more uniform topography, which may reduce photolithographic variability (e.g., of the openings 248, 250, and 252 described below) and may reduce thickness variability in subsequently formed conductive features (e.g., metallization pattern 256 described below).In some embodiments, the dry etching process includes a plasma etching process. The plasma etching process may include, for example, forming a plasma of oxygen, argon, CF 4 CHF 3, SF 6, the like, or a combination thereof. In some embodiments, the plasma etching process includes an ion bombardment process. In some embodiments, the plasma etching process is performed using a power between about 100 watts and about 1000 watts. Other process gases, performance, or other process conditions are possible.In some cases, the dry etching process etches the encapsulant 242 such that the conductive vias 216 protrude beyond the encapsulant 242, as shown in FIG. 10. In some cases, the conductive vias 116 may protrude from the encapsulant 242 between about 0.5 μm and about 5 μm. In some cases, surfaces of the encapsulant 242 are roughened by the dry etching process when these surfaces are etched by the dry etching process. In some cases, the dry etching process diamonds surfaces of the passivation films 106 when these surfaces of the passivation films 106 are exposed by the dry etching process. In some cases, after performing the dry etching process, the roughness of the surfaces of the encapsulant 242 and / or the roughness of the surfaces of the passivation films 106 may be between about Ra=1 μm and about Ra=10 μm. For example, the roughness of the surfaces of the passivation films 106 may be about Ra=1.03 μm, although other amounts of roughness are possible. After performing the dry etching process, the encapsulant 242 may have a corrugated surface. Additionally, the dry etching process may expose fill material of the encapsulant 242, and the exposed fill material may have rounded or roughened exposed surfaces by the dry etching process. In some embodiments, a cleaning process (e.g., a wet chemical process, a rinse, or the like) may be performed after the dry etching process to remove residue or particles. In some embodiments, a cleaning process is not performed after the dry etching process.FIGS. 11 through 16 illustrate forming a front side redistribution structure 264 (see FIG. 16 ) over the conductive vias 216, encapsulant 242, and sensor die 100, in accordance with some embodiments. The front side redistribution structure 264 includes a dielectric layer 246, a metallization structure 256, and a dielectric layer 262. The metallization structures may also be referred to as redistribution layers or redistribution lines. The front side redistribution structure 264 is shown as an example, and an example process for forming the front side redistribution structure 264 is described herein. More or fewer dielectric layers and metallization structures may be formed in the front side redistribution structure 264. If more dielectric layers and metallization structures are to be formed, steps and processes described below may be repeated. The front side redistribution structure 264 described herein may be used to electrically connect conductive features (e.g., the conductive vias 216) to the sensor die 100. By forming a front side redistribution structure 264 as described herein, a sensor package having a smaller size (e.g., thickness or area) may be formed. For example, a front side redistribution structure 264 may be used to form electrical connections in a sensor package, rather than using a wire bonding technique. The front side redistribution structure 264 may have a lower overall thickness than wire bonding, resulting in a thinner sensor package. Additionally, the use of a relatively thin redistribution structure 264 on the front side may allow the sensor portion 110 of the sensor die 100 to be closer to the outer surface of the sensor package. This allows the sensor region 110 to be closer to the environment to be detected, which can improve sensitivity and response time of the detection operation.In FIG. 11, the dielectric layer 246 is deposited over the structure, in accordance with some embodiments. In some embodiments, the dielectric layer 246 is formed of a material such as PBO, polyimide, BCB, or the like. In some embodiments, the dielectric layer 246 is formed of a photosensitive material that may be patterned using a lithography mask. The dielectric layer 246 may be formed by spin coating, lamination, CVD, or the like, or a combination thereof. As shown in FIG. 11, the tops of the dielectric layer 246 may be higher in regions above the encapsulant 242 and lower in regions above the sensor die 100. In further embodiments, the top surfaces of the dielectric layer 246 over the encapsulant 242 and over the sensor die 100 are approximately planar. In some embodiments, the dielectric layer 246 may have a thickness T 2 over the sensor die 100 that is between about 2 μm and about 50 μm. In some embodiments, the dielectric layer 246 over the sensor die 100 may have a height above the back redistribution structure 206 that is lower than a height of the encapsulant 242 above the back redistribution structure 206. In other words, the thickness T 2 may be such that a top surface of the dielectric layer 246 is below a top surface of the encapsulant 242. In some embodiments, a thickness T 3 between an upper corner region of the encapsulant 242 and a top surface of the dielectric layer 246 is between about 2 μm and about 10 μm. In some cases, a sufficient thickness of the dielectric layer 246 near the top corners of the encapsulant 242 may reduce thickness variability in subsequently formed conductive features (e.g., the metallization pattern 256 described below). In some cases, due to the roughness of the encapsulant 242, the dielectric layer 246 over the encapsulant 242 may have a roughness between about Ra=2 μm and about Ra=7 μm.As shown in FIG. 11, portions of the dielectric layer 246 that extend from about above the encapsulant 242 to above the sensor die 100 may have sloped tops. In some embodiments, upper portions of the sloped tops may have an angle A3with respect to a lateral direction that is between about 20 degrees and about 60 degrees. In some embodiments, lower portions of the sloped tops may have an angle A 4 with respect to a top surface of the dielectric layer 246 over the sensor die 100 that is between about 105 degrees and about 170 degrees. In some cases, by forming the dielectric layer 246 with sloped tops that extend over the encapsulant 242 and the sensor die 100, subsequently formed layers such as the dielectric layer 262 (described below) may have a more uniform topography and thickness variability in subsequently formed conductive features (e.g., metallization pattern 256 described below) may be reduced.In FIG. 12, the dielectric layer 246 is patterned to form openings 248, 250, and 252, in accordance with some embodiments. The openings 248 are formed to expose the conductive vias 216, the opening 250 is formed to expose the sensor region 110 of the sensor die 100, and the openings 252 are formed to expose the pads 104 of the sensor die 100. The patterning may be performed using a suitable photolithography process, for example, exposing the dielectric layer 246 to light when the dielectric layer 246 is a photosensitive material and developing the dielectric layer 246. The patterning may alternatively be performed by forming a patterned mask over the dielectric layer 246 and then etching the dielectric layer 246 using, for example, anisotropic etching.Referring to FIGS. 13 through 15, metallization pattern 256 of front side redistribution structure 264 is formed, in accordance with some embodiments. To form metallization pattern 256, a seed layer (not shown) is first formed over dielectric layer 246 and in openings 248, 250, and 252 that extend through dielectric layer 246. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising a plurality of sub-layers formed from different materials. In some embodiments, the seed layer is comprised of a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using PVD or the like, for example.Referring to FIG. 13, a photoresist 254 is then formed over the seed layer and patterned, in accordance with some embodiments. The photoresist 254 may be formed by spin coating, lamination, or the like. Patterning of the photoresist 254 may be performed using a suitable photolithography process, for example, exposing the photoresist 254 to light and developing the photoresist 254. The patterning forms openings through the photoresist 254 to expose portions of the seed layer corresponding to the metallization pattern 256. As shown in FIG. 13, the photoresist 254 may be patterned such that the conductive vias 216 are exposed through the openings 248 and the contact pads 104 are exposed through the openings 252. The opening 250 may remain at least partially filled by the photoresist 254 to protect the sensor region 110 of the sensor die 100.In FIG. 14, a conductive material is then formed in the openings of the photoresist 254 and on the exposed portions of the seed layer, in accordance with some embodiments. The conductive material may be formed by plating, for example, electroplating or electroless plating, or the like. The conductive material may be a metal such as copper, titanium, tungsten, aluminum, or the like, or combinations thereof. In some cases, the conductive material may be formed in different areas having different thicknesses. For example, portions of the conductive material over the sensor die 100 may have a higher thickness than portions of the conductive material over the encapsulant 242. The combination of the conductive material and the underlying portions of the seed layer forms metallization pattern 256. Metallization pattern 256 includes conductive traces on the main surface of dielectric layer 246 extending therealong. Metallization pattern 256 further includes conductive vias 258 extending through dielectric layer 246 to be spatially and electrically connected to conductive vias 216, and conductive vias 260 extending through dielectric layer 246 to be spatially and electrically connected to contact pads 104 of sensor die 100.In FIG. 15, the photoresist 254 and portions of the seed layer on which the conductive material is not formed are then removed. The photoresist may be removed by a suitable ashing or stripping method, for example, using an oxygen plasma or the like. After the photoresist is removed, exposed portions of the seed layer are removed, for example, using a suitable etching process, for example, by wet or dry etching. By removing the photoresist 254 and the seed layer, the sensor region 110 is exposed through the opening 250 in the dielectric layer 246.In FIG. 16, the dielectric layer 262 is deposited and patterned on the metallization pattern 256 and the dielectric layer 246, such that the front side redistribution pattern 264 is formed, in accordance with some embodiments. The dielectric layer 262 may be formed in a similar manner to the dielectric layer 246 and may be formed of the same material as the dielectric layer 246. The dielectric layer 262 is patterned so as to expose the sensor region 110 of the sensor die 100. In this manner, the opening 250 is extended by the dielectric layer 262. The structuring of the dielectric layer 262 may be performed in a similar manner as the structuring of the dielectric layer 246. After patterning the dielectric layer 262, the opening 250 has a depth D 1, which extends from a main surface of the dielectric layer 262 to an uppermost surface of the sensor die 100. In some embodiments, the depth D 1 is in a range between about 2 μm and about 100 μm.The opening 250 extends through the dielectric layers 246 and 262 of the front side redistribution structure 264. The metallization pattern 256 is not formed in the opening 250, such that the opening 250 is free of the materials of the front side redistribution structure 264 (e.g., materials of the metallization pattern 256 and the dielectric layers 246 and 262). In some embodiments, the dielectric layer 262 is patterned such that the portion of the opening that extends through the dielectric 262 has a greater width than the portion of the opening that extends through the dielectric layer 246. For example, the sidewall of the dielectric layer 262 may be offset from the sidewall of the dielectric layer 246 by a width W 2 that is between about 0 μm and about 100 μm, such as about 20 μm. In some cases, a greater offset may allow for greater exposure of the sensor region 110 to the sensed environment, which may increase the sensitivity and responsiveness of the sensing operation.In FIG. 17, a carrier substrate debond process is performed to release the carrier substrate 202 from the adhesive 228 and the backside redistribution structure 206 (e.g., dielectric layer 208) ("debond"). Openings are then formed through the dielectric layer 208, in accordance with some embodiments, to expose portions of the metallization pattern 210 and / or the conductive vias 216. In some embodiments, the debond process includes projecting a light such as a laser light or a UV light onto the release layer 204 such that the release layer 204 decomposes under the heat of the light and the carrier substrate 202 can be removed. The structure is then inverted and laid on a tape 160. The openings in the dielectric layer 208 may be formed using, for example, laser drilling, etching, or the like. A cleaning process may be performed after a laser drilling process to remove remaining debris (e.g., the dielectric layer 208).In FIG. 18, conductive connectors 266 are formed in the openings in the dielectric layer 208 to form the sensor package 200, in accordance with some embodiments. The conductive connectors 266 may be spatially and electrically connected to the metallization pattern 210 and / or the conductive vias 216. The conductive connectors 266 may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination thereof. In some embodiments, the conductive connectors 266 are formed by initially forming a solder layer by such commonly used methods as evaporation, electroplating, printing, solder transfer, ball placement, or the like. After a layer of solder is formed on the structure, reflow may be performed to form the material into the desired bump shape. In some embodiments, the conductive connectors 266 contain flux and are formed in a flux dipping process. In some embodiments, the conductive connectors 266 include a conductive paste such as solder paste, silver paste, or the like, and are dispensed in a printing process.In some embodiments, multiple sensor packages 200 are formed on a single carrier substrate 202, and a dicing process is performed to form the single sensor packages 200. The singulating process may be sawing, laser drilling or the like, for example. By forming a sensor package 200 as described herein (e.g., using a sacrificial layer 112 and removing the sacrificial layer 112 using a dry etching process), the thickness of the sensor package 200 may be reduced. In addition, the sensor region 110 may be formed closer to the top surface of the sensor package 200 (e.g., the top surface of the dielectric layer 262), which may improve sensing performance.In FIG. 19, the sensor package 200 is attached to a package substrate 302 using the conductive connectors 266 to form a sensor device 300 according to some embodiments. The package substrate 302 may be made of a semiconductor material such as silicon, germanium, diamond, or the like. Alternatively, compound materials such as silicon germanium, silicon carbide, gallium arsenic, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenic phosphide, gallium indium phosphide, combinations thereof, and the like may also be used. Additionally, the package substrate 302 may be an SOI substrate. Generally, an SOI substrate includes a layer of a semiconductor material such as epitaxial silicon, germanium, silicon germanium, SOI, SGOI, or combinations thereof. The package substrate 302 is based on an insulating core such as a fiberglass reinforced resin core in an alternative embodiment. An example of a core material is a glass fiber resin such as FR4. Alternatives for the core material include bismaleimide triazine BT resin or alternatively other PCB materials or films. Build-up films such as ABF or other laminates may be used for the package substrate 302.The package substrate 302 may include active and passive devices (not shown). As will be appreciated by those of ordinary skill in the art, a wide variety of devices such as transistors, capacitors, resistors, combinations thereof, and the like may be used to meet the structural and functional requirements of the design for the sensor device 300. The devices may be manufactured using any suitable methods.Package substrate 302 may also include metallization layers and vias (not shown) and bond pads 304 over the metallization layers and vias. The metallization layers may be formed over the active and passive devices and may be configured to connect the various devices to form functional circuits. The metallization layers may be formed from alternating layers of a dielectric (e.g., a low-k dielectric) and conductive material (e.g., copper), with vias interconnecting the layers of conductive material, and may be formed by any suitable process (e.g., deposition, damascene, dual damascene, or the like). In some embodiments, the package substrate 302 is substantially free of active and passive devices.In some embodiments, the conductive connectors 266 are reflowed to attach the sensor package 200 to the bond pads 304. The conductive connectors 266 electrically and / or spatially connect the package substrate 302, for example, the metallization layers in the package substrate 302, to the sensor package 200. In some embodiments, passive devices (e.g., surface mount devices (SMDs), not shown) may be attached (e.g., connected to bond pads 304) to the sensor device 300 before it is mounted on the package substrate 302. In such embodiments, the passive devices may be connected to the same surface of the sensor device 300 as the conductive connectors 266.The conductive connectors 266 may include an epoxy flux (not shown) formed thereon before being reflowed, leaving at least a portion of the epoxy portion of the epoxy flux after the sensor package 200 is attached to the package substrate 302. This remaining epoxy portion may serve as an underfill to reduce stresses and protect the connections resulting from the reflow of the conductive connectors 266. In some embodiments, an underfill (not shown) may be formed between the sensor package 200 and the package substrate 302 surrounding the conductive connectors 266. The underfill may be formed by a capillary flow process after the sensor package 200 is attached, or may be formed by a suitable deposition method before the sensor package 200 is attached.FIGS. 20-28 illustrate forming a sensor package 400 and a sensor device 500 in accordance with some embodiments. The sensor package 400 (see FIG. 27 ) is a package including the sensor die 100, and the sensor device 500 (see FIG. 28 ) is a device including the sensor package 400, according to some embodiments. The process shown in FIGS. 20-28 is similar to that shown in FIGS. 10-19 that forms the sensor package 200 and the sensor device 300 except that a wet etching process is used to remove the sacrificial layer 112 from the sensor die 100. Accordingly, the material of sacrificial layer 112 may be a material selected to be removed by a wet etching process. In some instances, certain process steps or features in the embodiment shown in Figures 20-26 are similar to analogous process steps or features of the embodiment shown in Figures 10-19, and therefore, some details are not repeated.In FIG. 20, a wet etching process is performed to remove the sacrificial layer 112 of the structure shown in FIG. 9, in accordance with some embodiments. As shown in FIG. 20, the wet etching process removes the sacrificial layer 112 over the sensor die 100 and forms a recess 244 in the encapsulant 242 exposing the sensor region 110 and the pads 104 of the sensor die 100. In some cases, the wet etching process etches portions of the encapsulant 242 very little or not, which may form a recess 244 with inwardly sloped top sidewalls, as shown in FIG. 20. In some embodiments, upper portions of the sidewalls of the recess 244 may have an angle A 5 with respect to a lateral direction that is between about 105 degrees and about 150 degrees. In some cases, layers formed subsequently, such as dielectric layer 246, by forming a recess 244 with inwardly sloped upper sidewalls may have a more uniform topography, which may reduce photolithographic variability (e.g., of openings 248, 250, and 252) and reduce thickness variability in subsequently formed conductive features (e.g., metallization pattern 256).The wet etching process may include, for example, immersing the structure in a wet chemical mixture containing a solvent such as DMSO, NMP, IPA, or the like and one or more additives such as a Cu corrosion inhibitor, a stabilizer, the like, or a combination thereof. In some embodiments, the wet chemical mixture may have a temperature between about 25° C. and about 90° C., such as about 50° C. In some embodiments, the wet etching process may be performed for a time period between about 30 seconds and about 600 seconds, such as about 120 seconds, during the wet etching process. In some cases, performing the wet etching process for about 120 seconds may be sufficient to adequately etch the sacrificial layer 112, and a drying time of 10 minutes or less may be sufficient to dry the structure after performing the wet etching process. In some cases, using a wet etching process to remove the sacrificial layer 112 may reduce the overall processing time or cost for a sensor package.In some cases, after performing the wet etching process, the conductive vias 216 are recessed below the top of the encapsulant 242. In some cases, the conductive vias 216 may be recessed between about 0.7 μm and about 2 μm below the encapsulant 242. In some cases, after performing the wet etching process, the surfaces of the encapsulant 242 and / or the passivation films 106 maintain a low degree of roughness (e.g., Ra of less than about 0.5 μm, for example about 0.03 μm). In some embodiments, the surface of the encapsulant 242 is substantially flat after performing the wet etching process. In some cases, the fill material of the encapsulant 242 is exposed by the wet etching process, and the exposed surfaces of the fill material are substantially flat after performing the wet etching process. In some embodiments, the wet etching process also acts as a cleaning process for removing debris or particles, and a separate cleaning process is not performed after the wet etching process.FIGS. 21-26 illustrate forming a front side redistribution structure 264 (see FIG. 26 ) over the conductive vias 216, encapsulant 242, and sensor die 100, in accordance with some embodiments. The front side redistribution structure 264 includes a dielectric layer 246, a metallization structure 256, and a dielectric layer 262. The front side redistribution structure 264 described herein may be used to electrically connect conductive features (e.g., the conductive vias 216) to the sensor die 100. By forming a front side redistribution structure 264 as described herein, a sensor package having a smaller size (e.g., thickness or area) may be formed. For example, a front side redistribution structure 264 may be used to form electrical connections in a sensor package, rather than using a wire bonding technique. The front side redistribution structure 264 may have a lower overall thickness than wire bonding, resulting in a thinner sensor package. Additionally, the use of a relatively thin redistribution structure 264 on the front side may allow the sensor portion 110 of the sensor die 100 to be closer to the outer surface of the sensor package. This allows the sensor region 110 to be closer to the environment to be detected, which can improve sensitivity and response time of the detection operation.In FIG. 21, the dielectric layer 246 is deposited over the structure, in accordance with some embodiments. As shown in FIG. 21, the tops of the dielectric layer 246 may be higher in regions above the encapsulant 242 and lower in regions above the sensor die 100. In further embodiments, the top surfaces of the dielectric layer 246 over the encapsulant 242 and over the sensor die 100 are approximately planar. In some embodiments, the dielectric layer 246 may have a thickness T 4 over the sensor die 100 that is between about 5 μm and about 150 μm. In some embodiments, the dielectric layer 246 over the sensor die 100 may have a height above the back redistribution structure 206 that is lower than a height of the encapsulant 242 above the back redistribution structure 206. In other words, the thickness T 4 may be such that a top surface of the dielectric layer 246 is below a top surface of the encapsulant 242. In some embodiments, a thickness T 5 between an upper corner region of the encapsulant 242 and a top surface of the dielectric layer 246 is between about 2 μm and about 10 μm. In some cases, a sufficient thickness of the dielectric layer 246 near the top corners of the encapsulant 242 may reduce thickness variability in subsequently formed conductive features (e.g., the metallization pattern 256). In some cases, the dielectric layer 246 over the encapsulant 242 may have a roughness of less than about Ra=0.2 μm.As shown in FIG. 21, portions of the dielectric layer 246 that extend from about above the encapsulant 242 to above the sensor die 100 may have sloped tops. In some embodiments, upper portions of the sloped tops may have an angle A 6 with respect to a lateral direction that is between about 5 degrees and about 45 degrees. In some embodiments, lower portions of the sloped tops may have an angle A 7 with respect to a top surface of the dielectric layer 246 over the sensor die 100, which is between about 105 degrees and about 170 degrees. In some cases, subsequently formed layers such as the dielectric layer 262 may have a more uniform topography by forming the dielectric layer 246 with sloped tops extending over the encapsulant 242 and the sensor die 100, and thickness variability in subsequently formed conductive features (e.g., the metallization pattern 256) may be reduced.In FIG. 22, the dielectric layer 246 is patterned to form openings 248, 250, and 252, in accordance with some embodiments. The openings 248 are formed to expose the conductive vias 216, the opening 250 is formed to expose the sensor region 110 of the sensor die 100, and the openings 252 are formed to expose the pads 104 of the sensor die 100. The patterning may be performed using a suitable photolithography process, for example, exposing the dielectric layer 246 to light when the dielectric layer 246 is a photosensitive material and developing the dielectric layer 246.Referring to FIGS. 23-25, metallization pattern 256 of front side redistribution structure 264 is formed, in accordance with some embodiments. To form metallization pattern 256, a seed layer (not shown) is first formed over dielectric layer 246 and in openings 248, 250, and 252 that extend through dielectric layer 246. Referring to FIG. 23, a photoresist 254 is then formed over the seed layer and patterned, in accordance with some embodiments. As shown in FIG. 23, the photoresist 254 may be patterned such that the conductive vias 116 are exposed through the openings 248 and the contact pads 104 are exposed through the openings 252. The opening 250 may remain at least partially filled by the photoresist 254 to protect the sensor region 110 of the sensor die 100.In FIG. 24, a conductive material is then formed in the openings of the photoresist 254 and on the exposed portions of the seed layer, in accordance with some embodiments. The conductive material may be formed by plating, for example, electroplating or electroless plating, or the like. The conductive material may be a metal such as copper, titanium, tungsten, aluminum, or the like, or combinations thereof. In some cases, the conductive material may be formed in different areas having different thicknesses. For example, portions of the conductive material over the sensor die 100 may have a higher thickness than portions of the conductive material over the encapsulant 242. The combination of the conductive material and the underlying portions of the seed layer forms metallization pattern 256. Metallization pattern 256 includes conductive traces on the main surface of dielectric layer 246 extending therealong. Metallization pattern 256 further includes conductive vias 258 extending through dielectric layer 246 to be spatially and electrically connected to conductive vias 216, and conductive vias 260 extending through dielectric layer 246 to be spatially and electrically connected to contact pads 104 of sensor die 100.In FIG. 25, the photoresist 254 and portions of the seed layer on which the conductive material is not formed are then removed. The photoresist may be removed by a suitable ashing or stripping method, for example, using an oxygen plasma or the like. After the photoresist is removed, exposed portions of the seed layer are removed, for example, using a suitable etching process, for example, by wet or dry etching. By removing the photoresist 254 and the seed layer, the sensor region 110 is exposed through the opening 250 in the dielectric layer 246.In FIG. 26, the dielectric layer 262 is deposited and patterned on the metallization pattern 256 and the dielectric layer 246, such that the front side redistribution pattern 264 is formed, in accordance with some embodiments. The dielectric layer 262 may be formed in a similar manner to the dielectric layer 246 and may be formed of the same material as the dielectric layer 246. The dielectric layer 262 is patterned so as to expose the sensor region 110 of the sensor die 100. In this manner, the opening 250 is extended by the dielectric layer 262. After patterning the dielectric layer 262, the opening 250 has a depth D 2, which extends from a main surface of the dielectric layer 262 to an uppermost surface of the sensor die 100. In some embodiments, the depth D 2 is in a range between about 2 μm and about 100 μm.The opening 250 extends through the dielectric layers 246 and 262 of the front side redistribution structure 264. The metallization pattern 256 is not formed in the opening 250, such that the opening 250 is free of the materials of the front side redistribution structure 264 (e.g., materials of the metallization pattern 256 and the dielectric layers 246 and 262). In some embodiments, the dielectric layer 262 is patterned such that the portion of the opening that extends through the dielectric 262 has a greater width than the portion of the opening that extends through the dielectric layer 246. For example, the sidewall of the dielectric layer 262 may be offset from the sidewall of the dielectric layer 246 by a width W 3 that is between about 0 μm and about 50 μm, such as about 20 μm. In some cases, a greater offset may allow for greater exposure of the sensor region 110 to the sensed environment, which may increase the sensitivity and responsiveness of the sensing operation.In FIG. 27, a carrier substrate debond process is performed to release (or "debond") the carrier substrate 202 from the adhesive 228 and the backside redistribution structure 206 (e.g., the dielectric layer 208). Openings are then formed through the dielectric layer 208 to expose portions of the metallization pattern 210 and / or the conductive vias 216. Conductive connectors 266 are then formed in the openings in the dielectric layer 208 such that the sensor package 400 is formed, in accordance with some embodiments. The conductive connectors 266 may be spatially and electrically connected to the metallization pattern 210 and / or the conductive vias 216.In some embodiments, multiple sensor packages 400 are formed on a single carrier substrate 202, and a dicing process is performed to form the single sensor packages 400. The singulating process may be sawing, laser drilling or the like, for example. By forming a sensor package 400 as described herein (e.g., using a sacrificial layer 112 and removing the sacrificial layer 112 using a wet etching process), the thickness of the sensor package 400 may be reduced. In addition, the sensor region 110 may be formed closer to the top surface of the sensor package 400 (e.g., the top surface of the dielectric layer 262), which may improve sensing performance.In FIG. 28, the sensor package 400 is attached to a package substrate 302 using the conductive connectors 266 to form a sensor device 500, according to some embodiments. The package substrate 302 may include active and passive devices (not shown). As will be appreciated by those of ordinary skill in the art, a wide variety of devices such as transistors, capacitors, resistors, combinations thereof, and the like may be used to meet the structural and functional requirements of the design for the sensor device 500. The devices may be manufactured using any suitable methods. Package substrate 302 may also include metallization layers and vias (not shown) and bond pads 304 over the metallization layers and vias. In some embodiments, the package substrate 302 is substantially free of active and passive devices.Certain embodiments may provide certain advantages. By forming a sacrificial layer (e.g., sacrificial layer 112) over a sensor die (e.g., sensor die 100) that may be removed using a wet etching process or a dry etching process, a redistribution structure may be formed to electrically connect the sensor die instead of using wire bonds. In this way, a sensor die may be used as part of a fan-out (InFO) integrated package (e.g., the sensor package 200). Packaging a sensor die into an InFO package may allow for a reduction in the shape factor of the final sensor package. For example, some InFO sensor packages may be thinner than wire bond sensor packages. This may allow the sensor region (e.g., the sensor region 110) of the sensor die to be closer to the outside of the sensor package, which may improve the sensitivity or electrical response of the sensing operation. Further, wire loops over the sensor area of the sensor die may be avoided, thereby also decreasing the distance between the sensing area and the target or environment to be sensed, thereby increasing the sensitivity of the sensor die. The mechanical reliability of the sensor package may also be improved over other (e.g., wire bond) packaging schemes. The manufacturing yield of InFO packages may also be higher than that of wire bond packages. Since an InFO package exposes less surface area of a sensor die than other packaging schemes, sensing areas of the sensor die can be more easily kept clean, thereby improving sensing accuracy. In addition, by using a removable sacrificial film, the manufacturing cost or the overall processing time of a sensor package may be reduced.In an embodiment, a device includes a sensor die having a sensing area at a top surface of the sensor die, an encapsulant at least laterally encapsulating the sensor die, a conductive via extending through the encapsulant, and a front redistribution structure on the encapsulant and on the top surface of the sensor die, wherein the front redistribution structure is connected to the conductive via and the sensor die, wherein an opening in the front redistribution structure exposes the sensing area of the sensor die, and wherein the front redistribution structure includes a first dielectric layer extending over the encapsulant and the top surface of the sensor die, a metallization structure on the first dielectric layer, and a second dielectric layer extending over the metallization structure and the first dielectric layer. In an embodiment, the device includes a back redistribution structure, wherein a bottom side of the sensor die is attached to the back redistribution structure, and wherein the conductive via is connected to the back redistribution structure. In an embodiment, a portion of the first dielectric layer extending over the top surface of the sensor die has a thickness that is greater than the thickness of a portion of the first dielectric layer extending over the encapsulant. In an embodiment, the front side redistribution structure is connected to the conductive via through a first via extending through the first dielectric layer and is connected to the sensor die through a second via extending through the first dielectric layer. In an embodiment, the conductive via protrudes from the encapsulant. In an embodiment, the second dielectric layer extends over the sensor die, wherein a vertical distance between the top surface of the sensor die and a top surface of the second dielectric layer is between 5 μm and 50 μm. In an embodiment, the first dielectric layer over the top surface of the sensor die has a top surface that is lower than the first dielectric layer over the encapsulant. In an embodiment, the opening is defined by a sidewall of the second dielectric layer and a sidewall of the first dielectric layer, wherein the sidewall of the second dielectric layer is laterally recessed from the sidewall of the first dielectric layer.In an embodiment, a package includes a semiconductor die having a contact pad on a top surface of the semiconductor die and a sensing area on the top surface of the semiconductor die, an encapsulant surrounding the semiconductor die, the top surface of the semiconductor die being free of the encapsulant, a conductive via extending through the encapsulant, the conductive via being separated from the semiconductor die by the encapsulant, a first dielectric layer extending over a top surface of the encapsulant, along a sidewall of the encapsulant, and over the top surface of the semiconductor die, the first dielectric layer having a first opening exposing the sensing area of the semiconductor die, a conductive layer over a top surface of the first dielectric layer, wherein the conductive layer extends through the first dielectric layer to contact the conductive via and extends through the first dielectric layer to contact the contact pad, and a second dielectric layer over the conductive layer, the second dielectric layer having a second opening exposing the sensing area of the semiconductor die through the first opening in the first dielectric layer. In an embodiment, the sidewall of the encapsulant extends beyond the semiconductor die. In one embodiment, the second opening has a greater width than the first opening. In an embodiment, a portion of the first dielectric layer extending over the semiconductor die has a top surface that is lower than a top surface of the encapsulant. In an embodiment, a thickness of the first dielectric layer on the encapsulant is between 2 μm and 10 μm. In an embodiment, the sidewall of the encapsulant slopes away from the semiconductor die. In an embodiment, the first opening in the first dielectric layer has a width between 5 μm and 50 μm. In an embodiment, a bottom side of the semiconductor die is attached to a redistribution structure.In an embodiment, a method includes forming a sacrificial layer on a semiconductor die, the semiconductor die having a sensor, forming a conductive via on a first redistribution structure, disposing the semiconductor die on the first redistribution structure adjacent to the conductive via, encapsulating the semiconductor die, the sacrificial layer, and the conductive via with an encapsulant, planarizing the encapsulant such that the conductive via and the sacrificial layer are exposed, removing the sacrificial layer using an etching process, and forming a second redistribution structure over the encapsulant and over the semiconductor die, wherein the second redistribution structure is electrically connected to the conductive via and to the semiconductor die, and wherein the second redistribution structure has an opening, exposing the sensor of the semiconductor die. In an embodiment, the etching process includes a wet chemical etching process. In an embodiment, the etching process includes a plasma dry etching process. In an embodiment, after forming the sacrificial layer on the semiconductor die, the method includes applying a laser process to remove the sacrificial layer over a scribe region and applying a dicing process to the scribe region to dicing the semiconductor die.

Claims

A device, comprising: a sensor die (100) having a sensing area at a top of the sensor die (100); an encapsulant (242) at least laterally encapsulating the sensor die (100); a conductive via (116, 216, 258, 260) extending through the encapsulant (242); and a front side redistribution structure (264) on the encapsulant (242) and on the top side of the sensor die (100), wherein the front redistribution structure (264) is connected to the conductive via (116, 216, 258, 260) and the sensor die (100), wherein an opening (248, 250, 252) in the front side redistribution structure (264) exposes the sensing area of the sensor die (100), and wherein the front side redistribution structure (264) comprises a first dielectric layer extending over the encapsulant (242) and the top side of the sensor die (100), a metallization structure (210, 256) on the first dielectric layer and a second dielectric layer extending over the metallization structure (210, 256) and the first dielectric layer; wherein a recess (244) exposing the sensor die (100) is formed in the encapsulant (242), and wherein the recess has sidewalls that are inclined.The device of claim 1, further comprising a back-side redistribution structure (206), wherein a bottom side of the sensor die (100) is attached to the back-side redistribution structure (206), and wherein the conductive via (116, 216, 258, 260) is connected to the back-side redistribution structure (206).The device of claim 1 or 2, wherein a portion of the first dielectric layer extending over the top surface of the sensor die (100) has a thickness that is greater than the thickness of a portion of the first dielectric layer extending over the encapsulant (242).The device of any preceding claim, wherein the front side redistribution structure (264) is connected to the conductive via (116, 216, 258, 260) by a first via extending through the first dielectric layer and is connected to the sensor die (100) by a second via extending through the first dielectric layer.The device of any preceding claim, wherein the conductive via (116, 216, 258, 260) protrudes from the encapsulant (242).The device of any of the preceding claims, wherein the second dielectric layer extends over the sensor chip, wherein a vertical distance between the top side of the sensor die (100) and a top side of the second dielectric layer is between 5 μm and 50 μm.The device of any preceding claim, wherein the first dielectric layer over the top surface of the sensor die (100) has a top surface that is lower than the first dielectric layer over the encapsulant (242).The apparatus of any preceding claim, wherein the opening (248, 250, 252) is defined by a sidewall of the second dielectric layer and a sidewall of the first dielectric layer, wherein the sidewall of the second dielectric layer is laterally recessed from the sidewall of the first dielectric layer.A package, comprising: a semiconductor die (100) having a contact pad (104) on a top surface of the semiconductor die and a sensing region on the top surface of the semiconductor die; an encapsulant (242) surrounding the semiconductor die, wherein the top surface of the semiconductor die is free of the encapsulant (242); a conductive via (116, 216, 258, 260) extending through the encapsulant (242), wherein the conductive via (116, 216, 258, 260) is separated from the semiconductor die by the encapsulant (242); a first dielectric layer extending over a top surface of the encapsulant (242), along a sidewall of the encapsulant (242), and over the top surface of the semiconductor die, the first dielectric layer having a first opening (248, 250, 252) exposing the sensing area of the semiconductor die; a conductive layer over a top surface of the first dielectric layer, the conductive layer extending through the first dielectric layer to contact the conductive via (116, 216, 258, 260) and extending through the first dielectric layer to contact the contact pad (104); and a second dielectric layer over the conductive layer, wherein the second dielectric layer has a second opening (248, 250, 252) exposing the sensing area of the semiconductor die through the first opening (248, 250, 252) in the first dielectric layer; wherein a recess (244) exposing the sensor die (100) is formed in the encapsulant (242), and wherein the recess has sidewalls that are inclined.The package of claim 9, wherein the sidewall of the encapsulant (242) extends over the semiconductor die.The package of claim 9 or 10, wherein the second opening (248, 250, 252) has a greater width than the first opening (248, 250, 252).The package of any of claims 9 to 11, wherein a portion of the first dielectric layer extending over the semiconductor die has a top surface that is lower than a top surface of the encapsulant (242).The package of any of claims 9 to 12, wherein a thickness of the first dielectric layer on the encapsulant (242) is between 2 μm and 10 μm.The package of any of claims 9 to 13, wherein the sidewall of the encapsulant (242) slopes away from the semiconductor die.The package of any of claims 9 to 14, wherein the first opening (248, 250, 252) in the first dielectric layer has a width between 5 μm and 50 μm.The package of any of claims 9 to 15, wherein a bottom side of the semiconductor die is attached to a redistribution structure (264).A method comprising: forming a sacrificial layer (112) on a semiconductor die, the semiconductor die having a sensor; forming a conductive via (116, 216, 258, 260) on a first redistribution structure (264); disposing the semiconductor die on the first redistribution structure (264) adjacent the conductive via (116, 216, 258, 260); encapsulating the semiconductor die, the sacrificial layer (112), and the conductive via (116, 216, 258, 260) with an encapsulant (242); planarizing the encapsulant (242) such that the conductive via (116, 216, 258, 260) and the sacrificial layer (112) are exposed; Removing the sacrificial layer (112) using an etching process such that a recess (244) exposing the sensor die (100) is formed in the encapsulant (242), and wherein the recess has sidewalls that are inclined; and forming a second redistribution structure (264) over the encapsulant (242) and over the semiconductor die, wherein the second redistribution structure (264) is electrically connected to the conductive via (116, 216, 258, 260) and to the semiconductor die, and wherein the second redistribution structure (264) has an opening (248, 250, 252) exposing the sensor of the semiconductor die.The method of claim 17, wherein the etching process comprises a wet chemical etching process.The method of claim 17 or 18, wherein the etching process comprises a plasma dry etching process.The method of any of claims 17 to 19, further comprising, after forming the sacrificial layer (112) on the semiconductor die, applying a laser process to remove the sacrificial layer (112) over a scribe area.

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