INTEGRATED CIRCUIT WITH REAR POWER RAIL AND REAR INTERCONNECT

Abstract

Integrated circuit comprising: a first layer with a first metal rail (210A); a second layer (M-1) with a second metal rail (240A), wherein the second layer (M-1) is located along a first direction (Z) above the first layer; a third layer (EPI) with an active region (262A) of a transistor, wherein the third layer (EPI) is located along the first direction (Z) above the second layer (M-1); and a fourth layer (MD) with a third metal rail (265A), wherein the fourth layer (MD) is located along the first direction (Z) above the third layer (EPI), wherein the first metal rail (210A) is configured to provide a supply voltage for the active region (262A) of the transistor via the second metal rail (240A), wherein the third metal rail (265A) is directly connected to a second side of the active area (262A) of the transistor, wherein the fourth layer (MD) contains a fifth metal rail (265B) which is directly connected to another active area (262B) of the transistor, wherein the second layer (M-1) contains a sixth metal rail (240B) which is connected to the further active area (262B) of the transistor.

Description

BACKGROUND

[0001] The recent trend toward miniaturization of integrated circuits (ICs) has led to smaller components that consume less power while offering more functionality at higher speeds. This miniaturization process has also resulted in stricter design and manufacturing specifications, as well as reliability challenges. Various electronic design automation (EDA) tools generate, optimize, and verify standard cell layout designs for integrated circuits, ensuring adherence to these designs and manufacturing specifications.

[0002] WO 2017 / 111792 A1 discloses: A device with a circuit structure comprising a device layer. US 2020 / 0135646 A1 discloses devices and methods for manufacturing monolithic three-dimensional integrated semiconductor circuit devices. US 2020 / 0035560A1 discloses architectures of integrated circuit cells comprising both front and back-side structures. DE 112016007503 T5 discloses transistor cell architectures comprising both front and back-side structures. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Aspects of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. Note that, in accordance with industry practice, several features are not drawn to scale. In fact, the dimensions of the various features may be enlarged or reduced as desired for clarity of description. The Fig. Figures 1A-1C are top views of a layout design of a circuit with a rear power rail and a rear metal rail according to one embodiment. Fig. 2A is a cross-sectional diagram along II' of the integrated circuit according to an embodiment, which is based on the layout design of the Fig. has been trained in 1A-1C. Fig. 2B is a cross-sectional diagram along II-II' of the integrated circuit according to an embodiment, which is based on the layout design of the Fig. has been trained in 1A-1C. The Fig. 3A and Fig. Figure 3B shows top views of a layout design of an integrated circuit with rear metal rails according to one embodiment. The Fig. 4A and Fig. Figure 4B shows top views of a layout design of an integrated circuit with rear metal rails according to one embodiment. The Fig. 5A and Fig. Figure 5B shows top views of a layout design of an integrated circuit with rear metal rails according to one embodiment. The Fig. 6A and Fig. Figure 6B shows top views of a layout design of an integrated circuit with rear metal rails according to one embodiment. Fig. 6C is a cross-sectional diagram along AA' of the integrated circuit according to an embodiment, which is based on the layout design of the Fig. 6A and Fig. 6B is trained. Fig. 6D is a cross-sectional diagram along BB' of the integrated circuit according to an embodiment, which is based on the layout design of the Fig. 6A and Fig. 6B is trained. Fig. Figure 7 is a top view of a layout design of an integrated circuit with rear metal rails according to one embodiment. Fig. Figure 8A is a schematic diagram of an exemplary multiplexer circuit according to one embodiment. Fig. 8B is a top view of a layout design of the exemplary multiplexer circuit of Fig. 8A according to one embodiment. The Fig. Figures 9A-9C are top views of a layout design for the exemplary multiplexer circuit of Fig. 8A with rear metal rails according to one embodiment. The Fig. Figures 10A-10C are top views of a layout design of the exemplary multiplexer circuit of Fig. 8A with rear metal rails according to one embodiment. The Fig. Figures 11A-11C are top views of a layout design of the exemplary multiplexer circuit of Fig. 8A with rear metal rails according to one embodiment. The Fig. 12A and Fig. Figures 12B are top views of a layout design of the exemplary multiplexer circuit of Fig. 8A with rear metal rails according to one embodiment. Fig. Figure 13A is a schematic diagram of an exemplary multiplexer circuit according to one embodiment. Fig. 13B is a top view of a layout design of the exemplary multiplexer circuit of Fig. 13A according to one embodiment. The Fig. Figures 13C to 13D are top views of a layout design of the exemplary multiplexer circuit of Fig. 13A with rear metal rails according to one embodiment. The Fig. Figures 13E-13F are top views of a layout design of the exemplary multiplexer circuit of Fig. 13A with rear metal rails according to one embodiment. The Fig. 13G-13I are top views of a layout design of the exemplary multiplexer circuit of Fig. 13A with rear metal rails according to one embodiment. Fig. Figure 14A is a schematic diagram of an exemplary circuit according to one embodiment. Fig. 14B is a top view of a layout design of the exemplary circuit of Fig. 14A according to one embodiment. Fig. Figure 15 is a flowchart of a process for manufacturing an integrated circuit according to some embodiments. Fig. Figure 16 is a block diagram of a system for generating an IC layout design according to some embodiments. Fig. Figure 17 is a block diagram of an IC manufacturing system and an associated IC manufacturing flow according to at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0004] The invention is defined by independent claim 1, which defines an integrated circuit, independent claim 15, which defines a method for forming an integrated circuit, and independent claim 18, which defines an integrated circuit. Preferred embodiments of the invention are provided by the dependent claims, the description, and the drawings. The following disclosure provides many different embodiments or examples to implement various features of the stated subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure.For example, forming a first feature over or on top of a second feature in the following description may include embodiments in which the first and second features are in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, so that the first and second features need not be in direct contact. Additionally, this disclosure may repeat reference numerals and / or letters in the various examples. This repetition serves the purpose of simplicity and clarity and does not in itself imply any relationship between the various described embodiments and / or configurations.

[0005] Furthermore, spatially relative terms such as "below," "under," "lower," "above," "upper," and similar terms can be used here for the sake of simplicity to describe the relationship of one element or feature to one or more other elements or features, as shown in the figures. These spatially relative terms are intended to encompass various orientations of the device being used or operated, in addition to the orientation shown in the figures. The device may be oriented differently (rotated by 90 degrees or in a different orientation), and the spatially relative terms used here can be interpreted accordingly.

[0006] According to some embodiments, the disclosure herein relates to an integrated circuit with a rear-side power rail and rear-side routing rails. In one aspect, the integrated circuit includes active regions in which a large number of transistors are formed, several layers of metal rails on a front side of the active regions, and at least two layers of metal rails on a rear side of the active regions. An active region is a semiconductor structure with either n- or p-doping. Metal rails on the front side of the active regions may be referred to as "front-side metal rails," and metal rails on the front side of the active regions used to conduct an electrical signal or for use as a local interconnect may be referred to as "front-side interconnect rails."Furthermore, metal rails on the rear side of the active areas can be referred to as "rear metal rails", metal rails on the rear side of the active areas for providing a supply voltage or power can be referred to as "rear power rails", and metal rails on the rear side of the active areas for conducting an electrical signal or for use as a local interconnect can be referred to as "rear interconnect rails".

[0007] In some embodiments, a first layer of metal rails on the back of the active areas can be located closer to the active areas compared to the front-side metal rails, and can provide the active areas with a more reliable supply voltage (e.g., VDD or GND) than the front-side metal rails. Additionally, a second layer of metal rails on the back of the active areas provides flexibility for routing or electrically connecting various components of the integrated circuit. By implementing at least two layers of metal rails on the back of the active areas, an integrated circuit can be designed in a smaller area because the number of contacts and front-side metal rails can be reduced. Furthermore, the use of the back-side metal rails allows components (e.g.,active regions, metal-over-diffusion (MD) regions or gate regions) for forming transistors have more regular or consistent shapes, so that the properties of the transistors can become more consistent.

[0008] Referring to the Fig. Figures 1A-1C and 100A-100C are top views of a layout design showing layout structures for fabricating an integrated circuit according to one embodiment. In one aspect, the top views 100A-100C of a layout design show layout structures for components in different layers of the integrated circuit. The circuit formed according to the layout design in the top views 100A-100C can be an inverter circuit. In one aspect, Fig. 1A Layout structures 110A, 110B, which correspond to the rear busbars. In one aspect, it shows Fig. 1B layout structures 130A, 130B, correspond to the active areas of transistors. In one aspect, it shows Fig. 1C Layout structures 170A-170E, corresponding to front-facing metal rails (e.g., M0 metal rails). In some embodiments, the layout design shown in plan views 100A-100C includes more, fewer, or different layout structures than shown in the Fig. 1A-1C. In some embodiments, the layout structures of the layout design shown in plan views 100A-100C are arranged differently than in the Fig. The components are arranged as shown in 1A-1C. An integrated circuit can be manufactured or formed according to the layout design shown in the top views 100A-100C.

[0009] In Fig. In Figure 1B, layout structures 120B and 130B represent a dimension and / or location of an n-transistor (e.g., an NMOS, an n-FinFET). In one aspect, layout structure 120B, extending in the Y direction, corresponds to a gate region of the n-transistor, and layout structure 130B, extending in the X direction, corresponds to an active region forming a source region and a drain region of the n-transistor. A gate region is a structure containing one or more conductive segments, which in turn contain one or more conductive materials, e.g., polysilicon, one or more metals, and / or one or more other suitable materials, substantially surrounded by one or more insulating materials, e.g.,Silicon dioxide and / or one or more other suitable materials, wherein the one or more conductive segments are configured to control a voltage applied to underlying and adjacent dielectric layers. A source region or a drain region is a semiconductor structure in an active region and is configured to have a doping type opposite to that of other sections of the active region. Layout structures 120A and 120C can correspond to gate regions of other transistors. In one aspect, layout structures 165B and 165C, extending in the Y direction, correspond to MD regions for supplying or sinking electrical current to the n-transistor. An MD region is a conductive region or structure that directly contacts the source region or the drain region.In some embodiments, the MD region contains one or more of polysilicon, copper (Cu), silver (Ag), tungsten (W), titanium (Ti), nickel (Ni), tin (Sn), aluminum (Al), or another metal or material suitable for providing a low-resistance electrical connection between IC structural elements. For example, a gate region of the n-transistor is formed where the layout structures 120B and 130B intersect; a source region of the n-transistor is formed where the layout structures 165C and 130B intersect; and a drain region of the n-transistor is formed where the layout structures 165B and 130B intersect.

[0010] In one embodiment, layout structures 120B and 130A indicate a dimension and / or location of a p-transistor (e.g., a PMOS or a p-FinFET). In one aspect, layout structure 120B, extending in the Y direction, corresponds to a gate region of the p-transistor, and layout structure 130A, extending in the X direction, corresponds to an active region for forming a source region and a drain region of the p-transistor. In another aspect, layout structures 165A and 165B, extending in the Y direction, correspond to MD regions for supplying or reducing current to the p-transistor. For example, a gate region of the p-transistor is formed where layout structures 120B and 130A intersect; a source region of the p-transistor is formed where layout structures 165A and 130A intersect; and a drain region of the p-transistor is formed where the layout structures 165B, 130A intersect.In this configuration, the drain region of the n-transistor and the drain region of the p-transistor are connected together, and the gate region of the n-transistor and the gate region of the p-transistor are connected together to form an inverter.

[0011] In one embodiment, layout structures 160A-160D show the dimensions and / or locations of vias for electrically contacting backside metal rails beneath the active areas. Electrical signals (e.g., voltage or current) can be passed to or from the transistors through the vias formed according to layout structures 160A-160D. In some embodiments, the vias contain one or more copper (Cu), silver (Ag), tungsten (W), titanium (Ti), nickel (Ni), tin (Sn), aluminum (Al), or another metal or material suitable for providing a low-resistance electrical connection between different layers.

[0012] In Fig. In one embodiment, layout structures 140A-140D show the dimensions and / or locations of backside metal rails. The backside metal rails can be made of metal or any conductive material. The backside metal rails formed according to layout structures 140A-140D can be located in an M-1 layer and can be implemented as backside interconnect rails. The backside metal rails can be electrically connected to the transistor (e.g., the source region, the drain region, or the gate region) by vias formed according to layout structures 160A-160D. In one embodiment, layout structures 110A and 110B show the dimensions and / or locations of backside power rails. The backside power rails can be made of metal or any conductive material. The backside power rails can be located on an M-2 layer or a lower layer.The rear busbars configured according to layout structures 110A and 110B can be electrically connected via vias to the rear metal busbars configured according to layout structures 140A-140D, which are configured according to layout structures 150A-150B. Layout structures 110A, 110B, 140A, 140B, 140C, and 140D can extend in the X direction, the Y direction, or in any other direction.

[0013] In one configuration, layout structures 110A and 110B for the rear power rails can have larger areas with uniform structures, thus providing reliable supply voltages (e.g., VDD, GND). For example, the rear power rail configured according to layout structure 110A can supply a voltage (e.g., VDD or 1V) to the source region of the p-transistor via the rear metal rail configured according to layout structure 140A. Similarly, the rear power rail configured according to layout structure 110B can supply a voltage (e.g., GND or 0V) to the source region of the n-transistor via the rear metal rail configured according to layout structure 140C.At the same time, the rear metal rails designed according to layout structures 140B, 140D can extend in any direction so that they are electrically connected to other transistors or metal rails for local connections.

[0014] In Fig. In one embodiment, layout structures 170A-170E show the dimensions and / or locations of front-facing metal rails. In one aspect, layout structures 170A-170E extend in the X direction. The front-facing metal rails can be made of metal or any conductive material. The front-facing metal rails can be located on an M0 layer. The front-facing metal rails can be electrically connected to the transistor (e.g., the source region, the drain region, or the gate region) by vias formed according to layout structures 175 and 180. For example, the metal rail formed according to layout structure 170A can be electrically connected to the drain region of the p-transistor by the MD region formed according to layout structure 165B and the via formed according to layout structure 175.For example, the metal rail formed according to layout structure 170D can be electrically connected to the common gate region of the n-transistor and the p-transistor by means of the via formed according to layout structure 180. In some embodiments, the integrated circuit, which is formed according to the [reference], contains [further details]. Fig. The layout structures shown in 1A-1C are formed, with further layers (e.g. M1-M7) for front metal rails.

[0015] In one aspect, the rear-side power rails and rear-side interconnect rails disclosed here offer several advantages. For example, the integrated circuit can be built in a smaller area because the number of front-side metal rails and vias can be reduced. For instance, by implementing rear-side interconnect rails, gate density can be improved by 4% or more compared to devices without them. Furthermore, in another example, the MD region or the gate region for forming the transistors can have more regular or consistent shapes, resulting in more consistent transistor characteristics.

[0016] Fig. 2A is a cross-sectional diagram 200A along II' of an integrated circuit according to an embodiment, which is based on the layout design of the Fig. has been trained in 1A-1C. Fig. 2B is a cross-sectional diagram 200B along II-II' of the integrated circuit according to an embodiment, which is based on the layout design of the Fig. has been trained in 1A-1C.

[0017] Referring to the Fig. 2A and Fig. Component 2B contains an integrated circuit with a rear busbar layer BM with rear busbars 210A and 210B, configured according to layout structures 110A and 110B. Above the rear busbar layer BM, along the Z-direction, a contact layer VB with vias 250A and 250C, configured according to layout structures 150A and 150C, can be configured. Above the contact layer VB, along the Z-direction, a rear metal busbar layer M-1 with rear metal busbars 240A and 240C, configured according to layout structures 140A and 140C, can be configured. Above the rear metal busbar layer M-1, along the Z-direction, a contact layer VDB with vias 260A and 260C, configured according to layout structures 160A and 160C, can be configured. Above the contact layer VDB along the Z-direction, an epitaxial layer EPI with source / drain areas 262A-262C can be formed at the intersections of the layout structures 130A, 130B and the layout structures 165A-165C.Above the epitaxial layer EPI along the Z-direction, a conductive layer MD with MD regions 265A-265C can be formed according to layout structures 165A-165C. Above the conductive layer MD along the Z-direction, a contact layer VD with a via 275 can be formed according to layout structure 175. Above the contact layer VD along the Z-direction, a front-facing metal layer M0 with a front-facing metal rail 270 can be formed according to layout structure 170A.

[0018] In Fig. In one aspect, the rear power rail 210A is configured to provide a supply voltage VDD. A via 250A is formed on the rear power rail 210A along the Z-direction. On the VB layer with the via 250A, the rear metal rail 240A is formed along the Z-direction. The rear metal rail 240A can be implemented as a rear interconnect rail below the source region 262A (e.g., in a direction opposite to the Z-direction). A via 260A is formed on the rear metal rail 240A along the Z-direction. The source region 262A of the p-transistor is formed on the via 260A along the Z-direction. The MD region 265A is formed on the source region 262A along the Z-direction. In one aspect, the MD area 265A is directly connected to the Source area 262A.In some implementations, the MD area 265A can be used as a local interconnect bus to electrically connect adjacent components (e.g., metal busbars and / or source / drain / gate areas). In one aspect, a side or surface of the source area 262A oriented in the Z direction is directly connected to the MD area 265A, and a side or surface of the source area 262A oriented in the opposite direction to the Z direction is directly connected to the via 260A. In this configuration, the supply voltage VDD can be provided to the source area 262A and the MD area 265A via the via 250A, the back metal busbar 240A, and the via 260A.

[0019] In one aspect, the rear power rail 210B is configured to provide a ground (GND) supply voltage. A via 250C is formed on the rear power rail 210B along the Z-direction. The rear metal rail 240C is formed on the via 250C along the Z-direction according to layout structure 140C. The rear metal rail 240C can be implemented as a rear interconnect rail. A via 260C is formed on the rear metal rail 240C along the Z-direction. The source region 262C of the n-transistor is formed on the via 260C along the Z-direction. The medium-precision (MD) region 265C is formed on the source region 262C along the Z-direction. In one aspect, the MD region 265C is directly connected to the source region 262C. In some implementations, the MD area 265C can be used as a local interconnect rail to connect adjacent components (e.g.,to electrically connect metal rails and / or source / drain / gate areas.

[0020] In Fig. Component 2B of the integrated circuit contains gate regions 220A-220C, configured according to layout structures 120A-120C. In one aspect, gate region 220B is located between source / drain regions 262A and 262B, and between medium-ductor regions 265A and 265B. A via 260B is formed on the backplate metal rail 240B along the Z-direction. Drain region 262B is formed on the via 260B along the Z-direction. Medium-ductor region 265B is formed on the drain region 262B of the p-transistor along the Z-direction. Thus, drain region 262B is located between the via 260B and medium-ductor region 265B. In particular, one side or surface of the drain area 262B, which is oriented in the Z direction, is directly connected to the MD area 265B, and one side or surface of the drain area 262B, which is oriented in a direction opposite to the Z direction, is directly connected to the via 260B.A via 275 is formed along the Z-direction on the MD area 265B according to the layout structure 175. The front metal rail 270 is formed on the via 275 along the Z-direction.

[0021] In this configuration, the source area 262A is electrically connected to the rear power rail 210A via via 250A, the rear metal rail 240A, and via 260A for the supply voltage VDD. This allows the transistors to be supplied with the supply voltage VDD via the rear power rail 210A and the rear metal rail 240A. Furthermore, the drain area 262B is electrically connected to the front metal rail 270 via via 275 and the MD area 265B, and to the rear metal rail 240B via via 260B. Therefore, electrical signals can be provided via the front metal rail 270, the rear metal rail 240B, or both.

[0022] The Fig. 3A and Fig. 3B are top views 300A and 300B of a layout design for an integrated circuit with rear-facing metal rails according to one embodiment. In one aspect, top views 300A and 300B of a layout design show layout structures for components in different layers of the integrated circuit. In one aspect, top view 300A shows layout structures of front-facing metal rails of the integrated circuit, and top view 300B shows layout structures of rear-facing metal rails of the integrated circuit. Fig. 3A shows the layout structure 320, extending in the Y direction, a dimension and / or location of a gate region of a transistor; the layout structure 330, extending in the X direction, shows a dimension and / or location of an active region; the layout structure 365, extending in the Y direction, shows a dimension and / or location of an MD region; and the layout structure 370, extending in the X direction, shows a dimension and / or location of a front metal rail (e.g., an M0 rail). Fig. 3B shows a layout structure 340 extending in the X direction, a dimension and / or location of a backside metal rail (e.g., in the M-1 layer), and the layout structure 350 (corresponding to 160A-D) shows a dimension and / or location of a via (e.g., in the VDB layer) between the transistor and the backside interconnect. The backside metal rails can be formed in a layer (e.g., the M-1 layer) between a first layer (e.g., the epitaxial layer EPI) in which the transistors are formed and a second layer (e.g., the BM layer) in which the backside power rails are formed, as shown in the Fig. 2A and Fig. 2B shown. In further embodiments, the layout design of the integrated circuit shown in top views 300A, 300B may include more, fewer, or layout structures for other layers.

[0023] In one respect, the backplate metal rails and backplate power rails allow transistor components to be configured in a regular or consistent structure. For example, supply voltages can be provided by underlying backplate power rails, so that the ends or edges of the 365 layout structure for the MD regions can be aligned with similar shapes without extending to the point of contact with frontplate power rails. Furthermore, the characteristics of the transistors can be more consistent compared to MD regions with irregular or inconsistent structures. Additionally, the backplate metal rails allow for a reduction in the number of frontplate metal rails and vias, thus reducing the area of ​​the integrated circuit.

[0024] The Fig. 4A and Fig. Figures 4B are top views 400A and 400B of a layout design for an integrated circuit with back-facing metal rails according to one embodiment. In one aspect, the top views 400A and 400B of a layout design show layout structures for components in different layers of the integrated circuit. In one aspect, top view 400A shows layout structures of front-facing metal rails (e.g., in the MD layer and / or the M0 layer) of the integrated circuit, and top view 400B shows layout structures of back-facing metal rails (e.g., in the M1 layer) of the integrated circuit. In one aspect, the layout is similar to that shown in the Fig. 4A, Fig. Layout design shown in 4B corresponds to the one in the Fig. The layout design shown in Figures 3A-3B differs from the top view shown in Figure 400B, except that the top view shows a layout structure 440 extending in the Y direction, indicating a dimension and / or location of a rear metal rail. Therefore, for the sake of brevity, a detailed description of these identical sections is omitted here. In one aspect, the rear metal rail extending in the Y direction contributes to providing flexibility with respect to routing or local interconnect. In other embodiments, the layout design of the integrated circuit shown in top views 400A and 400B may include more, fewer, or different layout structures for other layers.

[0025] The Fig. 5A and Fig. 5B are top views 500A, 500B of a layout design of an integrated circuit with back-side metal rails (e.g., in the M-1 layer) according to one embodiment. In one aspect, top views 500A, 500B of a layout design show layout structures for components in different layers of the integrated circuit. In one aspect, top view 500A shows layout structures of front-side metal rails of the integrated circuit, and top view 500B shows layout structures of back-side metal rails of the integrated circuit. In one aspect, the layout resembles that shown in the Fig. 5A, Fig. Layout design shown in 5B is shown in the Fig. The layout design shown in Figures 3A-3B is identical, except that the top view 500B includes a layout structure 540 extending in the X and Y directions, indicating a dimension and / or location of a rear metal rail. Therefore, for the sake of brevity, a detailed description of these identical sections is omitted here. In one aspect, the rear metal rail extending in the X and Y directions provides flexibility with respect to routing or local interconnect. In other embodiments, the layout design of the integrated circuit shown in top views 500A and 500B may include more, fewer, or different layout structures for other layers.

[0026] The Fig. 6A and Fig. Figures 6B and 600A are top views of a layout design for an integrated circuit with back-side metal rails (e.g., in the M-1 layer) according to one embodiment. In one aspect, top views 600A and 600B of a layout design show layout structures for components in different layers of the integrated circuit. In another aspect, top view 600A shows layout structures of front-side metal rails of the integrated circuit, and top view 600B shows layout structures of back-side metal rails of the integrated circuit. Fig. Layout structures 620A-620F, extending in the Y direction, indicate dimensions and / or locations of gate regions of transistors; layout structure 630, extending in the X direction, indicates a dimension and / or location of an active region; layout structures 665A-665E, extending in the Y direction, indicate dimensions and / or locations of MD regions; and layout structures 670A-670C, extending in the X direction, indicate dimensions and / or locations of front-side metal rails (e.g., M0 rails). Fig. 6B shows the layout structures 640A-640D, extending in the X direction, dimensions and / or locations of back-side metal rails, and the layout structures 650A-650C show dimensions and / or locations of vias between the transistors and the back-side metal rails (e.g., M-1 rails). In one aspect, the layout design includes, in an area corresponding to a cell, three layout structures 670A-670C for the front-side metal rails (e.g., M0 rails) and four layout structures 640A-640D for the back-side metal rails (e.g., M-1 rails). In other embodiments, the layout design of the integrated circuit shown in top views 600A, 600B may include more, fewer, or different layout structures for other layers.

[0027] In some embodiments, source / drain regions and MD regions of different heights can be configured in a nested sequence according to layout structures 665A-665E. For example, the source / drain regions and MD regions can be configured with a first height H1 according to layout structures 665A, 665C, ​​665E, wherein source / drain regions and MD regions can be configured with a second height H2 according to layout structures 665B, 665D, which is less than the first height H1. In one aspect, the source / drain regions and MD regions configured according to layout structures 665A, 665C, ​​665E can be electrically interconnected via vias configured according to layout structures 650A-650C and a rear metal busbar configured according to layout structure 640B.Such local interconnection via the rear metal rails can enhance flexibility in the locations and dimensions of the front metal rails (e.g., the M0 rails) configured according to layout structures 670A-670C. For example, a front metal rail according to layout structure 670B can be positioned close to an edge of the MD area or partially overlap the MD area. Implementing rear metal rails and rear power rails allows for a smaller number of front metal rails to connect the transistors. Therefore, an integrated circuit with a smaller footprint can be designed by implementing rear metal rails.

[0028] Fig. 6C is a cross-sectional diagram along AA' of the integrated circuit according to an embodiment, which is based on the layout design of the Fig. 6A and Fig. 6B is trained. Fig. 6D is a cross-sectional diagram along BB' of the integrated circuit according to an embodiment, which is based on the layout design of the Fig. 6A and Fig. 6B is trained.

[0029] Referring to the Fig. 6C and Fig. Component 6D contains an integrated circuit with a rear busbar layer BM, comprising rear busbars 698A and 698B for providing supply voltages VDD and GND. A contact layer VB with vias 695A and 695B can be formed along the Z-direction above the rear busbar layer BM. A rear metal busbar layer M-1, comprising four rear metal busbars 690A-690D according to layout structures 640A-640D, can be formed along the Z-direction above the contact layer VB. In one aspect, rear metal busbar 690A is used to provide a supply voltage VDD, and rear metal busbar 690D is used to provide a ground voltage GND, with rear metal busbars 690B and 690C being used for local interconnect. A contact layer VDB with vias 688A-688D can be formed above the rear metal rail layer M-1 along the Z-direction.For example, the via 688A can be configured according to layout structure 650A. Above the contact layer VDB, an epitaxial layer EPI with source / drain regions 686A-686D can be configured along the Z-direction. For example, the drain region 686A of a p-transistor can be configured at an intersection of layout structures 665A and 630, and the source region 686C of the p-transistor can be configured at an intersection of layout structures 665B and 630. Above the epitaxial layer EPI, a conductive layer MD with MD regions 684A-684D can be configured along the Z-direction. For example, MD regions 684A and 684C can be configured according to layout structures 665A and 665B. Above the conductive layer MD, a contact layer VD can be configured along the Z-direction.Above the contact layer VD, a front-side metal layer M0 with three front-side metal rails 682A-682C according to the layout structures 670A-670C can be formed along the Z-direction.

[0030] In Fig. In 6C, the rear power rail 698B is configured to provide a supply voltage GND. A via 695A is formed on the rear power rail 698B along the Z-direction. A rear metal rail 690D is formed on the via 695A along the Z-direction. The rear metal rail 690D can be implemented as a rear interconnect rail. A via 688B is formed on the rear metal rail 690D along the Z-direction. A source region 686B of the n-transistor is formed on the via 688B along the Z-direction. An MD region 684B is formed on the source region 686B along the Z-direction. In one aspect, the MD region 684B is directly connected to the source region 686B. In one aspect, a side or surface of the source area 686B, which is oriented in the Z direction, is directly connected to the MD area 684B, and a side orThe surface of source area 686B, which faces in a direction opposite to the Z-direction, is directly connected to via 688B. In this configuration, the GND supply voltage can be provided to source area 686B and MD area 684B via via 695A, the rear power rail 690D, and via 688B.

[0031] In Fig. In one aspect, the rear power rail 698A is configured to provide a supply voltage VDD. A via 695B is formed on the rear power rail 698A along the Z-direction. A rear metal rail 690A is formed on the VB layer with the via 695B along the Z-direction. The rear metal rail 690A can be implemented as a rear interconnect rail (e.g., in the opposite direction to the Z-direction) under the source region 686C. A via 688C is formed on the rear metal rail 690A along the Z-direction. A source region 686C of the p-transistor is formed on the via 688C along the Z-direction. The MD region 684C is formed on the source region 686C along the Z-direction. In one aspect, the MD area 684C is directly connected to the source area 686C. In one aspect, a page or...The surface of the source area 686C oriented in the Z direction is directly connected to the MD area 684C, and a side or surface of the source area 686C oriented in the opposite direction to the Z direction is directly connected to the via 688C. In this configuration, the supply voltage VDD can be provided to the source area 686C and the MD area 684C via the via 695B, the rear bus bar 690A, and the via 688C.

[0032] Fig. Figure 7 is a top view 700 of a layout design of an integrated circuit with backplate metal rails according to one embodiment. In one aspect, the top view 700 shows layout structures 710A-710E of backplate metal rails of the integrated circuit. The backplate metal rails formed according to the layout structures can be formed in an M-2 layer and arranged between a first layer (e.g., the M-1 layer) in which the backplate metal rails are formed and a second layer (e.g., the BM layer) in which backplate power rails are formed. The backplate metal rails formed according to the layout structures 710A-710E can contain metal or any conductive material. As shown in Fig. As shown in Figure 7, in some embodiments the layout structures 640A-640D for the back metal rails in the M-1 layer can extend in the X direction, while the layout structures 710A-710E for the back metal rails in the M-2 layer can extend in the Y direction. In some embodiments, one or more vias can be formed where a layout structure for a back metal rail in the M-1 layer and a layout structure for a back metal rail in the M-2 layer intersect to allow an electrical connection of the back metal rails in the different layers.Although not shown for simplicity, one or more vias can be formed where a layout structure for a backplate metal rail in the M-2 layer and a layout structure for a backplate power rail intersect to provide an electrical connection between the backplate metal rails in the M-2 layer and the backplate power rail. Using the backplate metal rails in the M-2 layer between the backplate metal rails in the M-1 layer and a backplate power rail in the BM layer offers further flexibility in placement and routing, enabling the design of a compact integrated circuit.

[0033] Fig. Figure 8A is a schematic diagram of an exemplary multiplexer circuit 800 according to one embodiment. In one configuration, the multiplexer circuit 800 includes p-transistors P1, P2 (e.g., PMOS transistors or p-FinFETs) and n-transistors N1, N2 (e.g., NMOS transistors or n-FinFETs). In one configuration, a first input terminal I1 of the multiplexer circuit 800 is connected to a drain region (or a source region) of transistor P1 and a drain region (or a source region) of transistor N2. Similarly, a second input terminal I2 of the multiplexer circuit 800 is connected to a drain region (or a source region) of transistor P2 and a drain region (or a source region) of transistor N2.Additionally, an output terminal Z of the 800 multiplexer circuit is connected to a source (or drain) region of transistor P1, a source (or drain) region of transistor P2, a source (or drain) region of transistor N1, and a source (or drain) region of transistor N2. Furthermore, a control terminal A of the 800 multiplexer circuit is connected to a gate region of transistor P1 and a gate region of transistor N2, and a control terminal B of the 800 multiplexer circuit is connected to a gate region of transistor P2 and a gate region of transistor N1. In this configuration, when a voltage at control terminal A is high (e.g., VDD) and a voltage at control terminal B is low (e.g., GND), an electrical signal at input terminal I2 can be passed to output terminal Z through transistors P2 and N2.Similarly, if a voltage at control terminal A is low (e.g. GND) and a voltage at control terminal B is high (e.g. VDD), an electrical signal at input terminal I1 can be passed to output terminal Z through transistors P1, N1.

[0034] Fig. 8B is a top view 805 of a layout design of the exemplary multiplexer circuit 800 by Fig. 8A according to one embodiment. In one aspect, the embodiment contains Fig. Layout design 8B shows layout structures 830A and 830B, which indicate the dimensions and / or locations of active areas, and layout structures 820A-820D, which indicate the dimensions and / or locations of gate areas. As above regarding Fig. As shown in Figure 1B, transistors can be formed where layout structures 830A and 830B for the active regions and layout structures 820A–820D for the gate regions intersect. For example, gate regions formed according to layout structures 820A and 820D can be assigned to or connected with control terminal A of the multiplexer circuit 800, and gate regions formed according to layout structures 820B and 820C can be assigned to or connected with control terminal B of the multiplexer circuit 800. To configure the multiplexer circuit 800 as shown in Figure 1B, the following steps are required: Fig. To implement 8A, cross-coupled connections 840A and 840B can be used. In one aspect, the rear metal rails can be used to provide a local interconnect, as shown below. Fig. 9A-9C, 10A-10C, 11A-11C and 12A-12B are described.

[0035] The Fig. 9A-9C are top views 900A-900C of layout designs of the exemplary multiplexer circuit 800 of Fig. 8A with rear-side metal rails (e.g., in the M-1 layer) according to one embodiment. In one aspect, the top views 900A-900C of a layout design show layout structures for components in different layers of the integrated circuit. In one aspect, a layout design 900A, which is in Fig. As shown in Figure 9A, layout structures 970A-970E extend in the X direction, and layout structures 980A-980B extend in the Y direction. Layout structures 970A-970E can indicate the dimensions and locations of front metal rails (e.g., M0 rails), and layout structures 980A and 980B can indicate the dimensions and locations of front metal rails (e.g., M1 rails). In one aspect, a layout design 900B, which is shown in Fig. Figure 9B shows layout structures 920A-920D, which extend in the Y direction, and layout structures 925A-925D. Layout structures 920A-920D can show the dimensions and locations of gate areas, and layout structures 925A-925D can show the dimensions and locations of vias between the gate areas and the front metal rails (e.g., the M0 rails). In one aspect, a layout design 900C, which is shown in Fig. Figure 9C shows layout structures 940A-940B extending in the X direction. Layout structures 940A and 940B can indicate the dimensions and locations of rear metal rails (e.g., in the M-1 layer). According to the Fig. In the layout design shown in 9A-9C, the cross-coupled connections 840A, 840B can be formed by the front metal rails (e.g., the M1 rails and the M0 rails). Furthermore, drain or source regions of the transistors can be locally interconnected by the rear metal rails (e.g., the M1 rails).

[0036] The Fig. 10A-10C are top views 1000A-1000C of a layout design of the exemplary multiplexer circuit 800 of Fig. 8A with rear-side metal rails (e.g., in the M-1 layer) according to one embodiment. In one aspect, the top views 1000A-1000C of a layout design show layout structures for components in different layers of the integrated circuit. In one aspect, the layout design shown in the top views 1000A-1000C is similar to the layout design in the top views 900A-900C, which are shown in the Fig. 9A-9C are shown, except that the one in the Fig. Layout design 10A-10C includes layout structures 1070A-1070D for four front-facing metal rails (e.g., M0 rails) instead of five front-facing metal rails. According to the Fig. In the layout design shown in 10A-10C, the cross-coupled connections 840A, 840B can be formed by the front metal rails (e.g., the M1 rails and the M0 rails). Furthermore, drain or source regions of the transistors can be locally interconnected by the rear metal rails (e.g., the M1 rails).

[0037] The Fig. Figures 11A-11C are top views of a layout design of the exemplary 800 multiplexer circuit. Fig. 8A with rear-side metal rails (e.g., of the M-1 layer) according to one embodiment. In one aspect, the top views 1100A-1100C of a layout design show layout structures for components in different layers of the integrated circuit. In one aspect, the layout design shown in the top views 1100A-1100C is similar to the layout design in the top views 900A-900C, which are shown in the Fig. 9A-9C are shown, except that the one in the Fig. Layout design 11A-11C shows layout structures 1170A-1170C for three front metal rails (e.g., M0 rails) instead of five front metal rails. According to the Fig. In the layout design shown in 11A-11C, the cross-coupled connections 840A, 840B can be formed by the front metal rails (e.g., the M1 rails and the M0 rails). Furthermore, drain or source regions of the transistors can be locally interconnected by the rear metal rails (e.g., the M1 rails).

[0038] The Fig. 12A and Fig. 12B are top views 1200A-1200B of a layout design of the exemplary multiplexer circuit 800 by Fig. 8A with rear-side metal rails (e.g., in the M-1 layer) according to one embodiment. In one aspect, the top views 1200A-1200B of a layout design show layout structures for components in different layers of the integrated circuit. In another aspect, the Fig. Layout design 12A shows layout structures 1230A-1230D, which indicate the dimensions and / or locations of active areas, and layout structures 1220A-1220C, which indicate the dimensions and / or locations of gate areas. As above regarding Fig. As shown in Figure 1B, transistors can be formed where the layout structures 1230A-1230D for the active regions and the layout structures 1220A-1220C for the gate regions intersect. In one example, various transistors are formed along the Y direction according to the layout structures 1230A-1230D and 1220A-1220C.

[0039] In one aspect, front and rear metal rails can be designed to connect different components. In one example, the [component] includes Fig. The layout design shown in Figure 12A also includes layout structures 1270A-1270D, which indicate dimensions and / or locations of front-facing metal rails (e.g., M0 rails), and a layout structure 1280, which indicates a dimension and / or location of a front-facing metal rail (e.g., an M1 rail). In one example, the layout shown in Figure 12A includes the following: Fig. Layout design 12B also shows layout structures 1240A-1240D, which indicate the dimensions and / or locations of rear metal rails (e.g., M-1 rails). According to the Fig. In the layout design shown in Figures 12A-12B, the cross-coupled connections 840A and 840B can be formed by the front metal rails (e.g., the M1 rail and the M0 rails). Furthermore, drain or source regions of the transistors can be locally interconnected by the rear metal rails (e.g., the M1 rails).

[0040] Fig. Figure 13A is a schematic diagram of an exemplary circuit 1300 according to one embodiment. In one configuration, the circuit 1300 resembles the multiplexer circuit 800 of Fig. 8A, except that dummy transistors D1 and D2 have been added. Therefore, for the sake of brevity, a detailed description of the identical sections is omitted here. In one aspect, the dummy transistors D1 and D2 allow for easy placement and interconnection of various components.

[0041] Fig. 13B is a top view 1305 of a layout design of the exemplary circuit 1300 of Fig. 13A according to one embodiment. In one aspect, the embodiment contains Fig. Layout design 13B shows layout structures 1310A and 1310B, which indicate the dimensions and / or locations of active areas, and layout structures 1320A-1320E, which indicate the dimensions and / or locations of gate areas. Layout structures 1310A and 1310B can extend in the X direction, and layout structures 1320A-1320E can extend in the Y direction. As above regarding Fig. As shown in Figure 1B, transistors can be formed where the layout structures 1310A, 1310B for the active areas and the layout structures 1320A-1320E for the gate areas intersect.

[0042] In some embodiments, front-side metal rails and / or rear-side metal rails can be used for local interconnection. For example, a drain region and a source region of a transistor configured according to layout structures 1330A and 1330B can be short-circuited or electrically connected to each other via a local interconnect 1350 to form the dummy transistor D1. Similarly, gate regions configured according to layout structures 1320B and 1320D can be short-circuited or electrically connected to each other via a local interconnect 1352. The local interconnect 1352 can be associated with or connected to the control terminal B of the circuit 1300.In one example, a drain or source region of a transistor configured according to layout structure 1330C and a drain or source region of a transistor configured according to layout structure 1330D can be short-circuited or electrically connected by a local interconnect 1354. The local interconnect 1354 can be associated with or connected to the output terminal Z of circuit 1300. Similarly, in another example, a drain and source region of a transistor configured according to layout structures 1330E and 1330F can be short-circuited or electrically connected by a local interconnect 1356 to form the dummy transistor D2. The local interconnects 1350, 1352, 1354, and 1356 can be metal rails in layer M-2, layer M-1, layer M-0, layer M-1, or any combination thereof.

[0043] In one aspect, the rear metal rails allow for flexibility in component placement and routing, enabling the 1320A-1320E and 1330A-1330F layout structures to have regular or consistent shapes. For example, the 1320A-1320E layout structures for forming the gate regions can have the same or similar shapes and extend across the 1330A and 1330B layout structures to form an active region. Similarly, the 1330A-1330E layout structures for forming the source / drain regions and / or MD regions can have the same or similar shapes with aligned edges. Advantageously, such regular or consistent shapes of the 1320A-1320E and 1330A-1330F layout structures allow transistor components (e.g., gate regions, source / drain regions) to be formed consistently, resulting in more consistent transistor characteristics.Furthermore, the 1300 circuit can be designed in a compact form, as the number of front-side metal rails and vias can be reduced.

[0044] The Fig. 13C-13D are top views 1360A, 1360B of a layout design of the exemplary multiplexer circuit 1300 by Fig. 13A with rear metal rails according to one embodiment. In one aspect, the top views 1360A, 1360B of a layout design show layout structures for components in different layers of the integrated circuit. In another aspect, the Fig. Layout design shown in 13C includes layout structures 1366A-1366D, which show the dimensions and / or locations of active areas, and layout structures 1364A-1364E, which show the dimensions and / or locations of gate areas.

[0045] In one aspect, front and rear metal rails can be designed to connect different components. In one example, the [component] includes Fig. Layout design 13C also includes layout structures 1362A-1362C, which indicate the dimensions and / or locations of front-facing metal rails (e.g., M0 rails). In one example, the layout design shown in Fig. The layout design shown in 13D also includes layout structures 1368A-1368B, which indicate the dimensions and / or locations of rear metal rails (e.g., M-1 rails). According to the Fig. In the layout design shown in Figures 13C-13D, the cross-coupled connections 1352 and 1354 can be formed by the front metal rails (e.g., an M1 rail and the M0 rails) and the rear metal rails (e.g., the M-1 rails). In one example, a drain region or a source region of a transistor configured according to layout structure 1366A can be electrically connected via a via configured according to layout structure 1369A to a rear metal rail (e.g., an M-1 rail) configured according to layout structure 1368A. Similarly, a source region or a drain region of the transistor, which is configured according to layout structure 1366B, can be electrically connected via a via configured according to layout structure 1369B to the rear metal rail (e.g. the M-1 rail) configured according to layout structure 1368A.In one example, a drain or source region of a transistor configured according to layout structure 1366C can be electrically connected via a via configured according to layout structure 1369C to a rear metal rail (e.g., an M-1 rail) configured according to layout structure 1368B. Similarly, a drain or source region of a transistor configured according to layout structure 1366D can be electrically connected via a via configured according to layout structure 1369D to the rear metal rail (e.g., the M-1 rail) configured according to layout structure 1368B. Thus, different transistors configured according to layout structures 1366C and 1366D can be electrically connected to each other via a rear metal rail configured according to layout structure 1368B. In this example, the... Fig. 13C and Fig. In the example shown in 13D, the layout structures 1368A, 1368B can extend in both the X and Y directions so that the layout structures 1366A-1366D for the source / drain areas can have a regular or consistent structure.

[0046] The Fig. Figures 13E to 13F are top views 1370A, 1370B of a layout design of the exemplary multiplexer circuit 1300 by Fig. 13A with rear metal rails according to one embodiment. In one aspect, the top views 1370A, 1370B of a layout design show layout structures for components in different layers of the integrated circuit. In one aspect, it resembles the one in the Fig. 13E and Fig. Layout design shown on page 13F, which is in the Fig. 13C and Fig. 13D layout design shown, except that the layout design shown in the Fig. 13E and Fig. Figure 13F shows layout structures 1376A-1376D, which indicate the dimensions and / or locations of source / drain sections of varying lengths, and layout structures 1378A-1378C, which indicate the dimensions and / or locations of back-side metal rails (e.g., M-1 rails) extending in the X direction. For example, layout structures 1376C and 1376D extend in Fig. 13E in the Y direction such that it partially overlaps the layout structure 1378B, which extends in the X direction. In one aspect, a drain region or a source region of a transistor formed according to layout structure 1376C can be electrically connected to a rear metal rail formed according to layout structure 1378B via a via formed according to layout structure 1379D. Similarly, a drain region or a source region of a transistor formed according to layout structure 1376D can be electrically connected to the rear metal rail formed according to layout structure 1378B via a via formed according to layout structure 1379C. Thus, the layout structures 1376A-1376D can exhibit fluctuating structures if the layout structures 1378A-1378C extend only in one direction (e.g., in the X direction).

[0047] The Fig. 13G-13I are top views 1380A-1380C of a layout design of the exemplary multiplexer circuit 1300 by Fig. 13A with rear metal rails according to one embodiment. In one aspect, the top views 1380A-1380C of a layout design show layout structures for components in different layers of the integrated circuit. In one aspect, it resembles the one in the Fig. The layout design shown in the 13G-13I corresponds to the one in the Fig. 13C and Fig. 13D layout design shown, except that the layout design shown in the Fig. Figures 13G-13I show layout structures 1388A-1388C, which indicate the dimensions and / or locations of backplate metal rails (e.g., M-1 rails) extending in the X direction, and layout structures 1395A-1395B for other backplate metal rails (e.g., M-2 rails) extending in the Y direction. In one aspect, transistors can be connected via the backplate metal rails (e.g., M-1 rails) configured according to layout structures 1388A-1388C, the backplate metal rails (e.g., M-2 rails) configured according to layout structures 1395A-1395B, and vias configured according to layout structures 1389A-1389B and 1398A-1398D. The use of different layers of rear metal rails can offer flexibility in routing or connecting different components of an integrated circuit.Furthermore, the rear metal rails allow for flexibility in component placement and routing, enabling transistor layout structures (e.g., drain regions, source regions, and gate regions) to have regular or consistent shapes. Advantageously, such regular or consistent layout structures allow transistor components (e.g., gate regions, source / drain regions) to be formed consistently, resulting in more consistent transistor characteristics.

[0048] Fig. Figure 14A is a schematic diagram of an exemplary circuit 1400 according to one embodiment. Fig. 14B is a top view 1450 of a layout design of the exemplary circuit of Fig. 14A according to one embodiment. In one example, circuit 1400 is implemented as a flip-flop circuit. In one aspect, circuit 1400 includes a first section 1410A and a second section 1420B, which have a similar configuration to circuit 1300 in Fig. exhibiting 13A. Therefore, the 1300 circuit can be configured with cross-coupled connections, as shown in Fig. 14B shown. As above in relation to Fig. As shown in Figure 13B, rear-side metal rails can be used for local interconnection. Such use of rear-side metal rails allows flexibility in component placement and routing, enabling layout structures for forming the transistors (e.g., drain regions, source regions, and gate regions) to have regular or consistent shapes. Advantageously, such regular or consistent layout structures allow transistor components (e.g., gate regions, source / drain regions) to be formed consistently, resulting in more consistent transistor characteristics. Furthermore, the 1400 circuit can be implemented in a compact form because the number of front-side metal rails and vias can be reduced.

[0049] Fig. Figure 15 is a flowchart of a method 1500 for forming or manufacturing an integrated circuit according to some embodiments. It is understood that further processes may occur before, during, and / or after the process described in Figure 15. Fig. Method 1500 can be carried out as shown in Figure 15. In some embodiments, Method 1500 can be used to form an integrated circuit according to various layout designs disclosed herein.

[0050] In step 1510 of procedure 1500, a layout design of an integrated circuit is generated. Step 1510 is performed by a processor device (e.g., the processor 1602 of Fig. 16) is executed, which is configured to execute commands to generate a layout design. In one approach, the layout design is generated by placing layout designs of one or more standard cells via a user interface. In another approach, the layout design is automatically generated by a processor executing a synthesis tool that converts a logic design (e.g., Verilog) into a corresponding layout design. In some embodiments, the layout design is rendered in a GDSII (Graphic Database System) file format.

[0051] In step 1520 of method 1500, the integrated circuit is fabricated based on the layout design. In some embodiments, step 1520 of method 1500 comprises fabricating at least one mask based on the layout design and fabricating the integrated circuit based on the at least one mask. In one approach, step 1520 comprises steps 1522, 1524, 1526, 1528, and 1530. In step 1522, a first layer (e.g., a BM layer) is formed with a first metal rail (e.g., a back-side busbar). In step 1524, a second layer (e.g., an M-2 or M-1 layer) is formed with a second metal rail (e.g., a back-side metal rail). In one aspect, the second layer lies above the first layer along one direction (e.g., the Z-direction). In another approach, a first contact layer (e.g.,A second contact layer (e.g., a VB layer) containing one or more vias is formed between the first and second layers. The one or more vias in the first contact layer (e.g., the VB layer) can electrically connect the first metal rail (e.g., the rear power rail) and the second metal rail (e.g., the rear metal rail). In Procedure 1526, a third layer (e.g., an EPI layer) with an active region of a transistor along the direction (e.g., the Z direction) is formed above the second layer. In one approach, a second contact layer (e.g., a VDB layer) containing one or more vias can be formed between the second and third layers. In one aspect, the one or more vias in the second contact layer (e.g., the VDB layer) can electrically connect the transistor and the rear metal rail.In process 1528, a fourth layer (e.g., an MD layer) is formed with a third metal rail (e.g., an MD region) along the direction (e.g., the Z-direction) above the third layer. In some embodiments, the MD region is directly connected to the active region. In process 1530, a fifth layer (e.g., an M0 layer) is formed with a metal rail (e.g., an M0 rail) along the direction (e.g., the Z-direction) above the fourth layer. In one approach, a third contact layer (e.g., a VD layer) can be formed with one or more vias between the fourth and fifth layers. The one or more vias in the third contact layer (e.g., the VD layer) can electrically connect the MD region and the M0 rail.

[0052] Advantageously, the rear-side power rail and the rear-side metal rail allow flexibility in component placement and routing, enabling transistor layout structures (e.g., drain, source, and gate structures) to have regular or consistent shapes. This regular or consistent layout structure allows transistor components (e.g., source / drain regions, gate regions, etc.) to be formed consistently, resulting in more consistent transistor characteristics. Furthermore, the integrated circuit can be built in a more compact form because the number of front-side metal rails and vias can be reduced.

[0053] Fig. Figure 16 is a schematic view of a system 1600 for designing and fabricating an IC layout design according to some embodiments. In some embodiments, the system 1600 generates or places one or more of the IC layout designs described herein. In other embodiments, the system 1600 fabricates one or more ICs based on the one or more IC layout designs described herein. The system 1600 includes a hardware processor 1602 and a non-volatile, computer-readable storage medium 1604, which is encoded, for example, with computer program code 1606, such as a set of executable instructions. The computer-readable storage medium 1604 is configured to communicate with fabrication machines for manufacturing the integrated circuit. The processor 1602 is electrically connected to the computer-readable storage medium 1604 via a bus 1608. The processor 1602 is also electrically connected to an I / O interface 1610 via the bus 1608.A network interface 1612 is also electrically connected to the processor 1602 via the bus 1608. The network interface 1612 is connected to a network 1614, so that the processor 1602 and the computer-readable storage medium 1604 can establish a connection to external elements via the network 1614. The processor 1602 is configured to execute the computer program code 1606, which is encoded in the computer-readable storage medium 1604, to enable the system 1600 to be used to perform some or all of the operations described in the procedure 1500.

[0054] In some embodiments, the 1602 processor is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC) and / or a suitable processing unit.

[0055] In some embodiments, the computer-readable storage medium 1604 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or component or device). For example, the computer-readable storage medium 1604 includes a semiconductor or solid-state memory, a magnetic tape, a removable computer disk, random-access memory (RAM), read-only memory (ROM), a solid magnetic disk, and / or an optical disk. In some embodiments using optical disks, the computer-readable storage medium 1604 includes a compact disc (CD-ROM), a rewritable compact disc (CD-RW), and / or a digital video disc (DVD).

[0056] In some embodiments, the storage medium 1604 stores the computer program code 1606, which is configured to cause the system 1600 to execute the method 1500. In some embodiments, the storage medium 1604 also stores information required for executing the method 1500, as well as information generated during the execution of the method 1500, for example, a layout design 1616, a user interface 1618, and a manufacturing unit 1620, and / or a set of executable instructions for performing the operations of the method 1500.

[0057] In some embodiments, the storage medium 1604 stores instructions (e.g., the computer program code 1606) for communication with manufacturing machines. These instructions (e.g., the computer program code 1606) enable the processor 1602 to generate manufacturing instructions that can be read by the manufacturing machines to effectively implement the method 1500 during a manufacturing process.

[0058] The System 1600 includes the I / O interface 1610. The I / O interface 1610 is connected to external circuitry. In some embodiments, the I / O interface 1610 includes a keyboard, keypad, mouse, trackball, trackpad, and / or cursor keys for transmitting information and commands to the processor 1602.

[0059] The System 1600 also includes the 1612 network interface, which is connected to the 1602 processor. The 1612 network interface allows the System 1600 to communicate with the 1614 network, to which one or more other computer systems are connected. The 1612 network interface includes wireless network interfaces such as BLUETOOTH®, WIFI, and WIMAX. TM , GPRS or WCDMA; or wired network interfaces such as ETHERNET, USB or IEEE-13154. In some embodiments, the method 1500 is implemented in two or more systems 1600, and information such as layout design, user interface and manufacturing unit is exchanged between the different systems 1600 through the network 1614.

[0060] The System 1600 is configured to receive layout design information via the I / O interface 1610 or the network interface 1612. This information is transferred from the bus 1608 to the processor 1602 to determine a layout design for manufacturing an IC. The layout design is then stored on the computer-readable medium 1604 as layout design 1616. The System 1600 is also configured to receive user interface information via the I / O interface 1610 or the network interface 1612. This information is stored on the computer-readable medium 1604 as user interface 1618. Finally, the System 1600 is configured to receive manufacturing unit information via the I / O interface 1610 or the network interface 1612. This information is stored on the computer-readable medium 1604 as manufacturing unit 1620.In some embodiments, the manufacturing unit 1620 contains manufacturing information that is used by the system 1600.

[0061] In some embodiments, Method 1500 is implemented as a standalone software application for execution by a processor. In some embodiments, Method 1500 is implemented as a software application that is part of another software application. In some embodiments, Method 1500 is implemented as a plug-in for a software application. In some embodiments, Method 1500 is implemented as a software application that is part of an EDA tool. In some embodiments, Method 1500 is implemented as a software application that is used by an EDA tool. In some embodiments, the EDA tool is used to generate a layout design of the integrated circuit device. In some embodiments, the layout design is stored on a non-volatile, computer-readable medium.In some embodiments, the layout design is generated using a tool such as VIRTUOSO®, available from CADENCE DESIGN SYSTEMS, Inc., or another suitable layout generation tool. In some embodiments, the layout design is generated based on a netlist created from the schematic design. In some embodiments, the method 1500 is implemented by a fabrication device for manufacturing an integrated circuit using a set of masks produced based on one or more layout designs generated by the system 1600. In some embodiments, the system 1600 is a fabrication device (e.g., a fabrication tool 1622) for manufacturing an integrated circuit using a set of masks produced based on one or more layout designs of the present disclosure. In some embodiments, the system 1600 generates... Fig. Sixteen layout designs of an IC that are smaller than in other approaches. In some embodiments, the system generates 1600 of Fig. 16 layout designs of an IC that occupy less space than in other approaches.

[0062] Fig. Figure 17 is a block diagram of a manufacturing system 1700 for integrated circuits (IC) and an associated IC manufacturing flow according to at least one embodiment of the present disclosure.

[0063] In Fig. Figure 17 contains the IC manufacturing system 1700, comprising entities such as a design house 1720, a mask house 1730, and an IC fabrication / manufacturing facility (“fab” or factory) 1740, which collaborate in the design, development, and manufacturing cycles and / or in providing services related to the manufacture of an IC device 1760. The entities in the system 1700 are connected by a communication network. In some embodiments, the communication network is a single network. In other embodiments, the communication network consists of several different networks, such as an intranet and the internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more of the other entities, providing and / or receiving services to one or more of the other entities.In some embodiments, two or more of the Design House 1720, the Mask House 1730, and the IC Factory 1740 belong to a single company. In some embodiments, two or more of the Design House 1720, the Mask House 1730, and the IC Factory 1740 share a common facility and use common resources.

[0064] Design House (or Design Team) 1720 creates an IC design layout 1722. The IC design layout 1722 contains various geometric structures designed for an IC device 1760. These geometric structures correspond to structures of metal, oxide, or semiconductor layers that form the various components of the IC device 1760 to be manufactured. The different layers together form various IC features. For example, part of the IC design layout 1722 contains various IC features such as active areas, gate structures, source structures, drain structures, metal traces or vias of an interlayer connection, and openings for bond pads, which are to be formed on a semiconductor substrate (such as a silicon wafer) and various material layers arranged on the semiconductor substrate. Design House 1720 implements a suitable design process to create the IC design layout 1722.The design process comprises a logical design, a physical design, and / or place-and-route (or layout synthesis). The IC design layout 1722 is represented in one or more files containing information about the geometric structures. For example, the IC design layout 1722 can be represented in a GDSII file format or a DFII file format.

[0065] The mask house 1730 contains a mask data preparation unit 1732 and a mask fabrication unit 1734. The mask house 1730 uses the IC design layout 1722 to produce one or more masks to be used for fabricating the various layers of the IC device 1760 according to the IC design layout 1722. The mask house 1730 performs the mask data preparation unit 1732, which translates the IC design layout 1722 into a representative file (“RDF”). The data preparation unit 1732 for the masks provides the RDF to the mask fabrication unit 1734. The mask fabrication unit 1734 contains a mask writer. A mask writer converts the RDF into an image on a substrate, such as a mask (a reticulum) or a semiconductor wafer. The design layout is manipulated by the mask data preparation 1732 to fit certain properties of the mask writer and / or requirements of the IC factory 1740. Fig. Figure 17 shows the mask data preparation 1732 and the mask manufacturing 1734 as separate elements. In some embodiments, the data preparation 1732 for the masks and the mask manufacturing 1734 can be referred to collectively as data preparation for the masks.

[0066] In some embodiments, the data preparation 1732 for the masks includes optical near-field correction (OPC), which uses lithography enhancement techniques to compensate for image defects such as those caused by diffraction, interference, other process effects, and the like. The OPC modifies the IC design layout 1722. In some embodiments, the data preparation 1732 for the masks also includes resolution enhancement techniques (RET) such as off-axis illumination, sub-resolution auxiliary features (SRAF), phase-shift masks, other suitable techniques, and the like, or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as an inverse imaging problem.

[0067] In some embodiments, the data preparation 1732 for the masks includes a mask rule checker (MRC) that checks the IC design layout, which has undergone OPC processes, against a set of mask creation rules that include certain geometric and / or interconnection constraints to ensure adequate spacing, account for variability in semiconductor manufacturing processes, and the like. In some embodiments, the MRC modifies the IC design layout to compensate for constraints during mask manufacturing 1734 that may undo some of the modifications made by the OPC to satisfy the mask creation rules.

[0068] In some embodiments, the data preparation 1732 for the masks includes Lithography Process Check (LPC), which simulates processing implemented by the IC factory 1740 to manufacture the IC fixture 1760. The LPC simulates this processing based on the IC design layout 1722 to generate a simulated manufactured fixture such as the IC fixture 1760. The processing parameters in the LPC simulation may include parameters associated with various processes of the IC manufacturing cycle, parameters associated with IC manufacturing tools, and / or other aspects of the manufacturing process. The LPC takes into account various factors such as aerial image contrast, depth of field (DOF), mask defect improvement factor (MEEF), other suitable factors, and the like, or combinations thereof.In some embodiments, the OPC and / or the MRC can be repeated to further improve the IC design layout 1722 after the simulated manufactured device has been generated by the LPC if the simulated device is not close enough to a shape that meets the design rules.

[0069] It is understood that the above description of the data preparation 1732 for the masks has been simplified for clarity. In some embodiments, the mask data preparation 1732 includes additional features such as Logic Operation (LOP) to modify the IC design layout according to the manufacturing rules. Additionally, the processes applied to the IC design layout 1722 during the mask data preparation 1732 can be executed in a variety of different sequences.

[0070] Following mask data preparation 1732 and during mask fabrication 1734, a mask or a group of masks is produced based on the modified IC design layout. In some embodiments, an electron beam (e-beam) or a mechanism consisting of multiple electron beams is used to form a structure on a mask (photomask or reticulum) based on the modified IC design layout. The mask can be fabricated using various technologies. In some embodiments, the mask is formed using binary technology. In some embodiments, a mask structure contains opaque and transparent regions. A beam of radiation, such as an ultraviolet (UV) beam used to expose a photosensitive material layer (e.g., photoresist) coated on a wafer, is blocked by the opaque regions and transmitted through the transparent regions.In one example, a binary mask contains a transparent substrate (e.g., quartz glass) and an opaque material (e.g., chromium) that is coated in the opaque areas of the mask. In another example, the mask is formed using phase-shift technology. In phase-shift masks (PSMs), various features in the structure formed on the mask are configured to have a suitable phase difference to improve resolution and image quality. In various examples, the phase-shift mask can be a halftone PSM or an alternating PSM. The masks produced by the Mask Fabrication 1734 are used in a variety of processes. For example, such masks are used in ion implantation processes to form different doped regions in the semiconductor wafer, in etching processes to form different etched regions in the semiconductor wafer, and / or in other suitable processes.

[0071] IC Factory 1740 is an IC manufacturing entity that contains one or more manufacturing facilities for producing a variety of different IC products. In some embodiments, IC Factory 1740 is a semiconductor foundry. For example, there may be one manufacturing facility for the front-end manufacturing of multiple IC products (front-end-of-line (FEOL) manufacturing), while a second manufacturing facility may provide back-end manufacturing for interconnection and packaging of the IC products (back-end-of-line (BEOL) manufacturing), and a third manufacturing facility may provide other services to the foundry entity.

[0072] IC Factory 1740 uses the mask (or masks) produced by Mask House 1730 to manufacture IC Device 1760. Thus, IC Factory 1740 uses, at least indirectly, IC Design Layout 1722 to manufacture IC Device 1760. In some embodiments, IC Factory 1740 produces a semiconductor wafer 1742 using the mask (or masks) to form IC Device 1760. The semiconductor wafer 1742 contains a silicon substrate or other suitable substrate with material layers formed on it. The semiconductor wafer further contains various doped regions, dielectric features, multi-layer interconnects, and / or the like (formed in subsequent manufacturing steps).

[0073] System 1700 is shown to have the Design House 1720, the Mask House 1730, or the IC Factory 1740 as separate components or entities. However, it is understood that the Design House 1720, the Mask House 1730, and / or the IC Factory 1740 can be part of the same component or entity.

[0074] Details regarding a manufacturing system for integrated circuits (ICs) (e.g., the System 1700 from Fig. 17) and an associated IC manufacturing flow can be found, for example, in US Patent Publication US 9 256 709 B2, granted on February 9, 2016, US Publication US 2015 / 0 278 429 A1, published on October 1, 2015, US Publication US 2010 / 0 040 838 A1, published on February 6, 2014, and US Patent Publication US 7 260 442 B2, granted on August 21, 2007.

[0075] One aspect of this description concerns an integrated circuit. In some embodiments, the integrated circuit includes a first layer with a first metal rail. In some embodiments, the integrated circuit includes a second layer with a second metal rail, the second layer being located above the first layer along a first direction. In some embodiments, the integrated circuit includes a third layer with an active region of a transistor, the third layer being located above the second layer along a first direction. In some embodiments, the integrated circuit includes a fourth layer with a third metal rail, the fourth layer being located above the third layer along a first direction.In some embodiments, the integrated circuit includes a fifth layer with a fourth metal rail, the fifth layer being located above the fourth layer along the first direction.

[0076] One aspect of this description relates to a method for forming an integrated circuit. In some embodiments, the method comprises forming a first layer with a first metal rail. In some embodiments, the method comprises forming a second layer with a second metal rail, wherein the second layer is located above the first layer along a first direction. In some embodiments, the method comprises forming a third layer with an active region of a transistor, wherein the third layer is located above the second layer along the first direction. In some embodiments, the method comprises forming a fourth layer with a third metal rail, wherein the fourth layer is located above the third layer along the first direction.In some embodiments, the method includes forming a fifth layer with a fourth metal rail, wherein the fifth layer is located above the fourth layer along the first direction.

[0077] One aspect of this description concerns an integrated circuit. In some embodiments, the integrated circuit includes a first layer with an active region of a transistor. In some embodiments, the integrated circuit includes a second layer with a first metal rail directly connected to a first side of the active region of the transistor, the second layer being located above the first layer along a first direction. In some embodiments, the integrated circuit includes a third layer with a second metal rail connected via a first via to a second side of the active region of the transistor, the second side being oriented away from the first side. In one aspect, the first layer is located above the third layer along the first direction.In some embodiments, the integrated circuit includes a fourth layer with a third metal rail connected to the second metal rail via a second via, with the third layer positioned above the fourth layer along the first direction. In some embodiments, the integrated circuit includes an additional active region of the transistor. In some embodiments, the second layer includes a fourth metal rail directly connected to a first side of the additional active region of the transistor. In some embodiments, the third layer includes a fifth metal rail connected to a second side of the additional active region of the transistor via a third via.The third metal rail can provide a supply voltage for the active area of ​​the transistor via the second metal rail, while the fifth metal rail can carry an electrical signal to or from the further active area of ​​the transistor.

Claims

[1] Integrated circuit comprising: a first layer with a first metal rail (210A); a second layer (M-1) with a second metal rail (240A), wherein the second layer (M-1) is located along a first direction (Z) above the first layer; a third layer (EPI) with an active region (262A) of a transistor, wherein the third layer (EPI) is located along the first direction (Z) above the second layer (M-1); and a fourth layer (MD) with a third metal rail (265A), wherein the fourth layer (MD) is located along the first direction (Z) above the third layer (EPI), wherein the first metal rail (210A) is configured to provide a supply voltage for the active region (262A) of the transistor via the second metal rail (240A), wherein the third metal rail (265A) is directly connected to a second side of the active area (262A) of the transistor, wherein the fourth layer (MD) contains a fifth metal rail (265B) which is directly connected to another active area (262B) of the transistor, wherein the second layer (M-1) contains a sixth metal rail (240B) which is connected to the further active area (262B) of the transistor. [2] Integrated circuit according to claim 1, further comprising a fifth layer (M0) with a fourth metal rail (270), wherein the fifth layer (M0) is located along the first direction (Z) above the fourth layer (MD). [3] Integrated circuit according to claim 1 or 2, wherein the fifth metal rail (265B) is configured to carry an electrical signal to or from the transistor. [4] Integrated circuit according to one of the preceding claims, wherein the first metal rail (210A) is electrically connected to the second metal rail (240A) via a first via (250A) and the second metal rail (240A) is electrically connected to a first side of the active area (262A) of the transistor via a second via (260A). [5] Integrated circuit according to any one of the preceding claims, wherein the third metal rail (265A) extends in a second direction (Y) perpendicular to the first direction (Z), wherein the third metal rail (265A) has a first end and a second end, and wherein the fifth metal rail (265B) extends in the second direction (Y), wherein the fifth metal rail (265B) has a third end and a fourth end, wherein the first end of the third metal rail (265A) and the third end of the fifth metal rail (265B) are aligned with each other, and wherein the second end of the third metal rail (265A) and the fourth end of the fifth metal rail (265B) are aligned with each other. [6] Integrated circuit according to one of the preceding claims, wherein the sixth metal rail (240B) is connected to an active area of ​​another transistor. [7] Integrated circuit according to claim 6, further comprising: a seventh metal rail of the transistor extending in one or the second direction (Y) perpendicular to the first direction (Z), wherein the seventh metal rail is arranged between the active area (262A) of the transistor and the further active area (262B) of the transistor, wherein the seventh metal rail partially overlaps the sixth metal rail (240B, 340, 540). [8] Integrated circuit according to any one of claims 2 to 7, wherein the integrated circuit has the fifth layer (M0) with the fourth metal rail (270) and the fourth metal rail (270) extends in a third direction (X) perpendicular to the first direction (Z), wherein the first metal rail (210A / B) extends in the third direction (X). [9] Integrated circuit according to claim 8, wherein the second metal rail (240A) extends in one or the second direction (Y), wherein the first direction (Z) is perpendicular to the third direction (X) and to the second direction (Y). [10] Integrated circuit according to claim 8, wherein the second metal rail (240A, 340, 540) extends in the third direction (X). [11] Integrated circuit according to any one of claims 1 to 8 or according to claim 10, further comprising: a sixth layer with an eighth metal rail (710A-E) between the first layer and the second layer (M-1), wherein the second metal rail (240A, 340, 540, 640A) extends in one or the third direction (X), wherein the eighth metal rail (710A-E) extends in one or the second direction (Y), and wherein the first direction (Z) is perpendicular to the third direction (X) and to the second direction (Y). [12] Method for forming an integrated circuit, the method comprising: Forming a first layer with a first metal rail (210A); Forming a second layer (M-1) with a second metal rail (240A), wherein the second layer (M-1) is located along a first direction (Z) above the first layer; Forming a third layer (EPI) with an active region (262A) of a transistor, wherein the third layer (EPI) is located along the first direction (Z) above the second layer (M-1); and Forming a fourth layer (MD) with a third metal rail (265A), wherein the fourth layer (MD) is located along the first direction (Z) above the third layer (EPI), wherein the first metal rail (210A) is configured to provide a supply voltage to the active area (262A) of the transistor via the second metal rail (240A), wherein the third metal rail (265A) is directly connected to a second side of the active area (262A) of the transistor, wherein the fourth layer (MD) contains a fifth metal rail (265B) which is directly connected to another active area (262B) of the transistor, wherein the second layer (M-1) contains a sixth metal rail (240B) which is connected to the further active area (262B) of the transistor. [13] The method of claim 12, further comprising: Forming a fifth layer (M0) with a fourth metal rail (270), wherein the fifth layer (M0) is located along the first direction (Z) above the fourth layer (MD), [14] Method according to claim 12 or 13, wherein the fifth metal rail (265B) is configured to carry an electrical signal to or from the transistor. [15] Method according to any one of claims 12 to 14, further comprising: Forming a first via (250A / C) for electrically connecting the first metal rail (210A / B) to the second metal rail (240A / C); and forming a second via (260A / C) for electrically connecting the second metal rail (240A / C) to the active area (262A / C) of the transistor.

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