PHASE CONTROL CIRCUIT AND CLOCK GENERATOR WITH SUCH A CIRCUIT

Abstract

Phase-locked loop (PLL) circuit (PLL_CKT), comprising: a voltage-controlled oscillator (40; 101) configured to generate an output clock signal; a subsampling PLL circuit (30; 30a) configured to receive the output clock signal as a feedback signal and to perform a fractional-frequency division-based phase-locking operation based on it; and a fractional frequency division control circuit (10; 10a) configured to supply a selection reference clock signal for the fractional frequency division-based phase locking operation of the subsampling PLL circuit (30; 30a), the fractional frequency division control circuit (10; 10a) comprises: a voltage-controlled delay line (16; 110) which is set up to guide the feedback signal and to generate delay information (or information) based on the feedback signal; a simulated voltage-controlled delay line (18; 112) to which the delay information(s) is / are applied and which is configured to carry a reference clock signal to generate a plurality of delay reference clock signals, each delayed by up to a different respective delay time; and a digital time converter (DTC) (12; 113a; 113b) which is configured to generate the selection reference clock signal from the plurality of delay reference clock signals and output the selection reference clock signal to the subsampling PLL circuit (30; 30a).

Description

CROSS-REFERENCE TO RELATED REGISTRATION

[0001] This application claims the benefits of Korean patent application No. 10-2019-0125676, which was filed with the Korean Intellectual Property Office on October 10, 2019, and whose disclosure is incorporated herein by reference in its entirety. Technical area

[0002] This disclosure generally relates to phase-locked loops (PLLs) and clock generators with PLLs, and in particular to a PLL that includes a subsampling PLL for fraction-frequency division-based phase locking of a clock. Discussion about the state of the art

[0003] A PLL in a clock generator or similar device is a circuit that can generate a phase-locked clock signal. This clock signal can be used, for example, to transmit data in a transmitter or to restore data in a receiver. In this respect, the PLL can be classified, for example, as a toroidal PLL or an inductor-capacitor (LC) PLL.

[0004] Recently, a technique for locking the phase of a clock signal through undersampling was applied to a PLL to improve its noise characteristics. For example, an undersampling PLL might include a phase detector and a voltage-controlled oscillator (VCO), where the phase detector undersamples an output of the VCO with a reference clock. Another technique is fractional frequency division, which uses a fractional frequency divider in the feedback path. However, because a divider does not perform frequency division on a clock signal during undersampling, this has limited the performance of fractional frequency division operations. To overcome this limitation, a technique was introduced that enables fractional frequency division during undersampling by using a digital-to-analog converter.However, the performance of the clock generator has deteriorated in this method due to the limited resolution and quantization noise.

[0005] German patent DE 102 32 382 A1 discloses a PLL circuit in which variable delay lines delay an input clock and a feedback clock, providing a delayed input clock and a delayed feedback clock to a PLL section. The PLL section receives the delayed input clock and the delayed feedback clock and outputs a PLL output so that these signals are synchronized. The PLL output is then fed back as the feedback clock via an external circuit. A phase detector detects a phase difference between the input clock and the feedback clock and outputs a phase comparison signal. A control logic circuit determines a degree of phase advance of the feedback clock relative to the input clock based on the phase comparison signal and controls a delay time of the variable delay line so that any phase error between the input clock and the feedback clock becomes zero.

[0006] Furthermore, WO 2006 / 081668A1 discloses a Delay-Locked Loop (DLL) with an initialization control unit which causes the DLL to first search for a latching point starting from an output delay, varying the delay in one direction, and the initialization control unit is further configured to skip a first latching point and continue varying the delay in one direction to search for another latching point and select it as the operating point. SUMMARY

[0007] Embodiments of the inventive concept provide a phase-locked loop (PLL) that includes a fractional frequency division control circuit which has a higher resolution with respect to fractional frequency division phase control over a clock and is able to reduce quantization noise, as well as a clock generator that includes a PLL.

[0008] According to one aspect of the inventive concept, a phase-locked loop (PLL) circuit is provided which includes a voltage-controlled oscillator configured to generate an output clock signal, a subsampling PLL circuit configured to receive the output clock signal as a feedback signal and to perform a fraction-rate division-based phase-lock operation based on it, and a fraction-rate division control circuit configured to supply a selection reference clock signal for the fraction-rate division-based phase-lock operation to the subsampling PLL circuit.The fractional frequency division control circuit includes a voltage-controlled delay line configured to route the feedback signal and generate delay information based on the feedback signal; a simulated voltage-controlled delay line to which the delay information is applied and configured to route a reference clock signal to generate a plurality of delay reference clock signals, each delayed by up to a different respective delay time; and a digital time converter (DTC) configured to generate the selection reference clock signal from the plurality of delay reference clock signals and output the selection reference clock signal to the subsampling PLL circuit.

[0009] According to another aspect of the inventive concept, a phase-locked loop (PLL) circuit is provided comprising a voltage-controlled oscillator configured to generate an output clock signal, a subsampling PLL circuit configured to receive the output clock signal as a feedback signal and to perform a fractional-frequency division-based phase-lock operation based thereon, and a fractional-frequency division control circuit configured to supply a selection reference clock signal for the fractional-frequency division-based phase-lock operation to the subsampling PLL circuit, wherein the fractional-frequency division control circuit is further configured to generate delay information with respect to a constant delay time within one cycle of the feedback signal by performing a delay operation using the feedback signal.which has a first frequency, to generate a multitude of delay reference clock signals based on the delay information(s), which are gradually delayed by up to the delay time by using a reference clock signal with a second frequency, and to generate the selection reference clock signal using the multitude of delay reference clock signals.

[0010] According to another aspect of the inventive concept, a clock generator comprises a voltage-controlled oscillator configured to generate an output clock signal, a support phase-locked loop (PLL) circuit configured to perform an integer frequency division-based phase-lock operation on the output clock signal, a subsampling PLL circuit configured to perform a fractional frequency division-based phase-lock operation on the output clock signal after the integer frequency division-based phase-lock operation, and a fractional frequency division control circuit configured to supply a selection reference clock signal for the fractional frequency division-based phase-lock operation to the subsampling PLL circuit, wherein the fractional frequency division control circuit includes a voltage-controlled delay line configured toto guide a feedback signal for generating delay information, a simulated voltage-controlled delay line to which the delay information(s) is / are applied, comprising the same characteristics as the voltage-controlled delay line and configured to guide a reference clock signal for generating a plurality of delay reference clock signals, each delayed by up to a different delay time, and a digital time converter (DTC) configured to generate the selection reference clock signal from the plurality of delay reference clock signals and output the selection reference clock signal to the subsampling PLL circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Embodiments of the inventive concept are more clearly understood with reference to the following detailed description in conjunction with the accompanying drawings, in which similar reference symbols denote similar elements or features, wherein Fig. 1 is a block diagram of a clock generator according to one embodiment; Fig. Figure 2 is a flowchart describing a phase locking operation of a phase control loop (PLL) circuit according to one embodiment; Fig. 3A and Fig. Figure 3B shows detailed block diagrams of a clock generator according to one embodiment; Fig. Figure 4 is a circuit diagram of a transconductance circuit. Fig. 3A or Fig. 3B according to one embodiment; Fig. Figure 5 is a flowchart describing a method for implementing a fractional-frequency division-based subsampling PLL of a PLL circuit according to one embodiment; Fig. Figure 6 is a timing diagram for describing a delay output clock signal that has passed through a voltage-controlled delay line and a delay reference clock signal that has passed through a simulated voltage-controlled delay line, according to one embodiment; Fig. Figure 7 is a block diagram describing the operation of a delay control loop (DLL) circuit according to one embodiment; Fig. Figure 8A is a block diagram of a DLL circuit according to one embodiment, and Fig. Figure 8B is a graph describing the functionality of the DLL circuit. Fig. 8A; Fig. 9 and Fig. Figure 10 shows detailed block diagrams of a digital time converter according to one embodiment; Fig. 11 is a block diagram of a wireless communication device according to one embodiment; Fig. 12 is a diagram showing communication devices that include clock generators for performing a phase-locking operation of a clock according to one embodiment; and Fig. Figure 13 is a block diagram of an IoT device (IoT = Internet of Things) according to one embodiment. DETAILED DESCRIPTION OF EXECUTION FORMS

[0012] The embodiments are described in detail below with reference to the attached drawings.

[0013] Fig. Figure 1 is a block diagram of a clock generator 1 according to one embodiment.

[0014] The clock generator 1 can include a phase-locked loop (PLL) circuit PLL_CKT, wherein the PLL circuit PLL_CKT can include a fractional frequency division control circuit 10, a support PLL circuit 20, a subsampling PLL circuit 30, and a voltage-controlled oscillator (VCO) 40. According to some embodiments, the VCO 40 can be implemented in various configurations, such as a ring oscillator or an inductor-capacitor (LC) oscillator, which may be used as examples below. For the sake of simplicity, phase delay and time delay may be used interchangeably below. Hereinafter, “PLL x” and “DLL y” refer to “PLL circuit x” and “DLL circuit y,” respectively, or similar, where “x” or “y” is the previously named key for the circuit element under discussion. For example, “PLL 20” refers to PLL circuit 20 and “DLL 14” refers to DLL circuit 14.

[0015] The support PLL 20 can perform a first phase-lock operation by receiving an output clock signal (generally referred to as a "vibration signal") from the VCO 40. Subsequently, the first phase-lock operation can be performed to achieve a difference between the phase of an output clock signal and the phase of a reference clock signal that falls within a specific locking range. This enables a second phase-lock operation for an output clock signal of the subsampling PLL 30. Therefore, the first phase-lock operation can be called a support phase-lock operation, preceding a second phase-lock operation of the subsampling PLL 30. The first phase-lock operation performed by the support PLL 20 can be referred to as a support PLL operation.According to one embodiment, the first phase-locking operation can be an integer frequency division-based phase-locking operation. In this case, an integer division ratio of the first phase-locking operation can be set to a fractional division ratio approximately equal to a target fractional division ratio, the setting being performed by the fractional frequency division control circuit 10 described below. In this context, the supporting PLL 20 can include a divider with a configuration in which a division ratio is set by the fractional frequency division control circuit 10. Although... Fig. Figure 1 shows that the support PLL 20 applies a specific control voltage signal directly to the VCO 40; however, other circuit arrangements are possible. For example, as shown in Fig. 3A below describes a support PLL 20a sharing a loop filter 106 with a subsampling PLL 30a and thereby applying a specific control voltage signal Vctrl via the loop filter 106 to a VCO 101.

[0016] The subsampling PLL 30 can receive an output clock signal (an output clock that is initially phase-locked by the support PLL 20) from the VCO 40 in a feedback path. The output clock signal in the feedback path can therefore be referred to here as the feedback signal. The subsampling PLL 30 can perform subsampling using the feedback signal. The subsampling PLL 30 can perform a fractional-frequency division-based phase-locking operation (or a second phase-locking operation) on the feedback signal, and the subsampling PLL 30 can receive a selection reference clock signal for the fractional-frequency division-based phase-locking operation from the fractional-frequency division control circuit 10. The fractional-frequency division control circuit 10 is described below according to one embodiment.

[0017] The fractional frequency division control circuit (10) can include a digital time converter (DTC) 12, a delay control loop (DLL) circuit 14, a voltage-controlled delay line 16, and a simulated voltage-controlled delay line 18. The voltage-controlled delay line 16 can receive an output clock signal from the VCO 40 as a feedback signal and, based on the received feedback signal, output a feedback signal delayed by up to a maximum phase. The maximum phase can vary depending on the type of input / output signal from the VCO 40 or the target fractional division ratio. For example, if an input / output signal from the VCO 40 is a single-terminated signal, the maximum phase can be 360 ​​degrees, and if, as another example, an input / output signal from the VCO 40 is a differential signal, the maximum phase can be 180 degrees.Although for the sake of simplicity, the following description assumes that an internal signal of the PLL PLL_CKT is a single-terminated signal, other signal types are also available. For example, an internal signal of the PLL PLL_CKT can alternatively be a differential signal. According to one embodiment, the voltage-controlled delay line 16 can contain multiple first delay elements connected in series, and the voltage-controlled delay line 16 can have a configuration that corresponds to the number of phases that a selection reference clock signal supplied to the subsampling PLL 30 can have. For example, as the number of phases that the selection reference clock signal can have increases, so too can the number of first delay elements in the voltage-controlled delay line 16.

[0018] In one embodiment, the DLL 14 can be connected to the voltage-controlled delay line 16 and generate delay information by latching a feedback signal that is delayed by passing through the voltage-controlled delay line 16. For example, the DLL 14 can generate delay information by a delay latching operation for a feedback signal that passes through the voltage-controlled delay line 16. The delay information can be used to control the time delay (or phase delay) at a first frequency (or a high frequency) of a feedback signal (or an output clock signal of the VCO 40).This means that the delay information(s) can be used to control a feedback signal, which is to be delayed by a maximum constant delay time corresponding to one cycle of the feedback signal through the voltage-controlled delay line 16. The delay information can, for example, contain a bias voltage for several initial delay elements contained in the voltage-controlled delay line 16. The bias voltage can be applied to a delay element so that the delay element can delay a signal by a constant delay time up to a target delay time, despite changes in the operating environment of the clock generator 1 or the PLL PLL_CKT, or the process, voltage, and temperature (PVT) conditions. The DLL 14 can supply delay information to the simulated voltage-controlled delay line 18.DLL 14 can perform a delay-locking operation to prevent harmonic locking and generate accurate delay information. For example, if the phase of a delayed feedback signal falls within a certain locking range by setting a delay level of the feedback signal caused by the voltage-controlled delay line 16, DLL 14 can initiate a locking-delay operation of the feedback signal.

[0019] According to one embodiment, the replicated voltage-controlled delay line 18, which is a replica of the voltage-controlled delay line 16, can contain a plurality of second delay elements with the same configurations or properties as the plurality of first delay elements contained in the voltage-controlled delay line 16. The delay information received by the DLL 14 can be fed to the replicated voltage-controlled delay line 18, and the replicated voltage-controlled delay line 18 can generate a plurality of delay reference clock signals by receiving a reference clock signal, each delayed by up to a different delay time. Each of the multiple delay reference clock signals can be delayed by a different amount.The reference clock signal can have a second frequency that is lower than a first frequency (or a high frequency) of a feedback signal (or an output clock signal of VCO 40), and the ratio of the first frequency of the output signal (or feedback signal), which is phase-locked by the subsampling PLL 30, to the second frequency of the reference clock signal can have a target fractional division ratio. For example, the simulated voltage-controlled delay line 18 can contain a plurality of second delay elements connected in series, to which delay information is / are supplied to delay a received signal by the same delay time as the plurality of first delay elements of the voltage-controlled delay line 16.The received signal can be delayed by the same amount as the plurality of first delay elements of the voltage-controlled delay line 16. The simulated voltage-controlled delay line 18 can output a plurality of delay reference clock signals, which are gradually delayed by the delay time from the received reference clock signal to the DTC 12. For example, a plurality of delay reference clock signals can be output to the DTC 12 via the respective output ends of the plurality of second delay elements of the simulated voltage-controlled delay line 18.

[0020] In one embodiment, the DTC 12 can receive a plurality of delay reference clock signals from the simulated voltage-controlled delay line 18 and generate a selection reference clock signal from the plurality of delay reference clock signals, outputting the selection reference clock signal to the subsampling PLL 30. The DTC 12 can generate a selection reference clock signal with a phase that is set based on a target fractional division ratio. For example, the DTC 12 can select a delay reference clock signal from the plurality of delay reference clock signals and generate a selection reference clock signal by fine-tuning the delay for the selected delay reference clock signal. A fine delay range for the selected delay reference clock signal in the DTC 12 can correspond to a constant delay time between the plurality of delay reference clock signals.For example, a fine delay range for the selected delay reference clock signal in the DTC 12 can be limited within the constant delay time. The DTC 12 can generate an A-bit signal (where A is an integer of 1 or higher) for internal selection of one of several delay reference clock signals and a B-bit signal (where B is an integer of 1 or higher) for setting the delay for the selected delay reference clock signal. The A-bit signal can have a larger, smaller, or the same number of bits as the B-bit signal.

[0021] According to the embodiments described above, the output clock signal of the VCO 40 can be phase-locked by the subsampling PLL 30, and the output clock signal can be output to a sampling block (e.g. an analog-to-digital converter (ADC) or a digital-to-analog converter (DAC)).

[0022] It should be noted here that an implementation example of the in Fig. The clock generator shown in Figure 1 is merely an example. Minimum configurations to which the inventive concept can be applied can be designed in various other ways.

[0023] According to one embodiment, the PLL circuit PLL_CKT can generate delay information by the voltage-controlled delay line 16 by receiving an output clock signal from the VCO 40 as a feedback signal, and can use a variety of delay reference clock signals generated by feeding the delay information to the simulated voltage-controlled delay line 18 in a fractional-frequency division-based phase-locking operation, thereby efficiently increasing the resolution for a phase of a selection reference clock signal. Since a selection reference clock signal is generated using an output clock signal from the VCO 40, jitter of the output clock signal can be reflected in the selection reference clock signal.The overall jitter performance of the PLL PLL_CKT can be improved by mitigating the time shift between the selection reference clock signal received by the subsampling PLL circuit 30 and the output clock signal of the VCO 40.

[0024] Fig. Figure 2 is a flowchart describing a phase-lock operation of a PLL circuit according to one embodiment. The following section describes... Fig. 2 with reference to Fig. 1 described.

[0025] With reference to Fig. 2. In operation S100, the PLL circuit PLL_CKT can perform a first phase-lock operation for an output clock signal from VCO 40 using the supporting PLL circuit 20. In one embodiment, the first phase-lock operation can be an integer frequency division-based phase-lock operation. In other embodiments, however, the first phase-lock operation can be a fractional frequency division-based phase-lock operation, and a fractional division ratio of the first phase-lock operation can be set by the fractional frequency division control circuit 10.The support PLL circuit 20 can perform a first phase-locking operation to lock a phase of an output clock signal of the VCO 40 and can perform the first phase-locking operation to achieve a difference between a phase of a frequency-split output clock signal and a phase of a reference clock signal within a certain range, hereinafter referred to as the "dead zone". The support PLL circuit 20 can be deactivated if a difference between a phase of a frequency-split output clock signal and a phase of a reference clock signal lies within the dead zone.

[0026] In operation S110, the PLL PLL_CET can perform a second phase-lock operation on the output clock signal from VCO 40 by using the subsampling PLL circuit 30. According to one embodiment, the second phase-lock operation can be a fractional-frequency division-based phase-lock operation, and the fractional division ratio of the second phase-lock operation can be set by the fractional-frequency division control circuit 10. For example, the subsampling PLL 30 can receive a selection reference clock signal from the fractional-frequency division control circuit 10 and thus perform the second phase-lock operation based on the selection reference clock signal.

[0027] The fractional frequency division control circuit (10) according to one embodiment can receive an output clock signal from the VCO 40 and, using the DLL 14 and the voltage-controlled delay line 16, generate delay information at a frequency of the output clock signal. The fractional frequency division control circuit 10 can apply the delay information to the simulated voltage-controlled delay line 18 and can generate a plurality of delay reference clock signals from the reference clock signal using the simulated voltage-controlled delay line 18. The fractional frequency division control circuit 10 can generate a selection reference clock signal from the plurality of delay reference clock signals using the DTC 12 and can output the selection reference clock signal to the subsampling clock 30.

[0028] Fig. 3A and Fig. 3B are detailed example block diagrams of a clock generator 100 according to the respective embodiments. Although the signals in Fig. 3A and Fig. Figure 3B, which are shown simply for the sake of simplicity, shows that in some embodiments the VCO 101 can output differential signals with opposite phases over two lines, and the clock generator 100 can be implemented to perform phase locking using the differential signals. Fig. 3B illustrates additional signals and signal paths used in clock generator 100. Fig. 3A can be implemented.

[0029] Referring to Fig. 3A the clock generator 100 can be a support PLL circuit 20a, an FFD control circuit 10a, a subsampling PLL circuit 30a (the examples for the corresponding circuits 20, 10 and 30 in Fig. 1) and the VCO 101. The support PLL circuit 20a may include a divider 102, a phase-frequency detector 103, a dead-zone circuit 104, and a charge pump 105. The subsampling PLL circuit 30a may include a loop filter 106, a sampler 107, a transconductance (“GM”) circuit 108, and a pulse generator 109. The FFD control circuit 10a may include a voltage-controlled delay line 110, a DLL circuit 111, a simulated voltage-controlled delay line 112, and a DTC 113a.

[0030] The clock generator 100 differs slightly from the clock generator 1 in Fig. 1 by the fact that the support PLL circuit 20 and the subsampling PLL circuit 30 of Fig. 1. The loop filter 106 can be shared, while the loop filter 106 is part of the subsampling PLL circuit 30a of Fig. 3A is included.

[0031] The VCO 101 can supply an output clock signal VCO_clk to the divider 102, which can frequency-divide the output clock signal VCO_clk and supply a frequency-divided clock signal DIV_clk to the phase-frequency detector 103. The divider 102 can be implemented as an integer divider. The phase-frequency detector 103 can receive both a reference clock signal Ref_clk and the frequency-divided clock signal DIV_clk and can supply a detection result to the dead-zone circuit 104 by detecting a phase difference (a "phase offset") between the reference clock signal Ref_clk and the frequency-divided clock signal DIV_clk. Although Fig. Figure 3A shows that the phase-frequency detector 103 receives the reference clock signal Ref_clk from the DTC 113a; in other examples, the reference clock signal Ref_clk may be received via a different path. The dead zone circuit 104 can determine whether a phase difference between the reference clock signal Ref_clk and the frequency-split clock DIV_clk lies within a preset dead zone. If the phase difference is within the dead zone, the dead zone circuit 104, in conjunction with the other circuit of the support PLL circuit 20a, can complete an initial phase-lock operation and can deactivate the support PLL circuit 20a. If the phase difference is outside the dead zone, the dead zone circuit 104 can feed a detection result received from the phase-frequency detector 103 to the charge pump 105.Based on the acquisition result, the charge pump 105 can generate the control voltage signal Vctrl and supply it to the VCO 101. As described above, until a phase difference between the reference clock signal Ref_clk and the frequency-divided clock DIV_clk falls into the dead zone, the first phase-locking operation can be repeated using the divider 102, the phase frequency detector 103, the dead zone circuit 104, and the charge pump 105. Subsequently, the clock generator 100 can perform a second phase-locking operation using a subsampling PLL circuit for fine-tuning the phase of the output clock signal VCO_clk.

[0032] For example, VCO 101 can feed its output clock signal VCO_clk phase-locked to sampler 107 in a feedback path via the first phase-locking operation (and can therefore be referred to here as a feedback signal). Sampler 107 can receive both the output clock signal VCO_clk and the reference clock signal Ref_clk and generate a sampling voltage signal V_sam by sampling the output clock signal VCO_clk based on the reference clock signal Ref_clk. Although Fig. Figure 3A shows that the probe 107 receives the reference clock signal Ref_clk from the DTC 113a. However, the inventive concept is not limited to this, and the reference clock signal Ref_clk can be received via another path. The probe 107 can be described as a subsampling phase detector. The transconductance circuit 108 can receive the sampling voltage signal V_sam, convert the sampling voltage signal V_sam into a sampling current signal I_sam based on a pulse signal Pul received from the pulse generator 109, and output the sampling current signal I_sam to the loop filter 106. The loop filter 106 can generate the control voltage signal Vctrl by filtering the sampling current signal I_sam. The pulse generator 109 can receive a selection reference clock signal Ref_clk_sel from the DTC 113a and generate the pulse signal Pul based on the selection reference clock signal Ref_clk_sel.Detailed example configurations of the pulse generator 109 are given below with reference to . Fig. 4 described, and an operation to generate the selection reference clock signal Ref_clk_sel is described below.

[0033] The voltage-controlled delay line 110 can receive the output clock signal VCO_clk from VCO 40 and, based on this, output: (i) a first delay output clock signal VCO_clk_Φ1, which is identical to the output clock signal VCO_clk (effectively passing the output clock signal VCO_clk through it), and (ii) a second delay output clock signal VCO_clk_Φn, which has a specific phase difference Φn-Φ1 to the first delay output clock signal VCO_clk_Φ1. The voltage-controlled delay line 110 can contain multiple first delay elements connected in series, and the second delay output clock signal VCO_clk_Φn can be a signal generated by sequentially passing the output clock signal VCO_clk through all of the multiple first delay elements.

[0034] The DLL circuit 111 can perform a delay-locking operation using the first delay output clock signal VCO_clk_Φ1 and the second delay output clock signal VCO_clk_Φn received from the voltage-controlled delay line 110, thus generating delay information VDLL with respect to the output clock signal VCO_clk. For example, if the number of first delay elements of the voltage-controlled delay line 110 is 'K', the delay information VDLL can contain information to control each of the first delay elements to delay a signal by up to (Φn-Φ1) / K degrees. The delay information VDLL can be a bias applied to each of several first delay elements of the voltage-controlled delay line 110. For example, ifIf the second delay output clock signal VCO_clk_Φn has a phase difference of 360 degrees relative to the first delay output clock signal VCO_clk_Φ1 and the number of first delay elements of the voltage-controlled delay line is 110 32, the delay information(s) can contain information to control each of the first delay elements to delay a signal by up to 11.25 degrees (a delay by a time corresponding to a phase difference of 11.25 degrees).

[0035] The DLL circuit 111 can supply the delay information VDLL to the simulated voltage-controlled delay line 112. The simulated voltage-controlled delay line 112, which is a simulation of the voltage-controlled delay line 110, can contain multiple second delay elements with the same configurations or properties as the multiple first delay elements in the voltage-controlled delay line 110. The delay information VDLL received by the DLL circuit 111 can be applied to the simulated voltage-controlled delay line 112. The simulated voltage-controlled delay line 112 can receive the reference clock signal Ref_clk and, based on this, generate a variety of delay reference clock signals Ref_clk_Φ1 to Ref_clk_Φn. and can output the multitude of delay reference clock signals Ref_clk_Φ1 to Ref_clk_Φn to the DTC 113a.A delay time unit in the simulated voltage-controlled delay line 112, to which the delay information(s) VDLL is applied, can be equal to or similar to a delay time unit in the voltage-controlled delay line 110. For example, if it is assumed that a delay time unit of the voltage-controlled delay line 110 is a delay time corresponding to a phase difference of 11.25 degrees relative to the output clock signal VCO_clk, then a delay time unit in the simulated voltage-controlled delay line 112, to which the delay information(s) VDLL is / are applied, can be equal to or similar to the delay time corresponding to a phase difference of 11.25 degrees relative to the output clock signal VCO_clk.In this respect, an nth delay reference clock signal Ref_clk_Φn, which is generated by the longest delay of the reference clock signal Ref_clk by the simulated voltage-controlled delay line 112, can be delayed relative to the reference clock signal Ref_clk by a delay time corresponding to a 360-degree phase difference relative to the output clock signal VCO_clk.

[0036] The DTC 113a can generate the selection reference clock signal Ref_clk_sel from the plurality of delay reference clock signals Ref_clk_Φ1 to Ref_clk_Φn output by the simulated voltage-controlled delay line 112 based on a frequency coarse value (FCV) and a frequency fine value (FFV). For example, the FCV and FFV can be bit data, and assuming that the FCV and FFV are A-bit data and B-bit data, respectively, the DTC 113a can generate the selection reference clock signal Ref_clk_sel, which is used for a fractional-frequency division-based phase-lock operation in [Equation 1].

[0037] The FCV, the FFV and the frequency division information(s) DIV_N, which are described below, are external input signals that are applied to determine a frequency of a PLL from the outside, and the FCV, the FFV and the frequency division information(s) DIV_N can be set so that the PLL covers a wide band. FVCO_clk=FRef_clk*{N−(FCV+(FFV2B))2A}

[0038] In [Equation 1], F refers to VCO_clk to a frequency of the output clock signal VCO_clk, F Ref_clk refers to a frequency of the reference clock signal Ref_clk, and N refers to a specific integer division ratio; for example, N can correspond to the integer division ratio of the divider 102. F VCO_clk and F Ref_clkA target fractional division ratio can be specified by the selection reference clock signal Ref_clk_sel, which is generated based on the FCV and FFV. For example, an integer division ratio can be determined by setting N for the PLL with a target fractional division ratio, and a fractional division ratio can be determined by setting the FCV (A bit data) and the FFV (B bit data).

[0039] With reference to Fig. According to one embodiment, a DTC 113b can further receive the frequency division information DIV_N, which specifies an integer division ratio N of the divider 102, and thus supply a division ratio control signal DIV_CS to the divider 102 to perform a frequency division operation at a fractional division ratio approximately equal to a target fractional division ratio. The DTC 113b can supply the division ratio control signal DIV_CS to the divider 102 during a first phase-lock operation using the supporting PLL circuit 20a, and the divider 102 can be implemented in a configuration capable of changing a division ratio based on the division ratio control signal DIV_CS.

[0040] Although the Fig. 3A and Fig. Figure 3B shows the charge pump 105 and the transconductance circuit 108 as separate configurations; this is merely one embodiment, so that the inventive concept is not limited to this and the transconductance circuit 108 of the clock generator 100 can replace the charge pump 105.

[0041] Fig. Figure 4 is a circuit diagram of the transconductance circuit 108 by Fig. 3A or Fig. 3B according to one embodiment.

[0042] With reference to Fig. The transconductance circuit 108 can contain first and second current sources IS1 and IS2 and first and second switching circuits SW1 and SW2. The first current source IS1 can generate a positive current signal by converting a positive sampling voltage signal V_samP received from the sampler 107. The second current source IS2 can generate a negative current signal by converting a negative sampling voltage signal V_samN received from the sampler 107. The first and second switching circuits SW1 and SW2 can perform a switching operation in response to the pulse signal pul by receiving the pulse signal pul from the pulse generator 109. As a result, the transconductance circuit 108 can generate the sampling current signal I_sam and output the sampling current signal I_sam to the loop filter 106.For example, the sampling current signal I_sam of the transconductance circuit 108 can be determined by the positive current signal magnitude of the first current source IS1, the negative current signal magnitude of the second current source IS2, and a duty cycle of the pulse signal pul. If, for example, the duty cycle of the pulse signal pul is assumed to be 20%, the magnitude of the sampling current signal I_sam can be 20% as large as the positive current signal magnitude of the first current source IS1.

[0043] Fig. Figure 5 is a flowchart describing a method for implementing a fractional frequency division-based subsampling PLL of a PLL circuit according to one embodiment.

[0044] With reference to Fig. In operation S200, a PLL circuit can obtain delay information regarding an output clock signal from a VCO using a voltage-controlled delay line. In operation S210, the PLL circuit can apply the delay information to a simulated voltage-controlled delay line. In operation S220, the PLL circuit can generate a selection reference clock signal from a plurality of delay reference clock signals generated by the simulated voltage-controlled delay line. In operation S230, the PLL circuit can perform a fractional-frequency division-based phase-lock operation by performing a subsampling PLL using the selection reference clock signal.

[0045] Fig. Figure 6 is a timing diagram for describing a delay output clock signal VCO_clk_D that has passed through a voltage-controlled delay line and a delay reference clock signal Ref_clk_D that has passed through a simulated voltage-controlled delay line, according to one embodiment.

[0046] For better understanding, the following descriptions refer to... Fig. 3A given.

[0047] With reference to the Fig. As described above, the voltage-controlled delay line 110 can contain several first delay elements, and as the output clock signal VCO_clk successively passes through the several first delay elements, a frequency of the output clock signal VCO_clk can be delayed stepwise to a first time t1 (or a first phase Φ1), a second time t2 (or a second phase Φ2), a third time t3 (or a third phase Φ3), ..., an (m-1)th time t(m-1) (or an (m-1)th phase Φ(m-1)), an mth time tm (or an mth phase (Φm)), etc. As in Fig. As shown in Figure 3A, the voltage-controlled delay line 110 can be configured such that the second delay output clock signal VCO_clk_Φn is ultimately delayed, and the first delay output clock signal VCO_clk_Φ1 is output to the DLL circuit 111 with the same phase as the output clock signal VCO_clk. The delay information VDLL(s) generated by the DLL circuit 111 can be used to control the simulated voltage-controlled delay line 112 in order to delay the reference clock signal Ref_clk stepwise by the same delay time as the voltage-controlled delay line 110.

[0048] The simulated voltage-controlled delay line 112 can contain multiple second delay elements. When the delay information VDLL is applied to these multiple second delay elements, and the reference clock signal Ref_clk sequentially passes through them, the reference clock signal Ref_clk can be delayed stepwise to the first time t1, the second time t2, the third time t3, ..., the (m-1)th time t(m-1), the mth time tm, and so on. The simulated voltage-controlled delay line 112 can be configured to output the plurality of delay reference clock signals Ref_clk_Φ1 to Ref_clk_Φn. As described above, when the delay information VDLL is applied to the simulated voltage-controlled delay line 112, the reference clock signal Ref_clk can be sequentially delayed by a more fragmented delay time.This can improve the resolution for a phase of a selection reference clock signal, and the circuit complexity may not increase further.

[0049] Fig. Figure 7 is a block diagram describing an operation of a DLL circuit 111a according to one embodiment. The DLL circuit 111a of Fig. 7 can contain a phase-frequency detector 111a_1 and a charge pump 111a_2. A voltage-controlled delay line 110a can contain a plurality of first delay elements D11 to Dn1. A simulated voltage-controlled delay line 112a can contain a plurality of second delay elements D12 to Dn2. The simulated voltage-controlled delay line 112a, which is a simulated voltage-controlled delay line 110a, can contain the plurality of second delay elements D12 to Dn2 with the same configurations or properties as the plurality of first delay elements D11 to Dn1 contained in the voltage-controlled delay line 110a. For example, the number of second delay elements D12 to Dn2 can be the same as the number of first delay elements D11 to Dn1.

[0050] The voltage-controlled delay line 110a can receive the first delay output clock signal VCO_clk_Φ1 and output the second delay output clock signal VCO_clk_Φn to the DLL circuit 111a with a delay via the plurality of first delay elements D11 to Dn1. For example, the first delay output clock signal VCO_clk_Φ1 can be a signal identical to an output clock signal from a VCO, and the second delay output clock signal VCO_clk_Φn can have a certain phase difference (e.g., 360 degrees) to the first delay output clock signal VCO_clk_Φ1. The phase-frequency detector 111a_1 can receive the first delay output clock signal VCO_clk_Φ1 and the second delay output clock signal VCO_clk_Φn and supply a detection result DR to a charge pump CP by detecting a phase difference between them.Based on the acquisition result DR, the charge pump CP can set the delay information(s) (or a bias voltage) VDLL and supply the delay information VDLL to the plurality of first delay elements D11 to Dn1. The DLL circuit 111a can repeat the preceding delay locking operation until the phases of the first delay output clock signal VCO_clk_Φ1 and the second delay output clock signal VCO_clk_Φn are equal.

[0051] The DLL circuit 111a can feed the delay information(s) VDLL, generated as a result of the repeated delay-locking operation, to the multiple second delay elements D12 to Dn2 of the simulated voltage-controlled delay line 112a. The simulated voltage-controlled delay line 112a can delay a received reference clock signal Ref_clk step by step and can output each of the multiple delay reference clock signals Ref_clk_Φ1 to Ref_clk_Φn. The plurality of delay reference clock signals Ref_clk_Φ1 to Ref_clk_Φn can be used to generate a selection reference clock signal required for a fractional-frequency division-based phase-locking operation using a subsampling PLL.

[0052] Fig. Figure 8A is a block diagram of a DLL circuit 111b according to one embodiment, and Fig. 8B is a diagram describing an operation of the DLL circuit 111b from Fig. 8A.

[0053] With reference to Fig. 8A The DLL circuit 111b can include the first switch SW1, the second switch SW2, a phase frequency detector 111b_1, a charge pump 111b_2, a latching detector 111b_3, and a state machine 111b_4. Before performing a delay latching operation using the charge pump 111b_2, the DLL circuit 111b can adjust the delay of the second delay output clock signal VCO_clk_Φn so that it falls within a specific latching range, thus preventing harmonic latching. For example, the phase frequency detector 111b_1 can receive the first delay output clock signal VCO_clk_Φ1 and the second delay output clock signal VCO_clk_Φn from the voltage-controlled delay line 110 and detect a phase difference between these two signals and supply a first detection result DR1 to the interlock detector 111b_3.The interlock detector 111b_3 can be activated in response to a first activation signal EN1. Based on the first detection result DR1, it can detect whether a phase of the second delay output clock signal VCO_clk_Φn falls within a specific interlock range or not, and can supply an interlock detection result LDR to the state machine 111b_4. Based on the interlock detection result LDR, the state machine 111b_4 can supply a delay control signal DL to the voltage-controlled delay line 110. Based on the interlock detection result LDR, the state machine 111b_4 can also generate a second activation signal EN2 and supply the second activation signal EN2 to the first switch SW1 and the second switch SW2.

[0054] If, for example, a phase of the second delay output clock signal VCO_clk_Φn does not fall within a specific locking range, the state machine 111b_4 can generate the second activation signal EN2 at a high level and generate a new delay control signal DL to adjust the delay of the second delay output clock signal VCO_clk_Φn differently than before. The phase frequency detector 111b_1, the locking detector 111b_3, and the state machine 111b_4 can repeat the above process until a phase of the second delay output clock signal VCO_clk_Φn falls within a specific locking range.

[0055] As another example, if a phase of the second delay output clock signal VCO_clk_Φn falls within a specific locking range, the state machine 111b_4 can generate the second activation signal EN2 at a low level and stop an operation to set the delay of the second delay output clock signal VCO_clk_Φn. Subsequently, the phase frequency detector 111b_1 can detect a phase difference between the first delay output clock signal VCO_clk_Φ1 and the second delay output clock signal VCO_clk_Φn and supply a second detection result DR2 to the charge pump 111b_2. Based on the second detection result DR2, the charge pump 111b_2 can generate the delay information VDLL.

[0056] Further regarding Fig. During the interval 't0' to 't1', state machine 111b_4 can generate the second activation signal EN2 at a high level and the delay control signal DL with a value of 'D1'. In this respect, the phase frequency detector 111b_1 can detect a phase difference between the first delay output clock signal VCO_clk_Φ1 and the second delay output clock signal VCO_clk_Φn and feed the first detection result DR1 to the interlock detector 111b_3. Based on the first detection result DR1, the interlock detector 111b_3 can detect a phase of the second delay output clock signal VCO_clk_Φn as not falling within an interlock region and feed the interlock detection result LDR to state machine 111b_4. During an interval 't1' to 't2', the state machine 111b_4 can generate the second activation signal EN2 with a high level and the delay control signal DL with a value of 'D2'.In this respect, the phase frequency detector 111b_1 can detect a phase difference between the first delay output clock signal VCO_clk_Φ1 and the second delay output clock signal VCO_clk_Φn with a set delay and feed the first detection result DR1 to the interlock detector 111b_3. Based on the first detection result DR1, the interlock detector 111b_3 can detect a phase of the second delay output clock signal VCO_clk_Φn as not falling within an interlock range and feed the interlock detection result LDR to the state machine 111b_4. During an interval 't2' to 't3', the state machine 111b_4 can generate the second activation signal EN2 at a high level and the delay control signal DL with a value of 'D3'.The phase-frequency detector 111b_1 can detect a phase difference between the first delay output clock signal VCO_clk_Φ1 and the second delay output clock signal VCO_clk_Φn with a regulated delay and feed the first detection result DR1 to the interlock detector 111b_3. Based on the first detection result DR1, the interlock detector 111b_3 can detect a phase of the second delay output clock signal VCO_clk_Φn as not falling within an interlock region and can feed the interlock detection result LDR to the state machine 111b_4. During an interval 't3' to 't4', the state machine 111b_4 can generate the second activation signal EN2 with a high level at the beginning and the delay control signal DL with a value of 'D4'.The phase-frequency detector 111b_1 can detect a phase difference between the first delay output clock signal VCO_clk_Φ1 and the second delay output clock signal VCO_clk_Φn with a regulated delay and feed the first detection result DR1 to the interlock detector 111b_3. Based on the first detection result DR1, the interlock detector 111b_3 can detect a phase of the second delay output clock signal VCO_clk_Φn as falling into an interlock region and feed the interlock detection result LDR to the state machine 111b_4. The state machine 111b_4 can generate the second activation signal EN2, which transitions to a low level after a certain time from 't3', and in response to the second activation signal EN2 being at a low level, the DLL circuit 111b can perform a delay interlock operation to generate the delay information(s) VDLL.

[0057] Fig. 9 and Fig. Figure 10 are detailed block diagrams of DTC 113a according to one embodiment.

[0058] With reference to Fig. 9 the DTC 113a can contain a Delta-Sigma modulator 113a_1, a frequency state machine 113a_2, a multiplexer 113a_3 and a fine time control circuit 113a_4.

[0059] The delta-sigma modulator 113a_1 can receive the FFV and generate a digital sequence (DS) based on the FFV, feeding the DS to the frequency-state machine 113a_2. The FFV can be used to specify a desired frequency synthesis ratio in order to perform a phase-locking operation according to a target fractional division ratio. The delta-sigma modulator 113a_1 can generate the DS with the same time-averaged ratio as the FFV.

[0060] The frequency state machine 113a_2 can receive the DS and the FCV and, based on the DS and the FCV, generate a phase control signal (PCS) to control a phase of the selection reference clock signal Ref_clk_sel. The frequency state machine 113a_2 can perform a partial PCS MSB with the most significant bit (MSB) of the PCS (hereinafter referred to as the first phase control signal) the multiplexer 113a_3 and a part of the PCS LSB feed the least significant bit (LSB) of the PCS (hereinafter referred to as the second phase control signal) to the fine timing control circuit 113a_4.

[0061] The multiplexer 113a_3 can receive the multitude of delay reference clock signals Ref_clk_Φ1 to Ref_clk_Φn and, based on the first phase control signal PCS, MSBSelect one of the multiple delay reference clock signals Ref_clk_Φ1 to Ref_clk_Φn and feed a selected delay reference clock signal Ref_clk_Φm to the fine timing control circuit 113a_4. In this respect, the first phase control signal PCS MSB can be implemented with bit data corresponding to the number of multiple delay reference clock signals Ref_clk_Φ1 to Ref_clk_Φn. For example, if the number of multiple delay reference clock signals Ref_clk_Φ1 to Ref_clk_Φn is 32, the first phase control signal PCS can be MSB be implemented with 5-bit data.

[0062] The fine timing control circuit 113a_4 can use the selected delay reference clock signal Ref_clk_Φm and the second phase control signal PCS. LSBReceive and fine-tune the selection reference clock signal Ref_clk_sel by adjusting a delay time (or phase) of the selected delay reference clock signal Ref_clk_Φm based on the second phase control signal PCS. LSB A delay setting range of the selected delay reference clock signal Ref_clk_Φm, set by the fine timing control circuit 113a_4, can be limited within a constant delay time between the plurality of delay reference clock signals Ref_clk_Φ1 to Ref_clk_Φn. For example, if the delay time between a first delay reference clock signal Ref_clk_Φ1 and a second delay reference clock signal Ref_clk_Φ2 is 5, the delay setting range can be limited within 5.

[0063] In the frequency state machine 113a_2, a timing problem can occur due to the continuous updating of the PCS. Accordingly, to solve the above problem, the delta-sigma modulator 113a_1 can be synchronized with the selection reference clock signal Ref_clk_sel, which is output by the fine-time control circuit 113a_4, to generate the DS, and the frequency state machine 113a_2 can be synchronized with the nth delay reference clock signal Ref_clk_Φn to generate the PCS.

[0064] With further reference to Fig. The DTC 113b can contain a delta-sigma modulator 113b_1, a frequency state machine 113b_2, a multiplexer 113b_3, and a fine-time control circuit 113b_4. The following mainly describes the frequency state machine 113b_2, which differs from the frequency state machine 113a_2 in that... Fig. 9 performs an additional operation.

[0065] The frequency state machine 113b_2 can also receive the frequency division information(s) DIV_N, which is an integer division ratio of the divider 102 (of Fig. 3A) in a support PLL circuit, and can thus use the division ratio control signal DIV_CS to control the divider 102 (from Fig. 3A) to perform a frequency division operation at a fractional division ratio close to a target fractional division ratio. For example, during a first phase-lock operation using the support PLL circuit, the frequency state machine 113b_2 can generate the division ratio control signal DIV_CS and send the division ratio control signal DIV_CS to the divider 102 (from Fig. 3A). In this respect, the divisor 102 (of Fig. 3A) include a configuration that is capable of changing a division ratio based on the division ratio control signal DIV_CS.

[0066] Fig. Figure 11 is a block diagram of a wireless communication device 1000 according to one embodiment. The wireless communication device 1000 can include a digital signal processor 1100, a DAC 1200, an ADC 1300, a radio frequency integrated circuit (RFIC) 1400, a front-end module 1500, and an antenna 1600. The digital signal processor 1100 can process a signal with information to be transmitted or received according to a defined communication scheme. For example, the digital signal processor 1100 can process a signal according to a communication scheme such as Orthogonal Frequency-Division Multiplexing (OFDM), Orthogonal Frequency-Division Multiple Access (OFDMA), Wideband Code Division Multiple Access (WCDMA), or High Speed ​​Packet Access+ (HSPA+).

[0067] The DAC 1200 can convert a digital signal containing the information to be transmitted into an analog signal and feed the converted transmission signal to the RFIC 1400. The ADC 1300 can convert an analog signal received by the RFIC 1400 into a digital signal and feed the converted digital signal to the digital signal processor 1100.

[0068] The RFIC 1400 can include a first mixer 1410, a second mixer 1420, and a PLL circuit 1430. The RFIC 1400 can generate a high-frequency (HF) signal by up-converting the frequency of a transmitted signal into a baseband received by the DAC 1200 using the first mixer 1410 and the PLL circuit 1430. The RFIC 1400 can generate a baseband signal by down-converting the frequency of a received signal into an HF band received by the front-end module 1500 using the second mixer 1420 and the PLL 1430. The above, with reference to Fig. The embodiments described in sections 1 to 10 can all be applied to the PLL 1430.

[0069] The front-end module 1500 can contain an amplifier, a duplexer, etc. The front-end module 1500 can amplify an RF transmission signal supplied by the RFIC 1400 and transmit the amplified signal via the antenna 1600. In some embodiments, the wireless communication device 1000 can contain a plurality of antennas 1600, and the front-end module 1500 can separate an RF transmission signal for each frequency band and transmit it to the corresponding antenna 1600.

[0070] Fig. Figure 12 is a diagram showing communication devices that include clock generators for performing a phase-locking operation of a clock according to one embodiment.

[0071] With reference to Fig. 12. A household appliance 2100, household appliances 2120, an entertainment device 2140, and an access point (AP) 2200 can each include a clock generator for performing a phase-locking operation of a clock according to embodiments. In some embodiments, the household appliance 2100, the household appliances 2120, the entertainment device 2140, and the AP 2200 can form an IoT network system (IoT = Internet of Things). The in Fig. The 12 communication devices shown are merely an example, and it goes without saying that others, not included, exist. Fig. The communication devices shown in Figure 12 may also include a wireless communication device, depending on the embodiment.

[0072] Fig. Figure 13 is a block diagram of an IoT device 3000 according to one embodiment. The IoT device 3000 can include an application processor 3100, a transmitter / receiver 3200, a memory 3300, a display 3400, a sensor 3500, and an input / output device (I / O device) 3600.

[0073] The IoT device 3000 can communicate with external units via the transmitter / receiver 3200. The transmitter / receiver 3200 can be a modem communication interface accessible, for example, to wired local area networks (LANs), short-range wireless communication interfaces such as Bluetooth, Wireless Fidelity (Wi-Fi), and Zigbee, power line communication (PLC), or mobile cellular networks such as 3G (3rd generation), LTE (LTE = Long Term Evolution), etc. The transmitter / receiver 3200 can include a clock generator according to the embodiments described above.

[0074] The Application Processor 3100 can control the overall operation of the IoT Device 3000 and the operation of its configurations. The Application Processor 3100 can perform various operations. In some embodiments, the Application Processor 3100 may contain a single core or multiple cores.

[0075] The 3500 sensor can, for example, be an image sensor for capturing an image. The 3500 sensor can be connected to the 3100 application processor and can transmit generated image information to the 3100 application processor. The 3500 sensor can also be a biosensor for capturing biometric information. The 3500 sensor can be any type of sensor, such as an illuminance sensor, an acoustic sensor, or an accelerometer.

[0076] The 3400 display can show internal status information of the 3000 IoT device. The 3400 display can include a touch sensor (not shown). The 3400 display can also include input or output functionality and the appearance of a user interface. A user can control the 3000 IoT device via a touch sensor and a user interface.

[0077] The input / output device 3600 can include an input unit, such as a touch panel, keypad, or enter button, and an output unit, such as a display or speaker. The memory 3300 can store a control command code, control data, or user data for controlling the IoT device 3000. The memory 3300 can include at least one volatile or non-volatile memory.

[0078] The IoT device 3000 can also include a power supply unit with a battery for internal power or for drawing power from an external source. The IoT device 3000 can also include a storage device. The storage device can be a non-volatile medium, such as a hard disk drive (HDD), a solid-state drive (SSD), an embedded multimedia card (eMMC), or a universal flash memory (UFS). The storage device can store user information provided by the input / output device 3600 as well as individual sample information collected by the sensor 3500.

[0079] An output clock signal can be used in at least some of the aforementioned components of the IoT device 3000, e.g., in the application processor 3100, in the transmitter / receiver 3200, in the memory 3300, in the display 3400, in the sensor 3500, and in the input / output device 3600, and the output clock signal can be generated by a clock generator according to embodiments of the inventive concept as described above. Fig. The numbers 1-10 described are generated.

[0080] While the inventive concept has been shown and described in particular with reference to embodiments thereof, it is assumed that various changes in form and details can be made therein without deviating from the spirit and scope of the following claims.

Claims

[1] Phase-locked loop (PLL) circuit (PLL_CKT), comprising: a voltage-controlled oscillator (40; 101) configured to generate an output clock signal; a subsampling PLL circuit (30; 30a) configured to receive the output clock signal as a feedback signal and to perform a fractional-frequency division-based phase-locking operation based on it; and a fractional frequency division control circuit (10; 10a) configured to supply a selection reference clock signal for the fractional frequency division-based phase locking operation of the subsampling PLL circuit (30; 30a), the fractional frequency division control circuit (10; 10a) comprises: a voltage-controlled delay line (16; 110) which is set up to guide the feedback signal and to generate delay information (or information) based on the feedback signal; a simulated voltage-controlled delay line (18; 112) to which the delay information(s) is / are applied and which is configured to carry a reference clock signal to generate a plurality of delay reference clock signals, each delayed by up to a different respective delay time; and a digital time converter (DTC) (12; 113a; 113b) which is configured to generate the selection reference clock signal from the plurality of delay reference clock signals and output the selection reference clock signal to the subsampling PLL circuit (30; 30a). [2] PLL circuit according to claim 1, wherein the simulated voltage-controlled delay line (18; 112) comprises a plurality of delay elements having the same properties as a plurality of delay elements within the voltage-controlled delay line (16; 110). [3] PLL circuit according to claim 1, wherein a frequency of the reference clock signal has a value obtained by applying a target fractional division ratio to a frequency of the output clock signal which is phase-locked by the subsampling PLL circuit (30; 30a). [4] PLL circuit according to claim 1, wherein the fractional frequency division control circuit (10; 10a) further comprises a delay control loop (DLL) circuit (14; 111) which is connected to the voltage-controlled delay line (16; 110) and is configured to generate the delay information(s) by latching delay of the feedback signal that has passed through the voltage-controlled delay line (16; 110). [5] PLL circuit according to claim 4, wherein the delay information(s) comprises a bias for a plurality of delay elements contained in the voltage-controlled delay line (16; 110). [6] PLL circuit according to claim 4, wherein the DLL circuit (14; 111) is connected to the simulated voltage-controlled delay line (18; 112) and is further configured to supply the delay information(s) to the simulated voltage-controlled delay line (18; 112). [7] PLL circuit according to claim 4, wherein the voltage-controlled delay line (16; 110) comprises several first delay elements connected in series and configured to delay each received signal by up to the same delay time in order to output a delayed feedback signal having a certain phase offset relative to the feedback signal. [8] PLL circuit according to claim 7, wherein the simulated voltage-controlled delay line (18; 112) comprises several second delay elements connected in series and configured to delay a received signal by as much as the same delay time as the several first delay elements of the voltage-controlled delay line (16; 110), and is further configured to gradually output the several delay reference clock signals from the reference clock signal to the DTC (12; 113a; 113b) via respective output ends of the several second delay elements. [9] PLL circuit according to claim 4, wherein the DLL circuit (14; 111) is further configured to initiate a latching delay operation of the feedback signal when a phase of the delayed feedback signal falls into a certain latching range by setting a delay level of the feedback signal caused by the voltage-controlled delay line (16; 110) to prevent harmonic latching. [10] PLL circuit according to claim 1, wherein the DTC comprises (113a; 113b): a multiplexer (113a_3; 113b_3) configured to output a delay reference clock signal from the plurality of delay reference clock signals; and a fine time control circuit (FTC) (113a_4; 113b_4) which is set up to generate the selection reference clock signal by setting the delay for the delay reference clock signal output by the multiplexer (113a_3; 113b_3). [11] PLL circuit according to claim 10, wherein the number of bits of a first bit signal received for the selection of the multiplexer (113a_3; 113b_3) is greater than the number of bits of a second bit signal received for the setting operation of the FTC circuit (113a_4; 113b_4). [12] PLL circuit according to claim 10, wherein a delay setting range of the FTC circuit (113a_4; 113b_4) corresponds to a constant delay time between the multiple delay reference clock signals. [13] PLL circuit according to claim 10, further comprising a support PLL circuit (20a) configured to perform an integer frequency division-based phase-lock operation on the output clock signal prior to the fractional frequency division-based phase-lock operation of the subsampling PLL circuit (30a), wherein the DTC (113a; 113b) is configured to set a division ratio in the integer frequency division-based phase-lock operation to generate the output clock signal having a frequency approximately equal to a target division ratio of the fractional frequency division-based phase-lock operation within a certain range. [14] Phase-locked loop (PLL) circuit (PLL_CKT), comprising: a voltage-controlled oscillator (40; 101) configured to generate an output clock signal; a subsampling PLL circuit (30; 30a) configured to receive the output clock signal as a feedback signal and to perform a fractional-frequency division-based phase-locking operation based on it; and a fractional frequency division control circuit (10; 10a) which is set up to to supply a selection reference clock signal for the fractional frequency division-based phase locking operation of the subsampling PLL circuit (30; 30a); (a) delay information(s) regarding a constant delay time within a cycle of the feedback signal by performing a delay operation using the feedback signal when the feedback signal has a first frequency; to generate a multitude of delay reference clock signals based on the delay information(s), which are gradually delayed by up to the delay time by using a reference clock signal with a second frequency; and to generate the selection reference clock signal using the multitude of delay reference clock signals. [15] PLL circuit according to claim 14, wherein when a phase of the output clock signal is locked by the fractional frequency division-based phase locking operation, the first frequency and the second frequency have a target fractional division ratio. [16] PLL circuit according to claim 14, wherein the fractional frequency division control circuit (10a) comprises a digital time converter (DTC) (113a; 113b) comprising: a multiplexer (113a_3; 113b_3) configured to output a delay reference clock signal from the plurality of delay reference clock signals; and a fine time control (FTC) circuit (113a_4; 113b_4) which is set up to generate the selection reference clock signal by setting the delay for the delay reference clock signal output signal from the multiplexer. [17] PLL circuit according to claim 16, wherein the DTC (113a; 113b) further comprises a delta-sigma modulator (113a_1; 113b_1) configured to generate a first bit signal for selecting the multiplexer (113a_3; 113b_3) and a second bit signal for a fine-time control and a frequency state machine (113a_2; 113b_2). [18] PLL circuit according to claim 14, wherein the fractional frequency division control circuit (10; 10a) comprises a voltage-controlled delay line (16; 110) configured to receive the feedback signal to generate the delay information(s), and a simulated voltage-controlled delay line (18; 112) configured to receive the reference clock signal to generate the plurality of delay reference clock signals, wherein the simulated voltage-controlled delay line (18; 112) has the same configurations as the voltage-controlled delay line (16; 110) to perform a gradual delay operation by as much as the same delay time of the voltage-controlled delay line (16; 110) when the delay information(s) is applied to the simulated voltage-controlled delay line (18; 112). [19] PLL circuit according to claim 18, wherein the delay information(s) comprises a bias for a plurality of delay elements included in the voltage-controlled delay line (16; 110). [20] Clock generator (1; 100) comprising: a voltage-controlled oscillator (40; 101) configured to generate an output clock signal; a support phase-locked loop (PLL) circuit (20; 20a) configured to perform an integer frequency division-based phase-lock operation on the output clock signal; a subsampling PLL circuit (30; 30a) configured to perform a fractional frequency division-based phase-lock operation on the output clock signal after the integer frequency division-based phase-lock operation; and a fractional frequency division control circuit (10; 10a) configured to supply a selection reference clock signal for the fractional frequency division-based phase-lock operation of the subsampling PLL circuit (30; 30a), wherein the fractional frequency division control circuit (10; 10a) comprises: a voltage-controlled delay line (16; 110) which is set up to carry a feedback signal to generate one or more delay information; a simulated voltage-controlled delay line (18; 112) to which the delay information(s) is / are applied, which has the same properties as the voltage-controlled delay line (16; 110) and is configured to carry a reference clock signal to generate a plurality of delay reference clock signals, each delayed by up to a different delay time; and a digital time converter (DTC) (12; 113a; 113b) which is configured to generate the selection reference clock signal from the plurality of delay reference clock signals and output the selection reference clock signal to the subsampling PLL circuit (30; 30a).

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