Semiconductor device and semiconductor element

Abstract

Semiconductor device (1), comprising: - a substrate (21); - a semiconductor element (11) bonded to the substrate (21); and - a sealing resin (41) sealing at least a part of the substrate (21) and the semiconductor element (11), wherein: - the semiconductor element has: - an active region (AR) through which a main current flows in an ON state of the semiconductor element (11), - a connection area (11a) surrounding the active area (AR), - an anchor film (13) provided on an insulating film (12) of the terminal portion (11a), and - a protective film (14) covering at least the connection area including the anchor film (13), and - the anchor film (13) - consists of a material different from the insulating film (12) and - has a plurality of individually provided openings (13a).

Description

BACKGROUND OF THE INVENTIONField of the invention

[0001] The present invention relates to a semiconductor device, particularly to a semiconductor device in which a semiconductor element is sealed with a resin, wherein peeling of a protective film for protecting the semiconductor element is suppressed. Description of the background technology

[0002] Japanese Patent Application Laid-Open No. 2004-165406 discloses a semiconductor device in which a semiconductor element is sealed with a curable resin such as an epoxy resin. Furthermore, Japanese Patent Application Laid-Open No. 2001-274177 discloses a semiconductor device in which electrode members are bonded to a front and a back surface of a semiconductor element, and at least a part of the electrode member and the semiconductor element are covered with a sealing resin. In recent years, to further reduce loss and provide high-temperature operation, SiC semiconductor elements made of silicon carbide (SiC) have been developed and put into practical use. Such SiC semiconductor elements are also mounted on the semiconductor device described above.WO 2013 / 137 177 A1 discloses a semiconductor device in which an insulating layer in which a first and a second insulating layer are laminated is formed on a SiC layer, the first insulating layer is provided with a through hole reaching the surface of the SiC layer, a second insulating layer is buried in the through hole to form a convex portion, and the convex portion improves the adhesion of the insulating layer.

[0003] The document US 2014 / 0 084 476 A1 discloses a package comprising a chip comprising a semiconductor substrate, a plurality of vias penetrating the semiconductor substrate, a sealing ring overlapping and connected to the plurality of vias, and a plurality of electrical connections located beneath the semiconductor substrate and connected to the sealing ring. An intermediate circuit lies beneath the chip and is connected to the semiconductor substrate. The intermediate circuit includes a substrate and a plurality of metal lines above the substrate. The plurality of metal lines are electrically connected to the plurality of electrical connections. Each of the plurality of metal lines has a first portion overlapped by the first chip and a second portion offset from the chip.A thermally conductive block surrounds the chip and is attached to the numerous metal lines of the intermediate circuit. SUMMARY

[0004] In a conventional semiconductor device, there has been a problem in that a semiconductor element receives stress from a sealing resin due to stress caused by a temperature cycle, a protective film on a surface of the semiconductor element is peeled off, and its reliability is reduced. In the semiconductor device having a structure disclosed in Japanese Patent Application Laid-Open No. 2001-274177, the stress applied to the semiconductor element is further increased, so the possibility of peeling off the protective film is considered high. If the peeling off of the protective film progresses to a portion covering the gate wiring within the terminal region, for example, the gate wiring may be disconnected, ultimately resulting in a characteristic defect.Particularly, in a semiconductor device mounting a SiC semiconductor element, the elastic modulus of SiC is higher than that of Si; therefore, the stress applied to the protective film increases, and delamination is more likely to progress. Even if the configuration disclosed in WO 2013 / 137177 A1, which improves the adhesion of the insulating layer, is adopted, if delamination cannot be completely suppressed, there is also a likelihood that the terminal region of the SiC semiconductor element will be exposed to an intense electric field, an electric discharge will occur from the delaminated region, and the breakdown voltage will be reduced.

[0005] Provided is a semiconductor device in which a protective film on a surface of a semiconductor element is prevented from peeling off even when the semiconductor element receives a stress from a sealing resin due to a stress caused by a temperature cycle.

[0006] The object underlying the invention is achieved in a semiconductor device according to the invention with the features of claim 1 and in a semiconductor element according to the invention with the features of claim 11. Advantageous further developments are the subject of the respective dependent claims.

[0007] According to the present invention, a semiconductor device comprises a substrate, a semiconductor element bonded to the substrate, and a sealing resin that seals at least a part of the substrate and the semiconductor element, wherein the semiconductor element includes an active region through which a main current flows in an ON state of the semiconductor element, a terminal region surrounding the active region, an anchor film provided on an insulating film of the terminal region, and a protective film covering at least the terminal region including the anchor film, and the anchor film is made of a material different from the insulating film and has a plurality of individually provided openings.

[0008] According to the semiconductor device of the present invention, by providing the anchor film on the insulating film of the terminal portion of the semiconductor element, even if the semiconductor element receives stress from the sealing resin due to a temperature cycle, the protective film is hooked to the openings of the anchor film. Therefore, the stress from the sealing resin is distributed on the protective film and absorbed as tensile stress. As a result, the compressive stress at the peeling tip can be reduced, and peeling of the protective film is prevented.

[0009] These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings, SHORT DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional view illustrating a configuration of a semiconductor device of an embodiment 1 according to the present invention; Fig. 2 is a plan view illustrating a configuration of a semiconductor element mounted on the semiconductor device of Embodiment 1 according to the present invention; Fig. 3 is a partial sectional view illustrating the configuration of the semiconductor element mounted on the semiconductor device of Embodiment 1 according to the present invention; Fig. 4 is a partial plan view illustrating the configuration of the semiconductor element mounted on the semiconductor device of Embodiment 1 according to the present invention; Fig. 5 is a partial plan view illustrating the configuration of the semiconductor element mounted on the semiconductor device of Embodiment 1 according to the present invention; Fig. 6 is a partial plan view illustrating the configuration of the semiconductor element mounted on the semiconductor device of Embodiment 1 according to the present invention; Fig. 7 is a set of contour diagrams illustrating a simulation result of a stress generated at an interface between a protective film and a semiconductor element when stress is applied by a temperature cycle; Fig. 8 is a set of contour diagrams illustrating a simulation result of a stress generated at an interface between a protective film and a semiconductor element when stress is applied by a temperature cycle; and Fig. 9 is a set of contour diagrams illustrating a simulation result of a stress generated at an interface between a protective film and a semiconductor element when a stress is applied by a temperature cycle. DESCRIPTION OF THE PREFERRED EMBODIMENTS<Einführung>

[0010] In the following description, an "active region" is a region where a main current flows in an ON state of a semiconductor element. Hereinafter, "outside" is a direction toward the outer periphery of the semiconductor element, and "inside" is a direction opposite to "outside." Although in the following description, with respect to the conductivity type of impurities, an n-type is generally defined as a "first conductivity type" and a p-type, which is a conductivity type opposite to an n-type, is generally defined as a "second conductivity type," the reverse definition may also be adopted.

[0011] The drawings are schematically illustrated, and the correlation between the size and position of the representation illustrated in each of the different drawings is not necessarily drawn precisely and may be changed as applicable. In the following description, similar components are designated by the same reference numerals and have the same names and functions. Accordingly, their detailed descriptions may be omitted. Furthermore, in the description, the terms "on" and "cover" do not preclude the presence of inclusions between the components. For example, the expressions "B provided on A" and "A covers B" can indicate both that another component C is provided between A and B and that another component C is not provided between A and B.Although terms indicating specific positions and directions such as "on", "low", "side", "bottom", "front" or "rear" are used in the description described below, these terms are used for convenience to facilitate understanding of the contents of the embodiment and have no relation to the direction in an actual embodiment.

[0012] The term "MOS" was previously used to refer to a metal-oxide-semiconductor junction structure and is the acronym for metal-oxide-semiconductor. However, especially in a field-effect transistor with a MOS structure (hereinafter referred to simply as a "MOS transistor"), the materials of a gate insulating film and a gate electrode have been improved due to recent integration and improvements in a manufacturing process.

[0013] For example, in a MOS transistor, polycrystalline silicon has been predominantly used instead of metal as the gate electrode material from the perspective of self-aligning the source and drain. Although a material with a high dielectric constant is used as the gate insulating film material from the perspective of improving electrical characteristics, the material is not necessarily limited to oxide.

[0014] Therefore, the term "MOS" is not necessarily limited to the metal-oxide-semiconductor lamination structure alone, and the present patent specification does not imply any such limitation. That is, with regard to common technical knowledge, "MOS" here has a meaning not only as an abbreviation derived from its word origin, but also includes, in a broad sense, a conductor-insulator-semiconductor lamination structure. <Ausführungsform 1><vorrichtungskonfiguration>

[0015] Fig. 1 is a cross-sectional view illustrating a configuration of a semiconductor device according to Embodiment 1, and Fig. 2 is a plan view illustrating a configuration of semiconductor elements 11 mounted on the semiconductor device 1.

[0016] As in Fig. 1, the semiconductor device 1 includes a plurality of semiconductor elements 11 bonded to a main surface (upper surface) of a conductive substrate 21 via a bonding material 31 such as a solder material. In one semiconductor element 11, the lead frame 22 is bonded via a bonding material 32 such as a solder to the upper surface opposite to the lower surface bonded with the bonding material 31. The lead frame 22 is electrically connected to a source electrode (not shown) on the upper surface of the semiconductor elements 11, and one end of the lead frame 22 protrudes from the semiconductor device 1.

[0017] One end of an external terminal 23 is connected to an edge portion of the upper surface of the conductive substrate 21, and the other end of the external terminal 23 protrudes from the semiconductor device 1. The external terminal 23 is electrically connected to a drain electrode (not shown) on the lower surface of the semiconductor elements 11.

[0018] One end of a wire WR is connected by wire bonding to the upper surface of a semiconductor element 11, and the other end of the wire WR is connected by wire bonding to one end of the control terminal 24. The other end of the control terminal 24 protrudes from the semiconductor device 1. The wire WR is connected to a gate pad 11d ( Fig. 2) of the semiconductor element 11, and a control signal is input via the control terminal 24 from outside the semiconductor device 1.

[0019] At least a portion of each of the lead frame 22, the external terminal 23, and the control terminal 24, the wire WR, the conductive substrate 21, and the semiconductor element 11 are sealed with a sealing resin 41, and the other end of each of the lead frame 22, the external terminal 23, and the control terminal 24 protrudes from the sealing resin 41. The lower surface of the conductive substrate 21 is not covered with the sealing resin 41 and is exposed to the outside. Note that the Fig. 1 is an example, and the present invention is not limited to this configuration.

[0020] As in Fig. As illustrated in Figure 2, the semiconductor element 11 has a quadrangular outer shape, and its central portion is an active region AR. The active region AR in plan view is a quadrilateral having four corners with a curvature, and the central part of one side thereof has an inwardly concave quadrangular shape. A gate pad 11d is formed such that the gate pad 11 penetrates into a concave portion within the active region AR. A source electrode 11c having substantially the same shape and size as the active region AR is provided on the active region AR.

[0021] Further, a gate wiring 11b connected to one side of the gate pad 11d is provided along the outer periphery of the active region AR; that is, the active region AR is surrounded by the gate wiring 11b. The arrangement and shapes of the active region AR, the source electrode 11c, and the gate pad 11d in plan view are not limited to the above.

[0022] An anchor film 13 is provided on the more outer peripheral side of the gate wiring 11b along the gate wiring 11b. A region from the outer edge of the gate wiring 11b to the outer edge of the semiconductor element 11, including the anchor film 13, is defined as the terminal region 11a.

[0023] Fig. Figure 3 is a cross-sectional view of an area defined by a line AA with the arrows in Fig. 2 is specified, and Fig. 4 is a partial plan view of a Fig. 3 corresponding area.

[0024] As in Fig. As illustrated in FIG. 3, in the terminal region 11a, the anchor film 13 is provided on an interlayer insulating film 12, and a protective film 14 is formed, covering the interlayer insulating film 12 and the gate wiring 11b and covering at least a portion of the source electrode 11c. The protective film 14 is made of a material different from that of the interlayer insulating film 12. Although not illustrated, an impurity region for maintaining a breakdown voltage may be provided in the terminal region.

[0025] The semiconductor element 11 is a SiC semiconductor element (silicon carbide semiconductor element) made of silicon carbide (SiC), and includes a semiconductor layer epitaxially grown on a SiC wafer, which is a semiconductor substrate. After a plurality of semiconductor element patterns are formed on the SiC wafer through various wafer processes, the anchor film 13 is formed in the terminal region 11a of each semiconductor element pattern, and the terminal region 11a is covered with the protective film 14. Thereafter, the SiC wafer is polished to a thickness of about 100 μm, and a plurality of semiconductor element patterns are cut into individual pieces along a dicing line by, for example, a dicing method or the like, so that the semiconductor element 11 is obtained.

[0026] Although illustration and description of the semiconductor element structure of the semiconductor element 11 are omitted, in Embodiment 1, it is assumed that it is a MOS transistor. However, the semiconductor element 11 is not limited to a MOS transistor, and an insulated gate bipolar transistor (IGBT), a pn junction diode, a Schottky diode, or the like can be adopted.

[0027] The protective film 14 is made of, for example, polyimide or polyamide as its main material. The protective film 14 is formed in a desired pattern by a photolithography process after applying a precursor solution for the protective film 14 to the SiC wafer using a spin-coating method in a wafer process. As this structure, for example, openings are formed over the source electrode 11c and the gate pad 11d of the MOS transistor, and the remaining area, that is, the area surrounding the area where the terminal region 11a and the gate wiring 11b are formed, is covered with the protective film 14.

[0028] Specifically, when a semiconductor wafer is diced using a disk-shaped knife sharpener, chipping or the like may occur during dicing if the dicing line is covered with the protective film 14, and the yield may be reduced. Therefore, the outer end surface of the protective film 14 is preferably provided at a position retracted inward from the dicing line so as not to come into contact with the knife sharpener at the time of dicing, and is a structure that also has an opening above the dicing line. As shown in Fig. Therefore, as illustrated in Figure 3, the outer end surface of the protective film 14 is located at a position retracted from the end surface of the semiconductor element 11. The retraction distance varies depending on the dicing conditions, such as the blade width of the grinding knife, which is, for example, 20 to 100 µm.

[0029] The interlayer insulating film 12 is made of, for example, silicon oxide as a main material and can be formed to any thickness by a thermal oxidation method or a method of depositing a tetraethoxysilane (TEOS) oxide film using TEOS.

[0030] The terminal region 11a of the semiconductor element 11 is also a breakdown voltage holding region for maintaining a breakdown voltage and experiencing a high electric field. Therefore, the thickness and formation area of ​​the interlayer insulating film 12 covering the terminal region 11a are set so that at least the terminal region 11a is not exposed. The thickness of the interlayer insulating film 12 is set so that a high electric field does not generate leakage current and does not reduce the breakdown voltage.

[0031] The anchor film 13 consists of silicon nitride as the main material. As shown in Fig. 2, the anchor film 13 is provided along the terminal portion 11a in plan view and has a loop shape. In addition, as shown in Fig. 4, the entire anchor film 13 is individually provided with a plurality of openings 13a.

[0032] The anchor film 13 is formed in a loop shape outside the gate wiring 11b so as to surround the gate wiring 11b and the active region AR; therefore, the peeling of the protective film 14 is prevented from progressing and reaching the gate wiring 11b and the active region AR.

[0033] The anchor film 13 is formed by forming a silicon nitride film over the entire SiC wafer using a chemical vapor deposition (CVD) method in a wafer process. Then, a resist film is formed on the silicon nitride film using a photolithography film, leaving the resist film in a loop shape along the terminal region 11a. At the same time, the resist film is patterned to individually form a plurality of openings 13a. Afterward, a desired pattern is obtained by etching the silicon nitride film using the patterned resist film as an etching mask.

[0034] Here, the interlayer insulating film 12 is made of silicon oxide, and the anchor film 13 is made of silicon nitride; therefore, etching selectivity can be achieved. Accordingly, removal of the interlayer insulating film 12 during the patterning process of the anchor film 13 can be suppressed.

[0035] The shape of the opening 13a of the anchor film 13 in plan view, which in Fig. 4 is a circular shape, and the minimum interval between the openings 13a is set to 5 µm or more and 20 µm or less.

[0036] By forming the shape of the opening 13a in plan view as a circular shape, it is possible to evenly absorb the tensile stress generated when the detached protective film 14 is hooked to the openings 13a.

[0037] Furthermore, the shape of the opening 13a in plan view is not limited to a circular shape and may, for example, have a shape as shown in Fig. 5 illustrates close to a semicircle (semicircle shape), or the shape can be as in Fig. 6 illustrates a shape close to a crescent (crescent shape). The inner side (on the side where the active region AR and the gate wiring 11b are formed) may be a circular arc shape, and the minimum interval between the openings 13a may be 5 μm or more and 20 μm or less.

[0038] The number of openings 13a per unit area can be increased by giving them a semicircular or crescent shape, and the anchoring effect of the protective film 14 can be enhanced by providing the openings 13a. The anchoring effect is an effect for obtaining resistance to horizontal tension with the elasticity of the protective film 14 due to the unevenness of the surface, which is hooked to the openings 13a. <herstellungsverfahren>

[0039] In order to form the semiconductor element 11 having such a configuration on the semiconductor device 1 as shown in Fig. 1, when the semiconductor element 11 is a MOS transistor, the drain electrode serving as the lower surface is bonded to the conductive substrate 21 by using a bonding material 31 such as a solder material consisting of tin as a main material and a sintering material consisting of silver and copper as a main material.

[0040] The conductive substrate 21 is a substrate in which an insulating substrate (not shown) is mounted on a heat spreader (not shown) made of a material with good thermal conductivity, such as copper, and a circuit pattern is formed on the upper surface of the insulating substrate. The drain electrode of the semiconductor element 11 is thermally and electrically connected to the circuit pattern by the bonding material 31.

[0041] The source electrode 11c serving as the upper surface of the semiconductor element 11 is bonded to the lead frame 22 made of copper as the main material using a bonding material 32 such as a solder material made of tin as the main material and a sintering material made of silver and copper as the main material. The source electrode 11c can be configured such that a wire made of aluminum or copper as the main material and having a diameter of hundreds of micrometers is mechanically bonded by wire bonding or the like, and the other end of the wire is connected to an external terminal.

[0042] After the mounting of the semiconductor element 11 on the circuit board 21 is completed, for example, a semi-finished product in which the conductive substrate 21 and the semiconductor element 11 to which the lead frame 22 is bonded are mounted on a mold is assembled, and after the molding resin is injected into the mold under pressure, the sealing resin 41 is molded by an injection-sealing technique accompanied by heating, thereby completing the semiconductor device 1.

[0043] Using an epoxy resin for the sealing resin 41 improves reliability such as moisture resistance and resistance to temperature cycles compared with the case where a gel is used for the sealing material.

[0044] When a thermosetting resin is used as the sealing resin 41, the semiconductor element 11 receives the stress from the sealing resin 41, and stress is generated on the semiconductor element 11 when the semiconductor device 1 receives the stress due to a temperature cycle, and the protective film 14 on the surface of the semiconductor element 11 is likely to be peeled off.

[0045] Therefore, the results of a stress simulation of the stress generated at the interface between the protective film 14 and the semiconductor element 11 when the semiconductor device 1 is subjected to a stress due to the temperature cycle will be described with reference to the sets of stress contour diagrams shown in Fig. 7 to 9 are illustrated.

[0046] Fig. 7 is a set of voltage contour diagrams illustrating a result of a voltage simulation of the semiconductor element 111 without the anchor film 13 on the outer peripheral side of the gate wiring 11b.

[0047] In Fig. 7, the peeling of the protective film 14 starts from the end of the semiconductor element 111 as its starting point, and the change in the position of the peeling tip 14E as the peeling proceeds inward (on the side of the source electrode 11c) is illustrated in order from above.

[0048] In the top stress contour diagram of Fig. 7, tensile stress peaks occur at the ends of the semiconductor element 111 and the protective film 14, and a compressive stress peak occurs at the peeling tip 14E. Note that in Fig. 7 to 9 the voltage is higher the darker the color is.

[0049] As illustrated in the second stress contour diagram from the top, as the stress continues to increase, the detachment peak 14E moves inward, and the detachment region 14O expands. The same is true in the third, fourth, and fifth stress contour diagrams from the top: one can understand that the detachment peak 14E moves inward, and the detachment region 14O expands.

[0050] In addition, as in Fig. 7, it can be understood that the area of ​​the peak of the tensile stress at the starting point of the peeling off of the ends of the semiconductor element 111 and the protective film 14 increases with the progress of the peeling off.

[0051] In the semiconductor element 111, as the detachment on the terminal region 11a progresses inward, the peak value of the compressive stress at the detachment peak 14E does not change and is maintained at a high value. That is, this indicates that once the detachment of the protective film 14 has occurred, the progression of the detachment of the protective film 14 cannot be suppressed. As the detachment of the protective film 14 progresses further inward and reaches, for example, the gate wiring 11b, a short circuit occurs between the gate electrode and the source electrode, and a decrease in the ignition voltage between the gate electrode and the drain electrode occurs, and the reliability of the semiconductor device decreases.

[0052] Fig. 8 is a set of stress contour diagrams illustrating a stress simulation result of the semiconductor element 11 having the anchor film 13 on the outer peripheral side of the gate wiring 11b, and indicates the stress simulation result in the case where the interval between the openings 13a of the anchor film 13 is 10 μm.

[0053] Also in Fig. 8 begins, as in Fig. 7, the peeling of the protective film 14 from the end of the semiconductor element 11 as its starting point, and the change in the position of the peeling tip 14E as the peeling proceeds inward (on the side of the source electrode 11c) is illustrated in order from above.

[0054] In the top stress contour diagram of Fig. 8, peaks of tensile stress occur at the ends of the semiconductor element 11 and the protective film 14, and a peak of compressive stress occurs at the peeling tip 14E.

[0055] As illustrated in the second stress contour diagram from the top, as the stress further increases, the peeling peak 14E moves inward, and the peeling region 14O expands. This is equally true in the third, fourth, and fifth stress contour diagrams from the top; although it is the same as in the semiconductor element 111 in that the peeling peak 14E moves inward and the peeling region 14O expands as the peeling progresses inward on the terminal region 11a, it can be understood that the protective film 14 on the anchor film 13 is hooked in the peeling region 14O outside the peeling peak 14E, and the tensile stress is dispersed in the peeling region 14O.

[0056] That is, in the stress contour diagrams of the second and lower ones from the top, there are a plurality of peak points of the tensile stress in the peeling region 14O, and in these partial regions, the protective film 14 is hooked to the openings 13a of the anchor film 13; therefore, the stress is distributed by the sealing resin 41 on the protective film 14 and absorbed as tensile stress. As a result, the peak of the compressive stress at the peeling peak 14E can be made smaller than that of the semiconductor element 111. This is also understood from the fact that, compared with Fig. 7, even if the detachment proceeds, the area of ​​the peak of the tensile stress at the starting point of the detachment at the ends of the semiconductor element 11 and the protective film 14 does not become large.

[0057] If the peak of the compressive stress at the peeling tip 14E decreases, the progress of the peeling can be suppressed, and if the progress of a peeling can be suppressed, the speed at which a peeling progresses further inward is reduced and the longer lifetime of the semiconductor device 1 can be realized.

[0058] Even if the peeling of the protective film 14 occurs from the outermost periphery of the semiconductor element 11 and partially progresses beyond the terminal region 11a, the state in which the silicon carbide layer in the terminal region 11a is covered with the interlayer insulating film 12 is also maintained because the openings 13a of the anchor film 13 do not penetrate the interlayer insulating film 12 and are present only in the anchor film 13. Therefore, no deterioration phenomenon such as the occurrence of a discharge occurs in the terminal region 11a, and a decrease in the breakdown voltage of the semiconductor element 11 can be suppressed.

[0059] Fig. 9 is a set of stress contour diagrams illustrating a stress simulation result of the semiconductor element 11 having the anchor film 13 on the outer peripheral side of the gate wiring 11b, and indicates the stress simulation result in the case where the interval between the openings 13a of the anchor film 13 is 50 μm.

[0060] Also in Fig. 9 begins, as in Fig. 8, the peeling of the protective film 14 from the end of the semiconductor element 11 as its starting point, and the change in the position of the peeling tip 14E as the peeling proceeds inward (on the side of the source electrode 11c) is illustrated in order from above.

[0061] In the top stress contour diagram of Fig. 9 is in the sense that tensile stress peaks occur at the ends of the semiconductor element 11 and the protective film 14 and a compressive stress peak occurs at the peeling tip 14E, it is the same as in Fig. 8. However, as can be seen from the stress contour diagrams of the second and subsequent ones from the top, the compressive stress of the release tip 14E is not distributed and absorbed by the anchor film 13 because there are fewer hooking portions of the protective film 14 on the openings 13a in the release region 14O outside the release tip 14E. This is presumably the case because the extension of the protective film 14 itself prevents the compressive stress generated at the release tip 14E from being sufficiently held by hooking onto the openings 13a of the anchor film 13.

[0062] Accordingly, the intervals between the openings 13a of the anchor film 13 must be designed according to the elastic modulus and yield strength of the protective film 14. When the protective film 14 is formed of polyimide, the interval between the openings 13a is preferably 5 µm or more and 20 µm or less, taking into account a change in structural dimensions such as shrinkage after baking of the polyimide. This can achieve both the effect of stress reduction and structural accuracy.

[0063] For example, the interlayer insulating film 12 is formed of silicon oxide, the anchor film 13 is formed of silicon nitride, and the protective film 14 is formed of polyimide, so that the interlayer insulating film 12 and the anchor film 13 are formed as materials harder than the protective film 14. This ensures that when the protective film 14 detaches, the stress caused by the deformation of the protective film 14 is dispersed, and accordingly, the detachment of the anchor film 13 and the cracking of the interlayer insulating film 12 can be prevented. Furthermore, formation by a conventional wafer process is easily performed with the above materials used for each of the films; therefore, an increase in manufacturing costs can be suppressed.

[0064] By making the shape of an inner side (on the side where the active area AR and the gate wiring 11b are formed) of the opening 13a of the anchor film 13 circular, the tensile stress generated when the peeled protective film 14 is hooked thereon can be dispersed and the peeling of the protective film 13 is prevented.

[0065] Furthermore, by arranging the openings 13a individually, the compressive stress can be dispersed in a plane within the plane of the terminal portion 11a when the peeling of the protective film 14 takes place, and local peeling can be prevented from progressing.

[0066] In the semiconductor device 1 of Embodiment 1 described above, although the semiconductor element 11 is a SiC semiconductor element, a Si semiconductor element made of silicon may be adopted.

[0067] SiC has a dielectric strength about 10 times higher than that of Si, and the thickness of the semiconductor layer can be reduced to about 1 / 10 of that of Si. Therefore, the SiC semiconductor device can achieve a low turn-on voltage and can even operate at high temperatures. Accordingly, the SiC semiconductor device can be made smaller and more efficient than the Si semiconductor device.

[0068] Furthermore, the semiconductor element 11 is not limited to being formed on the semiconductor device 1 having the Fig. 1, but can be mounted on a semiconductor device in which the semiconductor element is sealed with resin. Thus, the same effect as the one described above can be obtained.< / herstellungsverfahren> < / vorrichtungskonfiguration>

Claims

[1] Semiconductor device (1), comprising: - a substrate (21); - a semiconductor element (11) bonded to the substrate (21); and - a sealing resin (41) sealing at least a part of the substrate (21) and the semiconductor element (11), wherein: - the semiconductor element has: - an active region (AR) through which a main current flows in an ON state of the semiconductor element (11), - a connection area (11a) surrounding the active area (AR), - an anchor film (13) provided on an insulating film (12) of the terminal portion (11a), and - a protective film (14) covering at least the connection area including the anchor film (13), and - the anchor film (13) - consists of a material different from the insulating film (12) and - has a plurality of individually provided openings (13a). [2] The semiconductor device (1) according to claim 1, wherein the anchor film (13) is provided along the terminal region (11a) in plan view and has a loop shape. [3] The semiconductor device (1) according to claim 1, wherein each of said plurality of openings (13a) has a shape in which at least one side on the active region side is an arc shape in plan view. [4] A semiconductor device (1) according to claim 3, wherein each of said plurality of openings (13a) has a circular shape in plan view. [5] A semiconductor device (1) according to claim 3, wherein each of said plurality of openings (13a) has a semicircular shape in plan view. [6] A semiconductor device (1) according to claim 3, wherein each of said plurality of openings (13a) has a crescent shape in plan view. [7] A semiconductor device (1) according to claim 1, wherein a minimum interval between the openings (13a) is 5 µm or more and 20 µm or less. [8] A semiconductor device (1) according to claim 1, wherein the semiconductor element is a silicon carbide semiconductor element. [9] A semiconductor device (1) according to claim 1, wherein the protective film is a film made of polyimide or polyamide as a main material. [10] A semiconductor device (1) according to claim 1, wherein the anchor film is a film made of silicon nitride as a main material. [11] Semiconductor element (11), - comprising: - an active area (AR) through which a main current flows in an ON state; - a connection area (11a) surrounding the active area (AR); - an anchor film (13) provided on an insulating film (12) of the terminal portion (11a); and - a protective film (14) covering at least the connection area (11a) including the anchor film (13), - where: - the anchor film (13) consists of a different material from the insulating film (12) and - has a plurality of openings (13a) provided individually over the entire anchor film (13).

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