Substrate Loss Reduction for Semiconductor Devices

Abstract

IC chip comprising: a semiconductor substrate (106), a first dielectric region recessed in a top surface of the semiconductor substrate (106), an IMD layer located above the semiconductor substrate (106) and the first dielectric region, the IMD layer being bonded to the top surface of the semiconductor substrate (106), a semiconductor layer (108) located above the IMD layer (122), a semiconductor device (102) being inverted and located in the semiconductor layer (108), between the semiconductor layer (108) and the IMD layer (122), the semiconductor device (102) having a first source / drain electrode (114) located above the first dielectric region; a first pad (118) in the IMD layer (122) located above the first dielectric region, the first pad (118) being connected to the first source / drain electrode (114) is electrically coupled, and a through-hole (120) from the first pad (118) to the first source / drain electrode (114).

Description

BACKGROUNDSilicon-based semiconductor devices have been the standard for several decades. However, due to advantages over silicon-based semiconductor devices, semiconductor devices based on alternative materials are receiving increasing attention. For example, semiconductor devices based on group III-V semiconductor materials are increasingly receiving attention due to high electron mobility and wide band gaps compared to silicon-based semiconductor devices. Such high electron mobility and wide band gaps allow for improved performance and high temperature applications.US 2016 / 0 027 665 A1 discloses a semiconductor device comprising: a first substrate including a front-end device including a transistor, a radio frequency (RF) device, and a first interconnection structure; and a second substrate including a cavity disposed at a location corresponding to a location of the RF device. The first substrate and the second substrate are bonded together such that the first surface of the first substrate faces the cavity in the second substrate and the cavity overlies the RF device. Further prior art is known from Herrautt, F. [et al.]: Silicon-Packaged GaN Power HEMTs with Integrated Heat Spreaders. In: Electronic Components & Technology Conference, 2015, 1109-1114.The invention is defined in the claims.BRIEF DESCRIPTION OF THE DRAWINGSAspects of the present disclosure will be best understood from the following detailed description when read in conjunction with the accompanying figures. It should be noted that, according to the standard industry process, various elements are not drawn to scale. Indeed, for clarity of explanation, the dimensions of the various elements may be arbitrarily increased or decreased. FIG. 1 shows a cross-sectional view of some embodiments of an integrated circuit (IC) chip having a semiconductor device inverted and overlying a cavity recessed into a semiconductor substrate. FIG. 2 shows a top layout view of some embodiments of the IC chip of FIG. 1. FIGS. 3A and 3B show orthogonal cross-sectional views of some embodiments of the IC chip of FIG. 1, in which a semiconductor layer includes multiple individual layers. FIGS. 4A through 4C show cross-sectional views of some other embodiments of the IC chip of FIGS. 3A and 3B in which a bottom side of the cavity has recesses and / or the cavity is filled with a cavity filling dielectric layer. FIGS. 5A and 5B show orthogonal cross-sectional views of some alternative embodiments of the IC chip of FIGS. 3A and 3B in which multiple small cavities replace the cavity. FIG. 6 shows a top layout view of some embodiments of the IC chip of FIGS. 5A and 5B. FIGS. 7A to 4C show cross-sectional views of some other embodiments of the IC chip of FIGS. 5A and 5B in which bottom surfaces of the cavities have recesses and / or the cavities are filled with a cavity filling dielectric layer. FIGS. 8A to 8D show cross-sectional views of some other alternative embodiments of the semiconductor device of FIGS. 3A and 3B. FIGS. 9, 10, 11A, 11B, and 12 through 18 show a series of cross-sectional views of some embodiments of a method of forming an IC chip having a semiconductor device inverted and overlying at least one cavity recessed into a semiconductor substrate. Figure 19 shows a block diagram of some embodiments of the method of Figures 9, 10, 11A, 11B and 12-18. Figures 20A, 20B and 21-28 show a series of cross-sectional views of some alternative embodiments of the method of Figures 9, 10, 11A, 11B and 12-18 in which the at least one cavity is filled with a high-volume filling dielectric layer. Figure 29 is a block diagram of some embodiments of the method of Figures 20A, 20B and 21-28. Figures 30, 31A, 31B, and 32 through 38 show a series of cross-sectional views of some alternative embodiments of the method of Figures 9, 10, 11A, 11B, and 12 through 18 in which recesses are located at a bottom of the at least one cavity. Figure 39 shows a block diagram of some embodiments of the method of Figures 30, 31A, 31B and 32-38. Figures 40A, 40B, and 41-48 show a series of cross-sectional views of some alternative embodiments of the method of Figures 30, 31A, 31B, and 32-38 in which the at least one cavity is filled with a cavity-filling dielectric layer. Figure 49 shows a block diagram of some embodiments of the method of Figures 40A, 40B, and 41-48.DETAILED DESCRIPTIONThe present disclosure provides many different embodiments, or examples, for implementing different features of this disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, forming a first element over or on a second element in the description below may include embodiments in which the first and second elements are formed in direct contact, and may also include embodiments in which additional elements may be formed between the first and second elements such that the first and second elements may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in the various examples. This repetition is for purposes of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or embodiments discussed.Moreover, terms relating to spatial relativeity, such as "below," "below," "lower," "above," "upper," and the like, may be used herein for ease of discussion to describe the relationship of one element or feature to another element or feature (to other elements or features) as depicted in the figures. The terms relating to spatial relativeness are intended to encompass different orientations of the device being used or operated in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or otherwise oriented) and the spatially relative terms used herein may likewise be construed accordingly.Some integrated circuit (IC) chips include a group III-V semiconductor stack overlying and epitaxially grown on a first silicon substrate, and further include a high-electron-mobility transistor (HEMT) overlying and formed on the group III-V semiconductor stack. However, a challenge with the IC chips is that a power added efficiency (PAE) of the HEMT may be low due to a high substrate power loss. A substrate power loss may be high due to a low substrate resistance. The substrate resistance may be low due to a low silicon resistance of the first silicon substrate, a low interfacial resistance between the first silicon substrate and the group III-V semiconductor stack, and a high substrate capacitance from source / drain electrodes of the HEMT to the first semiconductor substrate. The silicon resistance may be low due to epitaxial growth of the group III-V semiconductor stack on the first silicon substrate. If the silicon resistance were high, the group III-V semiconductor stack may be epitaxially grown with a poor crystal quality unsuitable for the HEMT. The interfacial resistance may be low due to band bending, which may induce formation of a two-dimensional hole gas (2-DHG).To increase the PAE of the HEMT, the HEMT may be transferred to a second silicon substrate having a high resistance compared to the first silicon substrate. In particular, an interconnect structure may be formed over and electrically coupled to the HEMT, and the second silicon substrate may be disposed over and bonded to the interconnect structure. The first silicon substrate may then be removed. By transferring the HEMT, a silicon resistance may be high because the second silicon substrate has the high resistance. As such, substrate resistance may be increased and substrate power loss may be reduced. This, in turn, may increase the PAE of the HEMT. Nevertheless, the increase in PAE of the HEMT may be slight. For example, the improvement may be as low as 5% or less. The increase may be slight because the interfacial resistance may still be low and / or the substrate capacitance may still be high.Various embodiments of the present disclosure are directed to an IC chip including a semiconductor device and methods of forming the IC chip in which the semiconductor device has a low substrate loss and a high PAE. In some embodiments of the IC chip, a semiconductor layer overlies a semiconductor substrate. The semiconductor layer may be or comprise, for example, one or more Group III-V semiconductor materials and / or another suitable semiconductor material(s). The semiconductor substrate may be or comprise, for example, silicon and / or another suitable semiconductor material(s). An interconnect structure is located between the semiconductor substrate and the semiconductor stack and includes an inter-metal dielectric (IMD) layer and source / drain pads in the IMD layer. The semiconductor device is located on a lower side of the semiconductor layer, between the semiconductor layer and the interconnect structure, and includes source / drain electrodes electrically coupled to the source / drain pads, respectively. The semiconductor device may be, for example, a HEMT or another suitable type of semiconductor device. A dielectric region lies below the source / drain pads, between the semiconductor substrate and the interconnect structure, and is recessed into a top surface of the semiconductor substrate. The dielectric region is independent of the interconnect structure and may be, for example, a cavity or a dielectric layer.The source / drain pads are capacitively coupled to the semiconductor substrate via the IMD layer to define a substrate capacitance. Since the dielectric region is under the source / drain pads, the capacitive coupling may also take place via the dielectric region. In addition, since the IMD layer and the dielectric region are independent, the substrate capacitance may be modeled as two different capacitors electrically coupled in series and located in the IMD layer and the dielectric region, respectively. Multiple capacitors in series provide a smaller capacitance than the capacitances of the individual capacitors, so that the dielectric region may reduce the substrate capacitance compared to what would be without the dielectric region. Since the substrate capacitance can be reduced, the substrate resistance can be increased and a substrate power loss can be reduced. This, in turn, may increase PAE.Since the dielectric region is buried in the semiconductor substrate, an interface between the semiconductor substrate and the IMD layer and between the semiconductor substrate and the dielectric region may be uneven, and thus may have an increased length compared to a flat state. Due to the increased length, the interfacial resistance may be increased. Due to the increased interfacial resistance, substrate resistance may be increased and substrate power loss may be decreased. This, in turn, may increase PAE.Referring to FIG. 1, a cross-sectional view of some embodiments of an integrated circuit (IC) chip including a semiconductor device 102 is provided in which the semiconductor device is vertically inverted and overlies a cavity 104 recessed into a semiconductor substrate 106. In addition, the semiconductor device 102 is located on a lower side of a semiconductor layer 108 spaced above the semiconductor substrate 106 by an interconnect structure 110. The semiconductor device 102 is a HEMT and includes a semiconductor active region 112, a pair of source / drain electrodes 114 and a gate electrode 116.The active semiconductor region 112 is defined by the semiconductor layer 108, and the source / drain electrodes 114 and the gate electrode 116 are under the active semiconductor region 112. Since the source / drain electrodes 114 and the gate electrode 116 are below the active semiconductor region 112 instead of being above the active semiconductor region 112, the semiconductor device 102 is referred to as being "vertically inverted.". The source / drain electrodes 114 are respectively located on and electrically coupled to opposite sides of the semiconductor active region 112, and the gate electrode 116 is located between the source / drain electrodes 114.The interconnect structure 110 includes a plurality of pads 118 and a plurality of vias 120. The pads 118 are located in an IMD layer 122 that interfaces with the semiconductor substrate 106 and further defines a top surface of the cavity 104. The vias 120 are located in an interlayer dielectric (ILD) layer 124 that surrounds the source / drain electrodes 114 and the gate electrode 116, and further separates the IMD layer 122 from the semiconductor layer 108. The pads 118 are individually electrically coupled to the source / drain electrodes 114 and the gate electrodes 116, respectively, and to them via the vias 120, respectively.The source / drain pads 118 s / d individual to and electrically coupled to the source / drain electrodes 114 are capacitively coupled to the semiconductor substrate 106 via the IMD layer 122 and the cavity 104 to define individual source / drain capacitances. In addition, the cavity 104 is electrically insulating, such that the source / drain capacitances may each be modeled as two capacitors electrically coupled in series and located in the IMD layer 122 and the cavity 104, respectively. For clarity, the capacitors on the IMD layer 122 and cavity 104, respectively, are each labeled C IMD and C, respectively. C CAV.Multiple capacitors in series provide a smaller capacitance than the capacitances of the individual capacitors, so that the cavity 104 may reduce the source / drain capacitances compared to the source / drain capacitances without the cavity 104. For example, a source / drain capacitance may be the same. Thus, assuming that the IMD capacitors C IMD and the cavity capacitors CCAVare 1 microfarad and 0.25 microfarad, respectively, a source / drain capacitance may achieve a 80% reduction (e.g.,). It should be noted that these capacitances are non-limiting examples and other capacitances are possible. Since the source / drain capacitances can be reduced by the cavity 104, a substrate capacitance can be reduced and, therefore, a substrate resistance can be increased. Since the substrate resistance can be increased, a substrate power loss can be reduced. This, in turn, may increase the PAE of the semiconductor device 102. The PAE is an important parameter for, among other things, 5G mobile communication and other suitable radio frequency (RF) applications.As described above, the cavity 104 is electrically insulating. Therefore, the cavity 104 may be considered a dielectric region. In some embodiments, a dielectric constant of the cavity 104 is less than that of the IMD layer 122. The lower the dielectric constant of cavity 104, the lower the capacitances of cavity capacitors CCAVand the more significant the reduction in source / drain capacitances. Additionally, in some embodiments, the cavity 104 is hermetically sealed and / or filled with air or other suitable gas.Because the cavity 104 is recessed into the semiconductor substrate 106, the semiconductor substrate 106 has a first thickness T 1 at a portion underlying the cavity 104, and further has a second thickness T 2, which is greater than the first thickness T 1, at portions laterally offset from and / or exposed by the cavity 104. In addition, a length of an interface 126 between the semiconductor substrate 106 and the IMD layer 122, and between the semiconductor substrate 106 and the cavity 104, is increased from a drain side of the semiconductor device 102 to a source side of the semiconductor device 102. By increasing the length, an interfacial resistance from the drain side to the source side is increased. Due to the increased interfacial resistance, substrate resistance may be increased and substrate power loss may be decreased. This, in turn, may increase the PAE of the semiconductor device 102.In some embodiments, the semiconductor substrate 106 has a high resistance to further increase the PAE of the semiconductor device 102. The high resistance may be, for example, a resistance greater than about 5, 7.5, or 10 kiloohms / centimeter (kΩ / cm), or another suitable resistance. In addition, the high resistance may be, for example, a resistance of about 5 to 10 kΩ / cm, about 5 to 7.5 kΩ / cm, or about 7.5 to 10 kΩ / cm. Other suitable resistors are possible, however. Due to the high resistance, the substrate resistance may be increased and a substrate power loss may be decreased. This, in turn, may increase PAE. The semiconductor substrate 106 may be or include, for example, a bulk substrate of single crystal silicon, a bulk substrate of silicon carbide, or another suitable type of semiconductor substrate.A passivation layer 128 overlies the first semiconductor layer 108. The passivation layer 128 may be or include, for example, silicon nitride, aluminum oxide, another suitable dielectric(s), or any combination of the foregoing.A plurality of contacts 130 extend through the passivation layer 128, the semiconductor layer 108, and the ILD layer 124, respectively, to the pads 118. The contacts 130 are individual to the pads 118 and provide electrical coupling to the pads 118 and therefore the source / drain electrodes 114 and the gate electrodes 116 from outside the IC chip. In addition, the contacts 130 are separated from the passivation layer 128, the semiconductor layer 108, and the ILD layer 124 by individual contact liner layers 132. The contacts 130 may be or include, for example, aluminum copper, aluminum, other suitable metal(s) and / or conductive material(s), or any combination of the foregoing. The contact liner layers 132 may be or include, for example, silicon oxide and / or another suitable dielectric(s).In some embodiments, the IMD layer 122 is or includes a dielectric oxide and / or other suitable dielectric(s). In some embodiments, the IMD layer 122 has a dielectric constant of about 3 to 4.2, but other suitable values are possible. In some embodiments, a thickness of the IMD layer 122 is about 1 to 2 micrometers, about 1 to 1.5 micrometers, about 1.5 to 2 micrometers, or another suitable value. In some embodiments, the ILD layer 124 is or comprises a dielectric oxide and / or other suitable dielectric(s). In some embodiments, a thickness of the ILD layer 124 is about 2 to 3 micrometers, about 2 to 2.5 micrometers, about 2.5 to 3 micrometers, or another suitable value. In some embodiments, the pads 118 and the vias 120 are metal and / or other suitable conductive material(s).In some embodiments, the semiconductor layer 108 represents or comprises multiple individual layers. In some embodiments, the semiconductor layer 108 includes a plurality of different semiconductor materials corresponding to the plurality of individual layers. In alternative embodiments, the semiconductor layer 108 is made of or substantially consists of a single material. In some embodiments, the semiconductor layer 108 is or includes a group III-V semiconductor material, a group II-VI semiconductor material, a group IV-IV semiconductor material, other suitable material(s), or any combination of the foregoing.In some embodiments, the semiconductor device 102 is a depletion mode HEMT, an enhancement mode HEMT, a depletion mode metal oxide semiconductor HEMT (MOS HEMT), an enhancement mode MOS HEMT, or another suitable type of HEMT. In alternative embodiments, the semiconductor device 102 is a MOS field effect transistor (MOSFET) or other suitable type of semiconductor device.Referring to FIG. 2, an upper layout view 200 of some embodiments of the IC chip of FIG. 1 is provided. For example, the cross-sectional view 100 of FIG. 1 may be drawn along line A, but other suitable positions are possible. The semiconductor device 102 completely overlaps the cavity 104 (shown in dashed lines) to promote a reduction in substrate capacitance, as described above. The cavity 104 has a rectangular shape, but may alternatively have a square shape, a circular shape, an oval shape, or another suitable shape. The source / drain electrodes 114 are respectively located on opposite sides of the cavity 104, and the gate electrode 116 is located between the source / drain electrodes 114. Additionally, the active semiconductor region 112 (shown in dashed lines) extends between the source / drain electrodes 114.The contacts 130 are located at a perimeter of the cavity 104, wherein the source / drain contacts 130 s / d partially overlap the cavity 104, and a gate contact 130 g is laterally offset from the cavity 104. Note that the gate contact 130 g is not visible in the cross-sectional view 100 of FIG. 1. In alternative embodiments, none of the contacts 130 overlap the cavity 104. In alternative embodiments, all of the contacts 130 overlap the cavity 104. In alternative embodiments, a gate contact 10g partially overlaps the cavity 104, but the source / drain contacts 130 s / d are laterally offset from the cavity 104. The gate contact 130 g is electrically coupled to the gate electrode 116. The source / drain contacts 130 s / d are each individually electrically coupled to and for an adjacent one of the source / drain electrodes 114.Referring to FIGS. 3A and 3B, orthogonal cross-sectional views 300A, 300B of some embodiments of the IC chip of FIG. 1 are provided in which a semiconductor layer 108 includes multiple individual layers. In some embodiments, the IC chip has an upper layout as in FIG. 2. in such embodiments, the cross-sectional view 300A of FIG. 3A may be drawn along the line A in FIG. 2, and the cross-sectional view 300B of FIG. 3B may be drawn along the line B in FIG. 2. In alternative embodiments, the IC chip has another suitable top layout. The semiconductor layer 108 includes a buffer layer 302, a channel layer 304 underlying the buffer layer 302, and a barrier layer 306 underlying the channel layer.The buffer layer 302 compensates for differences in lattice constants, crystal structures, coefficients of thermal expansion, or any combination of the foregoing between the channel layer 304 and a semiconductor substrate (not shown) on which the semiconductor layer 108 is formed. In some embodiments, the buffer layer 302 is formed from multiple individual layers (e.g., a seed buffer, a graded buffer layer, etc.).The barrier layer 306 is polarized such that positive charge is displaced to a top surface of the barrier layer 306 and negative charge is displaced to a bottom surface of the barrier layer 306, or vice versa. The polarization may result from, for example, spontaneous polarization effects and / or piezoelectric polarization effects. The channel layer 304 has a band gap different from that of the barrier layer 306, and directly contacts the barrier layer 306. As such, channel layer 304 directly contacts contacts of barrier layer 306 at a heterojunction.Because the barrier layer 306 is polarized, a two-dimensional carrier gas 308 having a high concentration of mobile carriers is formed in the channel layer 304 along the heterojunction. In the case that the barrier layer 306 is polarized such that positive charge is present on the upper surface of the barrier layer 306, the two-dimensional carrier gas 308 may be a two-dimensional electron gas (2 DEG). In the case that the barrier layer 306 is polarized such that negative charge is on the top surface of the barrier layer 306, the two-dimensional carrier gas 308 may be a 2-DHG. Due to the high concentration of mobile carriers, the two-dimensional carrier gas 308 is conductive and allows the semiconductor device 102 to operate in a depletion mode.In some embodiments, the semiconductor layer 108 is a group III-V semiconductor layer. The buffer layer 302 may be or include, for example, aluminum nitride, aluminum gallium nitride, another suitable Group III-V material(s), or any combination of the foregoing. The channel layer 304 may be or include, for example, gallium nitride and / or another suitable Group III-V material(s). For example, the barrier layer 306 may be or comprise, for example, aluminum gallium nitride, and / or another suitable Group III-V material(s). In alternative embodiments, the semiconductor layer 108 is a group II-VI semiconductor layer, a group IV-IV semiconductor layer, or another suitable type of semiconductor layer.Referring to FIGS. 4A to 4C, cross-sectional views 400A to 400C of some other alternative embodiments of the IC chip of FIGS. 3A and 3B are provided. Note that cross-sectional views 400A- 400C of FIGS. 4A-4C correspond to cross-sectional view 300A of FIG. 3A and therefore show modifications of cross-sectional view 300A of FIG. 3A.In FIG. 4A, a cavity filling dielectric layer 402 fills the cavity 104 to increase the bond strength between the semiconductor substrate 106 and the interconnect structure 110. Also, recall that cavity 104 introduces capacitance in series with that of IMD layer 122 to reduce substrate capacitance and increase substrate resistance. The cavity filling dielectric layer 402 serves the same purpose as the cavity 104, but allows for greater control of capacitance in series with that of the IMD layer 122, since a dielectric constant of the cavity filling dielectric layer 402 can be adjusted more easily than that of the cavity 104. Generally, the lower the capacitance of the cavity filling dielectric layer 402, the greater the decrease in substrate capacitance and the greater the increase in substrate resistance.In some embodiments, the cavity-filling dielectric layer 402 is or includes a dielectric oxide and / or other suitable dielectric(s). In some embodiments, the cavity filling dielectric layer 402 is a low-k dielectric material or an extreme low-k dielectric material. A low-k dielectric material may be, for example, a dielectric material having a dielectric constant of about 2 to 3.9, or another suitable value. On the other hand, an extreme low-k dielectric material may be, for example, a dielectric material having a dielectric constant less than about 2 or another suitable value. In some embodiments, the cavity filling dielectric layer 402 has a lower dielectric constant than the IMD layer 122 and / or the ILD layer 124.In FIG. 4B, the cavity 104 repeatedly switches between a first depth D 1 and a second depth D 2 from a first side of the cavity 104 to a second side of the cavity 104 opposite the first side. In some embodiments, the cavity 104 periodically switches between the first and second depths D 1, D 2 from the first side to the second side. In alternative embodiments, the cavity 104 randomly or pseudo-randomly alternates between the first and second depths D 1, D 2 from the first side to the second side. In alternative embodiments, the cavity 104 varies between more than two depths from the first side to the second side.Since the cavity 104 switches between the first and second depths D 1, D 2 from the first side of the cavity 104 to the second side of the cavity 104, the semiconductor substrate 106 switches between a first thickness T 1 and a third thickness T 3, which is less than the first thickness T 1, from the first side to the second side. Additionally, a lower profile of the cavity 104 is uneven and includes multiple upward protrusions or downward recesses as viewed. As such, a length of the interface 126 between the semiconductor substrate 106 and the IMD layer 122, and between the semiconductor substrate 106 and the cavity 104, is increased from a drain side of the semiconductor device 102 to a source side of the semiconductor device 102. By increasing the length, an interfacial resistance from the drain side to the source side is increased. Due to the increased interfacial resistance, substrate resistance may be increased and substrate power loss may be decreased. This, in turn, may increase PAE.In FIG. 4C, the cavity 104 is as in FIG. 4B and is filled by the cavity filling dielectric layer 402, as in FIG. 4A. Since the cavity 104 is such as in FIG. 4, the length of the interface 126 is increased, and therefore the substrate resistance is increased. Since the cavity 104 is filled by the cavity filling dielectric layer 402, as in FIG. 4A, a bonding strength between the semiconductor substrate 106 and the interconnect structure 110 is increased. In addition, the capacitance of the dielectric region at the cavity 104 may be better controlled. As discussed above, this allows for better control of substrate capacitance and, therefore, better control of substrate resistance.Although the cross-sectional views 400A to 400C of FIGS. 4A to 4C show modifications of the cross-sectional view 300A of FIG. 3A, the modifications may be applied to the cross-sectional view 300B of FIG. 3B. For example, the cavity 104 of FIG. 3B may be filled by the cavity filling dielectric layer 402, as shown in FIGS. 4A and 4C.Referring to FIGS. 5A and 5B, orthogonal cross-sectional views 500A, 500B of some alternative embodiments of the IC chip of FIGS. 3A and 3B are provided in which the cavity 104 is replaced by a plurality of small cavities 104 s. The small cavities 104s are individual to the source / drain electrodes 114 and are located under them, respectively. In addition, the small voids 104 sfor the source / drain pads 118 are s / d individual and are each under them. For example, the small voids 104 smay each be as described with the void 104 of FIGS. 3A and 3B, except for the smaller size.The small cavities 104 sincreases the bonding area between the semiconductor substrate 106 and the interconnect structure 110. This increases the bond strength and reduces the likelihood that the IC chip will experience mechanical failure along the bond pad. In addition, the small voids 104 s reduce a source / drain capacitance from the source drain pads 118 s / d to the semiconductor substrate 106 in the same manner as the void 104. As such, the small voids reduce substrate capacitance, increase substrate resistance, and reduce substrate power loss. This in turn increases the PAE of the semiconductor device 102. In some embodiments, the small voids 104 sfurther reduce capacitive coupling between the second semiconductor substrate 106 and the source / drain pads 118 s / d as compared to FIGS. 3A and 3B. By reducing the capacitive coupling, the source / drain capacitance is further reduced and the PAE is further increased.Referring to FIG. 6, an upper layout view 600 of some embodiments of the IC chip of FIGS. 5A and 5B is provided. For example, cross-sectional view 500A of FIG. 5A may be drawn along line C, but other suitable positions are possible. In addition, cross-sectional view 500B of FIG. 5B may be drawn along line D, for example, but other suitable positions are possible. The upper layout view 600 is as described in FIG. 2, except that the cavity 104 has been replaced with the plurality of small cavities 104 s(shown with dashed lines).Referring to FIGS. 7A to 7C, cross-sectional views 700A to 700C of some other alternative embodiments of the IC chip of FIGS. 5A and 5B are provided. It should be noted that cross-sectional views 700A- 700C of FIGS. 7A-7C correspond to cross-sectional view 500A of FIG. 5A and therefore represent modifications of cross-sectional view 500A of FIG. 5A. FIG. 5B is the same for embodiments of the IC chip in FIGS. 7A to 7C.In FIG. 7A, the cavity filling dielectric layer 402 fills the small cavities 104 sto increase the bond strength between the semiconductor substrate 106 and the interconnect structure 110. Additionally, as described with reference to FIG. 4A, the cavity filling dielectric layer 402 enables better control of the dielectric constant at the small cavities 104 s, which enables better control of the substrate capacitance and therefore the substrate resistance.In FIG. 7B, each small cavity 104 sreceeds repeatedly between a first depth D 1 and a second depth D 2 from a first side of the small cavity to a second side of the small cavity opposite the first side, as described with reference to FIG. 4B. In addition, a thickness of the semiconductor substrate 106 switches between a first thickness T 1 and a third thickness T 3 at each small cavity 104 s. Accordingly, a length of the interface 126 between the semiconductor substrate 106 and the IMD layer 122, and between the semiconductor substrate 106 and the small voids 104 s, is increased from a drain side of the semiconductor device 102 to a source side of the semiconductor device 102. By increasing the length, the substrate resistance may be increased and substrate power loss may be decreased.In FIG. 7C, the small voids 104 sis as in FIG. 7B and are filled by the void filling dielectric layer 402, as in FIG. 7A. Since the small voids 104 sare such as in FIG. 7B, the length of the interface 126 is increased, and therefore the substrate resistance is increased. Since the small voids 104 sare filled by the void filling dielectric layer 402, as in FIG. 7A, a bonding strength between the semiconductor substrate 106 and the interconnect structure 110 is increased. In addition, the capacitance of the dielectric regions at the small cavities 104 scan be controlled better.Referring to FIGS. 8A to 8D, cross-sectional views 800A to 800D of some other alternative embodiments of the semiconductor device 102 of FIGS. 3A and 3B are provided.In FIG. 8A, a capping layer 802 is disposed between the gate electrode 116 and the semiconductor layer 108. Additionally, the capping layer 802 distributes mobile carriers overlying the capping layer 802 in the two-dimensional carrier gas 308. As such, in the absence of an external electric field (e.g., applied through the gate electrode 116), the two-dimensional carrier gas 308 is discontinuous at the capping layer 802, and the semiconductor device 102 may operate in an accumulation mode. The distribution may result from, for example, polarization of the capping layer 802, doping of the capping layer 802, or other suitable property of the capping layer 802. In some embodiments, capping layer 802 is or comprises a doped Group III-V semiconductor material. For example, the capping layer 802 may be or comprise doped gallium nitride. In alternative embodiments, capping layer 802 is or comprises another suitable type of semiconductor material.In FIG. 8B, the capping layer 802 is the same as in FIG. 8A, except that the capping layer 802 blanketly covers the barrier layer 306. Also, the contacts 130 and the source / drain electrodes 114 extend through the capping layer 802. As such, in the absence of an external electric field, the two-dimensional carrier gas 308 is disposed over the source / drain electrodes 114 and the semiconductor device 102 may operate in an accumulation mode.In FIG. 8C, a gate dielectric layer 804 separates the gate electrode 116 from the barrier layer 306. As such, the semiconductor device 102 may be a MOS HEMT operating in depletion mode. The gate dielectric layer 804 may be or include, for example, aluminum oxide, silicon oxide, another suitable dielectric(s), or any combination of the foregoing.In FIG. 8D, the gate dielectric layer 804 separates the gate electrode 116 from the barrier layer 306 and the channel layer 304. In addition, the gate dielectric layer 804 and the gate electrode 116 extend through the barrier layer 306. As such, the two-dimensional carrier gas 308 is discontinuous in the gate electrode 116 in the absence of an external electric field and the semiconductor device 102 may be a MOS HEMT operating in an accumulation mode.Although FIGS. 8A to 8D show various embodiments of the semiconductor device 102 using embodiments of the IC chip in FIGS. 3A and 3B, the various embodiments of the semiconductor device 102 are also applicable to embodiments of the IC chip in any of FIGS. 4A to 4C, 5A, 5B, and 7A to 7C. In other words, the semiconductor device 102 in any of FIGS. 4A to 4C, 5A, 5B, and 7A to 7C may be replaced with the semiconductor device 102 in any of FIGS. 8A to 8D.Referring to FIGS. 9, 10, 11A, 11B, and 12 to 18, a series of cross-sectional views 900, 1000, 1100A, 1100B, 1200 to 1800 of some embodiments of a method of forming an IC chip are provided in which a semiconductor device is inverted and overlies at least one cavity recessed into a semiconductor substrate. The method may be used, for example, to form the IC chip of FIGS. 3A and 3B, the IC chip of FIGS. 5A and 5B, or another suitable IC chip.As illustrated by cross-sectional view 900 of FIG. 9, a semiconductor layer 108 is epitaxially deposited over a first semiconductor substrate 902. The semiconductor layer 108 includes a buffer layer 302, a channel layer 304 overlying the buffer layer 302, and a barrier layer 306 overlying the channel layer. In alternative embodiments, the semiconductor layer 108 has another suitable composition. The semiconductor layer 108 varies depending on a semiconductor device formed on the semiconductor layer 108 thereafter.The buffer layer 302 compensates for differences in lattice constants, crystal structures, coefficients of thermal expansion, or any combination of the foregoing between the channel layer 304 and the first semiconductor substrate 902. In some embodiments, buffer layer 302 is formed from multiple individual layers, not individually shown. The barrier layer 306 is polarized such that positive charge is displaced to a top surface of the barrier layer 306 and negative charge is displaced to a bottom surface of the barrier layer 306, or vice versa. The channel layer 304 has a band gap different from that of the barrier layer 306, and directly contacts the barrier layer 306 at a heterojunction. Since the barrier layer 306 is polarized, a two-dimensional carrier gas 308 (e.g., a 2-DHG or a 2-DEG) having a high concentration of mobile carriers is formed in the channel layer 304 along the heterojunction.The semiconductor layer 108 may be, for example, or include, one or more Group III-V semiconductor materials, one or more Group II-VI semiconductor materials, one or more Group IV-IV semiconductor materials, or other suitable type(s) of semiconductor material. In some embodiments where the semiconductor layer 108 is or includes Group III-V semiconductor material(s), the buffer layer 302 is or includes aluminum nitride, aluminum gallium nitride, other suitable Group III-V material(s), or any combination of the foregoing. In some embodiments where the semiconductor layer 108 is or includes a group III-V semiconductor material(s), the channel layer 304 is or includes gallium nitride and / or another suitable group III-V material(s). In some embodiments where the semiconductor layer 108 is or comprises a group III-V semiconductor material(s), the barrier layer 306 is or comprises aluminum gallium nitride and / or another suitable group III-V material(s).The first semiconductor substrate 902 may be or include, for example, a bulk substrate of single crystal silicon, a bulk substrate of silicon carbide, or another suitable type of semiconductor substrate. In some embodiments, the first semiconductor substrate 902 has a low resistance. The low resistance may be, for example, a resistance less than about 1 kΩ / cm, 1.5 kΩ / cm, 2 kΩ / cm, or another suitable resistance. In addition, the low resistance may be, for example, a resistance of about 1 to 1.5 kΩ / cm or about 1 to 1.5 to 2 kΩ / cm. Other suitable resistors are possible, however. When the first semiconductor substrate 902 has a high resistance, the semiconductor layer 108 may be epitaxially deposited with a poor crystal quality unsuitable for a semiconductor device 102 formed thereafter.As also illustrated by cross-sectional view 900 of FIG. 9, semiconductor device 102 is formed on semiconductor layer 108. The semiconductor device 102 is a depletion mode HEMT, but may alternatively be an enhancement mode HEMT, a depletion mode MOS HEMT, an enhancement mode MOS HEMT, or another suitable type of HEMT. Non-limiting examples of these alternatives are illustrated and described in Figures 8A-8D. In alternative embodiments, the semiconductor device 102 is a MOSFET or other suitable type of semiconductor device other than a HEMT.The semiconductor device 102 includes a semiconductor active region 112, a pair of source / drain electrodes 114, and a gate electrode 116. The active semiconductor region 112 is defined by the semiconductor layer 108, and the source / drain electrodes 114 and the gate electrode 116 are overlying the active semiconductor region 112. The source / drain electrodes 114 are respectively located on and electrically coupled to opposite sides of the semiconductor active region 112, and the gate electrode 116 is located between the source / drain electrodes 114. In some embodiments, the semiconductor device 102 has an upper layout as in FIG. 2 and / or FIG. 6.As illustrated by cross-sectional view 1000 of FIG. 10, an interconnect structure 110 is formed over and electrically coupled to semiconductor device 102. The interconnect structure 110 includes a plurality of pads 118 and a plurality of vias 120. The pads 118 are located in an IMD layer 122 and are individually electrically coupled to the source / drain electrodes 114 and the gate electrodes 116, respectively, via the vias 120. The pads 118 include source / drain pads 118 s / d corresponding to the source / drain electrodes 114 and further include a gate pad 118 g corresponding to the gate electrode 118. In some embodiments, the pads 118 have a top layout as in FIGS. 2 and / or 6, but other suitable top layouts are possible. In alternative embodiments, the gate pad 118 g is not visible in the cross-sectional view 1000. The vias 120 are located in an ILD layer 124 that surrounds the source / drain electrodes 114 and the gate electrode 116, and further separates the IMD layer 122 from the semiconductor layer 108.In some embodiments, the IMD layer 122 is or includes a dielectric oxide and / or other suitable dielectric(s). In some embodiments, the IMD layer 122 has a dielectric constant of about 3 to 4.2, but other suitable values are possible. In some embodiments, a thickness T IMD of the IMD layer 122 is about 1 to 2 micrometers, about 1 to 1.5 micrometers, about 1.5 to 2 micrometers, or another suitable value. In some embodiments, the ILD layer 124 is or comprises a dielectric oxide and / or other suitable dielectric(s). In some embodiments, a thickness TILDof the ILD layer 124 is about 2 to 3 micrometers, about 2 to 2.5 micrometers, about 2.5 to 3 micrometers, or another suitable value.As illustrated by cross-sectional view 1100A of FIG. 11A, a second semiconductor substrate 106 is patterned to form a cavity 104. As will be seen below, the second semiconductor substrate 106 is then placed over and bonded to the structure of FIG. 10. The cavity 104 is sized and oriented such that upon completion of the bonding, the cavity 104 overlaps the semiconductor device 102, and more particularly the source / drain pads 118, in s / d when viewed from above. This may help reduce substrate capacitance, as described in detail below.Due to the cavity 104, the second semiconductor substrate 106 has a first thickness T 1 at a portion underlying the cavity 104. In addition, the second semiconductor substrate 106 has a second thickness T 2, which is greater than the first thickness T 1, at portions laterally offset from the cavity 104. In some embodiments, the second thickness T 2 is about 950 to 1050 micrometers, about 950 to 1000 micrometers, about 1000 to 1050 micrometers, or another suitable value.In some embodiments, the second semiconductor substrate 106 has a high resistance compared to the first semiconductor substrate 902 (see, e.g., FIG. 10 ). As will be seen below, the semiconductor device 102 is subsequently transferred to the second semiconductor substrate 106. The high resistance reduces substrate losses and increases the PAE of the semiconductor device 102. The high resistance may be, for example, a resistance greater than about 5 kΩ / cm, 7.5 kΩ / cm, 10 kΩ / cm, or another suitable resistance. In addition, the high resistance may be, for example, a resistance of about 5 to 10 kΩ / cm, about 5 to 7.5 kΩ / cm, or about 7.5 to 10 kΩ / cm. Other suitable resistors are possible, however.The patterning may include, for example: 1) forming a mask 1102 over the second semiconductor substrate 106; 2) etching the second semiconductor substrate 106, the mask 1102 being arranged to form the cavity 104; 3) and removing the mask 1102. However, other suitable processes for patterning are possible. The mask 1102 may be, for example, a photoresist mask formed by photolithography or another suitable type of mask. The etching may be performed by dry etching, for example, but other suitable types of etching are possible.Alternatively, as illustrated by the cross-sectional view 1100B of FIG. 11B, the second semiconductor substrate 106 is patterned to form a plurality of small voids 104 s. As seen below and mentioned above, the second semiconductor substrate 106 is then placed over and bonded to the structure of FIG. 10. The small cavities 104 sare sized and aligned such that upon completion of the bonding, the small cavities 104 s, when viewed from above, overlap the semiconductor device 102 and, in particular, respectively overlap the source / drain pads 118 in s / d fashion. This may help reduce substrate capacitance, as described in detail below. In addition, the small voids increase a bonding area between the second semiconductor substrate 106 and the structure of FIG. 10 during bonding. This increases the bond strength and reduces the likelihood that the IC chip will experience mechanical failure along the bond pad. The second semiconductor substrate 106 and the patterning may be, for example, as described with reference to FIG. 11A.As illustrated by cross-sectional view 1200 of FIG. 12, the second semiconductor substrate 106 is vertically inverted and is disposed over and bonded to the interconnect structure 110. In some embodiments, the cavity 104 is hermetically sealed and / or filled with air or other suitable gas. As mentioned above, FIGS. 11A and 11B are alternatives to each other. FIG. 12 illustrates the method continuing from FIG. 11A while skipping FIG. 11B, and thus uses embodiments of the second semiconductor substrate 106 in FIG. 11A. In alternative embodiments, the method of FIG. 11B continues while skipping FIG. 11A, and thus uses embodiments of the second semiconductor substrate 106 in FIG. 11B. Bonding may be performed, for example, by fusion bonding or another suitable type of bonding.As illustrated by the cross-sectional view 1300 of FIG. 13, the structure of FIG. 12 is vertically reversed and the first semiconductor substrate 902 is thinned to reduce a thickness T fs of the first semiconductor substrate 902. In some embodiments, the thickness T fs is about 4 micrometers, about 3 to 5 micrometers, or another suitable value. Thinning may be performed, for example, using mechanical grinding, chemical mechanical planarization (CMP), or other suitable thinning process.As illustrated by cross-sectional view 1400 of FIG. 14, a residue of the first semiconductor substrate 902 is removed. The removal may be performed, for example, by etching or another suitable type of removal process.As illustrated by cross-sectional view 1500 of FIG. 15, a passivation layer 128 is deposited over the semiconductor layer 108. The passivation layer 128 may be or include, for example, silicon nitride, aluminum oxide, another suitable dielectric(s), or any combination of the foregoing.As illustrated by cross-sectional view 1600 of FIG. 16, the passivation layer 128, the semiconductor layer 108, and the ILD layer 124 are patterned to form contact openings 1602. The contact openings 1602 are individual to the pads 118 and expose the pads 118, respectively. In some embodiments, the contact openings 1602 have the same upper layout as the contacts 130 in FIGS. 2 and / or 6. The patterning may include, for example: 1) forming a mask 1604 over the passivation layer 128; 2) etching the passivation layer 128, the semiconductor layer 108, and the ILD layer 124, wherein the mask 1604 is arranged to form the contact openings 1602; 3) and removing the mask 1604. However, other suitable processes for patterning are possible. The mask 1604 may be, for example, a photoresist mask formed by photolithography or another suitable type of mask. The etching may be performed by dry etching, for example, but other suitable types of etching are possible.As illustrated by cross-sectional view 1700 of FIG. 17, contact liner layers 132 are formed lining sidewalls of contact openings 1602. The contact liner layers 132 are individual to the contact openings 1602 and are disposed on sidewalls of the respective contact openings 1602. The contact liner layers 132 are dielectric and may be or include, for example, silicon oxide and / or another suitable dielectric(s). A process for forming the contact liner layers 132 may include, for example: 1) depositing a dielectric layer covering the passivation layer 128 and lining the contact openings 1602; and 2) etching back the dielectric layer to remove the dielectric layer from the top surface of the passivation layer 128 and divide the dielectric layer into the contact liner layers 132. However, other suitable processes are possible.As also illustrated by cross-sectional view 1700 of FIG. 17, conductive layer 1702 is deposited over passivation layer 128 and contact liner layers 132 and further lines contact openings 1602. The conductive layer 1702 directly contacts and is electrically coupled to the pads 118 and may be, or include, for example, copper, aluminum copper, aluminum, other suitable conductive material(s), or any combination of the foregoing.As illustrated by cross-sectional view 1800 of FIG. 18, conductive layer 1702 is patterned to form contacts 130 individually electrically coupled to and for pads 118, respectively. The patterning may include, for example: 1) forming a mask 1802 over the conductive layer 1702; 2) etching the conductive layer 1702, the mask 1802 arranged to form the contacts 130; 3) and removing the mask 1802. However, other suitable processes for patterning are possible. The mask 1802 may be, for example, a photoresist mask formed by photolithography or another suitable type of mask. The etching may be performed by dry etching, for example, but other suitable types of etching are possible.During operation of the semiconductor device 102, capacitive coupling between the source / drain pads 118 s / d and the second semiconductor substrate 106 may decrease substrate resistance, increase substrate power loss, and decrease PAE. However, due to the cavity 104, the negative effects of this capacitive coupling may be mitigated.The cavity 104 is electrically insulating and thus serves as a dielectric region separating the second semiconductor substrate 106 from the IMD layer 122 and the source / drain pads 118 in s / d fashion. Thus, the source / drain capacitance at each of the source / drain pads 118 s / d may be modeled as two capacitors, respectively, that are electrically coupled in series and located in the IMD layer 122 and the cavity 104, respectively. For clarity, the capacitors on the IMD layer 122 and cavity 104 are labeled C IMD and C CAV respectively. Multiple capacitors in series provide a smaller capacitance than the capacitances of the individual capacitors, so that the cavity 104 may reduce the source / drain capacitances compared to the source / drain capacitances without the cavity 104. For example, a source / drain capacitance may be the same. Thus, assuming that the IMD capacitors C IMD and the cavity capacitors C CAV are 1 microfarad and 0.25 microfarads, respectively, a source / drain capacitance may achieve an 80% reduction (e.g.,). It should be noted that these capacitances are non-limiting examples and other capacitances are possible. Since the source / drain capacitances can be reduced by the cavity 104, a substrate capacitance can be reduced and, therefore, the substrate resistance can be increased. Since the substrate resistance can be increased, a substrate power loss can be reduced. This, in turn, may increase the PAE of the semiconductor device 102. The PAE is an important parameter for, among other things, 5G mobile communication and other suitable RF applications.As described above, the cavity 104 may be considered a dielectric region. In some embodiments, a dielectric constant of the cavity 104 is less than that of the IMD layer 122. The lower the dielectric constant, the lower the capacitances of the cavity capacitors CCAV and the more significant the reduction of the source / drain capacitances.To further improve the PAE of the semiconductor device 102, the cavity 104 is recessed into the second semiconductor substrate 106, and in some embodiments, the second semiconductor substrate 106 has a high resistance. The high resistance of the second semiconductor substrate 106 increases the substrate resistance and thus reduces substrate power loss. This in turn increases the PAE. Letting the cavity 104 into the second semiconductor substrate 106 increases a length of an interface 126 between the semiconductor substrate 106 and the IMD layer 122, and between the semiconductor substrate 106 and the cavity 104. This increases an interfacial resistance from a drain side of the semiconductor device 102 to a source side of the semiconductor device 102, which increases the substrate resistance and thus reduces a substrate power loss. This in turn increases the PAE.Although FIGS. 9, 10, 11A, 11B, and 12 to 18 are described with reference to a method, it is understood that the structures illustrated in FIGS. 9, 10, 11A, 11B, and 12 to 18 are not limited to the method, but rather may be separate from the method independently. Although FIGS. 9, 10, 11A, 11B, and 12 to 18 are described as a series of operations, it should be understood that the order of the operations may be changed in other embodiments. Although FIGS. 9, 10, 11A, 11B, and 12 through 18 show and describe a specific set of operations, some illustrated and / or described operations may be omitted in other embodiments. Additionally, operations not shown and / or described may be incorporated in other embodiments.Referring to FIG. 19, a block diagram 1900 of some embodiments of the method of FIGS. 9, 10, 11A, 11B, and 12 through 18 is provided.At 1902, a semiconductor layer is deposited over a first semiconductor substrate. See, for example, FIG. 9, in some embodiments, semiconductor layer 108 is a group III-V semiconductor layer, a group II-VI semiconductor layer, a group IV-IV semiconductor layer, or another suitable type of semiconductor layer. In some embodiments, the semiconductor layer is made of multiple different layers.At 1904, a semiconductor device is formed on the semiconductor layer. See, for example, FIG. 9, the semiconductor device may be, for example, a HEMT, a MOSFET, or another suitable type of semiconductor device.At 1906, an interconnect structure is formed over the semiconductor device and the semiconductor layer, the interconnect structure including pads electrically coupled to electrodes of the semiconductor device. See, for example, Fig. 10.At 1908 a second semiconductor substrate is patterned to form a cavity in the second semiconductor substrate. See, for example, FIGS. 11A and 11B. In some embodiments, the second semiconductor substrate has a higher resistance than the first semiconductor substrate.At 1910, the second semiconductor substrate is bonded to the interconnect structure such that the cavity above the semiconductor device is between the interconnect structure and the second semiconductor substrate. See, for example, Fig. 12.At 1912, the first semiconductor substrate is removed. See, for example, Figs. 13 and 14.At 1914, a passivation layer is deposited over the semiconductor layer. See, for example, Fig. 15.At 1916, the passivation layer and the semiconductor layer are patterned to form contact openings exposing the pads. See, for example, Fig. 16.At 1918, contacts are formed in the contact openings. See, for example, Figs. 17 and 18.Although the block diagram 1900 of FIG. 19 is illustrated and described herein as a series of acts or events, it should be understood that the illustrated order of such acts or events is not to be interpreted in a limiting sense. In addition to those illustrated and / or described herein, for example, some operations may occur in different orders and / or concurrently with other operations or events. In addition, operations not shown may be required to implement one or more aspects or embodiments of the specification, and one or more of the operations shown herein may be performed in one or more separate operations and / or phases.Referring to FIGS. 20A, 20B, and 21-28, a series of cross-sectional views 2000A, 2000B, 2100-2800 of some alternative embodiments of the method of FIGS. 9, 10, 11A, 11B, and 12-18 are provided in which the at least one cavity is filled with a high-space filling dielectric layer. The method may be used, for example, to form the IC chip of FIG. 4A, IC chip of FIG. 7A, or another suitable IC chip.As illustrated by cross-sectional view 2000A of FIG. 20A, a second semiconductor substrate 106 is patterned to form a cavity 104, as described above with reference to FIG. 11A. In addition, a cavity filling dielectric layer 402 is deposited, covering the second semiconductor substrate 106 and filling the cavity 104.In some embodiments, the cavity-filling dielectric layer 402 is or includes a dielectric oxide and / or other suitable dielectric(s). In some embodiments, the cavity filling dielectric layer 402 is a low-k dielectric material or an extreme low-k dielectric material. A low-k dielectric material may be, for example, a dielectric material having a dielectric constant of about 2 to 3.9, or another suitable value. An extreme low-k dielectric material may be, for example, a dielectric material having a dielectric constant less than about 2 or another suitable value. In some embodiments, the cavity filling dielectric layer 402 has a lower dielectric constant than an IMD layer to which the second semiconductor substrate 106 is subsequently bonded.Alternatively, as illustrated by cross-sectional view 2000B of FIG. 20B, the second semiconductor substrate 106 is patterned to form a plurality of small voids 104 s, as described with reference to FIG. 11B. In addition, the cavity filling dielectric layer 402 is deposited, covering the second semiconductor substrate 106 and filling the small cavities 104 s.As illustrated by cross-sectional view 2100 of FIG. 21, planarization is performed on the cavity-filling dielectric layer 402 to remove the cavity-filling dielectric layer 402 from above a top surface of the second semiconductor substrate 106. As mentioned above, FIGS. 20A and 20B are alternatives to each other. FIG. 21 shows the method continuing from FIG. 20A while skipping FIG. 20B, and therefore FIGS. 21, 22, 23, 24, 25, 26, 27 to 28 use embodiments of the second semiconductor substrate 106 in FIG. 20A. In alternative embodiments, the method of FIG. 20B continues while skipping FIG. 20A, and thus FIGS. 21, 22, 23, 24, 25, 26, 27-28 use embodiments of the second semiconductor substrate 106 in FIG. 20B. Planarization may be performed by, for example, a CMP or other suitable planarization process.As illustrated by the cross-sectional view 2200 of FIG. 22, the operations of FIGS. 9 and 10 are performed. A semiconductor layer 108 is epitaxially deposited over a first semiconductor substrate 902, and a semiconductor device 102 is formed on the semiconductor layer 108, as described with reference to FIG. 9. An interconnect structure 110 is formed over and electrically coupled to the semiconductor device 102, as described with reference to FIG. 10.As also illustrated by cross-sectional view 2200 of FIG. 22, the structure of FIG. 21 is vertically inverted and is disposed over and bonded to interconnect structure 110. Due to the presence of the cavity filling dielectric layer 402, a bonding area between the structure of FIG. 21 and the interconnect structure 110 is large. If the cavity filling dielectric layer 402 were omitted, the bonding area would be small. Due to the large bonding area, the bonding strength is strong and the likelihood of mechanical failure along the bonding area is low. Bonding may be performed, for example, by fusion bonding or another suitable type of bonding.As illustrated by the cross-sectional views 2300- 2800 of FIGS. 23, 24, 25, 26, 27- 28, the operations are performed in FIGS. 13, 14, 15, 16, 17- 18. In FIG. 23, the structure of FIG. 22 is vertically reversed and the first semiconductor substrate 902 is thinned as described with reference to FIG. 13. In FIG. 24, a residue of the first semiconductor substrate 902 is removed as described with reference to FIG. 14. In FIG. 25, a passivation layer 128 is deposited over the semiconductor layer 108, as described with reference to FIG. 15. In FIG. 26, the passivation layer 128, the semiconductor layer 108, and the ILD layer 124 are patterned to form contact openings 1602, as described with reference to FIG. 16. In FIG. 27, contact liner layers 132 are formed lining sidewalls of the contact openings 1602, and a conductive layer 1702 lining the contact openings 1602 is deposited as described with reference to FIG. 17. In FIG. 28, the conductive layer 1702 is patterned to form contacts 130 in the contact openings 1602, as described with reference to FIG. 18.Although FIGS. 20A, 20B, and 21 to 28 are described with reference to a method, it is understood that the structures illustrated in FIGS. 20A, 20B, and 21 to 28 are not limited to the method, but rather may be separate from the method independently. Although FIGS. 20A, 20B, and 21 to 28 are described as a series of operations, it should be understood that the order of the operations may be changed in other embodiments. Although FIGS. 20A, 20B, and 21- 28 show and describe a specific set of operations, some illustrated and / or described operations may be omitted in other embodiments. Additionally, operations not shown and / or described may be incorporated in other embodiments.Referring to FIG. 29, a block diagram 2900 of some embodiments of the method of FIGS. 20A, 20B, and 21-28 is provided.At 1902, a semiconductor layer is deposited over a first semiconductor substrate. See, for example, Fig. 22.At 1904, a semiconductor device is formed on the semiconductor layer. See, for example, Fig. 22.At 1906, an interconnect structure is formed over the semiconductor device and the semiconductor layer, the interconnect structure including pads electrically coupled to electrodes of the semiconductor device. See, for example, Fig. 22.At 1908 a second semiconductor substrate is patterned to form a cavity in the second semiconductor substrate. See, for example, FIGS. 20A and 20B.At 2902, a dielectric layer is deposited filling the cavity. See, for example, FIGS. 20A and 20B.At 2904, planarization of the dielectric layer is performed to remove the dielectric layer from above a top surface of the second semiconductor substrate. See, for example, Fig. 21.At 1910, the second semiconductor substrate is bonded to the interconnect structure such that the cavity above the semiconductor device is between the interconnect structure and the second semiconductor substrate. See, for example, Fig. 22.At 1912, the first semiconductor substrate is removed. See, for example, Figs. 23 and 24.At 1914, a passivation layer is deposited over the semiconductor layer. See, for example, Fig. 25.At 1916, the passivation layer and the semiconductor layer are patterned to form contact openings exposing the pads. See, for example, Fig. 26.At 1918, contacts are formed in the contact openings. See, for example, Figs. 27 and 28.Although the block diagram 2900 of FIG. 29 is illustrated and described herein as a series of acts or events, it should be understood that the illustrated order of such acts or events is not to be interpreted in a limiting sense. In addition to those illustrated and / or described herein, for example, some operations may occur in different orders and / or concurrently with other operations or events. In addition, operations not shown may be required to implement one or more aspects or embodiments of the specification, and one or more of the operations shown herein may be performed in one or more separate operations and / or phases.Referring to FIGS. 30, 31A, 31B, and 32 to 38, a series of cross-sectional views 3000, 3100A, 3100B, 3200 to 3800, of some alternative embodiments of the method of FIGS. 9, 10, 11A, 11B, and 12 to 18 are presented in which the at least one cavity is filled with a high-space filling dielectric layer. The method may be used, for example, to form the IC chip of FIG. 4B, IC chip of FIG. 7B, or another suitable IC chip.As illustrated by cross-sectional view 3000 of FIG. 30, a second semiconductor substrate 106 is patterned to form a cavity 104 extending into a second semiconductor substrate 106 to a first depth D 1. Due to the patterning, the second semiconductor substrate 106 has a first thickness T 1 at a portion underlying the cavity 104, and further has a second thickness T 2, which is greater than the first thickness T 1, at portions laterally offset from the cavity 104. The second semiconductor substrate 106, the cavity 104 and the patterning may be, for example, as described with reference to FIG. 11A.As illustrated by cross-sectional view 3100A of FIG. 31A, the second semiconductor substrate 106 is further patterned to form recesses 3102 at a bottom of the cavity 104 and thus extend the cavity 104 to a second depth D 2, which is greater than the first depth D 1, at the recesses 3102. In some embodiments, the recesses 302 are evenly spaced from a first side of the cavity 104 to a second side of the cavity 104 opposite the first side.By forming the recesses 3102, the second semiconductor substrate 106 switches between the first thickness T 1 and a third thickness T 3, which is smaller than the first thickness T 1, from the first side to the second side. In addition, the cavity 104 changes between the first depth D 1 and the second depth D 2 from the first side to the second side, and thus has an uneven lower profile. This increases the length of a substrate interface (e.g., 126 in FIG. 38 ), which increases the interface resistance and substrate resistance. This reduces substrate power loss and increases PAE.The patterning may include, for example: 1) forming a mask 3104 over the second semiconductor substrate 106; 2) etching the second semiconductor substrate 106, the mask 3104 being arranged to form the recesses 3102; 3) and removing the mask 3104. However, other suitable processes for patterning are possible. The mask 3104 may be, for example, a photoresist mask formed by photolithography or another suitable type of mask. The etching may be performed by dry etching, for example, but other suitable types of etching are possible.Alternatively, as illustrated by cross-sectional view 3100B of FIG. 31B, the second semiconductor substrate 106 includes a plurality of small cavities 104 sthat extend into a second semiconductor substrate 106 at the first depth D 1. The small cavities 104 smay be, for example, as described with reference to FIG. 1B. In addition, the second semiconductor substrate 106 is patterned to form recesses 3102 at a bottom of each small cavity 104 s, and therefore to extend each small cavity 104 sto the second depth D 2, which is larger than the first depth D 1.As illustrated by the cross-sectional view 3200 of FIG. 32, the operations of FIGS. 9 and 10 are performed. A semiconductor layer 108 is epitaxially deposited over the first semiconductor substrate 902, and a semiconductor device 102 is formed on the semiconductor layer 108, as described with reference to FIG. 9. An interconnect structure 110 is formed over and electrically coupled to the semiconductor device 102, as described with reference to FIG. 10.As also illustrated by cross-sectional view 3200 of FIG. 32, the structure of FIG. 31A is vertically inverted and is disposed over and bonded to the interconnect structure 110. As mentioned above, FIGS. 31A and 31B are alternatives to each other. FIG. 32 shows the method continuing from FIG. 31A while skipping FIG. 31B, and therefore FIGS. 32, 33, 34, 35, 36, 37 to 38 use embodiments of the second semiconductor substrate 106 in FIG. 31A. In alternative embodiments, the method continues from FIG. 31B while skipping FIG. 31A, and thus FIGS. 32, 33, 34, 35, 36, 37-38 use embodiments of the second semiconductor substrate 106 in FIG. 31B.As illustrated by the cross-sectional views 3300- 3800, of FIGS. 33, 34, 35, 36, 37- 38, the operations are performed in FIGS. 13, 14, 15, 16, 17- 18. In FIG. 33, the structure of FIG. 32 is vertically reversed and the first semiconductor substrate 902 is thinned as described with reference to FIG. 13. In FIG. 34, a residue of the first semiconductor substrate 902 is removed as described with reference to FIG. 14. In FIG. 35, a passivation layer 128 is deposited over the semiconductor layer 108, as described with reference to FIG. 15. In FIG. 36, the passivation layer 128, the semiconductor layer 108, and the ILD layer 124 are patterned to form contact openings 1602, as described with reference to FIG. 16. In FIG. 37, contact liner layers 132 are formed lining sidewalls of the contact openings 1602, and a conductive layer 1702 lining the contact openings 1602 is deposited as described with reference to FIG. 17. In FIG. 39, the conductive layer 1702 is patterned to form contacts 130 in the contact openings 1602, as described with reference to FIG. 18.Although FIGS. 30, 31A, 31B, and 32 to 38 are described with reference to a method, it is understood that the structures illustrated in FIGS. 30, 31A, 31B, and 32 to 38 are not limited to the method, but rather may be separate from the method independently. Although FIGS. 30, 31A, 31B, and 32 through 38 are described as a series of operations, it should be understood that the order of the operations may be changed in other embodiments. Although FIGS. 31A, 31B, and 32- 38 show and describe a specific set of operations, some illustrated and / or described operations may be omitted in other embodiments. Additionally, operations not shown and / or described may be incorporated in other embodiments.Referring to FIG. 39, a block diagram 3900 of some embodiments of the method of FIGS. 30, 31A, 31B, and 32- 38 is provided.At 1902, a semiconductor layer is deposited over a first semiconductor substrate. See, for example, Fig. 32.At 1904, a semiconductor device is formed on the semiconductor layer. See, for example, Fig. 32.At 1906, an interconnect structure is formed over the semiconductor device and the semiconductor layer, the interconnect structure including pads electrically coupled to electrodes of the semiconductor device. See, for example, Fig. 32.At 1908 a, a second semiconductor substrate is patterned to form a cavity extending into the second substrate to a first depth. See, for example, Fig. 30.At 1908 b, the second substrate is patterned to form recesses on a bottom of the cavity that extend into the second semiconductor substrate to a second depth greater than the first depth. See, for example, FIGS. 31A and 31B.At 1910, the second semiconductor substrate is bonded to the interconnect structure such that the cavity above the semiconductor device is between the interconnect structure and the second semiconductor substrate. See, for example, Fig. 32.At 1912, the first semiconductor substrate is removed. See, for example, Figs. 33 and 34.At 1914, a passivation layer is deposited over the semiconductor layer. See, for example, Fig. 35.At 1916, the passivation layer and the semiconductor layer are patterned to form contact openings exposing the pads. See, for example, Fig. 36.At 1918, contacts are formed in the contact openings. See, for example, Figs. 37 and 38.Although the block diagram 3900 of FIG. 39 is illustrated and described herein as a series of acts or events, it should be understood that the illustrated order of such acts or events is not to be interpreted in a limiting sense. In addition to those illustrated and / or described herein, for example, some operations may occur in different orders and / or concurrently with other operations or events. In addition, operations not shown may be required to implement one or more aspects or embodiments of the specification, and one or more of the operations shown herein may be performed in one or more separate operations and / or phases.Referring to FIGS. 40A, 40B, and 41-48, a series of cross-sectional views 4000A, 4000B, 4100-4800 of some alternative embodiments of the method of FIGS. 30, 31A, 31B, and 32-38 are provided in which the at least one cavity is filled with a high-space filling dielectric layer. The method may be used, for example, to form the IC chip of FIG. 4C, IC chip of FIG. 7C, or another suitable IC chip.As illustrated by cross-sectional view 4000A of FIG. 40A, a second semiconductor substrate 106 is patterned to form a cavity 104, as described above with reference to FIGS. 30 and 31A. In addition, a cavity filling dielectric layer 402 is deposited, covering the second semiconductor substrate 106 and filling the cavity 104. The cavity filling dielectric layer may be, for example, as described with reference to FIGS. 20A and 20B.Alternatively, as illustrated by cross-sectional view 4000B of FIG. 40B, the second semiconductor substrate 106 is patterned to form a plurality of small voids 104 s, as described with reference to FIG. 31B. In addition, the cavity filling dielectric layer 402 is deposited, covering the second semiconductor substrate 106 and filling the small cavities 1045.As illustrated by cross-sectional view 4100 of FIG. 41, planarization is performed on the cavity-filling dielectric layer 402 to remove the cavity-filling dielectric layer 402 from above a top surface of the second semiconductor substrate 106. As mentioned above, FIGS. 40A and 40B are alternatives to each other. FIG. 41 shows the method continuing from FIG. 40A while skipping FIG. 40B, and therefore FIGS. 41, 42, 43, 44, 45, 46, 47 to 48 use embodiments of the second semiconductor substrate 106 in FIG. 40A. In alternative embodiments, the method of FIG. 40B continues while skipping FIG. 40A, and thus FIGS. 41, 42, 43, 44, 45, 46, 47-48 use embodiments of the second semiconductor substrate 106 in FIG. 40B. Planarization may be performed by, for example, a CMP or other suitable planarization process.As illustrated by the cross-sectional view 4200 of FIG. 42, the operations of FIGS. 9 and 10 are performed. A semiconductor layer 108 is epitaxially deposited over a first semiconductor substrate 902, and a semiconductor device 102 is formed on the semiconductor layer 108, as described with reference to FIG. 9. An interconnect structure 110 is formed over and electrically coupled to the semiconductor device 102, as described with reference to FIG. 10.As also illustrated by cross-sectional view 4200 of FIG. 42, the structure of FIG. 41 is vertically inverted and is disposed over and bonded to interconnect structure 110. Due to the presence of the cavity filling dielectric layer 402, a bonding area between the structure of FIG. 41 and the interconnect structure 110 is large. If the cavity filling dielectric layer 402 were omitted, the bonding area would be small. Due to the large bonding area, the bonding strength is strong. Bonding may be performed, for example, by fusion bonding or another suitable type of bonding.As illustrated by the cross-sectional views 4300-4800 of FIGS. 43, 44, 45, 46, 47-48, the operations in FIGS. 13, 14, 15, 16, 17-18 are performed. In FIG. 43, the structure of FIG. 42 is vertically reversed and the first semiconductor substrate 902 is thinned as described with reference to FIG. 13. In FIG. 44, a residue of the first semiconductor substrate 902 is removed as described with reference to FIG. 14. In FIG. 45, a passivation layer 128 is deposited over the semiconductor layer 108, as described with reference to FIG. 15. In FIG. 46, the passivation layer 128, the semiconductor layer 108, and the ILD layer 124 are patterned to form contact openings 1602, as described with reference to FIG. 16. In FIG. 47, contact liner layers 132 are formed lining sidewalls of the contact openings 1602, and a conductive layer 1702 lining the contact openings 1602 is deposited as described with reference to FIG. 17. In FIG. 48, the conductive layer 1702 is patterned to form contacts 130 in the contact openings 1602, as described with reference to FIG. 18.Although FIGS. 40A, 40B to 41 to 48 are described with reference to a method, it is understood that the structures illustrated in FIGS. 40A, 40B, and 41 to 48 are not limited to the method, but rather may be separate from the method independently. Although FIGS. 40A, 40B, and 41- 48 are described as a series of operations, it should be understood that the order of the operations may be changed in other embodiments. Although FIGS. 40A, 40B, and 41- 48 show and describe a specific set of operations, some illustrated and / or described operations may be omitted in other embodiments. Additionally, operations not shown and / or described may be incorporated in other embodiments.Referring to FIG. 49, a block diagram 4900 of some embodiments of the method of FIGS. 40A, 40B, and 41-48 is provided.At 1902, a semiconductor layer is deposited over a first semiconductor substrate. See, for example, Fig. 42.At 1904, a semiconductor device is formed on the semiconductor layer. See, for example, Fig. 42.At 1906, an interconnect structure is formed over the semiconductor device and the semiconductor layer, the interconnect structure including pads electrically coupled to electrodes of the semiconductor device. See, for example, Fig. 42.At 1908 a, a second semiconductor substrate is patterned to form a cavity extending into the second substrate to a first depth. See, for example, FIGS. 30, 40A, and 40B.At 1908 b, the second substrate is patterned to form recesses on a bottom of the cavity that extend into the second substrate to a second depth greater than the first depth. See, for example, FIGS. 31A, 31B, 40A, and 40B.At 2902, a dielectric layer is deposited filling the cavity. See, for example, FIGS. 40A and 40B.At 2904, planarization of the dielectric layer is performed to remove the dielectric layer from above the second semiconductor substrate. See, for example, Fig. 41.At 1910, the second semiconductor substrate is bonded to the interconnect structure such that the cavity above the semiconductor device is between the interconnect structure and the second semiconductor substrate. See, for example, Fig. 42.At 1912, the first semiconductor substrate is removed. See, for example, Figs. 43 and 44.At 1914, a passivation layer is deposited over the semiconductor layer. See, for example, Fig. 45.At 1916, the passivation layer and the semiconductor layer are patterned to form contact openings exposing the pads. See, for example, Fig. 46.At 1918, contacts are formed in the contact openings. See, for example, Figs. 47 and 48.Although the block diagram 4900 of FIG. 49 is illustrated and described herein as a series of acts or events, it should be understood that the illustrated order of such acts or events is not to be interpreted in a limiting sense. In addition to those illustrated and / or described herein, for example, some operations may occur in different orders and / or concurrently with other operations or events. In addition, operations not shown may be required to implement one or more aspects or embodiments of the specification, and one or more of the operations shown herein may be performed in one or more separate operations and / or phases.

Claims

AN IC chip comprising: a semiconductor substrate (106); a first dielectric region recessed in a top surface of the semiconductor substrate (106); an IMD layer overlying the semiconductor substrate (106) and the first dielectric region, the IMD layer bonded to the top surface of the semiconductor substrate (106); a semiconductor layer (108) overlying the IMD layer (122); a semiconductor device (102) inverted and located in the semiconductor layer (108) between the semiconductor layer (108) and the IMD layer (122), the semiconductor device (102) having a first source / drain electrode (114) overlying the first dielectric region; a first pad (118) in the IMD layer (122) overlying the first dielectric region, the first pad (118) electrically coupled to the first source / drain electrode (114), and a via (120) from the first pad (118) to the first source / drain electrode (114).The IC chip of claim 1, wherein the first dielectric region is a cavity (104).The IC chip of claim 1 or 2, wherein the first dielectric region is a dielectric layer (402).The IC chip of any preceding claim, wherein the first dielectric region has a lower dielectric constant than the IMD layer (122).The IC chip of any preceding claim, wherein a lower profile of the first dielectric region is uneven.The IC chip of any preceding claim, wherein the semiconductor device (102) includes a second source / drain electrode (114) on a side of the semiconductor device (102) opposite the first source / drain electrode (114), and wherein the first dielectric region is continuous and underlying both the first and second source drain electrodes (114).The IC chip of any preceding claim, wherein the semiconductor device (102) includes a second source / drain electrode (114) on a side of the semiconductor device (102) opposite the first source / drain electrode (114), and wherein the IC chip further includes: a second dielectric region recessed in the top surface of the semiconductor substrate (106) independent of the first dielectric region and underlying the second source / drain electrode (114).AN IC chip comprising: a semiconductor substrate (106); a semiconductor layer (108) overlying the semiconductor substrate (106); a semiconductor device (102) on a lower side of the semiconductor layer (108), between the semiconductor layer (108) and the semiconductor substrate (106); and an interconnect structure (110) between the semiconductor device (102) and the semiconductor substrate (106), wherein the interconnect structure (110) is electrically coupled to the semiconductor device (102), wherein the semiconductor substrate (106) has a first thickness and a second thickness that is greater than the first thickness, and wherein the semiconductor device (102) overlies a first portion of the semiconductor substrate (106) where the semiconductor substrate (106) has the first thickness; and wherein the interconnect structure (110) comprises a plurality of levels of conductive elements comprising a level closest to the semiconductor substrate (106), wherein the level closest to the semiconductor substrate (106) comprises a pad (118) electrically coupled to a source / drain electrode (114) of the semiconductor device (102), and wherein the pad (118) is below the source / drain electrode (114) and above the first portion of the semiconductor substrate (106).The IC chip of claim 8, wherein the semiconductor substrate (106) further has a third thickness that is less than the first thickness, and wherein the semiconductor substrate (106) switches between the first and third thicknesses directly below the semiconductor device (102).The IC chip of claim 8 or 9, wherein the semiconductor device (102) includes a first source / drain electrode (114) and a second source / drain electrode (114), and wherein the first portion of the semiconductor substrate (106) is continuous from directly below the first source / drain electrode (114) to directly below the second source / drain electrode (114).The IC chip of claim 8 or 9, wherein the semiconductor device (102) includes a first source / drain electrode (114) and a second source / drain electrode (114), wherein the first portion of the semiconductor substrate (106) is below the first source / drain electrode (114), wherein the semiconductor substrate (106) further includes a second portion having the first thickness, and wherein the second portion is spaced apart from the first portion and is below the second source / drain electrode (114).The IC chip of any of claims 8 to 11, wherein the semiconductor substrate (106) and the interconnect structure (110) define individual areas of a cavity (104) recessed in a top surface of the semiconductor substrate (106) at the first portion of the semiconductor substrate (106).A method of forming an IC chip, the method comprising: depositing a semiconductor layer (108) over a first semiconductor substrate (902); forming a semiconductor device (102) over the semiconductor layer (108); forming an interconnect structure (110) over and electrically coupled to the semiconductor device (102); patterning a second semiconductor substrate (106) to form a first cavity in the second semiconductor substrate (106); bonding the second semiconductor substrate (106) to the interconnect structure (110) such that the first cavity overlies the semiconductor device (102); and removing the first semiconductor substrate (902); wherein the interconnect structure (110) has pads (118), the pads (118) being located at a top surface of the interconnect structure (110), wherein a first pad is electrically coupled to a first source / drain electrode (114) of the semiconductor device (102), wherein the first pad (118) lies below the first source / drain electrode (114) and above the first cavity in the second semiconductor substrate (106), and wherein the method further comprises: forming contacts extending through the semiconductor layer (108) to the pads (118), respectively.The method of claim 13, wherein the second semiconductor substrate (106) has a higher resistance than the first semiconductor substrate (902).The method of claim 13 or 14, wherein the patterning further forms a second cavity in the second semiconductor substrate (106), wherein the semiconductor device (102) includes a pair of source / drain electrodes (114), and wherein the bonding is such that the first cavity and the second cavity are over the source / drain electrodes (114), respectively.The method of any of claims 13 to 15, further comprising: depositing a cavity-filling dielectric layer (402) covering a top surface of the second semiconductor substrate and filling the first cavity; and performing planarization of the cavity-filling dielectric layer (402) to remove the cavity-filling dielectric layer (402) from the top surface of the second semiconductor substrate (106).The method of any of claims 13 to 16, further comprising: patterning the second semiconductor substrate (106) to form recesses on a bottom surface of the first cavity after patterning to form and independent of the first cavity.

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