Three-dimensional semiconductor memory device

Abstract

Semiconductor memory device, comprising: a substrate (SUB) containing a cell region (CAR) and a connection region (CNR); an electrode structure (ST) arranged on the substrate (SUB), the electrode structure (ST) having a step structure on the connection region (CNR); a first vertical channel structure (VS1) which at least partially penetrates the electrode structure (ST) on the cell region (CAR); and a first dummy structure (DS1) which at least partially penetrates the electrode structure on the connection region, wherein the electrode structure (ST) comprises: a first electrode structure (ST1) including a plurality of first electrodes (EL1) stacked on the substrate (SUB); and a second electrode structure (ST2) including a plurality of second electrodes (EL2) stacked on the first electrode structure (ST1), where both the first vertical channel structure (VS1) and the first dummy structure (DS1) have: a first vertically extended portion (VEP1) at least partially penetrating the first electrode structure (ST1); a second vertically extended portion (VEP2) at least partially penetrating the second electrode structure (ST2); and an extended section (EXP1, EXP3) arranged between the first and second vertically extended sections, wherein a first height in the direction of the second electrode structure (ST2) from a top surface of an uppermost one of the plurality of first electrodes (EL1) to a bottom of the extended section (EXP1) of the first vertical channel structure (VS1) is smaller than a second height in the direction of the second electrode structure (ST2) from the top surface of the uppermost one of the plurality of first electrodes (EL1) to a bottom of the extended section (EXP3) of the first dummy structure (DS1), further comprising a second dummy structure (DS2) which at least partially penetrates the electrode structure (ST) on the connection region (CNR), wherein a distance between the second dummy structure (DS2) and the cell area (CAR) is greater than a distance between the first dummy structure (DS1) and the cell area (CAR), and wherein a third height in the direction of the second electrode structure (ST2) from the top surface of the uppermost one of the plurality of first electrodes (EL1) to a bottom of an extended portion (EXP4) of the second dummy structure (DS2) is greater than the second height.

Description

Technical field

[0001] The present disclosure relates to a semiconductor device and, more particularly, to a three-dimensional semiconductor memory device. Description of related technology

[0002] Higher integration in semiconductor devices can be used to meet consumer demands for superior performance and cost-effective pricing. In conventional semiconductor devices, which can be referred to as two-dimensional or planar semiconductor devices because their size is mainly determined by the area occupied by a unit memory cell, integration is greatly influenced by how finely the patterns are formed. However, the cost of the equipment required to increase pattern fineness places practical limitations on increasing integration for two-dimensional or planar semiconductor devices. To overcome such a limitation, semiconductor devices, such as semiconductor memory devices, can be fabricated to include a stacked structure in which circuit components can be arranged in three dimensions.These semiconductor devices can be referred to as three-dimensional semiconductor devices. Three-dimensional semiconductor memory devices can thus include memory cells arranged in a stacked structure extending in three dimensions.

[0003] US 2011 / 0 312 174 A1 discloses methods for manufacturing three-dimensional semiconductor devices, which may comprise: forming a first spacer on a sidewall within a first opening formed in a first stack structure, forming a sacrificial fill pattern on the spacer to fill the first opening, forming a second stack structure comprising: a second opening exposing the sacrificial fill pattern on the first stack structure, forming a second spacer on a sidewall within the second opening, removing the sacrificial fill pattern, and removing the first spacer and the second spacer.

[0004] US 9,576,967 B1 discloses memory openings and support openings formed by an alternating stack of insulating layers and spacer material layers over a semiconductor substrate. The deposition of a semiconductor material in the support openings during the formation of epitaxial channel portions in the memory openings is prevented by converting portions of the semiconductor substrate underlying the support openings into impurity-doped semiconductor material portions. During the selective growth of epitaxial channel portions from the semiconductor substrate within the memory openings, the growth of a semiconductor material in the support openings is suppressed due to the impurity species in the impurity-doped semiconductor material portions. Subsequently, memory stack structures and support column structures are formed over the epitaxial channel portions and in the support openings, respectively.The support column structures are formed with an outermost dielectric layer to prevent a leakage path to subsequently formed electrically conductive layers.

[0005] US 2017 / 0 179 026 A1 discloses a three-dimensional NAND memory device comprising wordline driver devices arranged on or above a substrate, an alternating stack of wordlines and insulating layers arranged above the wordline driver devices, a plurality of memory stack structures extending through the alternating stack, each memory stack structure comprising a memory film and a vertical semiconductor channel, and memory-level via structures electrically coupling the wordlines in a first memory block to the wordline driver devices. The memory-level via structures extend through a memory-level via region located between a staircase region of the first memory block and a staircase region of another memory block.

[0006] WO 2019 / 160593 A1 discloses a contact feedthrough structure provided in a staircase region with stepped surfaces, extending vertically through an alternating stack of insulating layers and electrically conductive layers. The contact feedthrough structure is electrically insulated from each electrically conductive layer of the alternating stack, with the exception of an electrically conductive layer located directly beneath a horizontal interface of the stepped surfaces. A laterally projecting portion of the contact feedthrough structure contacts an annular upper surface of the electrically conductive layer. Electrical insulation may be provided by a ribbed insulating spacer having laterally projecting annular rib portions at the level of the insulating layers, or may be provided by annular insulating spacers arranged at the level of the electrically conductive layers.The via structure may contact a top surface of an underlying metallic interconnect structure overlying a substrate to provide an electrically conductive path.

[0007] US 2017 / 0 352 678 A1 discloses lower-level metallic interconnect structures formed over a substrate having semiconductor devices thereon. A layer of semiconductor material and an alternating stack of spacer dielectric layers and insulating layers are formed over the lower-level metallic interconnect structures. The alternating stack forms an array of memory stack structures. The alternating stack forms trenches such that a stair-step region is located farther from a lateral threshold distance from the trenches, while adjacent stair-step regions are formed within the lateral threshold distance from the trenches. Portions of the spacer dielectric layers near the trenches are replaced by electrically conductive layers, while a remaining portion of the alternating stack is present in the stair-step region.The remaining portions of the spacer dielectric layers and the insulating layers may form at least one via structure through the memory level to provide a vertical conductive path through a memory level assembly. Summary

[0008] According to one embodiment of the inventive concept, a semiconductor memory device includes a substrate including a cell region and an interconnection region, an electrode structure arranged on the substrate, the electrode structure having a staircase structure on the interconnection region, a first vertical channel structure at least partially penetrating the electrode structure on the cell region, and a first dummy structure at least partially penetrating the electrode structure on the interconnection region. The electrode structure includes a first electrode structure including a plurality of first electrodes stacked on the substrate and a second electrode structure including a plurality of second electrodes stacked on the first electrode structure.Both the first vertical channel structure and the first dummy structure include a first vertically extended portion that at least partially penetrates the first electrode structure, a second vertically extended portion that at least partially penetrates the second electrode structure, and an extended portion arranged between the first and second vertically extended portions. A first height in the direction of the second electrode structure (ST2) from a top surface of an uppermost one of the plurality of first electrodes (EL1) to a bottom of the extended portion (EXP1) of the first vertical channel structure (VS1) is smaller than a second height in the direction of the second electrode structure (ST2) from the top surface of the uppermost one of the plurality of first electrodes (EL1) to a bottom of the extended portion (EXP3) of the first dummy structure (DS1).The semiconductor memory device further comprises a second dummy structure (DS2) which at least partially penetrates the electrode structure (ST) on the connection region (CNR), wherein a distance between the second dummy structure (DS2) and the cell region (CAR) is greater than a distance between the first dummy structure (DS1) and the cell region (CAR), and wherein a third height in the direction of the second electrode structure (ST2) from the top surface of the uppermost one of the plurality of first electrodes (EL1) to a bottom of an extended portion (EXP4) of the second dummy structure (DS2) is greater than the second height.

[0009] According to one embodiment of the inventive concept, a semiconductor memory device includes a substrate including a cell region, an interconnection region, and a cell edge region disposed between the cell region and the interconnection region; an electrode structure on the substrate; a first vertical channel structure at least partially penetrating the electrode structure on the cell region; and a second vertical channel structure at least partially penetrating the electrode structure on the cell edge region. The electrode structure includes a first electrode structure including a plurality of first electrodes stacked on the substrate and a second electrode structure including a plurality of second electrodes stacked on the first electrode structure.Both the first and second vertical channel structures include a first vertically extended portion at least partially penetrating the first electrode structure, a second vertically extended portion at least partially penetrating the second electrode structure, and an extended portion disposed between the first and second vertically extended portions. A vertical length of the extended portion of the first vertical channel structure is greater than a vertical length of the extended portion of the second vertical channel structure.

[0010] The invention is defined in the appended independent claims and further developments of the invention are set out in the dependent claims. Short description of the drawings

[0011] The following brief description, taken in conjunction with the accompanying drawings, provides a better understanding of the embodiments. The accompanying drawings illustrate non-limiting embodiments as described herein. Fig. 1 is a schematic perspective view illustrating a three-dimensional semiconductor memory device according to an embodiment of the inventive concept; Fig. 2 is a schematic plan view illustrating a three-dimensional semiconductor memory device according to an embodiment of the inventive concept; Fig. 3 is a plan view illustrating a three-dimensional semiconductor memory device according to an embodiment of the inventive concept; Fig. 4A and Fig. 4B are cross-sectional views along lines II' and II-II', respectively, of Fig. 3; Fig. 5A and Fig. 5B are enlarged cross-sectional views showing sections “M” and “N” of Fig. 4A; Fig. 6A, Fig. 7A, Fig. 8A, Fig. 9A, Fig. 10A, Fig. 11A, Fig. 12A, Fig. 13A, Fig. 14A and Fig. 15A are cross-sectional views along line II' of Fig. 3 for illustrating a method of manufacturing a three-dimensional semiconductor memory device according to an embodiment of the inventive concept; Fig. 6B, Fig. 7B, Fig. 8B, Fig. 9B, Fig. 10B, Fig. 11B, Fig. 12B, Fig. 13B, Fig. 14B and Fig. 15B are cross-sectional views along the line II-II' of Fig. 3 for illustrating a method of manufacturing a three-dimensional semiconductor memory device according to an embodiment of the inventive concept; Fig. 16A and Fig. 16B are enlarged cross-sectional views showing sections (e.g., sections “M” and “N” of Fig. 4A) of a semiconductor memory device according to an embodiment of the inventive concept; Fig. 17 is a cross-sectional view along line II' of Fig. 3 for illustrating a semiconductor memory device according to an embodiment of the inventive concept; Fig. 18 is a plan view illustrating a three-dimensional semiconductor memory device according to an embodiment of the inventive concept; Fig. 19 is a cross-sectional view along line II' of Fig. 18; Fig. 20 is a cross-sectional view along line II' of Fig. 3; and Fig. 21 is a cross-sectional view of embodiments of the inventive concept. Detailed description

[0012] It should be noted that these figures are intended to illustrate the general characteristics of methods, structures, and / or materials employed in certain embodiments and to complement the written description provided below. These drawings need not be to scale and may not accurately reflect the precise structural or performance characteristics of any embodiment and should not be construed as defining or limiting the range of values ​​or properties included in the embodiments. For example, the relative thicknesses and positioning of molecules, layers, regions, and / or structural elements may be reduced or exaggerated for clarity.The use of similar or identical reference numerals in the various drawings may be intended to indicate the presence of a similar or identical element or feature.

[0013] Fig. 1 is a schematic perspective view illustrating a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

[0014] Referring to Fig. 1, a three-dimensional semiconductor memory device according to an embodiment of the inventive concept may include a peripheral circuit pattern PS, a cell array pattern CS arranged on the peripheral circuit pattern PS, and a piercing contact vertically connecting the cell array pattern CS to the peripheral circuit pattern PS. In a plan view, the cell array pattern CS may be overlapped by the peripheral circuit pattern PS and may have widths and lengths that are at least similar to each other.

[0015] In one embodiment of the inventive concept, the peripheral circuit structure PS may include row and column decoders, a page buffer, control circuits, and peripheral logic circuits. The peripheral logic circuits forming the peripheral circuit structure PS may be integrated on a semiconductor substrate.

[0016] The cell array structure CS may include a cell array in which a plurality of memory cells are arranged in three dimensions. For example, the cell array structure CS may include a plurality of memory blocks BLK0-BLKn. Each of the memory blocks BLK0-BLKn may include memory cells arranged three-dimensionally.

[0017] Fig. 2 is a schematic plan view illustrating a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

[0018] Referring to Fig. 1 and Fig. 2 may be used with reference to Fig. 1 described peripheral circuit structure PS and cell array structure CS are arranged on a first substrate SUB. In each of chip areas 10, row and column decoders ROW DEC and COL DEC, a page buffer PBR and control circuits, which comprise the peripheral circuit structure PS, Fig. 1, be arranged on the first substrate SUB.

[0019] A plurality of mats MT, which form the cell array structure CS from Fig. 1 may be arranged on the first substrate SUB. The mats MT may be arranged in a first direction D1 and a second direction D2. Each of the mats MT may have the configuration described above with reference to Fig. 1 described memory blocks BLK0-BLKn.

[0020] The mats MT can be arranged in such a way that they are connected to the peripheral circuit structure PS Fig. 1. In one embodiment, the peripheral logic circuits comprising the peripheral circuit structure PS of Fig. 1, be freely arranged below the mats MT.

[0021] Fig. 3 is a plan view illustrating a three-dimensional semiconductor memory device according to an embodiment of the inventive concept. Fig. 4A and Fig. 4B are cross-sectional views along lines II' and II-II', respectively, of Fig. 3. Fig. 5A and Fig. 5B are enlarged cross-sectional views showing sections “M” and “N” of Fig. 4A. The semiconductor memory device of Fig. 3 provides an example of the Fig. 2 shows the memory cell structure in one of the mats MT.

[0022] Referring to Fig. 3, Fig. 4A, Fig. 4B, Fig. 5A and Fig. 5B, the peripheral circuit structure PS, which includes peripheral transistors PTR, may be arranged on the first substrate SUB. The cell array structure CS, which includes an electrode structure ST, may be arranged on the peripheral circuit structure PS. The first substrate SUB may be a silicon substrate, a silicon germanium substrate, a germanium substrate, or a single-crystal epitaxial layer grown on a single-crystal silicon substrate. The first substrate SUB may include active regions defined by a device isolation layer DIL.

[0023] The peripheral circuit structure PS may include the peripheral transistors PTR arranged on the active areas of the first substrate SUB. The peripheral transistors PTR may form the row and column decoders, the page buffer, the control circuit, and the peripheral logic circuit, as described above.

[0024] The peripheral circuit structure PS may further include lower interconnect lines INL provided on the peripheral transistors PTR, and a first interlayer insulating layer ILD1 provided to cover the peripheral transistors PTR and the lower interconnect lines INL. A peripheral contact PCNT may be provided between the lower interconnect line INL and the peripheral transistor PTR to electrically connect the lower interconnect line INL to the peripheral transistor PTR. The first interlayer insulating layer ILD1 may include a plurality of stacked insulating layers. For example, the first interlayer insulating layer ILD1 may include a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and / or a low-k dielectric layer stacked on top of one another.

[0025] The cell array structure CS may be provided on the first interlayer insulating layer ILD1 of the peripheral circuit structure PS. The cell array structure CS will be described in more detail below. A second substrate SL may be provided on the first interlayer insulating layer ILD1. In one embodiment, the second substrate SL may be a plate-shaped structure forming a lower portion of the mat MT and having a rectangular shape in a plan view. The second substrate SL may support the electrode structure ST provided thereon.

[0026] The second substrate SL may include a lower semiconductor layer LSL, a source semiconductor layer SLL, and an upper semiconductor layer USL that are sequentially stacked. Each of the lower semiconductor layer LSL, the source semiconductor layer SSL, and the upper semiconductor layer USL may be formed of or otherwise contain a semiconductor material (e.g., silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), or a mixture thereof). Each of the lower semiconductor layer LSL, the source semiconductor layer SSL, and the upper semiconductor layer USL may have single-crystalline, amorphous, and / or polycrystalline structures. In one embodiment, each of the lower semiconductor layer LSL, the source semiconductor layer SSL, and the upper semiconductor layer USL may include an n-type polysilicon layer doped with impurities.The lower semiconductor layer LSL, the source semiconductor layer SSL and the upper semiconductor layer USL may have impurity concentrations that differ from each other.

[0027] The source semiconductor layer SSL may be sandwiched between the lower semiconductor layer LSL and the upper semiconductor layer USL. The lower semiconductor layer LSL and the upper semiconductor layer USL may be electrically connected to each other through the source semiconductor layer SSL. For example, the upper semiconductor layer USL and the source semiconductor layer SSL may be overlapped by the lower semiconductor layer LSL in a plan view.

[0028] The second substrate SL may include a cell array region CAR, a cell edge region EDR, and a connection region CNR. The cell array region CAR may overlap a center of the second substrate SL. The connection region CNR may be provided at a side region of the second substrate SL. The connection region CNR may be extended from the side region of the cell array region CAR in the second direction D2. The cell edge region EDR may be provided outside the cell array region CAR or around it. The cell edge region EDR may be interposed between the cell array region CAR and the connection region CNR.

[0029] The electrode structure ST may be provided on the second substrate SL. The electrode structure ST may include a first electrode structure ST1 and a second electrode structure ST2 arranged on the first electrode structure ST1. A second interlayer insulating layer ILD2 and a third interlayer insulating layer ILD3 may be provided on the second substrate SL. A top surface of the second interlayer insulating layer ILD2 may be coplanar with a top surface of the first electrode structure ST1. A top surface of the third interlayer insulating layer ILD3 may be coplanar with the top surface of the second electrode structure ST2. The second and third interlayer insulating layers ILD2 and ILD3 may at least partially cover the electrode structure ST on the connection region CNR.

[0030] The first electrode structure ST1 may include first electrodes EL1 stacked on the second substrate SL in a vertical direction (i.e., a third direction D3). The first electrode structure ST1 may further include first insulating layers IL1 separating the first electrodes EL1 from each other. The first insulating layers IL1 and the first electrodes EL1 of the first electrode structure ST1 may be alternately stacked in the third direction D3. A second insulating layer IL2 may be provided at the uppermost portion of the first electrode structure ST1. The second insulating layer IL2 may be thicker than each of the first insulating layers IL1.

[0031] The second electrode structure ST2 may include second electrodes EL2 stacked on the first electrode structure ST1 in the third direction D3. The second electrode structure ST2 may further include third insulating layers IL3 separating the second electrodes EL2 from each other. The third insulating layers IL3 and the second electrodes EL2 of the second electrode structure ST2 may be alternately stacked in the third direction D3. A fourth insulating layer IL4 may be provided at the uppermost portion of the second electrode structure ST2. The fourth insulating layers IL4 may be thicker than each of the third insulating layers IL3.

[0032] The electrode structure ST may be extended from the cell array region CAR to the connection region CNR. The electrode structure ST may have a stair structure on the connection region CNR. The stair structure of the electrode structure ST may have a height or thickness that decreases with an increase in a distance from the cell array region CAR. For example, the stair structure of the electrode structure ST on the cell array region CAR may have a decreasing height or thickness in the second direction D2.

[0033] The lowest of the first electrodes EL1 of the electrode structure ST can be a lower select line. The uppermost of the second electrodes EL2 of the electrode structure ST can be an upper select line. Both the first and second electrodes EL1 and EL2 can be word lines, unlike the lower select line and the upper select line.

[0034] The first and second electrodes EL1 and EL2 may be formed from or otherwise contain at least one conductive material, for example, doped semiconductor materials (e.g., doped silicon), metals (e.g., tungsten, copper, or aluminum), conductive metal nitrides (e.g., titanium nitride or tantalum nitride), and / or transition metals (e.g., titanium or tantalum). The first to fourth insulating layers IL1-IL4 may be formed from or otherwise contain silicon oxide.

[0035] A plurality of first vertical channel structures VS1 may be provided on the cell array region CAR to at least partially penetrate the electrode structure ST. In one embodiment, as shown in Fig. 3, the first vertical structures VS1 may be arranged to form a first column C1 consisting of four first vertical channel structures VS1 arranged in the first direction D1, and a second column C2 consisting of five first vertical channel structures VS1 arranged in the first direction D1. In one embodiment, the first columns C1 and the second columns C2 may be repeatedly and / or alternately stacked in the second direction D2. A diameter of each of the first vertical channel structures VS1 may gradually decrease with a decrease in a distance from the first substrate SUB.

[0036] A plurality of second vertical structures VS2 may be provided on the cell edge region EDR to at least partially penetrate the electrode structure ST. The second vertical channel structures VS2 may have the same arrangement and pattern density as the first vertical channel structures VS1, except that the second vertical channel structures VS2 are arranged on the cell edge region EDR.

[0037] First and second dummy structures DS1 and DS2 may be provided on the connection region CNR to at least partially penetrate the electrode structure ST. In a plan view, a size of each of the first and second dummy structures DS1 and DS2 may be larger than a size of each of the first and second vertical channel structures VS1 and VS2. The first dummy structures DS1 may be adjacent to the cell edge region EDR. The second dummy structures DS2 may be provided on an outer region of the connection region CNR. The second dummy structures DS2 may at least partially penetrate the third interlayer insulating layer ILD3, the second interlayer insulating layer ILD2, and the stair structure of the electrode structure ST below the second interlayer insulating layer ILD2.

[0038] Each of the first and second vertical channel structures VS1 and VS2 may include a vertical insulation pattern VP, a vertical semiconductor pattern SP, and a gap-fill insulation pattern VI. The vertical semiconductor pattern SP may be interposed between the vertical insulation pattern VP and the gap-fill insulation pattern VI. A conductive pad PAD may be provided on each of the first and second vertical channel structures VS1 and VS2.

[0039] The gap-filling insulation pattern VI may have a circular columnar shape. The vertical semiconductor pattern SP may at least partially cover a surface of the gap-filling insulation pattern VI and may be extended from the lower semiconductor layer LSL to the conductive pad PAD in the third direction D3. The vertical semiconductor pattern SP may be shaped like a tube with an open top end. The vertical insulation pattern VP may at least partially cover an outer surface of the vertical semiconductor pattern SP and may be extended from the lower semiconductor layer LSL to the top surface of the second insulation layer IL2 in the third direction D3. The vertical insulation pattern VP may also be shaped like a tube with an open top end. The vertical insulation pattern VP may be interposed between the electrode structure ST and the vertical semiconductor pattern SP.

[0040] The vertical isolation pattern VP may include one layer or a plurality of layers. In one embodiment, the vertical isolation pattern VP may include a data storage layer. For example, as shown in Fig. As shown in Fig. 5A, the vertical isolation pattern VP may include a tunnel isolation layer TNL, a charge storage layer CTL, and a barrier isolation layer BKL, which are used as the data storage layer of the NAND FLASH memory device.

[0041] For example, the charge storage layer CTL may be a trapping insulation layer, a floating gate electrode, or an insulation layer containing conductive nanodots. The charge storage layer CTL may be formed from, or otherwise include, a silicon nitride layer, a silicon oxynitride layer, a silicon-rich nitride layer, a nanocrystalline silicon layer, and / or a laminated trapping layer. The tunnel insulation layer TNL may be formed from, or otherwise include a material whose band gap is larger than the charge storage layer CTL. The tunnel insulation layer TNL may be formed from, or otherwise include high-k dielectric materials (e.g., alumina and hafnium oxide) or silicon oxide. As used herein, a high-k dielectric material is a material with a dielectric constant greater than silicon dioxide.The barrier insulating layer BKL may contain a silicon oxide layer.

[0042] The vertical semiconductor pattern SP may be formed from or otherwise contain semiconductor materials (e.g., silicon (Si), germanium (Ge), or mixtures thereof). Additionally, the vertical semiconductor pattern SP may be formed from or otherwise contain a doped or intrinsic semiconductor material. The vertical semiconductor pattern SP containing the semiconductor material may be used as channel regions of transistors forming cell strings of NAND FLASH memory devices.

[0043] The conductive pad PAD may at least partially cover a top surface of the vertical semiconductor pattern SP and a top surface of the gap-filling insulation pattern VI. The conductive pad PAD may be formed from or otherwise contain doped semiconductor materials and / or conductive materials. A bit line contact plug BPLG may be electrically connected to the vertical semiconductor pattern SP through the conductive pad PAD.

[0044] The source semiconductor layer SSL may directly contact a lower sidewall of each of the vertical semiconductor patterns SP. The source semiconductor layer SSL may electrically connect the vertical semiconductor patterns SP to each other. For example, the vertical semiconductor patterns SP may also be electrically connected to the second substrate SL. The second substrate SL may serve as the source electrodes of the memory cells. A common source voltage may be applied to the second substrate SL.

[0045] Each of the first and second dummy structures DS1 and DS2, similar to the first and second vertical channel structures VS1 and VS2, may include the vertical isolation pattern VP, the vertical channel pattern SP, and the gap-fill isolation pattern VI. However, unlike the first and second vertical channel structures VS1 and VS2, the first and second dummy structures DS1 and DS2 may not serve as the channel region of the memory cell. The first and second dummy structures DS1 and DS2 may not be electrically connected to bit lines BL and upper interconnect lines UIL, as described below. For example, the first and second dummy structures DS1 and DS2 may be dummy structures that have no operational function in a circuit (e.g., do not affect voltage or current characteristics of a circuit), but may be formed in a similar manner and / or together with actual circuit elements.The first and second dummy structures DS1 and DS2 can physically support the staircase structure of the electrode structure ST.

[0046] Referring to Fig. 4A and Fig. 5A, each of the first vertical channel structures VS1 may include a first vertical extended portion VEP1 at least partially penetrating the first electrode structure ST1, a second vertical extended portion VEP2 at least partially penetrating the second electrode structure ST2, and a first extended portion EXP1 between the first and second vertical extended portions VEP1 and VEP2. The first extended portion EXP1 may be provided in the second insulating layer IL2.

[0047] A width of the first vertical extended portion VEP1 in the second direction D2 may increase in an upward direction from bottom to top. For example, a width of an upper portion of the first vertical extended portion VEP1 in the second direction D2 may be a first width W1. The first width W1 of the first vertical extended portion VEP1 may be a value measured at the topmost level or the level of the first electrode EL1. The first width W1 may be the largest width of the first vertical extended portion VEP1. A width of the second vertical extended portion VEP2 in the second direction D2 may increase in the upward direction from bottom to top. The largest width of the second vertical extended portion VEP2 may be at least similar to the first width W1.

[0048] A width of an upper portion of the first extended portion EXP1 in the second direction D2 may be a third width W3. The third width W3 may be the largest width of the first extended portion EXP1. The third width W3 may be greater than the first width W1. For example, the first extended portion EXP1 may be horizontally extended by a first recess pitch RCD1 from the first vertical extended portion VEP1. Accordingly, the third width W3 may be equal to a sum of the first width W1 and twice the first recess pitch RCD1 (ie, W3 = W1 + 2 × RCD1).

[0049] A bottom of the first extended portion EXP1 may be located on a first plane LV1. The first plane LV1 may be the same plane as a top surface of the first electrode EL1. The first plane LV1 may be the same plane as a bottom surface of the second insulating layer IL2.

[0050] A vertical length or height of the first extended portion EXP1 may be a first length L1. The vertical length may be a length from the bottom of the first extended portion EXP1 to the top surface of the first extended portion EXP1.

[0051] Referring to Fig. 4A, each of the second vertical channel structures VS2 may include the first vertical extended portion VEP1, the second vertical extended portion VEP2, and a second extended portion EXP2 between the first and second vertical extended portions VEP1 and VEP2. The second extended portion EXP2 may be provided in the second insulating layer IL2. A bottom of the second extended portion EXP2 may be located at a second level LV2. The second level LV2 may be higher than the first level LV1. The second level LV2 may be positioned between the bottom surface and top surface of the second insulating layer IL2. A vertical length of the second extended portion EXP2 may be a second length L2 that is smaller than the first length L1.Except for the difference described above, the second vertical channel structure VS2 may be configured to have substantially the same features as those of the first vertical channel structure VS1.

[0052] Referring to Fig. 4A, each of the first dummy structures DS1 may include the first vertical extended portion VEP1, the second vertical extended portion VEP2, and a third extended portion EXP3 between the first and second vertical extended portions VEP1 and VEP2. The third extended portion EXP3 may be provided in the second insulating layer IL2. The bottom of the third extended portion EXP3 may be located on a third level LV3. The third level LV3 may be higher than the second level LV2. The third level LV3 may be positioned between the bottom surface and top surface of the second insulating layer IL2. A vertical length of the third extended portion EXP3 may be a third length L3 that is shorter than the second length L2.

[0053] A width of an upper portion of the first vertically extended portion VEP1 of the first dummy structure DS1 in the second direction D2 may be a second width W2. The second width W2 may be the largest width of the first vertically extended portion VEP1 of the first dummy structure DS1. The second width W2 may be larger than the first width W1. A width of an upper portion of the third extended portion EXP3 in the second direction D2 may be a fourth width W4.

[0054] The fourth width W4 may be the largest width of the third extended section EXP3. The fourth width W4 may be larger than the second width W2.

[0055] Referring to Fig. 4A and Fig. 5A, each of the second dummy structures DS2 may include the first vertical extended portion VEP1, the second vertical extended portion VEP2, and a fourth extended portion EXP4 between the first and second vertical extended portions VEP1 and VEP2. The fourth extended portion EXP4 may be provided in the second interlayer insulating layer ILD2. A bottom of the fourth extended portion EXP4 may be located on a fourth level LV4. The fourth level LV4 may be higher than the third level LV3. The fourth level LV4 may be lower than the top surface of the second interlayer insulating layer ILD2. A vertical length of the fourth extended portion EXP4 may be a fourth length L4 that is smaller than the third length L3.

[0056] A width of an upper portion of the first vertically extended portion VEP1 of the second dummy structure DS2 in the second direction D2 may be the second width W2. A width of an upper portion of the fourth extended portion EXP4 in the second direction D2 may be the fourth width W4. For example, the fourth extended portion EXP4 may be horizontally extended by a second recess pitch RCD2 from the first vertically extended portion VEP1. Accordingly, the fourth width W4 may be equal to a sum of the second width W2 and twice the second recess pitch RCD2 (i.e., W4 = W2 + 2 × RCD2). In one embodiment, the second recess pitch RCD2 may be equal to the first recess pitch RCD1. Fig. 4A be essentially the same.

[0057] Referring to Fig. 4A, top surfaces of the first to fourth extended sections EXP1-EXP4 may be coplanar with each other. The top surfaces of the first to fourth extended sections EXP1-EXP4 may be coplanar with the top surface of the second insulating layer IL2. The bottoms of the first to fourth extended sections EXP1-EXP4 may be located at different levels. The levels of the bottoms of the first to fourth extended sections EXP1-EXP4 may be elevated in a direction from the first extended section EXP1 to the fourth extended section EXP4. The vertical lengths of the first to fourth extended sections EXP1-EXP4 may be reduced in the direction from the first extended section EXP1 to the fourth extended section EXP4.

[0058] Referring to Fig. 5A and Fig. 5B, a ratio W3 / W1 of the third width W3 to the first width W1 in the first vertical channel structure VS1 may be larger than a ratio W4 / W2 of the fourth width W4 to the second width W2 in the second dummy structure DS2. For example, in the first vertical channel structure VS1, since the first width W1 is relatively small, a difference between the third width W3 and the first width W1 (i.e., 2 × RCD1) may be relatively large compared to the first width W1. In the second dummy structure DS2, since the second width W2 is relatively large, a difference between the fourth width W4 and the second width W2 (i.e., 2 × RCD2) may be relatively small compared to the second width W2.

[0059] Referring again to Fig. 3, Fig. 4A and Fig. 4B, a plurality of separation structures SPS can at least partially penetrate the electrode structure ST. The separation structures SPS can be extended parallel to one another in a second direction D2. The electrode structure ST can be divided into a plurality of structures that are horizontally spaced from one another by the separation structures SPS. For example, each electrode EL1 or EL2 of the electrode structure ST can be divided into a plurality of electrodes that are horizontally spaced from one another by the separation structures SPS. The separation structures SPS can be formed from an insulating material (e.g., silicon oxide) or otherwise contain it.

[0060] The three-dimensional semiconductor memory device according to an embodiment of the inventive concept may be a three-dimensional NAND FLASH memory device. NAND cell strings may be integrated into the electrode structure ST on the second substrate SL. For example, the electrode structure ST and the first and second vertical channel structures VS1 and VS2, which at least partially penetrate it, may form memory cells arranged three-dimensionally on the second substrate SL. The first and second electrodes EL1 and EL2 of the electrode structure ST may be used as the gate electrodes of the transistors.

[0061] A fourth interlayer insulating layer ILD4 may be provided on the third interlayer insulating layer ILD3. The bitline contact plugs BPLG may at least partially penetrate the fourth interlayer insulating layer ILD4 and may each be coupled to the conductive pads PAD. The bitlines BL may be arranged on the fourth interlayer insulating layer ILD4. The bitlines BL may be extended parallel to each other in the first direction D1. The bitlines BL may be electrically connected to the first and second vertical channel structures VS1 and VS2, respectively, through the bitline contact plugs BPLG.

[0062] The cell contact plugs PLG can at least partially penetrate the second to fourth interlayer insulating layers ILD2, ILD3, and ILD4 and can be respectively coupled to the first and second electrodes EL1 and EL2 forming the staircase structure. The upper connection lines UIL can be arranged on the fourth interlayer insulating layer ILD4. The upper connection lines UIL can be electrically connected to the first and second electrodes EL1 and EL2, respectively, through the cell contact plugs PLG.

[0063] According to one embodiment of the inventive concept, a vertical channel structure on a cell region may include an extended portion disposed between a first vertical extended portion and a second vertical extended portion. The first vertical extended portion and the second vertical extended portion may be stably connected to each other by the extended portion. Accordingly, it is possible to enhance the reliability and maintain the electrical characteristics of the semiconductor memory device according to one embodiment of the inventive concept.

[0064] Fig. 6A, Fig. 7A, Fig. 8A, Fig. 9A, Fig. 10A, Fig. 11A, Fig. 12A, Fig. 13A, Fig. 14A and Fig. 15A are cross-sectional views along line II' of Fig. 3 illustrating a method of manufacturing a three-dimensional semiconductor memory device according to an embodiment of the inventive concept. Fig. 6B, Fig. 7B, Fig. 8B, Fig. 9B, Fig. 10B, Fig. 11B, Fig. 12B, Fig. 13B, Fig. 14B and Fig. 15B are cross-sectional views along the line II-II' of Fig. 3 illustrating a method of manufacturing a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

[0065] Referring to Fig. 3, Fig. 6A and Fig. 6B, the peripheral circuit structure PS may be formed on the first substrate SUB. Forming the peripheral circuit structure PS may include forming the peripheral transistors PTR on the first substrate SUB and forming the lower interconnect lines INL on the peripheral transistors PTR. For example, forming the peripheral transistors PTR may include forming the device isolation layer DIL on the first substrate SUB to define active regions, forming a gate isolation layer and a gate electrode on the active regions, and injecting impurities into the active regions to form source / drain regions. The first interlayer isolation layer ILD1 may cover the peripheral transistors PTR and the lower interconnect lines INL.

[0066] Referring to Fig. 3, Fig. 7A and Fig. 7B, the second substrate SL may be formed on the first interlayer insulating layer ILD1. Forming the second substrate SL may include sequentially forming the lower semiconductor layer LSL, a fifth insulating layer IL5, a lower sacrificial layer LHL, a sixth insulating layer IL6, and the upper semiconductor layer USL. For example, the lower semiconductor layer LSL and the upper semiconductor layer USL may be formed of or otherwise include a semiconductor material (e.g., polysilicon). The fifth and sixth insulating layers IL5 and IL6 may include a silicon oxide layer, and the lower sacrificial layer LHL may include a silicon nitride layer or a silicon oxynitride layer.

[0067] A first mold structure MO1 may be formed on the second substrate SL. For example, the first insulating layers IL1 and first sacrificial layers HL1 may be alternately stacked on the upper semiconductor layer USL to form the first mold structure MO1. The second insulating layer IL2 may be formed as the uppermost layer of the first mold structure MO1.

[0068] The first insulating layers IL1, the first sacrificial layers HL1, and the second insulating layer IL2 may be deposited using a thermal chemical vapor deposition process, a plasma-enhanced chemical vapor deposition (PE-CVD) process, a physical chemical vapor deposition process, and / or an atomic layer deposition (ALD) process. The first insulating layers IL1 and the second insulating layer IL2 may be formed of or otherwise contain silicon oxide, and the first sacrificial layers HL1 may be formed of or otherwise contain silicon nitride or silicon oxynitride.

[0069] A step structure may be formed in the first mold structure MO1 on the interconnection region CNR. For example, the stair structure may be formed on the interconnection region CNR by performing a cyclic process on the first mold structure MO1. Forming the stair structure may include forming a mask pattern on the first mold structure MO1 and performing a cyclic process by reusing the mask pattern multiple times. Each cyclic process may include a process of etching a portion of the first mold structure MO1 using the mask pattern as an etching mask, and a trimming process of shrinking the mask pattern.

[0070] The second interlayer insulating layer ILD2 may be formed on the first mold structure MO1. Forming the second interlayer insulating layer ILD2 may include forming an insulating layer to cover the first mold structure MO1 and performing a planarization process on the insulating layer to expose the second insulating layer IL2.

[0071] Referring to Fig. 3, Fig. 8A and Fig. 8B, first channel holes CH1 may be formed on the cell array region CAR to at least partially penetrate the first mold structure MO1. Second channel holes CH2 may be formed on the cell edge region EDR to at least partially penetrate the first mold structure MO1. First and second dummy holes DH1 and DH2 may be formed on the interconnection region CNR to at least partially penetrate the first mold structure MO1. The second dummy holes DH2 may be provided to at least partially penetrate the second interlayer insulating layer ILD2. Each of the first and second channel holes CH1 and CH2 and the first and second dummy holes DH1 and DH2 may expose the lower semiconductor layer LSL.

[0072] For example, forming the first and second channel holes CH1 and CH2 and the first and second dummy holes DH1 and DH2 may include a mask pattern including openings that define the arrangement and positions of holes on the first mold structure MO1, and anisotropic etching of the first mold structure MO1 using the mask pattern as an etching mask. The anisotropic etching process may include a plasma etching process, a reactive ion etching (RIE) process, an inductively coupled reactive plasma ion etching (ICP-RIE) process, and / or an ion beam etching (IBE) process.

[0073] In a plan view, the first and second channel holes CH1 and CH2 may be arranged in a specific direction or in a zigzag shape. The first and second channel holes CH1 and CH2 may have the same planar arrangement as that of the previously described with reference to Fig. 3 described first and second vertical channel structures VS1 and VS2.

[0074] A pattern density of the first and second channel holes CH1 and CH2 may be larger than that of the first and second dummy holes DH1 and DH2. For example, the number of the first and second channel holes CH1 and CH2 formed within a unit region may be larger than the number of the first and second dummy holes DH1 and DH2 formed within the unit region.

[0075] An upper portion of each of the first and second channel holes CH1 and CH2 may have the first width W1 in the second direction D2. For example, the largest diameter of each of the first and second channel holes CH1 and CH2 may be equal to the first width W1. An upper portion of each of the first and second dummy holes DH1 and DH2 may have the second width W2 in the second direction D2. For example, the largest diameter of each of the first and second dummy holes DH1 and DH2 may be equal to the second width W2. In one embodiment, the second width W2 may be greater than the first width W1.

[0076] Referring to Fig. 3, Fig. 9A and Fig. 9B, a first sacrificial mask layer SAL1 may fill the first and second channel holes CH1 and CH2 and the first and second dummy holes DH1 and DH2. The first sacrificial mask layer SAL1 may be formed by a spin-coating process. The first sacrificial mask layer SAL1 may include a spin-on hard mask (SOH). For example, the first sacrificial mask layer SAL1 may include a layer (e.g., an amorphous carbon layer) with a high carbon content (e.g., a carbon content that is more than nominal). Immediately after forming the first sacrificial mask layer SAL1 on the first mold structure MO1, the first sacrificial mask layer SAL1 may have a uniform thickness on the first mold structure MO1. For example, the first sacrificial mask layer SAL1 may have a substantially coplanar top surface from the cell array region CAR to the interconnect region CNR.

[0077] Referring to Fig. 3, Fig. 10A and Fig. 10B, a heating process may be performed on the first sacrificial mask layer SAL1. A first sacrificial mask layer SAL1' may be shrunk as a result of the heating process.

[0078] The first sacrificial mask layer SAL1' may be more shrunk on the first channel holes CH1 with the high pattern density. The first sacrificial mask layer SAL1' may be less shrunk on the second dummy holes DH2 with the low pattern density. Thus, a thickness of the first sacrificial mask layer SAL1' on the first mold pattern MO1 may gradually increase in a direction from the first channel hole CH1 of the cell array region CAR to the second dummy hole DH2 of the interconnection region CNR. For example, a level of a top surface of the first sacrificial mask layer SAL1' may gradually increase in a direction from the cell array region CAR to the interconnection region CNR.

[0079] For example, the first sacrificial mask layer SAL1' of the cell array region CAR may have a first thickness T1, the first sacrificial mask layer SAL1 of the cell edge region EDR may have a second thickness T2, and the first sacrificial mask layer SAL1' of the connection region CNR may have a third thickness T3. The second thickness T2 may be greater than the first thickness T1, and the third thickness T3 may be greater than the second thickness T2.

[0080] The second substrate SL may include a peripheral circuit region PER, which is an outer edge region thereof and on which an upper peripheral transistor UPTR is formed. The first sacrificial mask layer SAL1' on the peripheral circuit region PER may have a fourth thickness T4. The fourth thickness T4 may be greater than the third thickness T3.

[0081] Referring to Fig. 3, Fig. 11A and Fig. 11B, the first sacrificial mask layer SAL1' may be recessed. As a result of the recession of the first sacrificial mask layer SAL1', the first and second channel holes CH1 and CH2 and the first and second dummy holes DH1 and DH2 may be filled with the first sacrificial mask layer SAL1' being recessed.

[0082] The first sacrificial mask layer SAL1' may be recessed to the same depth throughout the entire area of ​​the second substrate SL. Since the first sacrificial mask layer SAL1, as described above, has an increasing thickness in the direction from the cell array region CAR to the connection region CNR, the height of the recessed first sacrificial mask layer SAL1' may gradually increase in the direction from the cell array region CAR to the connection region CNR.

[0083] For example, the top surface of the first sacrificial mask layer SAL1' in the first channel hole CH1 may be positioned on the first level LV1, the top surface of the first sacrificial mask layer SAL1' in the second channel hole CH2 may be positioned on the second level LV2, the top surface of the first sacrificial mask layer SAL1' in the first dummy hole DH1 may be positioned on the third level LV3, and the top surface of the first sacrificial mask layer SAL1' in the second dummy hole CH2 may be positioned on the fourth level LV4. The second level LV2 may be higher than the first level LV1, the third level LV3 may be higher than the second level LV2, and the fourth level LV4 may be higher than the third level LV3.

[0084] First to fourth extended holes EXH1-EXH4 may be formed by respectively extending the upper portions of the first and second channel holes CH1 and CH2 and the first and second dummy holes DH1 and DH2 using the recessed first sacrificial mask layer SAL1' as a mask. Forming the first to fourth extended holes EXH1-EXH4 may include horizontally deepening the second insulating layer IL2 and the second interlayer insulating layer ILD2, which are exposed through the recessed first sacrificial mask layer SAL1', using a wet etching process.

[0085] During the recessing process, the second insulating layer IL2 can be formed by the first recessing distance RCD1 Fig. 5A. During the recessing process, the second interlayer insulating layer ILD2 can be formed by the second recess pitch RCD2 Fig. 5B. In one embodiment, the second recess pitch RCD2 may be equal to the first recess pitch RCD1 Fig. 5A be essentially the same.

[0086] The bottoms of the first to fourth extended holes EXH1-EXH4 may be located on the first to fourth levels LV1-LV4, respectively. Each of the first and second extended holes EXH1 and EXH2 may have the third width W3. The third width W3 may be greater than the first width W1. Each of the third and fourth extended holes EXH3 and EXH4 may have the fourth width W4. The fourth width W4 may be greater than the second width W2.

[0087] Referring to Fig. 3, Fig. 12A and Fig. 12B, the first sacrificial mask layer SAL1' may be selectively removed in the first and second channel holes CH1 and CH2 and the first and second dummy holes DH1 and DH2. A second sacrificial mask layer SAL2 may be formed in the first and second channel holes CH1 and CH2 and the first and second dummy holes DH1 and DH2. For example, the second sacrificial mask layer SAL2 may be formed of polysilicon or may otherwise include it. When the second sacrificial mask layer SAL2 is formed, a cavity VO1 may be formed in each of the first and second channel holes CH1 and CH2 and the first and second dummy holes DH1 and DH2.

[0088] A second mold structure MO2 may be formed on the first mold structure MO2. For example, the second mold structure MO2 may be formed by alternately stacking the third insulating layers IL3 and second sacrificial layers HL2 on the first mold structure MO1. The fourth insulating layer IL4 may be formed on the top level of the second mold structure MO2. The first mold structure MO1 and the second mold structure MO2 may form a single mold structure MO. The third insulating layers IL3 and the fourth insulating layer IL4 may be formed of silicon oxide or otherwise contain the same, and the second sacrificial layers HL2 may be formed of silicon nitride or silicon oxynitride or otherwise contain the same.

[0089] A stair structure may be formed in the second mold structure MO2 on the connecting region CNR. The stair structure on the second mold structure MO2 may be formed by the same method as that for the stair structure of the first mold structure MO1.

[0090] The third interlayer insulating layer ILD3 may be formed on the second mold structure MO2. Forming the third interlayer insulating layer ILD3 may include forming an insulating layer to cover the second mold structure MO2 and performing a planarization process on the insulating layer to expose the fourth insulating layer IL4.

[0091] Referring to Fig. 3, Fig. 13A and Fig. 13B, the first and second channel holes CH1 and CH2 and the first and second dummy holes DH1 and DH2 may at least partially penetrate the second mold structure MO2. The first and second channel holes CH1 and CH2 and the first and second dummy holes DH1 and DH2, which at least partially penetrate the second mold structure MO2, may be overlapped in a plan view, respectively, by the first and second channel holes CH1 and CH2 and the first and second dummy holes DH1 and DH2, which at least partially penetrate the first mold structure MO1.

[0092] The second sacrificial mask layer SAL2 may be exposed through the first and second channel holes CH1 and CH2 and the first and second dummy holes DH1 and DH2, which at least partially penetrate the second mold structure MO2. The exposed second sacrificial mask layer SAL2 may be selectively removed to form the first and second channel holes CH1 and CH2 and the first and second dummy holes DH1 and DH2, which at least partially penetrate the mold structure MO.

[0093] According to one embodiment of the inventive concept, the previously described extended holes EXH1-EXH4 may have diameters larger than underlying holes. Since the extended holes have relatively large areas, the holes at least partially penetrating the second mold structure MO2 can each be more easily aligned with the extended holes. As a result, when the holes at least partially penetrating the second mold structure MO2 are formed, it may be possible to prevent them from becoming misaligned with the holes formed in the first mold structure MO1. Since a process error such as the aforementioned misalignment is prevented, the reliability of the semiconductor memory device can be increased.

[0094] Referring to Fig. 3, Fig. 14A and Fig. 14B, the first and second vertical channel structures VS1 and VS2 may be formed in the first and second channel holes CH1 and CH2, respectively. Forming the first and second vertical channel structures VS1 and VS2 may include sequentially forming the vertical isolation pattern VP, the vertical semiconductor pattern SP, and the gap-fill isolation pattern VI on inner surfaces of the first and second channel holes CH1 and CH2. The vertical isolation pattern VP and the vertical semiconductor pattern SP may be conformally formed.

[0095] The first and second dummy structures DS1 and DS2 may be formed in the first and second dummy holes DH1 and DH2, respectively. In one embodiment, the first and second dummy structures DS1 and DS2 may be formed simultaneously with the first and second vertical channel structures VS1 and VS2. The conductive pad may be formed in or on an upper portion of each of the first and second vertical channel structures VS1 and VS2 and the first and second dummy structures DS1 and DS2.

[0096] The fourth interlayer insulating layer ILD4 may be formed on the mold structure MO. The mold structure MO may be patterned to form the recesses TR that at least partially penetrate the mold structure MO. The recesses TR may be extended in the second direction D2 parallel to each other (see, for example, Fig. 3). The recess TR may expose the lower semiconductor layer LSL. The recess TR may expose sidewalls of the first and second sacrificial layers HL1 and HL2. The recess TR may expose side surfaces of the fifth insulating layer IL5, the lower sacrificial layer LHL, and the sixth insulating layer IL6.

[0097] Referring to Fig. 3, Fig. 15A and Fig. 15B, the lower sacrificial layer LHL exposed by the recesses TR may be replaced by the source semiconductor layer SSL. For example, the lower sacrificial layer LHL exposed by the recesses TR may be selectively removed. As a result of the removal of the lower sacrificial layer LHL, a lower portion of the vertical isolation pattern VP of each of the first and second vertical channel structures VS1 and VS2 may be exposed.

[0098] The exposed lower portion of the vertical insulation pattern VP may be selectively removed. Accordingly, a lower portion of the vertical semiconductor pattern SP may be exposed. In one embodiment, the fifth insulation layer IL5 and the sixth insulation layer IL6 may be removed during the removal of the lower portion of the vertical insulation pattern VP.

[0099] The source semiconductor layer SSL may be formed in a space created by removing the fifth insulating layer IL5, the lower sacrificial layer LHL, and the sixth insulating layer IL6. The source semiconductor layer SSL may directly contact the exposed lower portion of the vertical semiconductor pattern SP. The source semiconductor layer SSL may directly contact the underlying lower semiconductor layer LSL. The source semiconductor layer SSL may directly contact the upper semiconductor layer USL located thereon. The lower semiconductor layer LSL, the source semiconductor layer SSL, and the upper semiconductor layer USL may form the second substrate SL.

[0100] The electrode structure ST may be formed by replacing the first and second sacrificial layers HL1 and HL2, which are exposed by the recesses TR, with the first and second electrodes EL1 and EL2. For example, the first and second sacrificial layers HL1 and HL2 exposed by the recesses TR may be selectively removed. The first and second electrodes EL1 and EL2 may be formed in spaces formed by removing the first and second sacrificial layers HL1 and HL2, respectively. The separation structures SPS may fill the recesses TR, respectively.

[0101] Referring again to Fig. 3, Fig. 4A and Fig. 4B, the bit line contact plugs BPLG, each coupled to the conductive pads PAD, may at least partially penetrate the fourth interlayer insulating layer ILD4. The cell contact plugs PLG, each coupled to the first and second electrodes EL1 and EL2, may at least partially penetrate the second to fourth interlayer insulating layers ILD2, ILD3, and ILD4. The bit lines BL electrically connected to the bit line contact plugs BPLG and the upper connection lines UIL electrically connected to the cell contact plugs PLG may be formed on the fourth interlayer insulating layer ILD4.

[0102] Fig. 16A and Fig. 16B are enlarged cross-sectional views showing sections (e.g., sections “M” and “N” of Fig. 4A) of a semiconductor memory device according to an embodiment of the inventive concept. For a precise description, a previously described with reference to Fig. 3, Fig. 4A, Fig. 4B, Fig. 5A and Fig. 5B is identified by the same reference numeral without repeating an overlapping description thereof, and features that differ from those of the previous embodiment are described in more detail below. Thus, to the extent that a detailed description of a particular element has been omitted, that element can be assumed to be at least similar to corresponding elements described elsewhere in the present specification.

[0103] Referring to Fig. 4A, Fig. 16A and Fig. 16B, the uppermost one of the first electrodes EL1 that contacts the first extended portion EXP1 may have a curved surface CTS. The curved surface CTS may directly contact a lower portion of the first extended portion EXP1. The curved surface CTS of the uppermost one of the first electrodes EL1 may be formed by etching a portion of the exposed surface of the uppermost one of the first sacrificial layers HL1 during the process for expanding the first channel hole CH1 previously described with reference to FIG. Fig. 3, Fig. 11A and Fig. 11B has been described.

[0104] The first extended section EXP1 may be horizontally extended from the first vertical extended section VEP1 by the first recess distance RCD1 (see e.g. Fig. 16A). The fourth extended section EXP4 may be horizontally extended from the first vertically extended section VEP1 by the second recess distance RCD2 (see e.g. Fig. 16B). The second recess pitch RCD2 may be larger than the first recess pitch RCD1. The first extended portion EXP1 may be formed by horizontally deepening the second insulating layer IL2, and the fourth extended portion EXP4 may be formed by horizontally deepening the second interlayer insulating layer ILD2. Since the second insulating layer IL2 and the second interlayer insulating layer ILD2 have different characteristics from each other, the recess depth of the second interlayer insulating layer ILD2 may be larger than that of the second insulating layer IL2.

[0105] Fig. 17 is a cross-sectional view along line II' of Fig. 3 to illustrate a semiconductor memory device according to an embodiment of the inventive concept. For a precise description, a previously described with reference to Fig. 3, Fig. 4A, Fig. 4B, Fig. 5A and Fig. 5B is identified by the same reference numeral without repeating an overlapping description thereof, and features that differ from those of the previous embodiment are described in more detail below. Thus, to the extent that a detailed description of a particular element has been omitted, that element can be assumed to be at least similar to corresponding elements described elsewhere in the present specification.

[0106] Referring to Fig. 3 and Fig. 17, the first and second vertical channel structures VS1 and VS2 may differ from the first and second dummy structures DS1 and DS2 in terms of layer or material properties. Each of the first and second vertical channel structures VS1 and VS2 may include the vertical insulation pattern VP, the vertical semiconductor pattern SP, and the gap-fill insulation pattern VI. Each of the first and second dummy structures DS1 and DS2 may be formed of or otherwise include insulating materials.

[0107] Fig. 18 is a plan view illustrating a three-dimensional semiconductor memory device according to an embodiment of the inventive concept. Fig. 19 is a cross-sectional view along line II' of Fig. 18. For a precise description, a previously defined Fig. 3, Fig. 4A, Fig. 4B, Fig. 5A and Fig. 5B is identified by the same reference numeral without repeating an overlapping description thereof, and features that differ from those of the previous embodiment are described in more detail below. Thus, to the extent that a detailed description of a particular element has been omitted, that element can be assumed to be at least similar to corresponding elements described elsewhere in the present specification.

[0108] Referring to Fig. 18 and Fig. 19, those of the first vertical channel structures VS1 that are adjacent to the separation structure SPS can be defined as third vertical channel structures VS3. The third vertical channel structures VS3 can be arranged along the separation structure SPS and in the second direction D2.

[0109] Each of the third vertical channel structures VS3 may include the first vertically extended portion VEP1 at least partially penetrating the first electrode structure ST1, the second vertically extended portion VEP2 at least partially penetrating the second electrode structure ST2, and a fifth extended portion EXP5 between the first and second vertically extended portions VEP1 and VEP2. The fifth extended portion EXP5 may be provided in the second insulating layer IL2.

[0110] An upper portion of the first vertical extended portion VEP1 of the third vertical channel structure VS3 may have a fifth width W5. The fifth width W5 may be greater than the first width W1. An upper portion of the fifth extended portion EXP5 may have a sixth width W6. The sixth width W6 may be greater than the fifth width W5. A ratio W6 / W5 of the sixth width W6 to the fifth width W5 in the third vertical channel structure VS3 may be smaller than the ratio W3 / W1 of the third width W3 to the first width W1 in the first vertical channel structure VS1.

[0111] Fig. 20 is a cross-sectional view along line II' of Fig. 3 to illustrate a three-dimensional semiconductor memory device according to another embodiment of the inventive concept. For a precise description, a figure previously described with reference to Fig. 3, Fig. 4A, Fig. 4B, Fig. 5A and Fig. 5B is identified by the same reference numeral without repeating an overlapping description thereof, and features that differ from those of the previous embodiment are described in more detail below. Thus, to the extent that a detailed description of a particular element has been omitted, that element can be assumed to be at least similar to corresponding elements described elsewhere in the present specification.

[0112] Referring to Fig. 20, the first and second dummy structures DS1 and DS2 on the connection area CNR may not contain the extended section. For example, the first dummy structure DS1 may not contain the previously described with reference to Fig. 4A. The second dummy structure DS2 may not contain the third extended section EXP3 described previously with reference to Fig. 4A. The first and second dummy structures DS1 and DS2 may be provided to include widths or diameters that gradually decrease with the decrease of a distance from the second substrate SL.

[0113] In contrast, the first and second vertical channel structures VS1 and VS2 provided on the cell array region CAR and the cell edge region EDR may each include first and second extended portions EXP1 and EXP2.

[0114] Forming the first and second dummy structures DS1 and DS2 may include forming dummy holes on the interconnection region CNR by a single etching process after forming the first and second mold structures MO1 and MO2 and the first and second channel holes CH1 and CH2 described in the above-described manufacturing method.

[0115] Fig. 21 is a cross-sectional view illustrating a three-dimensional semiconductor memory device according to embodiments of the inventive concept. Fig. 21 differs from the embodiments described above in that it includes an additional stacked third electrode structure ST3. For a precise description, a previously described Fig. 3, Fig. 4A, Fig. 4B, Fig. 5A and Fig. 5B is identified by the same reference numeral without repeating an overlapping description thereof, and features that differ from those of the previous embodiment are described in more detail below. Thus, to the extent that a detailed description of a particular element has been omitted, that element can be assumed to be at least similar to corresponding elements described elsewhere in the present specification.

[0116] Referring to Fig. 21, the electrode structure ST may further include a third electrode structure ST3 provided on the second electrode structure ST2. The third electrode structure ST3 may include third electrodes EL3 stacked on the second electrode structure ST2 in the third direction D3. The third electrode structure ST3 may further include seventh insulating layers IL7 separating the third electrodes EL3 from each other. An eighth insulating layer IL8 may be provided at the uppermost portion of the third electrode structure ST3.

[0117] Each of the first and second vertical channel structures VS1 and VS2 may include a lower extended portion LEXP disposed in the second insulating layer IL2 of the first electrode structure ST1 and an upper extended portion UEXP disposed in the fourth insulating layer IL4 of the second electrode structure ST2.

[0118] The first dummy structure DS1, the second dummy structure DS2, and a third dummy structure DS3 may be provided on the connection region CNR. The first dummy structure DS1 may be adjacent to the cell edge region EDR. The third dummy structure DS3 may be adjacent to an end portion of the staircase structure of the electrode structure ST. The second dummy structure ST2 may be arranged between the first dummy structure DS1 and the third dummy structure DS3.

[0119] The first dummy structure DS1 may include a first lower extended portion LEXP1 arranged in the second insulating layer IL2 of the first electrode structure ST1 and a first upper extended portion UEXP1 arranged in the fourth insulating layer IL4 of the second electrode structure ST2.

[0120] The second dummy structure DS2 may include the first lower extended portion LEXP1 arranged in the second insulating layer IL2 of the first electrode structure ST1 and a second upper extended portion UEXP2 arranged in the upper portion of the third interlayer insulating layer ILD3.

[0121] The second upper extended portion UEXP2 of the second dummy structure DS2 may have a width that is greater than the first lower extended portion LEXP1 of the second dummy structure DS2. For example, the second recess pitch RCD2 of the first lower extended portion LEXP1 may be relatively small, as previously described with reference to Fig. 5B. The second recess pitch RCD2 of the second upper extended portion UEXP2 may be relatively large, as previously described with reference to Fig. 16B.

[0122] The first lower extended portion LEXP1 may be formed by horizontally deepening the second insulating layer IL2 of the first electrode structure ST1, and the second upper extended portion UEXP2 may be formed by horizontally deepening the third interlayer insulating layer ILD3. Since the second insulating layer IL2 and the third interlayer insulating layer ILD3 have different properties, the second upper extended portion UEXP2 of the second dummy structure DS2 may have a width larger than the underlying first lower extended portion LEXP1.

[0123] The third dummy structure DS3 may include a second lower extended portion LEXP2 disposed in the upper portion of the second interlayer insulating layer ILD2 and a second upper extended portion UEXP2 disposed in the upper portion of the third interlayer insulating layer ILD3. Both the second lower extended portion LEXP2 and the second upper extended portion UEXP2 of the third dummy structure DS3 may have relatively large widths.

[0124] According to one embodiment of the inventive concept, a vertical channel structure on a cell region may include an extended portion disposed between a first vertically extended portion and a second vertically extended portion. Due to the presence of the extended portion, it may be possible to increase reliability and maintain electrical characteristics of a semiconductor memory device.

[0125] Although embodiments of the inventive concept have been particularly shown and described, it will be understood by one skilled in the art that variations in form and details may be made therein without departing from the spirit and scope of the present specification.

Claims

[1] A semiconductor memory device comprising: a substrate (SUB) containing a cell region (CAR) and a connection region (CNR); an electrode structure (ST) arranged on the substrate (SUB), the electrode structure (ST) having a step structure on the connection region (CNR); a first vertical channel structure (VS1) which at least partially penetrates the electrode structure (ST) on the cell region (CAR); and a first dummy structure (DS1) which at least partially penetrates the electrode structure on the connection region, where the electrode structure (ST) comprises: a first electrode structure (ST1) including a plurality of first electrodes (EL1) stacked on the substrate (SUB); and a second electrode structure (ST2) including a plurality of second electrodes (EL2) stacked on the first electrode structure (ST1), where both the first vertical channel structure (VS1) and the first dummy structure (DS1) have: a first vertically extended portion (VEP1) at least partially penetrating the first electrode structure (ST1); a second vertically extended portion (VEP2) at least partially penetrating the second electrode structure (ST2); and an extended section (EXP1, EXP3) arranged between the first and second vertically extended sections, wherein a first height in the direction of the second electrode structure (ST2) from a top surface of an uppermost one of the plurality of first electrodes (EL1) to a bottom of the extended section (EXP1) of the first vertical channel structure (VS1) is smaller than a second height in the direction of the second electrode structure (ST2) from the top surface of the uppermost one of the plurality of first electrodes (EL1) to a bottom of the extended section (EXP3) of the first dummy structure (DS1), further comprising a second dummy structure (DS2) which at least partially penetrates the electrode structure (ST) on the connection region (CNR), wherein a distance between the second dummy structure (DS2) and the cell area (CAR) is greater than a distance between the first dummy structure (DS1) and the cell area (CAR), and wherein a third height in the direction of the second electrode structure (ST2) from the top surface of the uppermost one of the plurality of first electrodes (EL1) to a bottom of an extended portion (EXP4) of the second dummy structure (DS2) is greater than the second height. [2] The semiconductor memory device according to claim 1, wherein the substrate (SUB) further comprises a cell edge region (EDR) arranged between the cell region (CAR) and the connection region (CNR), the semiconductor memory device further comprising a second vertical channel structure (VS2) at least partially penetrating the electrode structure (ST) on the cell edge region (EDR), a fourth height from the top surface of the uppermost one of the plurality of first electrodes (EL1) to a bottom of an extended portion (EXP2) of the second vertical channel structure (VS2) being greater than the first height and less than the second height. [3] A semiconductor memory device according to claim 1, wherein a largest width of the first vertical extended portion (VEP1) of the first vertical channel structure (VS1) is a first width, wherein a largest width of the extended portion (EXP1) of the first vertical channel structure (VS1) is a second width, wherein a largest width of the first vertical extended portion (VEP1) of the first dummy structure (DS1) is a third width, wherein a largest width of the extended portion (EXP3) of the first dummy structure (DS1) is a fourth width, and wherein a ratio of the second width to the first width is greater than a ratio of the fourth width to the third width. [4] A semiconductor memory device according to claim 3, wherein the extended portion (EXP1) of the first vertical channel structure (VS1) extends horizontally from the first vertical extended portion (VEP1) of the first vertical channel structure (VS1) by a first distance, wherein the extended portion (EXP3) of the first dummy structure (DS1) extends horizontally from the first vertical extended portion (VEP1) of the first dummy structure (DS1) by a second distance, and where the second distance is greater than the first distance. [5] The semiconductor memory device according to claim 1, wherein the first electrode structure (ST1) has an insulating layer on a highest one of the plurality of first electrodes (EL1), and wherein a top surface of the extended portion (EXP1) of the first vertical channel structure (VS1) and a top surface of the extended portion (EXP3) of the first dummy structure (DS1) are coplanar with a top surface of the insulating layer. [6] A semiconductor memory device according to claim 1, wherein an upper portion of a topmost one of the plurality of first electrodes (EL1) has a curved surface, and wherein the extended portion (EXP1) of the first vertical channel structure (VS1) contacts the curved surface. [7] A semiconductor memory device according to claim 1, wherein the extended portion (EXP1) of the first vertical channel structure (VS1) extends horizontally from the first vertical extended portion (VEP1) of the first vertical channel structure (VS1) by a first distance, wherein the extended portion (EXP3) of the first dummy structure (DS1) extends horizontally from the first vertical extended portion (VEP1) of the first dummy structure (DS1) by a second distance, and where the second distance is greater than the first distance. [8] A semiconductor memory device according to claim 1, further comprising: a separation structure (SPS) which at least partially penetrates the electrode structure (ST) and extends in a specific direction, wherein the separation structure (SPS) divides the electrode structure (ST) horizontally; and a second vertical channel structure (VS2) which at least partially penetrates the electrode structure (ST) and is adjacent to the separation structure (SPS), wherein a largest width of the first vertical extended portion (VEP) of the first vertical channel structure (VS1) is a first width, wherein a largest width of the extended portion (EXP1) of the first vertical channel structure (VS1) is a second width, wherein a largest width of a first vertical extended portion (VEP1) of the second vertical channel structure (VS2) is a third width, wherein a largest width of an extended portion (EXP2) of the second vertical channel structure (VS2) is a fourth width, and wherein a ratio of the second width to the first width is greater than a ratio of the fourth width to the third width. [9] A semiconductor memory device according to claim 1, wherein the substrate comprises a first substrate (SUB) and a second substrate (SL) arranged on the first substrate (SUB), wherein the semiconductor memory device further comprises a peripheral circuit structure (PS) inserted between the first substrate (SUB) and the second substrate (SL), and wherein the electrode structure (ST) is provided on the second substrate (SL) such that the first vertical channel structure (VS1) is connected to the second substrate (SL). [10] A semiconductor memory device according to claim 1, wherein both the first vertical channel structure (VS1) and the first dummy structure (DS1) comprise: a vertical semiconductor pattern (SP); and a vertical insulation pattern (VP) inserted between the vertical semiconductor pattern (SP) and the electrode structure (ST), wherein the vertical insulation pattern (VP) of the first vertical channel structure (VS1) comprises a data storage layer. [11] A semiconductor memory device comprising: a substrate (SUB) containing a cell region (CAR), a connection region (CNR) and a cell edge region (EDR) arranged between the cell region (CAR) and the connection region (CNR); an electrode structure (ST) arranged on the substrate (SUB); a first vertical channel structure (VS1) which at least partially penetrates the electrode structure (ST) on the cell region (CAR); and a second vertical channel structure (VS2) which at least partially penetrates the electrode structure (ST) on the cell edge region (EDR), where the electrode structure (ST) comprises: a first electrode structure (ST1) including a plurality of first electrodes (EL1) stacked on the substrate (SUB); and a second electrode structure (ST2) including a plurality of second electrodes (EL2) stacked on the first electrode structure (ST1), where both the first (VS1) and the second (VS2) have vertical channel structures: a first vertically extended portion (VEP1) at least partially penetrating the first electrode structure (ST1); a second vertically extended portion (VEP2) at least partially penetrating the second electrode structure (ST2); and an extended section (EXP1, EXP2) arranged between the first (VEP1) and second (VEP2) vertically extended section, wherein a vertical length of the extended portion (EXP1) of the first vertical channel structure (VS1) is greater than a vertical length of the extended portion (EXP2) of the second vertical channel structure (VS2). [12] The semiconductor memory device according to claim 11, further comprising a first dummy structure (DS1) at least partially penetrating the electrode structure (ST) on the connection region (CNR), wherein the vertical length of the extended portion (EXP2) of the second vertical channel structure (VS2) is greater than a vertical length of an extended portion (EXP3) of the first dummy structure (DS1). [13] A semiconductor memory device according to claim 12, further comprising a second dummy structure (DS2) which at least partially penetrates the electrode structure (ST) on the connection region (CNR), wherein a distance between the second dummy structure (DS2) and the cell area (CAR) is greater than a distance between the first dummy structure (DS1) and the cell area (CAR), and wherein the vertical length of the extended section (EXP3) of the first dummy structure (DS1) is greater than a vertical length of an extended section (EXP4) of the second dummy structure (DS2). [14] The semiconductor memory device according to claim 11, wherein the first electrode structure (ST1) comprises an insulating layer (IL1) on an uppermost one of the plurality of first electrodes (EL1), and wherein a top surface of the extended portion (EXP1) of the first vertical channel structure (VS1) and a top surface of the extended portion (EXP2) of the second vertical channel structure (VS2) are coplanar with a top surface of the insulating layer (IL1). [15] A semiconductor memory device according to claim 11, further comprising: a separation structure (SPS) which at least partially penetrates the electrode structure (ST) and extends in a specific direction, wherein the separation structure (SPS) divides the electrode structure (ST) horizontally; and a third vertical channel structure (VS3) which at least partially penetrates the electrode structure (ST) on the cell region (CAR) and is adjacent to the separation structure (SPS), wherein a largest width of the first vertical extended portion (VEP1) of the first vertical channel structure (VS1) is a first width, wherein a largest width of the extended portion (EXP1) of the first vertical channel structure (VS1) is a second width, wherein a largest width of a first vertical extended portion (VEP1) of the third vertical channel structure (VS3) is a third width, wherein a largest width of an extended portion (EXP5) of the third vertical channel structure (VS3) is a fourth width, and wherein a ratio of the second width to the first width is greater than a ratio of the fourth width to the third width.

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