WAFER BONDING METHOD AND APPARATUS

Abstract

Procedure comprising: Obtaining a first processed wafer comprising a first substrate and a first interconnect structure, the first substrate comprising a semiconductor material, the first interconnect structure comprising metal interconnects between dielectric material; Removing an edge region of the first interconnect structure with a first trimming process, wherein the first trimming process removes the dielectric material of the first interconnect structure at a faster rate than the semiconductor material of the first substrate; after removing the edge region of the first interconnect structure, removing an edge region of the first substrate with a second trimming process, wherein the second trimming process removes the semiconductor material of the first substrate at a faster rate than the dielectric material of the first interconnect structure; and Bonding a second processed wafer to a front side of the first processed wafer.

Description

BACKGROUND

[0001] Since the development of the integrated circuit (IC), the semiconductor industry has experienced sustained rapid growth due to continuous improvements in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). These improvements in integration density are largely due to the repeated reduction of the minimum component size, allowing more components to be integrated in a given area. With the growing demand for miniaturization, higher speed, wider bandwidth, lower power consumption, and lower latency, the need for smaller and more creative techniques for semiconductor chip packaging has increased.

[0002] Stacked semiconductor devices have emerged as an effective technique for further reducing the physical size of a semiconductor device. In a stacked semiconductor device, active circuits, such as logic and memory circuits, are fabricated on different semiconductor wafers. Two or more semiconductor wafers can be bonded together using suitable bonding techniques to further reduce the form factor of the semiconductor device.

[0003] US 2014 / 0 024 170 A1 discloses methods for producing semiconductor wafers with minimal edge delamination, wherein a first trimming process is performed on a wafer having a substrate and interconnections extending into the substrate, followed by a second trimming process. US 2018 / 0 226 390 A1 discloses methods for semiconductor structures, wherein a trimming process is performed on a wafer having a substrate and interconnections extending into the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. Indeed, the dimensions of various features may be arbitrarily increased or decreased to enhance the clarity of the description. The Fig. 1 to 9 are cross-sectional views of intermediate steps during a wafer bonding process, according to some embodiments. The Fig. 10A and Fig. 10B illustrate die stacks in accordance with some embodiments. The Fig. 11 to 15 are cross-sectional views of intermediate steps during a wafer bonding process, according to some other embodiments. The Fig. 16 through 20 are cross-sectional views of intermediate steps during a wafer bonding process, according to some other embodiments. The Fig. 21 to 25 are cross-sectional views of intermediate steps during a wafer bonding process, according to some other embodiments. DETAILED DESCRIPTION

[0005] The following disclosure includes many different embodiments or examples of implementing various features of the invention. Specific examples of components and arrangements are described below to clarify the present disclosure. These are, of course, only examples and are not to be considered limiting. For example, the formation of a first feature over or on a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features need not be in direct contact. Furthermore, the present disclosure may repeat reference numbers and / or letters in the various examples.This repetition is for simplicity and clarity and does not, in itself, dictate a relationship between the various embodiments and / or configurations discussed.

[0006] Furthermore, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," and the like may be used herein to describe the relationship of one element or feature to another element or feature, as illustrated in the figures. These spatially relative terms are intended to encompass other orientations of the device during use or operation in addition to the orientation illustrated in the figures. The device may be oriented differently (rotated 90 degrees or in other orientations), and the spatially relative terms used herein may be interpreted accordingly.

[0007] In accordance with some embodiments, a first wafer (e.g., a top wafer) is processed, tested, and trimmed, and then subsequently bonded to a second wafer (e.g., a bottom wafer). A processed wafer may have rounded or raised edges, e.g., due to uneven chemical mechanical polishing (CMP) that may occur at the edge of the wafer during processing. Grinding the edges of the first processed wafer prior to bonding may increase the uniformity of the bond strength in the resulting bonded wafer structure. Furthermore, trimming the edges of the first processed wafer prior to bonding may reduce the risk of edge chipping during subsequent thinning of the first processed wafer after bonding, thereby avoiding undesirable particle formation.In accordance with some embodiments, the edges of the first wafer are trimmed using multiple types of trimming processes. In particular, a first trimming process is used to trim dielectric features at the edges of the wafer, and a second trimming process is subsequently used to trim semiconductor features at the edges of the wafer. In some embodiments, the first trimming process is a chemical or ablative process, which allows for delicate features such as extra-low-K (ELK) dielectric layers to be trimmed with a lower risk of damage compared to mechanical processes. The yield of the resulting bonded wafer structures may thereby be improved, reducing manufacturing costs.

[0008] The Fig. 1 to 9 are cross-sectional views of intermediate steps during a wafer bonding process, according to some embodiments. As explained in more detail below, the Fig. 1 to 9 a process in which a first processed wafer (see Fig. 1) trimmed and attached to a second processed wafer (see Fig. 7) is bonded. The wafers contain a plurality of integrated circuit dies 50 formed in and / or on them. The integrated circuit dies 50 may be logic dies (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a system-on-chip (SoC), an application processor (AP), a microcontroller, etc.), memory chips (e.g., dynamic random access memory (DRAM) chips, static random access memory (SRAM) chips, etc.), power management chips (e.g., power management integrated circuit (PMIC) dies), radio frequency (RF) dies, sensor dies (e.g., image sensors), micro-electro-mechanical system (MEMS) dies, signal processing dies (e.g., digital signal processing (DSP) dies), front-end dies (e.g., analog front-end (AFE) dies), and the like, or combinations thereof.

[0009] In Fig. 1, a first wafer is formed or obtained. The first wafer includes a plurality of device regions 52D, and an integrated circuit die 50 is formed in and / or on each of the device regions 52D. Furthermore, the first wafer includes edge regions 52E arranged laterally at the edges of the first wafer and surrounding the device regions 52D. As explained in more detail below, a plurality of trimming processes are performed in the edge regions 52E. The first wafer includes a semiconductor substrate 52, an interconnect structure 54, conductive vias 56, one or more passivation layers 58, and contact pads 60.

[0010] The semiconductor substrate 52 may be silicon, doped or undoped, or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate 52 may contain other semiconductor materials, such as germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates, such as multilayer or gradient substrates, may also be used. The semiconductor substrate 52 has an active surface (e.g., the one shown in Fig. 1 upward-facing surface), sometimes referred to as the front, and an inactive surface (e.g. the one in Fig. 1 downward-facing surface), sometimes referred to as the back.

[0011] Devices are formed on the active surface of semiconductor substrate 52. The devices may be active devices (e.g., transistors, diodes, etc.) and / or passive devices (e.g., capacitors, resistors, etc.). The inactive surface may be free of devices. An interlayer dielectric (ILD) is located over the active surface of semiconductor substrate 52. The ILD surrounds and may cover the devices. The ILD may include one or more dielectric layers made of materials such as phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), or the like.

[0012] The interconnect structure 54 is located on the active surface of the semiconductor substrate 52. The interconnect structure 54 connects the devices on the active surface of the semiconductor substrate 52 to form integrated circuits. The interconnect structure 54 may, for example, include metallization patterns 54A in dielectric material 54B. The dielectric material 54B may include one or more dielectric layers, such as one or more layers of a low-K (LK) or extra-low-K (ELK) dielectric material. The metallization patterns 54A may be metallic interconnects (e.g., metal lines and vias) formed in the one or more dielectric layers. The interconnect structure 54 may be formed by a damascene process, such as a single damascene process, a dual damascene process, or the like.The metallization patterns 54A of the interconnect structure 54 are electrically coupled to the devices on the active surface of the semiconductor substrate 52.

[0013] The conductive vias 56 are formed to extend into the interconnect structure 54 and / or the semiconductor substrate 52. The conductive vias 56 are electrically coupled to the metallization patterns 54A of the interconnect structure 54. To form the conductive vias 56, for example, recesses may be formed in the interconnect structure 54 and / or the semiconductor substrate 52, for example, by etching, milling, laser techniques, a combination thereof, and / or the like. A thin dielectric material may be formed in the recesses, e.g., by an oxidation process. A barrier layer may be conformally deposited in the openings, e.g., by CVD, atomic layer deposition (ALD), physical vapor deposition (PVD), thermal oxidation, a combination thereof, and / or the like. The barrier layer may be formed from an oxide, a nitride, or an oxynitride, such as, for example,Titanium nitride, titanium oxynitride, tantalum nitride, tantalum oxynitride, tungsten nitride, a combination thereof, and / or the like. A conductive material may be deposited over the barrier layer and in the openings. The conductive material may be formed by an electrochemical deposition process, CVD, PVD, a combination thereof, and / or the like. Examples of conductive materials include copper, tungsten, aluminum, silver, gold, a combination thereof, and / or the like. Excess conductive material and the barrier layer are removed from the surface of the interconnect structure 54 and / or the semiconductor substrate 52, e.g., by chemical mechanical polishing (CMP). Remaining portions of the barrier layer and the conductive material form the conductive vias 56.In the illustrated embodiment, the conductive vias 56 extend only into the semiconductor substrate 52, but it should be understood that the conductive vias 56 may also extend into some (or all) of the layers of the interconnect structure 54.

[0014] In the illustrated embodiment, the conductive vias 56 are not yet exposed on the backside of the first wafer, e.g., the backside of the semiconductor substrate 52. Rather, the conductive vias 56 are buried in the semiconductor substrate 52. As explained in more detail below, the conductive vias 56 are exposed during subsequent processing on the backside of the first wafer. After exposure, the conductive vias 56 may be referred to as through-silicon vias or through-substrate vias (TSVs).

[0015] The passivation layer(s) 58 are formed on the interconnect structure 54. The passivation layer(s) 58 may be formed from one or more suitable dielectric materials such as silicon oxide, silicon nitride, low-k dielectrics such as carbon-doped oxides, extremely low-k dielectrics such as porous carbon-doped silicon dioxide, a polymer such as polyimide, solder resist, polybenzoxazole (PBO), a benzocyclobutene (BCB)-based polymer, molding compound, or the like, or a combination thereof. The passivation layer(s) 58 may be formed by spin coating, lamination, chemical vapor deposition (CVD), the like, or a combination thereof. In some embodiments, the passivation layer(s) 58 comprise a silicon nitride layer and a silicon oxide layer on the silicon nitride layer.

[0016] The contact pads 60 are formed to extend through the passivation layer(s) 58 to physically and electrically couple to the metallization patterns 54A of the interconnect structure 54. For example, the contact pads 60 may be physically and electrically coupled to metal features that are part of the topmost metallization pattern of the interconnect structure 54. The contact pads 60 are formed from a conductive material, such as aluminum, copper, tungsten, silver, gold, a combination thereof, and / or the like. In some embodiments, the contact pads 60 are formed from a less expensive conductive material (e.g., aluminum) than the metallization patterns 54A of the interconnect structure 54.To form the contact pads 60, for example, openings may be formed in the passivation layer(s) 58, and a seed layer may be formed along the passivation layer(s) 58 and in the openings through the passivation layer(s) 58. The openings may be formed using suitable photolithography and etching techniques. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising a plurality of sublayers of different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer may be formed, for example, using PVD or the like. A photoresist is formed and patterned on the seed layer. The photoresist may be formed by spin coating or the like and exposed to light for patterning. The pattern of the photoresist corresponds to the contact pads 60.Patterning creates openings through the photoresist to expose the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material can be formed by electroplating, such as electroless plating or the like. The conductive material can be made of a metal, such as copper, titanium, tungsten, aluminum, or the like. The photoresist can be removed by a suitable ashing or stripping process, such as an oxygen plasma or the like. Once the photoresist is removed, the exposed portions of the seed layer are removed, e.g., by a suitable etching process, such as wet or dry etching. The remaining portions of the seed layer and the conductive material form the contact pads 60.

[0017] As explained in more detail below, the contact pads 60 are used for device testing. In some embodiments, the contact pads 60 are test pads used only for device testing and are not electrically coupled or active during normal operation of the integrated circuit dies 50. In some embodiments, the contact pads 60 are die terminals used for both device testing and normal operation of the integrated circuit dies 50.

[0018] In Fig. 2, the integrated circuit dies 50 are tested with a circuit probe to determine whether the integrated circuit dies 50 are proven good dies (KGDs). The integrated circuit dies 50 are tested using a probe 62. The probe 62 is physically and electrically coupled to the contact pads 60, e.g., through reflowable test plugs. Only wafers containing integrated circuit dies 50 that are KGDs are further processed and packaged, and wafers containing integrated circuit dies 50 that fail the KGD test are not packaged. Testing may include testing the functionality of the various integrated circuit dies 50 or testing for known open or short circuits that may be expected based on the design of the integrated circuit dies 50. After completion of the tests, the probe 62 is removed and excess reflowable material on the contact pads 60 can be removed, for example.B. can be removed by an etching process, a chemical-mechanical polishing (CMP), a grinding process or similar.

[0019] In Fig. 3, a dielectric layer 64 is formed on the front side of the wafer, e.g., on the contact pads 60 and the passivation layer(s) 58. The dielectric layer 64 buries the contact pads 60. If the contact pads 60 are test pads, the test pads remain electrically isolated in the resulting integrated circuit dies 50. The dielectric layer 64 may be a polymer such as PBO, polyimide, a BCB-based polymer, or the like; a nitride such as silicon nitride or the like; an oxide such as silicon oxide, a tetraethyl orthosilicate-based oxide (TEOS), phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or the like; or a combination thereof. The dielectric layer 64 may, for example, B. by spin coating, lamination, deposition (e.g. CVD) or similar.

[0020] Die connectors 66 are formed that extend through the dielectric layer 64 and the passivation layer(s) 58 to physically and electrically couple to the metallization patterns 54A of the interconnect structure 54. The die connectors 66 are electrically coupled to the respective integrated circuits of the integrated circuit dies 50. The die connectors 66 may comprise through-holes or conductive pillars and may be formed from a metal such as copper. In the illustrated embodiment, the die connectors 66 each include a contact pad portion and a via portion, with the via portion connecting the contact pad portion to the metallization patterns 54A of the interconnect structure 54. The die connectors 66 may be formed by a damascene process, such as a single damascene process, a dual damascene process, or the like.After fabrication, the die connectors 66 and the dielectric layer 64 can be planarized. Planarization can be performed by an etching process, a chemical mechanical polishing (CMP) process, a grinding process, or the like.

[0021] In another embodiment, the die connectors 66 are formed before the dielectric layer 64. For example, the die connectors 66 may be formed in a similar manner to the contact pads 60 (e.g., they may be die connectors), and the dielectric layer 64 may then be applied to the die connectors 66. The die connectors 66 and the dielectric layer 64 may then be planarized in a similar manner as described above to expose the die connectors 66.

[0022] After formation, the dielectric layer 64, the passivation layer(s) 58, and / or the dielectric material 54B may extend into the edge regions 52E. For example, if such layers are formed by a conformal deposition process, the layers may be formed in the edge regions 52E. As explained in more detail below, portions of these layers in the edge regions 52E are removed by performing multiple trimming processes.

[0023] In Fig. 4, a first trimming process 70 is performed to remove edge portions of the dielectric layer 64, the passivation layer(s) 58, and the interconnect structure 54. In particular, the portions of the dielectric layer 64, the passivation layer(s) 58, and the dielectric material 54B in the edge regions 52E are removed by performing the first trimming process 70. A mask 72 may be used to cover portions of the dielectric layer 64, the passivation layer(s) 58, and the dielectric material 54B in the device regions 52D during the first trimming process 70. As explained in more detail below, the first trimming process 70 is a non-mechanical process, such as an etching process, such as a chemical process or an ablative process. As mentioned above, the dielectric material 54B of the interconnect structure 54 may be formed from an ELK material.ELK materials are fragile and can be easily damaged by mechanical processing. By trimming the interconnect structure 54 with the first trimming process 70 (e.g., an etching process), damage to the interconnect structure 54 can be avoided or reduced.

[0024] The mask 72 may be formed prior to performing the first trimming process 70. The mask 72 may be formed from a photoresist, such as a single-layer photoresist, a two-layer photoresist, a three-layer photoresist, or the like. In some embodiments, the mask 72 is a three-layer mask comprising a bottom layer (e.g., a bottom anti-reflective coating (BARC)), a middle layer (e.g., a nitride, an oxide, an oxynitride, or the like), and a top layer (e.g., a photoresist). The mask 72 may be formed by spin coating, a deposition process such as CVD, combinations thereof, or the like. The mask 72 may be patterned using suitable photolithographic techniques to cover the device regions 52D and expose the edge regions 52E. In embodiments where the mask 72 comprises a photoresist, the photoresist may be patterned by exposing the photoresist to a patterned energy source (e.g.,a structured light source) to induce a chemical reaction, thus causing a physical change in the portions of the photoresist exposed to the structured light source. The photoresist can then be developed by applying a developer to the exposed photoresist to exploit the physical changes and selectively remove either the exposed portion of the photoresist or the unexposed portion of the photoresist, depending on the desired pattern.

[0025] After the first trimming process 70, the trimmed layers (e.g., the dielectric layer 64, the passivation layer(s) 58, and the dielectric material 54B) each have a recessed profile shape, i.e., they have a width that continuously increases in a direction extending away from the active surface of the semiconductor substrate 52. In particular, a width W1 of the lower surface of the dielectric material 54B is greater than a width W2 of the upper surface of the dielectric layer 64. The width W1 may range from approximately 290 mm to approximately 299.5 mm, and the width W2 may range from approximately 290 mm to approximately 299.5 mm. Each of the widths W1, W2 is smaller than a width W3 of the semiconductor substrate 52. The width W3 may range from approximately 299.8 mm to approximately 300.2 mm.Since the trimmed layers each have a re-entrant profile shape, the sidewalls of the trimmed layers each form a first obtuse angle θ1 with a plane parallel to the sidewall of the semiconductor substrate 52. For example, the first obtuse angle θ1 may be in the range of approximately 170 degrees to approximately 180 degrees. The first trimming process 70 can thus be considered a directional trimming process performed along a first direction D1.

[0026] The first trimming process 70 is selective for the material(s) of the dielectric layer 64, the passivation layer(s) 58, and the dielectric material 54B. In other words, the first trimming process 70 selectively removes the dielectric material(s) of the trimmed layers (e.g., the dielectric layer 64, the passivation layer(s) 58, and the dielectric material 54B) at a faster rate than the semiconductor material(s) of the semiconductor substrate 52. For example, the etch selectivity between the dielectric material(s) (e.g., oxides) and the semiconductor material(s) (e.g., silicon), relative to the first trimming process 70, may range from about 5 to about 50. The profile shape of the trimmed layers may be controlled by controlling parameters of the first trimming process 70.In particular, the trimmed layers can each be formed with a recessed profile shape by performing the first trimming process 70 with a high etching selectivity. If the first trimming process 70 is performed with an etching selectivity within the above-mentioned range, the trimmed layers can each have a recessed profile shape. If the first trimming process 70 is performed with an etching selectivity outside the above-mentioned range, the trimmed layers may not have a recessed profile shape.

[0027] In some embodiments, the first trimming process 70 is a chemical process, such as plasma etching, performed to achieve a desired etch selectivity. The mask 72 covers the device regions 52D during the plasma etching process. The plasma etching process is performed in a process chamber, with process gases supplied to the process chamber. The process gases may be activated by any suitable plasma generation method, such as transformer-coupled plasma (TCP) systems, inductively coupled plasma (ICP) systems, capacitively coupled plasma (CCP) systems, magnetically enhanced reactive ion processes, electron cyclotron resonance processes, or the like. In some embodiments, the plasma generation power is pulsed between low power and high power during the plasma etching process.In some embodiments, an applied bias voltage is also pulsed between a low voltage and a high voltage during the plasma etching process. In some embodiments, the plasma generation power and the bias voltage have synchronized pulses such that the plasma generation power and the bias voltage are in their respective low state or high state simultaneously. The plasma etching process may be performed with a high-power plasma generation power in the range of about 100 W to about 5000 W. The plasma etching process may be performed with a high-voltage bias in the range of about 100 volts to about 5000 volts. In some embodiments, the plasma generation power or the bias voltage may be pulsed with a duty cycle in the range of about 10% to about 90% and have a pulse frequency in the range of about 5 Hz to about 5000 Hz.The process gases used in the plasma etching process include at least one or more etching gases. When etching the dielectric material(s) discussed above (e.g., ELK dielectrics), suitable examples of the etching gas(es) include a fluorocarbon (CxFy), a fluorocarbon (CxHyFz), oxygen (O2), or the like, or combinations thereof. Carrier gases such as nitrogen, argon, helium, or the like may be used to guide the process gases into the process chamber. The plasma etching process may be performed at a temperature ranging from about -20°C to about 50°C. The pressure in the process chamber may range from about 133 mPa to about 66.6 Pa (about 1 mTorr to about 500 mTorr). The plasma etching process may be performed for a duration ranging from about 10 seconds to about 600 seconds.

[0028] In some embodiments, the first trimming process 70 is an ablative process, such as laser etching, performed to achieve a desired etch selectivity. The laser etching process is performed by firing one or more laser shots, each directed at the edge regions 52E. In some embodiments, the laser shots are directed at the edge regions 52E but not at the device regions 52D, so that the mask 72 can be omitted. In some embodiments, the laser shots are directed at the entire active surface of the semiconductor substrate 52, while the mask 72 covers the device regions 52D, so that only the edge regions 52E are exposed to the laser shots. The laser used can be a CO2 laser, a UV laser, a green light laser, a fiber laser, and yttrium aluminum garnet (YAG) laser, or the like. The wavelength of the laser can range from about 300 nm to about 600 nm.The average output power of the laser can range from approximately 1 W to approximately 30 W. The laser etching process can last for approximately 10 -15 seconds to approx. 10 -9 seconds.

[0029] The first trimming process 70 may form recesses 74 in the semiconductor substrate 52 by removing some portions of the semiconductor substrate 52 in the edge regions 52E. As mentioned above, the first trimming process 70 is performed with high etch selectivity, such that the first trimming process 70 selectively removes the dielectric material(s) of the dielectric layer 64, the passivation layer(s) 58, and the dielectric material 54B at a faster rate than the semiconductor material(s) of the semiconductor substrate 52. Therefore, the recesses 74 may be formed with a shallow depth D3. The depth D3 of the recesses 74 may range from about 10 μm to about 150 μm.

[0030] In Fig. 5, a second trimming process 80 is performed to remove edge regions of the semiconductor substrate 52. In particular, some of the portions of the semiconductor substrate 52 in the edge regions 52E are removed by performing the second trimming process. In the second trimming process 80, some of the layers trimmed by the first trimming process 70 are not trimmed. In particular, the second trimming process 80 is not used to trim sensitive features, such as the interconnect structure 54, when the dielectric material 54B is an ELK material. The second trimming process 80 may be a more aggressive trimming process than the first trimming process 70, e.g., it may have a faster removal rate than the first trimming process 70. The second trimming process 80 differs from the first trimming process 70 and may be a different type of trimming process.The second trimming process 80 may be a mechanical process or an etching process, and in this embodiment, it is a mechanical process. By trimming the semiconductor substrate 52 with the second trimming process 80 (e.g., a mechanical process), the semiconductor substrate 52 can be trimmed more quickly, thus improving the throughput of wafer processing.

[0031] The second trimming process 80 is selective for the material(s) of the semiconductor substrate 52. In other words, the second trimming process 80 selectively removes the semiconductor material(s) of the semiconductor substrate 52 at a faster rate than the dielectric material(s) of the dielectric layer 64, the passivation layer(s) 58, and the dielectric material 54B. For example, if the second trimming process 80 is an etching process, the etch selectivity between the semiconductor material(s) and the dielectric material(s) relative to the second trimming process 80 may range from about 5 to about 50. Likewise, if the second trimming process 80 is a mechanical process, the removal rate of the dielectric material(s) may be zero, and the removal rate of the semiconductor material(s) may be non-zero.

[0032] The second trimming process 80 deepens the recesses 74 in the semiconductor substrate 52 by removing some portions of the semiconductor substrate 52 in the edge regions 52E. A majority of the material of the semiconductor substrate 52 in the edge regions 52E is removed, but some portions 52P of the semiconductor substrate 52 remain in the edge regions 52E. After the first trimming process 70 and the second trimming process 80, the recesses 74 have a depth D4. The portions 52P of the semiconductor substrate 52 remaining in the edge regions 52E have a depth D5 that is less than the depth D4. The depth D4 may range from about 20 µm to about 300 µm, and the depth D5 may range from about 475 µm to about 755 µm. The portions 52P of the semiconductor substrate 52 remaining in the edge regions 52E are so thin that they can be subsequently removed by an etching or grinding process (explained in more detail below).The recesses 74 are recessed along a second direction D2, which is perpendicular to the active surface of the semiconductor substrate 52. The second trimming process 80 can therefore be considered a directional trimming process performed along the second direction D2. In particular, the first trimming process 70 and the second trimming process 80 are performed along different directions. The first direction D1 (see . Fig. 4) and the second direction D2 form the first obtuse angle θ1 (see Fig. 4).

[0033] In this embodiment, the second trimming process 80 is a mechanical process, e.g., a sawing process. A sawing process can be performed by applying a rotating saw blade 82, e.g., a half-cut saw blade, to the edge regions 52E of the semiconductor substrate 52. Fig. 6 is a detailed view of a region 50R after the sawing process. The first trimming process 70 and the second trimming process 80 jointly remove a cut region 52C from the semiconductor substrate 52. In particular, the first trimming process 70 removes a first portion of the cut region 52C1, and the second trimming process 80 removes a second portion of the cut region 52C2. In the illustrated embodiment, the saw blade 82 is shaped such that, after the sawing process, the semiconductor substrate 52 has a first sidewall 52S1, a second sidewall 52S2, and a third sidewall 52S3 in each edge region 52E. The third sidewall 52S3 has a plurality of sections. In particular, the third sidewall 52S3 has a first section 52S 3A and a second section 52S 3B . The first section 52S 3A connects the second section 52S 3B with the active surface of the semiconductor substrate 52. The first section 52S 3Aforms the first obtuse angle θ1 (described above) with the second section 52S 3B , and also forms a second obtuse angle θ2 with the active surface of the semiconductor substrate 52. The second obtuse angle θ2 may range from about 90 degrees to about 100 degrees. The second section 52S 3B is perpendicular to a plane parallel to the active surface of the semiconductor substrate 52. The first sidewall 52S1 and the second sidewall 52S2 are connected by a straight section 52S4. The second sidewall 52S2 and the third sidewall 52S3 are connected by a curved segment 52S5. The second sidewall 52S2 and the curved segment 52S5 together define a notch 52N at the corner of the cutting region 52C. The cutting region 52C may also have other shapes depending on the nature and parameters of the second trimming process 80 (discussed in more detail below).

[0034] In Fig. 7, a second wafer is formed or obtained. The second wafer includes a semiconductor substrate 102, an interconnect structure 104, one or more passivation layers 108, and contact pads 110, which may be similar to the semiconductor substrate 52, the interconnect structure 54, the passivation layer(s) 58, and the contact pads 60, respectively. A dielectric layer 114 is formed on the front side of the wafer, e.g., on the contact pads 110 and the passivation layer(s) 108. Die connectors 116 are formed, extending through the dielectric layer 114 and the passivation layer(s) 108 to physically and electrically couple to the metallization patterns of the interconnect structure 104. The dielectric layer 114 and the die connectors 116 may be similar to the dielectric layer 64 and the die connectors 66, respectively.

[0035] The first wafer is then bonded to the second wafer. In the illustrated embodiment, the wafers are bonded by hybrid bonding from one end face to the other, such that the front side of the first wafer is bonded to the front side of the second wafer. The dielectric layer 114 is connected to the dielectric layer 64 by dielectric-to-dielectric bonding without the use of an adhesive material (e.g., a die attach film), and the die leads 116 are connected to the die leads 66 by metal-to-metal bonding without the use of a eutectic material (e.g., solder). The bonding may include pre-bonding and annealing. During pre-bonding, a small pressing force is applied to press the wafers against each other. The pre-bonding is performed at a low temperature, e.g., at room temperature.at a temperature in the range of about 15°C to about 30°C, and after pre-bonding, the dielectric layer 64 and the dielectric layer 114 are bonded together. The bond strength is then improved in a subsequent annealing step in which the dielectric layer 64 and the dielectric layer 114 are annealed at a high temperature, for example, at a temperature in the range of about 100°C to about 400°C. After annealing, bonds, such as fusion bonds, are formed that bond the dielectric layer 64 and the dielectric layer 114 together. The bonds can be, for example, covalent bonds between the material of the dielectric layer 114 and the material of the dielectric layer 64. The die interconnects 66 and the die interconnects 116 are connected to each other with a one-to-one correspondence.Die interconnects 66 and die interconnects 116 may be in physical contact after pre-bonding or may expand to be brought into physical contact during annealing. Furthermore, during annealing, the material of die interconnects 66 and die interconnects 116 (e.g., copper) mixes, forming metal-to-metal bonds. Therefore, the resulting interconnects between the wafers are hybrid interconnects that include both dielectric-to-dielectric bonds and metal-to-metal bonds.

[0036] In Fig. 8, the semiconductor substrate 52 is thinned. The thinning can be performed using a CMP process, a grinding process, an etch-back process, or the like, or combinations thereof, and is performed on the inactive surface of the semiconductor substrate 52. The thinning exposes the conductive vias 56. After the thinning, the surfaces of the conductive vias 56 and the inactive surface of the semiconductor substrate 52 are coplanar (within process variations). Thus, the conductive vias 56 are exposed on the backside of the first wafer.

[0037] Through the thinning process, the parts 52P of the semiconductor substrate 52 remaining in the edge regions 52E are removed. Thus, the first sidewall 52S1, the second sidewall 52S2, the straight segment 52S4, the bent segment 52S5 and the notch 52N (see Fig. 6) is removed. After the thinning process, only the third sidewalls 52S3 of the semiconductor substrate 52 remain. As mentioned above, the third sidewalls 52S3 each have a first section 52S 3A and a second section 52S 3B (see Fig. 6). The third sidewalls 52S3 are the outermost sidewalls 52S of the thinned semiconductor substrate 52. Because the first wafer is trimmed prior to bonding, the sidewalls 52S, 102S of the semiconductor substrates 52, 102 are laterally offset from each other. For example, the sidewalls 52S of the semiconductor substrate 52 are laterally offset from the sidewalls of the semiconductor substrate 102 and the sidewalls of the interconnect structure 104. During bonding, some displacement may occur such that the centers of the die connectors 66 and the die connectors 116 are not laterally aligned, but contact enough of the surface of the die connectors 66 and the die connectors 116 to form electrical connections. Furthermore, since the first wafer is trimmed, the footprint of the semiconductor substrate 52 is laterally limited to the footprint(s) of the semiconductor substrate 102 and the interconnect structure 104.

[0038] In Fig. 9, a third wafer is formed or obtained. The third wafer includes a semiconductor substrate 152, an interconnect structure 154, conductive vias 156, one or more passivation layers 158, and contact pads 160, which may be similar to the semiconductor substrate 52, the interconnect structure 54, the conductive vias 56, the passivation layer(s) 58, and the contact pads 60, respectively. A dielectric layer 164 is formed on the front side of the wafer, e.g., on the contact pads 160 and the passivation layer(s) 158. Die connectors 166 are formed, extending through the dielectric layer 164 and the passivation layer(s) 158 to establish a physical and electrical coupling with the metallization patterns of the interconnect structure 154. The dielectric layer 164 and the die connectors 166 may be similar to the dielectric layer 64 and the die connectors 66, respectively.

[0039] The third wafer is then bonded to the first wafer. In the illustrated embodiment, the wafers are bonded back-to-front using hybrid bonding, such that the front side of the third wafer is bonded to the back side of the first wafer. The dielectric layer 164 is bonded to the semiconductor substrate 52 using dielectric-to-dielectric bonding without the use of an adhesive material (e.g., a die attach film), and the die leads 166 are connected to the conductive vias 56 using metal-to-metal bonding without the use of a eutectic material (e.g., solder). The bonding may include pre-bonding and annealing. During pre-bonding, a small pressing force is applied to press the wafers against each other. The pre-bonding is performed at a low temperature, e.g., room temperature.at a temperature in the range of about 15°C to about 30°C, and after pre-bonding, the dielectric layer 164 and the semiconductor substrate 52 are bonded together. In some embodiments, an oxide, such as a native oxide, is formed on the backside of the semiconductor substrate 52 and used for bonding. The bond strength is then improved in a subsequent annealing step in which the dielectric layer 164 and the semiconductor substrate 52 are annealed at a high temperature, for example, at a temperature in the range of about 100°C to about 400°C. After annealing, bonds, such as fusion bonds, are formed that bond the dielectric layer 164 and the semiconductor substrate 52 together. The bonds may be, for example, covalent bonds between the dielectric layer 164 and the semiconductor substrate 52.The die connectors 166 and the conductive vias 56 are connected to each other with a one-to-one correspondence. The die connectors 166 and the conductive vias 56 may be in physical contact after pre-bonding or may expand to be brought into physical contact during annealing. Furthermore, during annealing, the material of the die connectors 166 and the conductive vias 56 (e.g., copper) mixes, forming metal-to-metal bonds. Therefore, the resulting interconnects between the wafers are hybrid interconnects that include both dielectric-to-dielectric bonds and metal-to-metal bonds.

[0040] The third wafer may be trimmed before bonding and thinned after bonding in a similar manner as described above, so that the side walls 152S of the semiconductor substrate 152 also each have two sections, similar to the third side walls 52S3 of the semiconductor substrate 52, which are Fig. 6. Because the third wafer is trimmed prior to bonding, the sidewalls of the semiconductor substrate 152 and the semiconductor substrate 52 are laterally offset from each other. For example, the sidewalls 152S of the semiconductor substrate 152 are laterally offset from the sidewalls 52S of the semiconductor substrate 52 and the sidewalls of the interconnect structure 54. During bonding, some shifting may occur such that the centers of the die connectors 166 and the conductive vias 56 are not laterally aligned with each other, but contact enough of the surface of the die connectors 166 and the conductive vias 56 to form electrical connections. Furthermore, because the third wafer is trimmed, the footprint of the semiconductor substrate 152 is laterally constrained to the footprint(s) of the semiconductor substrate 102 and the interconnect structure 104.

[0041] The Fig. The steps described in Figures 7 to 9 can be repeated any number of times to form a stack of wafers. The stack may contain, for example, four wafers, eight wafers, or the like. After the wafer bonding is complete, a dicing process is performed by sawing along scribe line regions, for example, around the device regions 52D. The dicing process separates the component regions 52D from each other to form die stacks.

[0042] The Fig. 10A and Fig. 10B illustrate die stacks in accordance with some embodiments. Fig. 10A shows a first die stack 202A being singulated from a device region 52D located near the edge regions 52E. Fig. 10B shows a second die stack 202B being singulated from a device region 52D located distal to the edge regions 52E, e.g., in a central region of the wafers. For the first die stack 202A, the first sidewalls 52S A , 102S A , 152S A the semiconductor substrates 52, 102, 152 are laterally connected within process variations, but the second side walls 52S B , 102S B , 152S B the semiconductor substrates 52, 102, 152 are laterally offset from one another. The first side walls 52S A , 102S A , 152S A point in a different direction than the second side walls 52S B , 102S B , 152S B . For the second die stack 202B, the first side walls 52S are A , 102S A , 152S A the semiconductor substrates 52, 102, 152 laterally adjacent to each other (within process variations) and the second side walls 52SB , 102S B , 152S B The semiconductor substrates 52, 102, 152 are also laterally adjacent to one another. The coterminal sidewalls are the sidewalls that are sawn during singulation. The laterally offset sidewalls are the sidewalls that are trimmed before bonding.

[0043] The Fig. 11 to 15 are cross-sectional views of intermediate steps during a wafer bonding process, according to some other embodiments. In this embodiment, the second trimming process 80 is also a non-mechanical process, such as an etching process. As such, the sidewalls of the semiconductor substrate 52 may have a different profile shape than that described above with respect to Fig. 6 was described.

[0044] In Fig. 11, a first wafer similar to that in Fig. 3. Then, the first trimming process 70 and the second trimming process 80 are performed to remove the edge regions of the semiconductor substrate 52. The second trimming process 80, in this embodiment, is an etching process, such as a chemical process or an ablative process. The second trimming process 80 deepens the recesses 74 in the semiconductor substrate 52 by removing some portions of the semiconductor substrate 52 in the edge regions 52E. As previously mentioned, the portions 52P of the semiconductor substrate 52 remaining in the edge regions 52E are so thin that they can subsequently be removed by an etching or grinding process (discussed in more detail below).

[0045] In some embodiments, the second trimming process 80 is a chemical process, such as plasma etching. The plasma etching process may be similar to the plasma etching process discussed above with respect to the first trimming process 70, except that it may be performed with some different etching parameters than the first trimming process 70. In particular, the plasma etching process may be performed with a different etching gas(es) and with a different plasma generation power. When etching the semiconductor material(s) of the semiconductor substrate 52, suitable examples of the etching gas(es) include, for example, sulfur hexafluoride (SF6), a fluorocarbon (CxHyFz), argon (Ar), oxygen (O2), helium (He), or the like, or combinations thereof, and the plasma etching process may be performed using a high-power plasma generation power in the range of about 100 W to about 5000 W.

[0046] In some embodiments, the second trimming process 80 is an ablative process, such as laser etching. The laser etching process may be similar to the laser etching process discussed above with respect to the first trimming process 70, except that it may be performed with some different etching parameters than the first trimming process 70. In particular, the laser etching process may be performed at a different wavelength and with a different laser generation power. For example, when etching the semiconductor material(s) of the semiconductor substrate 52, the wavelength of the laser may range from about 300 nm to about 600 nm, and the average output power of the laser may range from about 1 W to about 30 W.

[0047] Fig. 12 is a detailed view of a region 50R after the second trimming process 80. In the illustrated embodiment, the second trimming process 80 is performed such that the semiconductor substrate 52, after the trimming process, has a first sidewall 52S1 and a second sidewall 52S2 in each edge region 52E. The first sidewall 52S1 and the second sidewall 52S2 are connected by a straight segment 52S3. The second sidewall 52S2 forms a first acute angle θ3 with the active surface of the semiconductor substrate 52 and also forms a second acute angle θ4 with the straight segment 52S3. The first acute angle θ3 may range from about 80 degrees to about 90 degrees, and the second acute angle θ4 may range from about 80 degrees to about 90 degrees.

[0048] In Fig. 13 a second wafer is used, similar to Fig. 7. The first wafer is then bonded to the second wafer. In the illustrated embodiment, the wafers are bonded in a face-to-face manner by hybrid bonding, such that the front side of the first wafer is bonded to the front side of the second wafer.

[0049] In Fig. 14, the semiconductor substrate 52 is thinned. The thinning can be carried out by a method similar to that described with respect to Fig. 8. After thinning, the surfaces of the conductive vias 56 and the inactive surface of the semiconductor substrate 52 are coplanar (within process variations). Thus, the conductive vias 56 are exposed on the backside of the first wafer. Even after thinning, the sidewalls 52S, 102S of the semiconductor substrates 52, 102 are laterally offset from one another.

[0050] In Fig. 15 a third wafer is used, similar to Fig. 9. The third wafer is then bonded to the first wafer. In the illustrated embodiment, the wafers are joined in a back-to-face manner by hybrid bonding, such that the front side of the third wafer is bonded to the back side of the first wafer.

[0051] The Fig. 16 to 20 are cross-sectional views of intermediate steps during a wafer bonding process, according to some other embodiments. In this embodiment, the second trimming process 80 is also a non-mechanical process, such as an etching process. As such, the sidewalls of the semiconductor substrate 52 may have a different profile shape than that described above with respect to Fig. 6. Furthermore, in this embodiment, the parameters of the second trimming process 80 are modified so that the sidewalls of the semiconductor substrate 52 can have a different profile shape than that described above with respect to Fig. 12 described.

[0052] In Fig. 16, a first wafer similar to that in Fig. 3. Then, the first trimming process 70 and the second trimming process 80 are performed to remove the edge regions of the semiconductor substrate 52. The second trimming process 80, in this embodiment, is an etching process, such as a chemical process or an ablative process. The second trimming process 80 deepens the recesses 74 in the semiconductor substrate 52 by removing some portions of the semiconductor substrate 52 in the edge regions 52E. As previously mentioned, the portions 52P of the semiconductor substrate 52 remaining in the edge regions 52E are so thin that they can subsequently be removed by an etching or grinding process (discussed in more detail below).

[0053] In some embodiments, the second trimming process 80 is a chemical process, such as plasma etching. The plasma etching process may be similar to the plasma etching process discussed above with respect to the first trimming process 70, except that it may be performed with some different etching parameters than the first trimming process 70. In particular, the plasma etching process may be performed with a different etching gas(es) and with a different plasma generation power. When etching the semiconductor material(s) of the semiconductor substrate 52, suitable examples of the etching gas(es) include, for example, sulfur hexafluoride (SF6), a fluorocarbon (CxHyFz), argon (Ar), oxygen (O2), helium (He), or the like, or combinations thereof, and the plasma etching process may be performed with a high-power plasma generation power in the range of about 100 W to about 5000 W.

[0054] In some embodiments, the second trimming process 80 is an ablative process, such as laser etching. The laser etching process may be similar to the laser etching process discussed above with respect to the first trimming process 70, except that it may be performed with some different etching parameters than the first trimming process 70. In particular, the laser etching process may be performed at a different wavelength and with a different laser generation power. For example, when etching the semiconductor material(s) of the semiconductor substrate 52, the wavelength of the laser may range from about 300 nm to about 600 nm, and the average output power of the laser may range from about 1 W to about 30 W.

[0055] Fig. 17 is a detailed view of a region 50R after the second trimming process 80. In the illustrated embodiment, the second trimming process 80 is performed such that the semiconductor substrate 52, after the trimming process, has a first sidewall 52S1 and a second sidewall 52S2 in each edge region 52E. The first sidewall 52S1 and the second sidewall 52S2 are connected by a straight segment 52S3. The second sidewall 52S2 forms a first right angle θ5 with the active surface of the semiconductor substrate 52 and also forms a second right angle θ6 with the straight segment 52S3.

[0056] In Fig. 18 a second wafer, similar to Fig. 7. The first wafer is then bonded to the second wafer. In the illustrated embodiment, the wafers are bonded in a face-to-face manner by hybrid bonding, such that the front side of the first wafer is bonded to the front side of the second wafer.

[0057] In Fig. 19, the semiconductor substrate 52 is thinned. The thinning can be carried out by a method similar to that described with respect to Fig. 8. After thinning, the surfaces of the conductive vias 56 and the inactive surface of the semiconductor substrate 52 are coplanar (within process variations). Thus, the conductive vias 56 are exposed on the backside of the first wafer. Even after thinning, the sidewalls 52S, 102S of the semiconductor substrates 52, 102 are laterally offset from one another.

[0058] In Fig. 20 a third wafer, similar to the one in Fig. 9. The third wafer is then bonded to the first wafer. In the illustrated embodiment, the wafers are bonded back-to-face using hybrid bonding, so that the front side of the third wafer is bonded to the back side of the first wafer. Subsequently, the semiconductor substrate 152 is thinned. After thinning, the sidewalls of the semiconductor substrate 152 and the semiconductor substrate 52 are laterally offset from each other.

[0059] The Fig. 21 to 25 are cross-sectional views of intermediate steps during a wafer bonding process according to some other embodiments. In this embodiment, the first trimming process 70 and the second trimming process 80 are performed at an earlier stage of wafer processing. In the embodiment of Fig. 21 to 25, a similar trimming process as that with regard to the Fig. 16 to 20. It should be understood that the first trimming process 70 and the second trimming process 80 may also be performed at an earlier stage of the Fig. 1 to 9 and in the Fig. 11 to 15 described process can be carried out.

[0060] In Fig. 21 a first wafer similar to the one in Fig. 1. The first trimming process 70 and the second trimming process 80 are then performed to remove the edge regions of the semiconductor substrate 52. In particular, the first trimming process 70 and the second trimming process 80 are performed before the dielectric layer 64 (see Fig. 22). After trimming is complete, the circuit can be tested with a probe 62 in a similar manner as in Fig. 2. Testing after trimming can help avoid further processing of wafers that could be damaged by trimming.

[0061] In Fig. 22, a dielectric layer 64 is formed on the front side of the wafer, e.g., on the contact pads 60 and the passivation layer(s) 58. Die terminals 66 extending through the dielectric layer 64 and the passivation layer(s) 58 are formed to establish a physical and electrical coupling with the contact pads 60. The dielectric layer 64 and the die connectors 66 may be formed in a similar manner as described with respect to Fig. 3. In this embodiment, the die connectors 66 are connected to the contact pads 60 instead of the metallization patterns 54A of the interconnect structure 54. In another embodiment, the die connectors 66 are connected to metallization patterns of the interconnect structure 54.

[0062] In Fig. 23, a second wafer similar to that in relation to Fig. 7. In this embodiment, the die connectors 116 are connected to the contact pads 110 instead of the metallization patterns of the interconnect structure 104. In another embodiment, the die connectors 116 are connected to metallization patterns of the interconnect structure 104. The first wafer is then bonded to the second wafer. In the illustrated embodiment, the wafers are bonded face-to-face by hybrid bonding, such that the front side of the first wafer is bonded to the front side of the second wafer.

[0063] In Fig. 24, the semiconductor substrate 52 is thinned. The thinning can be carried out by a method similar to that described with respect to Fig. 8. After thinning, the surfaces of the conductive vias 56 and the inactive surface of the semiconductor substrate 52 are coplanar (within process variations). As such, the conductive vias 56 are exposed on the backside of the first wafer. Because the dielectric layer 64 is formed before the first wafer is trimmed and thinned, the dielectric layer 64 extends along and contacts the sidewalls 52S of the semiconductor substrate 52. After thinning, the sidewalls 52S, 102S of the semiconductor substrates 52, 102 are laterally offset from one another.

[0064] In Fig. 25 a third wafer, similar to Fig.9. The third wafer is then bonded to the first wafer. In the illustrated embodiment, the wafers are bonded back-to-face using hybrid bonding, so that the front side of the third wafer is bonded to the back side of the first wafer. Subsequently, the semiconductor substrate 152 is thinned. After thinning, the sidewalls of the semiconductor substrate 152 and the semiconductor substrate 52 are laterally offset from each other.

[0065] Embodiments may achieve advantages. Trimming dielectric features (such as the interconnect structure 54) at the edges of a wafer using a non-mechanical process, such as an etching process, enables the trimming of fragile features, such as extra-low-K (ELK) dielectric layers, with a lower risk of damage compared to mechanical processes. Trimming semiconductor features (such as the semiconductor substrate 52) at the edges of a wafer using a mechanical process, such as sawing, enables the faster trimming of rigid features, thus improving wafer processing throughput. Alternatively, trimming semiconductor features (such as the semiconductor substrate 52) at the edges of a wafer using a non-mechanical process, such as an etching process, enables the simplification of wafer processing by avoiding the need to perform a sawing step.

[0066] In one embodiment, a method comprises: obtaining a first processed wafer comprising a first substrate and a first interconnect structure, the first substrate comprising a semiconductor material, the first interconnect structure comprising metal interconnects between dielectric material; removing an edge region of the first interconnect structure with a first trimming process, the first trimming process removing the dielectric material of the first interconnect structure at a faster rate than the semiconductor material of the first substrate; after removing the edge region of the first interconnect structure, removing an edge region of the first substrate with a second trimming process, the second trimming process removing the semiconductor material of the first substrate at a faster rate than the dielectric material of the first interconnect structure;and bonding a second processed wafer to a front side of the first processed wafer.;

[0067] In some embodiments of the method, the first trimming process removes the edge region of the first interconnect structure along a first direction, and the second trimming process removes the edge region of the first substrate along a second direction, wherein the first direction and the second direction form an obtuse angle, and the second direction is perpendicular to an active surface of the first substrate. In some embodiments of the method, the first trimming process is a first etching process.In some embodiments of the method, the first etching process is a plasma etching performed with a fluorocarbon, a fluorocarbon, or oxygen, wherein the plasma etching is performed with a plasma generation power in a range of 100 W to 5000 W, the plasma etching is performed at a pressure in a range of 133 mPa to 66.6 Pa (from 1 mTorr to 500 mTorr), and the plasma etching is performed for a duration in a range of 10 seconds to 600 seconds. In some embodiments of the method, the first etching process is a laser etching performed with a wavelength in a range of 300 nm to 600 nm, the laser etching is performed with a laser generation power in a range of 1 W to 30 W, and the laser etching is performed for a duration in a range of 10 -15 seconds to 10 -9seconds. In some embodiments of the method, the second trimming process is a mechanical process. In some embodiments of the method, the second trimming process is a second etching process, wherein the second etching process is performed with different etching parameters than the first etching process.In some embodiments of the method, bonding the second processed wafer to the first processed wafer comprises: depositing a first dielectric layer on the first processed wafer; forming first metal features in the first dielectric layer; depositing a second dielectric layer on the second processed wafer; forming second metal features in the second dielectric layer; forming dielectric-to-dielectric bonds between the first dielectric layer and the second dielectric layer; and forming metal-to-metal bonds between the first metal features and the second metal features. In some embodiments of the method, removing the edge region of the first substrate is performed after depositing the first dielectric layer on the first processed wafer.In some embodiments of the method, removing the edge region of the first substrate is performed before applying the first dielectric layer to the first processed wafer. In some embodiments, the method further comprises: obtaining a third processed wafer including a third substrate and a third interconnect structure; removing an edge region of the third interconnect structure with the first trimming process; after removing the edge region of the third interconnect structure, removing an edge region of the third substrate with the second trimming process; and bonding the third processed wafer to a backside of the first processed wafer, wherein a sidewall of the third substrate is laterally offset from a sidewall of the first substrate.

[0068] In one embodiment, a method comprises: obtaining a first processed wafer comprising a substrate and an interconnect structure; etching the interconnect structure to remove the interconnect structure from an edge region of the first processed wafer; after etching the interconnect structure, sawing the substrate to remove a first portion of the substrate in the edge region of the first processed wafer; bonding the first processed wafer to a second processed wafer; and thinning the substrate to remove a second portion of the substrate in the edge region of the first processed wafer.

[0069] In some embodiments of the method, etching the interconnect structure comprises etching the interconnect structure with a plasma etching process, wherein the plasma etching process removes a dielectric material of the interconnect structure at a faster rate than a semiconductor material of the substrate, wherein the dielectric material of the interconnect structure is not removed during sawing of the substrate. In some embodiments of the method, etching the interconnect structure comprises etching the interconnect structure with a laser etching process, wherein the laser etching process removes a dielectric material of the interconnect structure at a faster rate than a semiconductor material of the substrate, wherein the dielectric material of the interconnect structure is not removed during sawing of the substrate.

[0070] In one embodiment, an apparatus comprises: a first wafer having a first substrate and a first interconnect structure, wherein a sidewall of the first interconnect structure forms an obtuse angle with a sidewall of the first substrate; and a second wafer interconnected to the first wafer, the second wafer comprising a second substrate and a second interconnect structure, the sidewall of the first substrate being laterally offset from a sidewall of the second substrate and a sidewall of the second interconnect structure.

[0071] In some embodiments, the device further comprises: a dielectric layer bonding the second wafer to the first wafer, wherein a sidewall of the dielectric layer forms the obtuse angle with the sidewall of the first substrate. In some embodiments, the device further comprises: a dielectric layer bonding the second wafer to the first wafer, wherein the dielectric layer extends along the sidewall of the first interconnect structure and the sidewall of the first substrate. In some embodiments of the device, the sidewall of the first substrate has a first portion and a second portion, wherein the first portion connects the second portion to an active surface of the first substrate and the first portion forms the obtuse angle with the second portion.In some embodiments of the device, the sidewall of the first substrate forms a right angle with an active surface of the first substrate. In some embodiments of the device, the sidewall of the first substrate forms an acute angle with an active surface of the first substrate.

Claims

[1] Procedure comprising: Obtaining a first processed wafer comprising a first substrate and a first interconnect structure, the first substrate comprising a semiconductor material, the first interconnect structure comprising metal interconnects between dielectric material; Removing an edge region of the first interconnect structure with a first trimming process, wherein the first trimming process removes the dielectric material of the first interconnect structure at a faster rate than the semiconductor material of the first substrate; after removing the edge region of the first interconnect structure, removing an edge region of the first substrate with a second trimming process, wherein the second trimming process removes the semiconductor material of the first substrate at a faster rate than the dielectric material of the first interconnect structure; and Bonding a second processed wafer to a front side of the first processed wafer. [2] The method of claim 1, wherein the first trimming process removes the edge region of the first interconnect structure along a first direction, and the second trimming process removes the edge region of the first substrate along a second direction, the first direction and the second direction forming an obtuse angle, the second direction being perpendicular to an active surface of the first substrate. [3] The method according to claim 1 or 2, wherein the first trimming process is a first etching process. [4] The method according to claim 3, wherein the first etching process is a plasma etching performed with a fluorocarbon, a fluorocarbon or oxygen, wherein the plasma etching is performed using a plasma generation power in a range of 100 W to 5000 W, wherein the plasma etching is performed at a pressure in a range of 133 mPa to 66.6 Pa (from 1 mTorr to 500 mTorr), wherein the plasma etching is performed for a duration in a range of 10 seconds to 600 seconds. [5] The method according to claim 3, wherein the first etching process is laser etching performed with a wavelength in a range of 300 nm to 600 nm, the laser etching being performed with a laser generation power in a range of 1 W to 30 W, the laser etching being performed for a duration in a range of 10-15 seconds to 10-9 seconds. [6] A method according to any one of the preceding claims, wherein the second trimming operation is a mechanical operation. [7] The method according to any one of claims 3 to 5, wherein the second trimming process is a second etching process, wherein the second etching process is performed with different etching parameters than the first etching process. [8] A method according to any one of the preceding claims, wherein bonding the second processed wafer to the first processed wafer comprises: depositing a first dielectric layer on the first processed wafer; forming first metal features in the first dielectric layer; depositing a second dielectric layer on the second processed wafer; forming second metal features in the second dielectric layer; Forming dielectric-to-dielectric bonds between the first dielectric layer and the second dielectric layer; and Forming metal-to-metal bonds between the first metal features and the second metal features. [9] The method of claim 8, wherein removing the edge region of the first substrate is performed after depositing the first dielectric layer on the first processed wafer. [10] The method of claim 8, wherein removing the edge region of the first substrate is performed prior to depositing the first dielectric layer on the first processed wafer. [11] Method according to one of the preceding claims, further comprising: Obtaining a third processed wafer comprising a third substrate and a third interconnect structure; removing an edge region of the third interconnect structure with the first trimming process; after removing the edge region of the third interconnection structure, removing an edge region of the third substrate with the second trimming process; and Bonding the third processed wafer to a backside of the first processed wafer, wherein a sidewall of the third substrate is laterally offset from a sidewall of the first substrate. [12] Method comprising: Obtaining a first processed wafer comprising a substrate and an interconnect structure; etching the interconnect structure to remove the interconnect structure from an edge region of the first processed wafer; after etching the interconnect structure, sawing the substrate to remove a first part of the substrate in the edge region of the first processed wafer Bonding the first processed wafer to a second processed wafer; and Thinning the substrate to remove a second portion of the substrate in the edge region of the first processed wafer. [13] The method of claim 12, wherein etching the interconnect structure comprises etching the interconnect structure with a plasma etching process, wherein the plasma etching process removes a dielectric material of the interconnect structure at a faster rate than a semiconductor material of the substrate, and wherein the dielectric material of the interconnect structure is not removed during sawing of the substrate. [14] The method of claim 12 or 13, wherein etching the interconnect structure comprises etching the interconnect structure with a laser etching process, wherein the laser etching process removes a dielectric material of the interconnect structure at a faster rate than a semiconductor material of the substrate, and wherein the dielectric material of the interconnect structure is not removed during sawing of the substrate. [15] Device comprising: a first wafer comprising a first substrate and a first interconnect structure, wherein a sidewall of the first interconnect structure forms an obtuse angle with a sidewall of the first substrate; and a second wafer bonded to the first wafer, the second wafer having a second substrate and a second interconnect structure, the sidewall of the first substrate being laterally offset from a sidewall of the second substrate and a sidewall of the second interconnect structure. [16] The apparatus of claim 15, further comprising: a dielectric layer bonding the second wafer to the first wafer, wherein a sidewall of the dielectric layer forms the obtuse angle with the sidewall of the first substrate. [17] The apparatus of claim 15, further comprising: a dielectric layer bonding the second wafer to the first wafer, the dielectric layer extending along the sidewall of the first interconnect structure and the sidewall of the first substrate. [18] The device of any one of claims 15 to 17, wherein the sidewall of the first substrate comprises a first portion and a second portion, the first portion connecting the second portion to an active surface of the first substrate, the first portion forming the obtuse angle with the second portion. [19] The device of any one of claims 15 to 17, wherein the sidewall of the first substrate forms a right angle with an active surface of the first substrate. [20] The device of any one of claims 15 to 17, wherein the sidewall of the first substrate forms an acute angle with an active surface of the first substrate.

Images