Fieldbus system with switchable slew rate

Abstract

A circuit that features the following: an output stage (T H , T L ), which is connected to a first bus line (CANH) and a second bus line (CANL); a driver circuit (11) designed to drive the output stage (T H , T L ) depending on a first logic signal (DOUT) such that a corresponding bus voltage (V BUS ) is generated between the first bus line (CANH) and the second bus line (CANL); a slew rate control (16) coupled to the driver circuit (11) and configured to set a slew rate of the driver circuit (11) depending on an input signal (SR); and a monitoring circuit (15) configured to generate the input signal (SR) for the slew rate control (16), wherein the input signal (SR) indicates a higher slew rate during an arbitration phase of a data frame contained in the first logic signal (DOUT) than during a data transmission phase of the data frame.

Description

TECHNICAL AREA

[0001] The present description concerns the field of fieldbuses such as a Controller Area Network (CAN). BACKGROUND

[0002] The Controller Area Network (CAN) is one of the most widely used fieldbus systems in automotive applications. The network topology is typically star-shaped, and bus communication is implemented using differential signals, with a dominant state represented by a relatively high bus voltage (e.g., greater than 0.9 V) and a recessive state by a relatively low voltage (e.g., less than 0.5 V). In other fieldbus systems, these states are also referred to as "active" and "idle." In practical applications with a star-shaped bus topology, typically only a few bus nodes are properly terminated. Publication US 9,614,505 B1 describes a driver circuit for differential communication interfaces such as Controller Area Network (CAN).The driver circuit is designed to improve signal quality and electromagnetic compatibility (EMC) in high-speed CAN systems by compensating for asymmetries in the output current.

[0003] Especially at higher data rates, the integrity of the bus signal can be compromised by reflections from improperly terminated bus nodes or from low-impedance star points. As the rise and fall times of the bus signal decrease, signal integrity can deteriorate, which argues for slow transitions (i.e., a low slew rate) between dominant and recessive states (and vice versa). On the other hand, a low slew rate results in a relatively high loop delay. Particularly during the arbitration phase of bus communication, it can be crucial that the signals arrive at all bus nodes with minimal delay (relative to each other). Therefore, the loop delay should be sufficiently small to allow for proper arbitration. The relevant standards specify a maximum loop delay and thus indirectly a lower limit for the slew rate.

[0004] A simple way to ensure sufficient signal integrity is to limit the cable lengths for specific transmission rates (e.g., longer cable lengths for 2 Mbit / s and shorter cable lengths for 5 Mbit / s). Other approaches use transceiver circuits with temporary terminations, for example, immediately after a signal change is detected at the bus terminals. However, such transceiver circuits should only be used in bus nodes that lack proper electrical termination. If used in an already terminated bus node, signal integrity deteriorates; that is, the temporary termination used by the transceiver is counterproductive. Such transceivers with so-called ringing suppression can, under certain circumstances, also overwrite an error frame from a bus node that is important for the CAN protocol.

[0005] It is important to understand that the problems described are not limited to CAN systems and can also occur with other fieldbus systems. One object of the present invention can be seen, among other things, as providing a transceiver circuit for a fieldbus system—and in particular for a CAN system with a flexible data rate—that can be used in both terminated and unterminated bus nodes. SUMMARY

[0006] The aforementioned problem is solved by a circuit according to claim 1 and the method according to claim 11. Various embodiments and further developments are the subject of the dependent claims. A circuit for a bus driver is described below. According to one embodiment, the circuit comprises a driver circuit with slew rate control, an output stage, and a monitoring circuit. The output stage is connected to a first bus line and a second bus line, and the driver circuit is configured to control the output stage based on a first logic signal such that a corresponding bus voltage is generated between the first bus line and the second bus line. The slew rate control is coupled to the driver circuit and configured to set a slew rate of the driver circuit based on an input signal.The monitoring circuit is designed to generate the input signal for the slew rate control, whereby the input signal indicates a higher slew rate during an arbitration phase of a data frame contained in the first logic signal than during a data transmission phase of the data frame.

[0007] Furthermore, a method for controlling the bus lines of a data bus is described. According to one embodiment, the method comprises generating a bus voltage between a first bus line and a second bus line depending on a logic signal, wherein changes in the bus voltage are made with an adjustable slew rate. The method further comprises setting the slew rate, whereby a higher slew rate is set during an arbitration phase of a data frame contained in the logic signal than during a data transmission phase of the data frame. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The following illustrations explain exemplary embodiments in more detail. The illustrations are not necessarily to scale, and the exemplary embodiments are not limited to the aspects shown. Rather, the emphasis is placed on illustrating the underlying principles of the exemplary embodiments. Regarding the illustrations: Fig. Figure 1 illustrates an example of a CAN bus system with a large number of bus nodes. Fig. Figure 2 illustrates, using timing diagrams, a relationship between the line length and the ringing (diagram (a)) as well as the slew rate and the loop delay (diagram (b)) in a bus transceiver of a bus node. Fig. Figure 3 is a diagram illustrating the data frame in a flexible data rate (CAN FD) bus system. Fig. 4 and Fig. Figure 5 illustrates different variants of an exemplary embodiment of a transceiver circuit that can be used in a bus node. Fig. Figure 6 illustrates an alternative embodiment. Fig. Figure 7 illustrates an example of a bus node with a microcontroller and a CAN transceiver. Fig. Section 8 contains two flowcharts to illustrate an example of the procedure described here. DETAILED DESCRIPTION

[0009] Fig. Figure 1 illustrates an example of a CAN bus system with multiple bus nodes 101 to 108. The bus system has two subsystems, both with a star network topology. The first subsystem comprises bus nodes 101 to 105, each connected to a first star point SN1. The second subsystem comprises bus nodes 106 to 108, each connected to a second star point SN2. The two subsystems are coupled, for example, via a bus line connecting the first star point SN1 to the second star point SN2.

[0010] The bus lines between individual bus nodes 101 to 105 and the first star point SN1, as well as the bus lines between individual bus nodes 106 to 108 and the second star point SN2, can vary in length in practice. Line lengths can range from a few centimeters to several meters (e.g., 10 m or more). In the example shown, the maximum distance between two bus nodes is 13.3 m; bus node 104 is connected to the first star node SN1 via a 6.6 m long bus line. The two star nodes SN1 and SN2 are connected via a 2.1 m long bus line, and the second star node SN2 is connected to bus node 107 via a 4.7 m long bus line (6.6 + 2.0 + 4.7 = 13.3). The shortest distance (2.9 m line length) between two bus nodes is between bus nodes 106 and 108 (2 + 0.9 = 2.9). In the example shown, only bus nodes 104 and 107 each contain a termination resistance of 120Ω.

[0011] Optimal termination of all bus nodes is practically impossible, as the structure of the bus system (topology, line lengths, number of bus nodes) is unknown to the manufacturer of bus transceivers. Reflections at the bus nodes and star points, and the associated degradation of signal integrity, are unavoidable in practice.

[0012] However, for a specific bus topology, there is a relationship between the transmission rate and the maximum lengths of the bus lines. Some bus system developers therefore specify maximum line lengths for a given transmission rate. Another parameter relevant to signal integrity is the slew rate of the transmitter in a bus node. The slew rate specifies (usually in volts per microsecond or millivolts per nanosecond) the steepness of the edges that a transmitter can ideally generate (with perfect line termination). Thus, the slew rate can be considered a parameter of the transmitter circuitry in a bus node. However, the actual signal present at the bus node depends on the length of the bus line connected to the node and its termination. Fig. 2. The signal waveforms shown in diagrams (a) and (b) can be measured at the CANH and CANL pins of a CAN transceiver (in the diagrams in Fig. Figure 2, however, represents simulation results) to which a bus line was connected, the other end of which was connected to a 60Ω termination resistor. Both diagrams show step responses of the bus voltage V. BUS to a jump from approximately 2V to 0V. Fig. 2, Diagram (a), shows the (differential) bus voltage V BUS between the CANH and CANL pins at a transmitter circuit slew rate of 53 mV / ns and various line lengths from 1 m to 50 m. Fig. 2, Diagram (b), shows the bus voltage V BUS between the CANH and CANL pins over a cable length of 5 m and various slew rates between 25 mV / ns and 80 mV / ns. Fig. Diagram (b) 2 clearly shows that low slew rates lead to longer transmitter delays (with weaker oscillations). The transmitter delay is a part of the aforementioned loop delay and is the delay between a rising edge at the digital input (see Figure 2). Fig. 5, pin TXD) and the resulting low level of the bus voltage (this is defined as falling below the threshold for the recessive state). Longer lines and higher slew rates lead to stronger transient oscillations, which are referred to as ringing (see Fig. 2, Diagrams (a) and (b)).

[0013] The following examples relate to a CAN bus system, and in particular a CAN bus system with flexible data rate (FD), also known as a CAN FD system. CAN FD is an extension of the original CAN bus protocol specified in ISO 11898-1. The automotive standards SAE J2284-4:2016 and SAE J2284-5:2016 address high-speed CAN for automotive applications at 500 kbit / s with CAN FD data transmission at 2 Mbit / s and 5 Mbit / s, respectively. CAN FD is now included in the ISO 11898-1:2015 standard. It should be noted that the concepts described here are not necessarily limited to CAN and CAN FD systems and can, in principle, also be used in other fieldbus systems.In particular, the concepts and examples described here can also be used in future modifications and extensions of CAN FD systems, even if these are no longer referred to as CAN or CAN FD (sometimes such modifications are called "non-ISO CAN FD implementations"). Furthermore, it should be noted that applications using CAN systems are not necessarily limited to automotive applications. Besides automotive applications, CAN systems can also be used in general industrial applications.

[0014] Fig. Figure 3 illustrates a data frame in a CAN bus system with an 11-bit identifier (ID) (see Florian Hartwich, “CAN with flexible data-rate”, in: CAN Newsletter 2 / 2012, CAN in Automation GmbH, 2012). Accordingly, a data frame comprises an arbitration phase and a data transmission phase. Following the data transmission phase, the next arbitration phase is continued in the next data frame. The individual fields of a data frame and the bits contained within them are standardized, thus familiar to a specialist, and therefore not explained in detail here. For the examples described here, the FDF (FD Format) bit and the BRS (Bit Rate Switch) bit, which are contained in the control field, are relevant. The FDF bit allows a distinction between a CAN frame format and a CAN FD frame format. In CAN FD frames, the FDF bit is always recessive, followed by a dominant res bit.The `res` bit is a reserved bit that is always transmitted dominantly. The value of the `BRS` bit determines whether the bit rate in the data transmission phase is the same as in the arbitration phase (BRS dominant) or whether a predefined higher bit rate is used in the data transmission phase (BRS recessive). A switch in the bit rate from the standard rate to the predefined higher rate is therefore indicated by a bit sequence "FDF recessive, res dominant, BRS recessive" in the control field. The end of the data transmission phase is indicated by the `D` (delimiter) bit at the end of the `CRC` (cyclic redundancy check) field, and the standard rate is used again in the subsequent `ACK` (acknowledge) field. The designations of the individual bits are specified in the ISO 11898 standard.

[0015] During the arbitration phase, the data rate is typically 500 kbit / s or lower, and multiple bus nodes can transmit. To avoid collisions during bus communication in the arbitration phase, the bus nodes must be well synchronized, and the loop delay of the bus nodes must not exceed a maximum value. In the current ISO standard, the loop delay is specified at a maximum of 255 ns. This maximum value for the loop delay also indirectly determines a minimum value for the slew rate. This means that a slew rate that is too low would result in exceeding the maximum permissible loop delay (according to the ISO standard), and problems due to collisions during bus communication could occur during the arbitration phase.Due to the lower bit rate (which means longer bit durations), the bus voltage has more time to settle during the arbitration phase, and therefore a comparatively high slew rate is also uncritical (but results in a sufficiently low loop delay).

[0016] At the start of the data transmission phase, the system can switch to a higher bit rate, for example, 2 Mbit / s or 5 Mbit / s (or even more); and only the bus node with the highest priority that has "won" the arbitration transmits. During the data transmission phase, ringing is more problematic due to the shorter bit durations, whereas a comparatively large loop delay is not critical, since only one bus node transmits during a data transmission phase. Therefore, the slew rate can be reduced despite the higher data rate compared to the arbitration phase. In certain situations, the slew rate can even be reduced so drastically during the data transmission phase that the loop delay exceeds the specified maximum value. The loop delay simply results in a constant phase shift.

[0017] According to the concept described above, the slew rate is only temporarily reduced during the data transmission phase, whereas the transmitter applies a higher slew rate during the arbitration phase. Depending on the application and a given network topology, this can even enable higher bit rates or (for a given bit rate) greater transmission distances.

[0018] Fig. Figure 4 illustrates a first example of a transceiver circuit 10 configured to adjust the slew rate of the transmitter circuit contained within the transceiver circuit 10, whereby a higher slew rate (at a lower bit rate) is set during the arbitration phase of a data frame than during the data transmission phase. The transmitter circuit is essentially driven by an output stage (transistors T). H and T L) and a driver circuit 11 configured to drive the output stage. As mentioned, the slew rate can be considered a parameter of the transmitter circuit in a bus node, with the actual slew rate being determined by the driver circuit 11. Driver circuits capable of switching transistors with a specific, defined slew rate are known per se and are therefore not discussed further here (see, e.g., US 9,495,317 B2). The transceiver circuit 10 can be implemented as an integrated circuit and arranged in a chip package with multiple pins (e.g., CANL, CANL, TXD, RXD, etc.) (see also Fig. 5-7).

[0019] In the Fig. The example shown in section 4 is the output stage with transistors T H and T L trained to generate a bus signal which is expressed as a differential voltage V BUSThe output stage is located between the bus terminals CANH and CANL. This output stage is typical for a CAN bus system and may be designed differently in other bus systems. The transceiver circuit 10 also features a power supply terminal VCC and a ground terminal GND. During operation, the power supply terminal VCC is supplied with a voltage Vcc, and the ground terminal GND is connected to a reference potential V during operation. GND (e.g., ground potential) connected. The transistor T H couples the supply terminal VCC with the bus terminal CANH and the transistor T L couples the ground connection GND with the bus connection CANL. The transistors T H and T Lare designed to activate and interrupt a low-impedance current path between the supply terminal VCC and the bus terminal CANH, or a low-impedance current path between the bus terminal CANL and the ground terminal GND, according to the control signals output by the driver circuit 11. In the example shown, a diode D1 is connected in series with the load current path of transistor T. H switched to prevent reverse current flow. Similarly, a diode D2 can be connected in series with the load current path of transistor T. L The diodes D1 and D2 can also be omitted – depending on the actual implementation – and are therefore optional.

[0020] In the example shown, the transistor is T H as p-channel MOS transistor and the transistor T Limplemented as an n-channel MOS transistor. The aforementioned control signals, output by the driver circuit 11, are applied to the gate electrodes of transistors T. L and T H supplied. The transistors T L and T H Each transistor can have a multitude of transistor cells that can be sequentially switched on and off to generate switching edges with a desired slew rate. As mentioned, driver circuits designed to switch transistors with a defined slew rate are known per se (see, e.g., US 9,495,317 B2).

[0021] The transceiver circuit 10 from Fig. Section 4 further includes a transmit buffer (TX buffer 12) configured to receive a data signal at a digital input TDX of the transceiver circuit 10 and to output a corresponding logic signal DOUT. The logic signal DOUT is essentially a binary signal containing a bitstream of the data to be transmitted over the bus. Essentially, the TX buffer 12 is configured to buffer the received data and, if necessary, output it again as a logic signal DOUT at an adjusted level. The logic signal DOUT is fed to the driver circuit 11 as an input signal, and the driver circuit 11 generates suitable control signals based on the logic signal DOUT to control the output stage (transistors T). H and T L ) to control and a corresponding bus voltage V BUSto output between the bus terminals CANH and CANL. In other words, the transmitter circuit (driver circuit 11 with output stage) outputs the bus voltage V between the bus terminals CANH and CANL. BUS according to the bitstream contained in the logic signal DOUT.

[0022] The transceiver circuit 10 further includes a receiver circuit 13, which is connected to the bus terminals CANH and CANL to provide the bus voltage V BUS to receive and generate a corresponding logic signal DIN. That is, the receiver circuit 13 detects the level (low or high) of the bus voltage V. BUS (for example, by means of a comparator) and generates a binary signal (i.e., the logic signal DIN) which represents the current level of the bus voltage V. BUSThe transceiver circuit 10 further includes a receive buffer (RX buffer 14) that receives the logic signal DIN and outputs a corresponding data signal at the digital output RXD. Similar to the TX buffer 12, the RX buffer 14 essentially buffers the data contained in the logic signal DIN and, if necessary, performs level adjustment. Transceiver circuits for CAN systems with transmitter circuitry (driver circuitry 11 and output stage), receiver circuitry, TX and RX buffers are known per se and are therefore not described in more detail.

[0023] Additionally, the example from Fig. 5 a monitoring circuit with a protocol handler 15 and a slew rate control 16. In the in Fig. In the example shown in Figure 4, the protocol handler 15 is connected to the output of the TX buffer 12 to monitor the logic signal DOUT. That is, the protocol handler 15 receives the logic signal DOUT at its input and is configured to detect, taking into account the relevant bus protocol, when the arbitration phase ends and the data transmission phase begins, and conversely, when the data transmission phase ends and the next arbitration phase begins. The protocol handler 15 can be configured to generate a control signal SR, which indicates when a data transmission phase begins and ends. For example, the control signal SR output by the protocol handler 15 can be a logic signal that has a high level (e.g., logic 1) during a data transmission phase and a low level (e.g., logic 0) otherwise.Protocol handler 15 can, for example, include a finite state machine trained to detect the BRS bit or the sequence of FDF bit, res bit, and BRS bit to detect a transition from the arbitration phase to the data transmission phase. To detect the end of the data transmission phase, the finite state machine can also be trained to detect the delimiter bit at the end of the CRC field of a data frame (see...). Fig. 3).

[0024] The slew rate controller 16 receives the control signal SR and is configured to configure the driver circuit 11 to set the slew rate used by the driver circuit to a desired, defined value. As mentioned, a higher slew rate is used during the arbitration phase of a data frame, and a lower slew rate is used during the data transmission phase. For example, if a high level of the control signal SR indicates the data transmission phase (SR=1), then the slew rate controller 16 can reconfigure the driver circuit 11 to reduce the slew rate. Depending on the implementation of the driver circuit 11, this can be done in various ways. For example, one or more current sources in the driver circuit can be deactivated to reduce the current to transistors T. H and T Lto reduce the supplied gate current (which slows down the switching process). In the aforementioned example, where the transistors consist of a multitude of cells that are sequentially driven with a specific delay to switch the transistor at a defined slew rate, this delay can be increased (e.g., by changing a resistor or capacitance) to reduce the slew rate. The specific implementation of the driver circuit to enable switching at a defined slew rate is not important for the concepts described here and will therefore not be discussed further. Various suitable implementations of driver circuits and output stages are known to those skilled in the art.

[0025] Fig. Figure 5 illustrates a modification of the example from Fig. 4. In the example from Fig. In step 5, the protocol handler monitors the logic signal DIN, not the DOUT signal. Furthermore, the example is from... Fig. 5 identical to the example from Fig. 4 and reference is made to the description above. The logic signal DIN provided by the receiver circuit 13 contains—while the transmitter circuit is transmitting—essentially the same information as the logic signal DOUT, with the logic signal DIN being delayed relative to the signal DOUT by the aforementioned loop delay. However, a delay on the order of the loop delay is not critical when adjusting the slew rate, so the protocol handler 15 and the slew rate control 16 can be implemented essentially the same way as described above. Fig. The example shown in section 4 describes this. The logic signals DOUT and DIN contain the same information if recessive bits output to the bus line (pins CANH and CANL) are not overwritten by another bus node. The protocol handler could detect this and, if necessary, switch back to the arbitration phase (with a correspondingly higher slew rate).

[0026] According to another example, protocol handler 15 can monitor both logic signals, DIN and DOUT, to detect the end of the arbitration phase and the beginning of the data transmission phase. This is represented by the dashed line in Fig. 5 indicated. Monitoring both logic signals enables the detection of inconsistencies and thus the detection of errors in bus communication and a detection of a loss of arbitration.

[0027] Fig. Figure 6 illustrates another example of a transceiver circuit. This is essentially the same as the examples from Fig. 4 and Fig. 5, however, the example shows Fig. 6 does not have a protocol handler. Instead, the transceiver circuit 10 (i.e., the monitoring circuit contained therein, mentioned above) has an additional digital input SRIN configured to receive the control signal SR from an external circuit, such as a microcontroller connected to the transceiver circuit 10. The monitoring circuit may optionally include a buffer for storing the received control signal SR. The buffer may be constructed essentially the same way as the TX buffer 12. An example of an arrangement with a microcontroller 20 and an associated transceiver circuit 10 is shown in Fig. Figure 7 is shown (the power supply connections VCC and GND are omitted for simplicity). The microcontroller 20 is configured to generate a data signal (with one or more CAN data frames) to be sent via the CAN bus and to supply it to the TXD input of the transceiver circuit 10, which outputs a corresponding bus signal V. BUS The data signal is output at the CANH and CANL bus terminals, to which the bus line (e.g., a twisted-pair cable) is connected. The data signal output by the transceiver circuit 10 at the RXD output is received and processed by the microcontroller 20.

[0028] Since the microcontroller 20 generates the data signal (and the data frames it contains) supplied to the TX port, the microcontroller "knows" when the arbitration phase of a data frame is over and the data transmission phase begins. The microcontroller can generate the control signal SR, which is supplied to the SRIN input of the transceiver circuit 10 (see Fig. 7, dashed line). For example, the microcontroller 20 outputs a control signal SR at a high level simultaneously with the BRS bit of a data frame. As mentioned, the transceiver circuit 10 does not require a separate protocol handler in this case, and the slew rate controller 16 can process the control signal SR directly (see Fig. 6).

[0029] Fig. Section 8 contains two flowcharts (diagrams (a) and (b)) to illustrate an example of the procedure described here. According to Fig. 8, Diagram (a) includes the method for controlling a bus line, generating a bus voltage V BUS between a first bus line (connected to the CANH terminal) and a second bus line (connected to the CANL terminal) depending on a first logic signal DOUT, whereby changes in the bus voltage V BUS with an adjustable slew rate (see Fig. 8, Step S1; see also Fig. 4).

[0030] The procedure further includes setting the slew rate, whereby a higher slew rate is set during an arbitration phase of a data frame (contained in the first logic signal DOUT) than during the subsequent data transmission phase of the data frame (see Fig. 8, step S2). An example of how setting the slew rate can be implemented is in Fig. Figure 8, Diagram (b), shows in more detail. Accordingly, the first logic signal DOUT is monitored taking into account a bus protocol (see also Protocol Handler 15 in Fig. 4) to detect a bit (especially the BRS bit) which indicates the end of the arbitration phase (see Fig. 8, step 21). In response to the detection of the bit indicating the end of the arbitration phase (and thus the start of the data transmission phase), the slew rate is reduced by the transmitter circuit (in particular the driver circuit contained in the transmitter circuit, see 8, step 21). Fig. 4), which is the bus voltage V BUS is created, reconfigured (see Fig. 8, step 22).

Claims

[1] A circuit which has the following features: an output stage (T H , T L ), which is connected to a first bus line (CANH) and a second bus line (CANL); a driver circuit (11) designed to drive the output stage (T H , T L ) depending on a first logic signal (DOUT) such that a corresponding bus voltage (V BUS ) is generated between the first bus line (CANH) and the second bus line (CANL); a slew rate control (16) coupled to the driver circuit (11) and configured to set a slew rate of the driver circuit (11) depending on an input signal (SR); and a monitoring circuit (15) configured to generate the input signal (SR) for the slew rate control (16), wherein the input signal (SR) indicates a higher slew rate during an arbitration phase of a data frame contained in the first logic signal (DOUT) than during a data transmission phase of the data frame. [2] The circuit according to claim 1, further comprising: a transmit buffer (12) configured to receive a first data signal (TXD) and to provide the first logic signal (DOUT) representing the first data signal (TXD). [3] The circuit according to claim 2, further comprising: a receiver circuit (13) which is coupled to the first bus line (CANH) and the second bus line (CANL) to measure the bus voltage (V BUS ) to receive, and which is designed to generate a second logic signal (DIN) which represents a current level of the bus voltage (V BUS) represents; and a receive buffer (14) which is configured to output a second data signal (RXD) which represents the second logic signal (DIN). [4] The circuit according to any one of claims 1 to 3, wherein the monitoring circuit (15) has a protocol handler to which the first logic signal (DOUT) is supplied and which is configured to detect, based on the first logic signal (DOUT), when the arbitration phase ends and the data transmission phase begins according to a bus protocol. [5] The circuit according to claim 4, insofar as it relates back to claim 3, wherein the second logic signal (DIN) is also supplied to the protocol handler. [6] The circuit according to claim 3, wherein the monitoring circuit (15) has a protocol handler to which the second logic signal (DIN) is supplied and which is configured to detect, based on the second logic signal (DIN), when the arbitration phase ends and the data transmission phase begins according to a bus protocol. [7] The circuit according to any one of claims 1 to 3, wherein the monitoring circuit (15) has an input pin (SRIN) configured to receive a control signal indicating when, according to a bus protocol, the arbitration phase ends and the data transmission phase begins. [8] The circuit according to any one of claims 4 to 7, wherein the bus protocol is a CAN bus protocol. [9] The circuit according to any one of claims 4 to 6, wherein the bus protocol is a flexible data rate CAN bus protocol (CAN FD) and the protocol handler is configured to detect the bit rate switch (BRS) bit of a data frame. [10] The circuit according to any one of claims 4 to 6, wherein the protocol handler (15) is configured to detect the end of the data transmission phase. [11] A method which features: Generating a bus voltage (V BUS ) between a first bus line (CANH) and a second bus line (CANL) depending on a logic signal (DOUT, DIN), whereby changes in the bus voltage (V BUS ) with an adjustable slew rate; Setting the slew rate, whereby a higher slew rate is set during an arbitration phase of a data frame contained in the logic signal (DOUT; DIN) than during a data transmission phase of the data frame. [12] The method according to claim 11, wherein the adjustment of the slew rate comprises: Monitoring the logic signal (DOUT; DIN) taking into account a bus protocol; Detect when, according to the bus protocol, the arbitration phase ends and the data transmission phase begins, and Reducing the slew rate during the data transfer phase. [13] The method according to claim 12, where the bus protocol is a CAN bus protocol with flexible data rate (CAN FD) and the end of the arbitration phase is detected by detecting an FD format (FDF) bit and / or a bit rate switch (BRS) bit of a data frame. [14] The method according to claim 11, wherein the adjustment of the slew rate comprises: Detect when, according to the bus protocol, the data transmission phase ends and the next arbitration phase begins, and Change the slew rate at the beginning of the next arbitration phase to a standard value that is higher than the reduced value in the data transmission phase.

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