METHOD FOR PRODUCING SOURCE / DRAIN EPITAXIC LAYERS FOR TRANSISTORS

Abstract

A method comprising: forming a fin structure (160, 170, 300) comprising a first part and a second part located near the first part; forming a gate structure (190, 310) on the first part of the fin structure (160, 170, 300); removing the second part of the fin structure (160, 170, 300); and growing an S / D epitaxy structure (100) on the removed second part of the fin structure (160, 170, 300), wherein the growth of the S / D epitaxy structure (100) comprises: applying a precursor and one or more reaction gases to the removed part of the fin structure (160, 170, 300) to form part of the S / D epitaxy structure (100); applying Etching chemicals applied to the part of the S / D epitaxy structure (100), after exposure to the etching chemicals, hydrogen treatment applied to the part of the S / D epitaxy structure (100) to improve the growth of the S / D epitaxy structure (100),to form a hydrogen-terminated surface, and to allow further precursor action on the hydrogen-terminated surface to form another part of the S / D epitaxy structure (100), wherein the growth of the S / D epitaxy structure (100) comprises repeating the growth of the S / D epitaxy structure (100) for more than 9 cycles, the duration of hydrogen treatment increasing with each cycle.

Description

CROSS-REFERENCE TO RELATED REGISTRATION

[0001] This application claims priority over the preliminary US patent application No. 63 / 002,293 entitled “Source / Drain Epitaxial Layers for Transistor Reliability Improvement”, which was filed on March 30, 2020, and is hereby incorporated in its entirety by reference to it. GENERAL STATE OF THE ART

[0002] In fin field-effect transistors (FinFETs), source / drain epitaxy layers can be subject to material loss during subsequent processing steps such as cleaning, etching, and thermal treatment. This material loss can reduce the size of the source / drain epitaxy layers to such an extent that parts of the fin structures are exposed. This, in turn, leads to degraded transistor performance, fluctuating transistor performance, and reliability issues. List of characters

[0003] Aspects of this revelation are best understood by studying the detailed description below along with the accompanying figures. The Fig. 1A and Fig. Figure 1B shows isometric views of source / drain epitaxy structures formed between two fin structures according to some embodiments. Fig. Figure 1C is an isometric view of a source / drain epitaxy structure formed at an end part of a fin structure according to some embodiments. Fig. Figure 1D is a cross-sectional view of a source / drain epitaxy structure formed at an end part of a fin structure according to some embodiments. Fig. Figure 1E is an isometric view of a source / drain epitaxy structure formed between two fin structures according to some embodiments, wherein a gate structure is formed on one of the fin structures. Fig. Figure 2 is a flowchart for a method for forming hexagonal source / drain epitaxy structures according to some embodiments. The Fig. 3 and Fig. Figure 4 shows isometric views of intermediate structures during the fabrication of a source / drain epitaxy structure according to some embodiments. The Fig. 5 to Fig. Figure 7 shows cross-sectional views of intermediate structures during the fabrication of a hexagonal source / drain epitaxy structure according to some embodiments. DETAILED DESCRIPTION

[0004] The following disclosure provides various embodiments or examples for implementing different features of the respective subject matter. To simplify the present disclosure, certain examples of components and arrangements are described below. These are, of course, merely examples and are not intended to represent a limitation. For example, the following description of the formation of a first feature on a second feature may include embodiments in which the first and second features are in direct contact, as well as embodiments in which additional features can be formed that lie between the first and second features, such that the first and second features are not in direct contact.

[0005] Terms with spatial reference, such as "below," "under," "lower," "above," "over," "upper," and the like, can also be used here to simplify the description and describe the relationship of an element or feature to one or more other elements or features, as illustrated in the figures. In addition to the orientation shown in the figures, these terms with spatial reference are intended to encompass other orientations of the component during use or operation. The device may be oriented differently (rotated by 90 degrees or in a different orientation), and the descriptors with spatial reference used here can be interpreted accordingly.

[0006] The term "nominal" here refers to a target or setpoint value for a characteristic or parameter of a component or process step, which, together with a series of values ​​above and / or below the target value, is defined during the design phase for a product or process. The range of values ​​is generally due to slight deviations in manufacturing processes or tolerances.

[0007] In some embodiments, the terms "approximately" and "essentially" may indicate a value of a certain magnitude that varies within 5% (e.g., ±1%, ±2%, ±3%, ±4%, ±5%) of the value. These values ​​are, of course, merely examples and are not intended to constitute a limitation. The terms "approximately" and "essentially" may refer to a percentage of the values, which is subject to interpretation by experts trained in the relevant fields based on the teaching presented here.

[0008] The term "vertical" here nominally means perpendicular to the surface of a substrate.

[0009] In a fin-based field-effect transistor (FinFET), source / drain epitaxy structures (S / D epitaxy structures) are grown in physical contact with the end portions of the transistor's fin structure such that each end portion of the fin structure is essentially covered by a side face of the S / D epitaxy structure. Since the S / D epitaxy structure contains multiple crystalline epitaxy layers and can exhibit crystallographic orientations with higher growth rates than others, the final shape of the S / D epitaxy structures is determined by the growth rate achieved in each crystallographic orientation. For example, a rhomboid-shaped S / D epitaxy structure is grown because a higher growth rate in an orientation perpendicular to the silicon crystal plane ( 100 ) direction (e.g. GR)

[100] ) is higher than a growth rate in a plane perpendicular to the silicon crystal plane ( 111 ) direction (e.g. GR)

[111] ). The resulting rhomboid S / D epitaxy structures develop where the silicon crystal planes ( 111 ) meet, edge-like upper surfaces. Due to width and height requirements in the FinFET design, the rhomboid S / D epitaxic structures are grown such that their edge-like upper surfaces cover the upper corners of the fin structure's end parts.

[0010] S / D epitaxic structures tend to lose material during subsequent processing steps such as cleaning, etching, and thermal processes. These steps can reduce the size of S / D epitaxic structures to such an extent that the upper corners of the fin endpoints become exposed. This reduction in size is not uniform across all S / D epitaxic structures. For example, some S / D epitaxic structures may experience greater material loss than others. This processing-related inconsistency in material loss can lead to differences in the final dimensions of the S / D epitaxic structures and ultimately result in performance variations among the transistors. Furthermore, exposed fin endpoints are potentially susceptible to defects.

[0011] In light of the aforementioned problems, the embodiments described here relate to methods for forming hexagonal S / D epitaxy structures. The hexagonal S / D epitaxy structures described here can be advantageous compared to other (e.g., rhomboid) S / D epitaxy structures because they adequately cover the end portion of the fin structure, even if they are subject to material loss due to subsequent processing steps. In some embodiments, the hexagonal S / D epitaxy structures are grown such that their upper corners, which abut the end portions of the fin structure, are higher than the upper corners of the fin structure. In some embodiments, the corners of the hexagonal S / D epitaxy structure near the upper corners of the fin structure are at least approximately 2 nm higher than the upper corners of the fin structure.In some embodiments, the growth of hexagonal S / D epitaxy structures is achieved by means of hydrogen treatment during growth. According to some embodiments, the hydrogen treatment can increase the growth rate in a manner perpendicular to the silicon crystal plane ( ). 111 ) direction (e.g. GR)

[111] ) increase.

[0012] In some embodiments Fig. 1A an isometric view of a hexagonal S / D epitaxy structure 100 (S / D epitaxy structure 100) between adjacent fin structures 110 and 120 , each on a substrate 130 are trained. As in Fig. As shown in Figure 1A, the S / D epitaxic structure 100 essentially covers the end faces. 110S and 120s the fin structures 110 and 120 . To others in Fig. The structural elements shown in 1A include an insulation layer. 140 and an S / D spacer 150.

[0013] In some embodiments, the fin structures are 110 and 120 to end parts of a single fin structure 160 , which are separated by the S / D epitaxy structure 100. The S / D epitaxy structure 100 is applied, for example, to an excluded part of the single fin structure. 160 grew up in Fig. 1A contains the excluded part of the single fin structure 160 , which is not shown, below an upper surface of the insulation layer 140 . Fig. Figure 1B, for example, shows the structure of Fig. 1A without the S / D spacer 150, so that a lower section 100b the S / D epitaxy structure 100 on an excluded part of the single fin 160 is visible. As in Fig. As shown in Figure 1B, the S / D epitaxic structure 100 extends through the insulation layer. 140 up to the end faces 110s and 120s the end parts 110 and 120for the fin structure 160 .

[0014] In some embodiments, the S / D epitaxic structure 100 is applied to an excluded end part of a fin structure such as the one in Fig. Fin structure shown in 1C 170 grew up.

[0015] Based on the above, the S / D epitaxy structure 100 can be as in Fig. 1A shown between fin structures, as in Fig. 1B shown on an extruded central portion of a single-fin structure, as in Fig. 1C shown on an excluded end portion of a single fin structure or combinations thereof. The combinations mentioned do not constitute a limitation, and further combinations fall within the scope and protection of this disclosure.

[0016] In some embodiments, each of the features in the Fig. 1A, Fig. 1B and Fig. The fin structures shown in Figure 1C exhibit a gate structure formed on them. To simplify the description, these gate structures are shown in the Fig. 1A, Fig. 1B and Fig. 1C not shown. Fig. 1E shows, as a non-restrictive example, the structure from Fig. 1A with a fin structure 120 trained, exemplary gate structure 190 In some embodiments, the fin structure is used. 110 a similar (not shown) gate structure is formed. In some embodiments, the gate structure is... 190 to create a sacrificial gate structure with a gate electrode 190a , a gate dielectric 190b , Gate spacers 190c and a top layer 190d In some embodiments, the S / D epitaxic structure 100 is located at the gate spacers. 190c the gate structure 190 on. The gate spacers 190c insulate the gate electrode 190aelectrically from the S / D epitaxy structure 100. In some embodiments, the gate structure 190 After the formation of the S / D epitaxy structure 100, it is replaced by a metal gate structure. In subsequent figures, gate structures formed on the fin structures are not shown for the sake of simplicity. Gate structures such as the gate structure 190 However, the fin structures presented here fall within the scope and protection of this revelation.

[0017] In some embodiments, the following are included: Fig. 1A, Fig. 1B and Fig. 1C shown fin structures 160 and 170A single crystalline material or a stack of crystalline layers in the form of nanosheets. The crystalline materials (or crystalline nanosheet layers) mentioned may include silicon (Si), germanium (Ge), a compound semiconductor (e.g., silicon carbide, gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), indium antimonide (InSb)), an alloy semiconductor (e.g., silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), gallium indium arsenide phosphide (GaInAsP), or combinations thereof). The substrate 130 It can also contain a crystalline material similar to that of the fin structures 110 and 120 or the individual fin structures 160 and 170 resembles or differs from it.

[0018] Fin structures can be formed by structuring using any suitable method. For example, fin structures can be structured using one or more photolithography processes, such as double or multiple structuring processes. Double or multiple structuring processes can combine photolithography with self-alignment processes, allowing the creation of structures with, for example, smaller spacing than those achievable with a single direct photolithography process. For example, a fin structure on the substrate can be created using a single, direct photolithography process. 130 A sacrificial layer is structured using a photolithography process. Spacers are formed along the structured sacrificial layer using a self-aligning process. The sacrificial layer is then removed, and the remaining spacers can be used to structure the fin structures.

[0019] For illustrative purposes and to simplify the description, the substrate 130 and the fin structures described here are related to monolithic crystalline silicon fin structures. Based on the disclosure presented here, other materials and / or nanosheet layers can be used, as explained above. These other materials and layers fall within the scope of this disclosure.

[0020] In some embodiments, the S / D epitaxic structure 100 has Fig. 1C a substantially planar upper surface 100t on, which are parallel to the silicon crystal plane ( 100 ) runs. In some embodiments, the silicon crystal plane ( 100 ) parallel to the xy-plane, e.g. parallel to an upper surface of the substrate 130 and an upper surface of the fin structure 170Compared to a diamond-shaped S / D structure, the upper surface offers 100t The S / D epitaxy structure 100 provides a larger contact area for an S / D contact formed thereon. Thus, the S / D epitaxy structure 100 offers lower contact resistance compared to a rhomboid-shaped S / D epitaxy structure according to some embodiments.

[0021] One at a right angle to the silicon crystal plane ( 100 The direction extending is denoted by

[100] and runs parallel to the vertical direction z. According to some embodiments, facets extend 100f the S / D epitaxy structure 100 parallel to the silicon crystal plane ( 111 ) or to their equivalent crystal planes {111}. In some embodiments, the facets 100f referred to as “facets (111)”. One at a right angle to the silicon crystal plane ( 111 ) or the direction extending to their equivalent crystal planes {111} is as in Fig. 1C shown with

[111] . In some embodiments the silicon crystal plane ( 110 ) parallel to the xz-plane, e.g. parallel to side wall surfaces 170s the fin structure 170 A direction perpendicular to (110) is denoted by

[110] and proceeds as in Fig. 1C shown parallel to the yz plane.

[0022] In some embodiments, Fig. 1D to create a cross-sectional view of Fig. 1C along line AB. As explained above, the S / D epitaxic structure 100 covers the terminal part. 170e the fin structure 170 Essentially. In particular, the facets form 100f , which, as explained above, are parallel to the silicon crystal plane ( 111 ) run at an angle θ, such that the smallest distances d1 and d2 between upper facets 100f near the upper corners of the fin structures and the upper corners of the fin structure 170more than approximately 2 nm (e.g., d1, d2 > 2 nm). This ensures that the upper corners of the fin structure 160 even if, according to some embodiments, the size of the S / D structure 100 decreases during one or more subsequent processing steps. As in Fig. The top surface is shown in 1D. 100t the S / D epitaxic structure is 100 times higher than the upper surface 170t the fin structure 170 The height difference between 100t and 170t can, for example, be up to approximately 30 nm. The aforementioned features of the S / D epitaxy structure 100 are also evident in the isometric views of Fig. 1A, Fig. 1B and Fig. 1C shown.

[0023] In some embodiments, the width W resembles SDThe S / D epitaxy structure 100 essentially has the same width as the rhomboid S / D epitaxy structure. Thus, similar FinFET densities can be achieved with S / D epitaxy structures 100 as with rhomboid D epitaxy structures. In some embodiments, the width W SD in the range between approximately 5 nm and approximately 100 nm. As in Fig. As shown in 1D, the width W runs SD the S / D epitaxy structure 100 parallel to the yz-plane or to the direction

[110] in Fig. 1C. In some embodiments, an S / D epitaxic structure 100 has a width W SD of less than about 5 nm, a d1 and a d2, which is less than about 2 nm. An S / D epitaxic structure 100 with a width W SD However, dimensions larger than approximately 100 nm can touch D-epitaxy structures of neighboring FinFETs, leading to electrical short circuits.

[0024] As in Fig. As shown in 1D, the upper surface 100tthe S / D epitaxy structure 100 parallel to the width W SD (e.g. parallel to the yz-plane or to the direction

[110] ) a width Wt. In some embodiments, the width Wt of the upper surface 100t in the range between approximately 2 nm and approximately 80 nm.

[0025] In some embodiments, there is an angle Θ between facets. 100f The angle θ formed by the S / D epitaxic structure 100 is between approximately 109° and 180°. In some embodiments, the angle θ is larger than the angle formed by the facets of a rhomboid S / D epitaxic structure. This is because the angle formed by the facets of the rhomboid S / D epitaxic structure is limited to a range between approximately 40° and approximately 70°. Due to this limitation, the facets of a rhomboid S / D epitaxic structure intersect above the upper surface. 170t the fin structure 170 and form a planar upper surface instead of a 100tan edge. This in turn limits the distance between the facets and the upper corners of the fin structure. 170 to less than about 2 nm, even if the S / D width is essentially W SD This corresponds to (e.g., lies between approximately 5 nm and approximately 100 nm). For example, in a rhomboid S / D epitaxy structure, the distance between the facets and the upper corners of the fin structure is... 170 (e.g. the equivalent of the distances d1 and d2 in Fig. 1D) in the range between 0 nm and approximately 2 nm. This means that the upper corners of the fin structure can be exposed if material loss occurs in a rhomboid S / D epitaxy structure due to one or more subsequent processing steps.

[0026] The S / D epitaxy structure 100 is, as explained above, placed on an excluded part of the fin structure. 170 trained. The S / D epitaxy structure 100 in Fig. 1D, for example, refers to an excluded part. 170r the fin structure 170 During the initial phase of epitaxial growth, the S / D epitaxial layers of the S / D epitaxial structure 100 are enclosed by the S / D spacers 150. Therefore, the lower part of the S / D epitaxial structure 100 has no facets and is grown vertically (e.g., in the z-direction), with lateral growth being limited by the S / D spacers 150. In some embodiments, the S / D spacers 150 are positioned before the fin structure is formed. 170 trained and have a height of 150 H on, which lies in the range between approximately 10 nm and approximately 18 nm. In some embodiments, the fin structure 170 to pay an exemption amount 180 , which lies in the range between approximately 5 nm and approximately 10 nm, extending below the upper surface of the insulating layer 140excepted. If the S / D epitaxic layers have grown beyond the enclosure by the S / D spacer 150, lateral growth will proceed as described in Fig. 1D continued. In some embodiments, the height H sD the S / D epitaxy structure 100 when measured from the upper surface of the removed part 170r as in Fig. 1D shown in the range of approximately 90 nm to approximately 95 nm.

[0027] According to some embodiments, Fig. 2. To create a flowchart for a process 200 , which the manufacturing process for the in Fig. 1C and Fig. The S / D epitaxy structure shown in 1D is described in Figure 100. The procedure 200 is not on the in Fig. 1C and Fig. The S / D epitaxy structure shown in 1D is limited to 100 and can be used to form the in Fig. 1A and Fig. The S / D epitaxy structure shown in 1B is used. Between the different steps of the procedure...200 Other manufacturing steps may be carried out, which may have been omitted for the sake of clarity. These various steps fall within the scope and protection of this disclosure. Furthermore, not all steps may be necessary to carry out the disclosure presented here. Some steps may be performed simultaneously or in a different order than those described in Fig. The procedures described in section 2 are carried out as follows: 200 limited. The exemplary procedure 200 will be with reference to the Fig. 3 to Fig. 7 described.

[0028] The procedure 200 in Fig. 2 begins with step 210 and the process of forming a fin structure on a substrate with an insulating layer surrounding a lower part of the fin structure, as in Fig. 3 fin structure shown300 In some designs, the fin structure resembles 300 the in Fig. Fin structure shown in 1C 170 and the one in Fig. 1A and Fig. Fin structure shown in 1B 160 As above regarding the fin structures 170 and 160 As explained, the fin structure 300 The fin structure can be monolithic (e.g., made from a single crystalline material) or have alternating layers of different materials (e.g., alternating epitaxially grown nanosheet layers). 300 can be made, for example, from crystalline silicon (C-Si) or have a stack of alternating layers, such as alternating C-Si and crystalline silicon germanium (SiGe) nanosheet layers.

[0029] Fig. Although version 3 only has a single fin structure, this does not pose a limitation. Additional fin structures, such as the fin structure explained above, can be added. 300 on the substrate 130 They can be formed. For example, groups of two or more fin structures can be arranged according to a chip layout on different areas of the substrate. 130 be trained.

[0030] The fin structure 300 is through the insulating layer 140 separated from (not shown) adjacent fin structures. In some embodiments, the insulating layer consists of 140 to use a silicon-based dielectric based on the fin structure 300 and the substrate 130 deposited, then planarized in a chemical-mechanical polishing process (CMP process) and removed in an isotropic etching process to a height at which a lower part of the fin structure is removed.300 is covered. The one covered by the insulation layer. 140 covered part of the fin structure 300 is in Fig. Figures 3 and subsequent figures are shown with dashed lines. As in Fig. As shown in section 3, the fin structure is 300 in physical contact with the substrate 130 formed, and the insulating layer 140 is designed in such a way that it forms the lower sidewall surfaces and lower end parts of the fin structure 300 covered. In some embodiments and after the aforementioned recessing step, the fin structure exhibits 300 a height H above the excluded insulation layer 140 which lies in the range between approximately 30 nm and approximately 35 nm. The fin structure 300 It also has a width W that lies in the range between approximately 3.5 nm and 5 nm.

[0031] In some embodiments, part of the fin structure is 300covered with a gate structure (e.g. masked), which is in Fig. 3 as shaded area 310 This is shown. As a non-restrictive example, the gate structure covers a central part of the fin structure. 300 and subdivides these as in Fig. 3 shown in two exposed end parts 300A and 300B . Regarding the masked parts of the fin structure 300 The fin structure includes an upper part and a side wall part. 300 The gate structure extends further, as shown in the shaded area. 310 shows, on the insulation layer 140 In some embodiments, the gate structure extends to adjacent fin structures, which are in Fig. 3 are not shown. As a non-restrictive example, neighboring fin structures can be similar to the fin structure. 300 They share a single gate structure. In some embodiments, this serves as the shaded area.310 The depicted gate structure serves as a mask layer for subsequent etching steps.

[0032] The procedure 200 in Fig. 2 moves at a pace 220 and the process of forming S / D spacers 150 on the lower sidewall surfaces of the fin structure 300 , for example at the in Fig. 3 exposed end parts shown 300A and 300B , continued. The S / D spacers 150 can be designed as follows as a non-restrictive example. The S / D spacer material can be applied across the entire surface of the end pieces. 300A and 300B , which is through the shaded area 310 depicted gate structure and the insulation layer 140 The S / D spacer material is then deposited. Following this, an anisotropic etching process is used to remove the S / D spacer material from horizontal surfaces, such as surfaces parallel to the xy-plane, like the horizontal surfaces of the end pieces.300A and 300B , the insulation layer 140 and the shaded area 310 , etched. Consequently, the remaining S / D spacer material forms on the lower sidewall surfaces of the end pieces. 300A and 300B the S / D-Spacer 150. In some embodiments, S / D-Spacer material not removed from vertical sidewall surfaces of the gate structure can be removed if necessary in additional photolithography and etching steps.

[0033] As explained above, the height of the S / D spacer 150 is in the range of approximately 3 nm to approximately 5 nm. The S / D spacer material can, as a non-limiting example, contain a nitride (e.g., silicon nitride, silicon carbonitride, silicon oxynitride, etc.) which, with respect to the fin structure, 300 (e.g. silicon) and the insulating layer 140 (e.g., a silicon oxide-based dielectric) can be selectively etched.

[0034] The procedure 200 in Fig. 2 then proceeds at a pace 230 and the process of etching the fin structure 300 between the S / D spacers 150 for the purpose of excluding the fin structure 300 (e.g. for removing the end parts) 300A and 300B) with regard to the insulation layer 140 as in Fig. 4 continued. In some embodiments, the gate structure (e.g., shaded area) is used. 310 ) masked parts of the fin structure 300 not as in Fig. Except as shown in section 4. In some embodiments, the fin structure is included among the features to be excluded. 300 at step 230 The etching chemicals used were chlorine- or fluorine-based gases that could selectively etch silicon instead of nitrides or oxides. As explained above, the fin structure 300 below an upper surface of the insulation layer 140 to pay an exemption amount 200 (e.g. in Fig. (shown in 1D) excepted, which lies in the range between approximately 5 nm and approximately 10 nm. According to some embodiments, at step 230 between the S / D spacers 150 as in Fig. Figure 4 shows a recess opening 400 educated.

[0035] In some embodiments, if the fin structure 300The material contains alternating nanosheet layers, such as silicon and silicon-germanium nanosheet layers, and the etching process is either dry, wet, or a combination thereof. In some embodiments, the etching chemicals are selective with respect to the Si nanosheet layers and the SiGe nanosheet layers. In some embodiments, a dry etching process may include etchants containing an oxygen-containing gas, a fluorine-containing gas (e.g., tetrafluoromethane (CF4), sulfur hexafluoride (SF6), difluoromethane (CH2F2), trifluoromethane (CHF3) and / or hexafluoroethane (C2F6)), a chlorine-containing gas (e.g., chlorine (Cl2), chloroform (CHCl3), tetrachloromethane (CCl4) and / or boron trichloride (BCl3)), a bromine-containing gas (e.g., hydrogen bromide (HBr) and / or bromoform (CHBr3)), an iodine-containing gas, other suitable etching gases and / or plasmas or combinations thereof.A wet etching process can involve etching in dilute hydrofluoric acid (vFW acid), potassium hydroxide solution (KOH solution), ammonia, a solution containing hydrofluoric acid (HF), nitric acid (HNO3), acetic acid (CH3COOH), or combinations thereof. In some embodiments, the etching chemicals etch the insulating layer. 140 , the S / D spacer 150 and the gate stack (e.g., shaded area) 310 ) not significant.

[0036] In some embodiments, Fig. 5 to get a cross-sectional view of the in Fig. 4 fin structure shown 300 along line CD. In Fig. 5 is the non-exempted part of the fin structure 300 e.g. the part of the fin structure masked by the gate structure 300 , behind the excluded part 300r the fin structure 300 .

[0037] The procedure 200 in Fig. 2 moves at a pace 240and the process of the growth of the S / D epitaxy structure 100 on the excluded part 300r the fin structure 300 between the S / D spacers 150. In some embodiments, the S / D epitaxy structure for n-FinFET contains elongated, carbon-doped silicon (Si:C), phosphorus-doped silicon (Si:P), or arsenic-doped silicon (Si:As). The S / D epitaxy structure for p-FinFET contains elongated, boron-doped SiGe (SiGe:B), boron-doped Ge (G:B), or boron-doped germanium-tin (GeSn:B). As a non-restrictive example, the amount of P incorporated into the S / D epitaxy structure for n-FinFET can be approximately 3 × 10 21 atoms / cm- 3 and the amount of B incorporated into the S / D epitaxy structure for p-FinFET is approximately 1 × 10 21 atoms / cm- 3The concentrations of phosphorus (P) and boron (B) dopants can be incorporated during the growth process, for example, by using phosphine or diborane, respectively. As a non-limiting example, the concentration of carbon (C) in Si:C can be a maximum of approximately 5 mol%. The concentration of geinoide (Ge) in SiGe can range from approximately 20 mol% to approximately 40 mol%. Furthermore, the concentration of tin (Sn) in GeSn can range from approximately 5 mol% to approximately 10 mol%. The dopant and atomic concentrations mentioned above are non-limiting examples. Therefore, other dopant and atomic concentrations also fall within the scope of protection of the embodiments described herein.

[0038] In some embodiments, the S / D epitaxy structure can contain one or more layers that are successively formed with different dopant and / or atomic concentrations. According to some embodiments, the S / D epitaxy structure is grown with a hexagonal shape, as is the case for the S / D epitaxy structure 100 in the Fig. 1C and Fig. Figure 1D shows the S / D epitaxy structure as a non-restrictive example. This structure can be deposited by chemical vapor deposition (CVD) at temperatures of approximately 680°C for Si:P and Si:As, between approximately 600°C and 700°C for Si:C, approximately 620°C for SiGe, between approximately 300°C and 400°C for GeSn, and between approximately 500°C and 600°C for Ge.

[0039] In some embodiments, Si:C, Si:P, or Si:As S / D epitaxy structures are formed with SiH4 and / or dichlorosilane precursors (DCS precursors) in the presence of H2 and / or N2. SiGe S / D epitaxy structures are formed with SiH4, disilane (Si2H6), or monogerman (GeH4) precursors in the presence of H2, N2, helium (He), argon (Ar), or combinations thereof.

[0040] In the initial phase of the growth process, the S / D-Spacer 150, as explained above, suppress the lateral growth of the S / D epitaxic structure and promote vertical growth, as seen in Fig. Figure 6 shows the S / D epitaxy structure 100. As soon as the S / D epitaxy structure 100 is taller than the S / D spacer 150, facets begin to form. In some embodiments and in Fig. 1C a rhomboid S / D epitaxy structure is formed when the growth rate is in the direction of

[100] (GR

[100] ) is significantly higher (e.g. 5 to 10 times higher) than the growth rate in the direction of

[111] (GR

[111] ) (e.g. GR)

[100] >> GR

[111] ). If, however, GR

[100] is significantly lower (e.g., 5 to 10 times lower) than GR

[111] (e.g. GR)

[100] << GR

[111] ), then a hexagonal S / D epitaxy structure is formed, as in Fig. S / D epitaxy structure 100 shown in 1A-D. In some embodiments, the hexagonal shape for the in Fig. To achieve the S / D epitaxy structure 100 shown in 1A-D, the growth conditions for the S / D epitaxy structure 100 can be adjusted so that the growth rate accelerates in the direction of

[111] and decreases or slows down in the direction of

[100] .

[0041] In some embodiments, the S / D epitaxy structure 100 is formed during the growth process of the procedure. 200Hydrochloric acid vapor (HCl vapor) is introduced to remove atomic nuclei from S / D epitaxy material from surfaces of surrounding layers such as the surfaces of the insulation layer. 140 , the S / D-Spacer 150 and the one through the shaded area 310 to remove the depicted gate structure. Thus, HCl vapor removes (e.g., etching) S / D epitaxy material grown on surfaces outside the excluded end parts. 300r the fin structure 300During the action of the HCl vapor, chlorine atoms are chemisorbed onto exposed surfaces of the S / D epitaxy material, and the surfaces of the S / D epitaxy structure are chlorine-terminated (e.g., the surfaces of the S / D epitaxy structure are chemically passivated with chlorine atoms). In some embodiments, the density of chemisorbed chlorine atoms is higher on surfaces {111} than on other surfaces, such as surfaces {100}. In some embodiments, chlorine-terminated surfaces inhibit facet growth. 100f compared to the upper surface 100t , when the precursor and reaction gases are reintroduced and the growth process continues. In other words, the growth rate is increased in the direction of

[111] (GR.[ 111]) artificially reduced by the chlorine atoms chemisorbed on the surfaces of the S / D epitaxy structure. This is an undesirable side effect of chlorine-terminated surfaces, since the S / D epitaxy structure, when GR.[ 111] is larger than GR.[ 111] , as explained above, grows in a diamond shape. For chlorine-terminated surfaces, the difference between GR

[100] and GR

[111] furthermore, it depends on the growth temperature. This means that the difference between GR

[100] and GR

[111] GR is greater in S / D epitaxic structures grown at high temperatures than in S / D epitaxic structures grown at low temperatures.

[100] and GR

[111] For example, the saturation is higher for Si:C epitaxy layers grown at 700°C than for GeSn epitaxy layers grown at a lower temperature (e.g., between approximately 300°C and approximately 400°C). This effect can lead to the formation of p- and nS / D epitaxy structures of different widths and facet angles.

[0042] In some embodiments, to form S / D epitaxic structures of the same width and with the same facet angles after the action of HCl vapor in order to increase the growth rate in the direction of

[111] (GR

[111] ) and promote the growth of hexagonal S / D epitaxy structures, a hydrogen treatment (H treatment) is used. In some embodiments, the H treatment also increases the growth rate in the direction of

[110] (GR

[110] ).

[0043] In some embodiments, the H treatment leads to a hydrogen-chlorine exchange process in which chlorine atoms on the surfaces of the S / D epitaxic structure are replaced by hydrogen atoms, thus forming hydrogen-terminated (H-terminated) surfaces (e.g., the surfaces of the S / D epitaxic structure are chemically passivated with hydrogen atoms). The H-terminated surfaces result in an advantageous shift in the growth rate in the direction of

[111] and

[100] . In some embodiments, the H treatment includes the application of atomic hydrogen ( H2) (e.g., hydrogen gas) or hydrogen radicals generated by a remote hydrogen plasma from which the ions have been removed (e.g., by means of an ion filter) are applied to the chlorine-terminated surfaces. In some embodiments, if ions are present in the plasma during the hydrogen treatment, undesired ion bombardment and / or charge transfer may occur. In some embodiments, the hydrogen treatment takes place at a process pressure between approximately 0.1 Torr and approximately 10 Torr and a process temperature between approximately 50°C and approximately 400°C. High-frequency (HF) or direct current (DC) plasma sources are within the scope of this disclosure. In some embodiments, the plasma power may be in the range of approximately 200 W to approximately 5 kW.

[0044] In some embodiments, the growth process for the S / D epitaxy structure can be described as follows. The growth process begins with the introduction of the precursor and the reaction gases to the structure made of Fig. 5, to support the growth of the in Fig. To stimulate 100 S / D epitaxy structures as shown in 6. In this step, on the removed part 300r thicker S / D epitaxy material layers and on surrounding surfaces, such as the surfaces of the insulation layer 140 , the S / D-Spacer 150 and the one through the shaded area 310 In the depicted gate structure, significantly thinner layers are formed. The growth process is then interrupted, and the structure is removed from surrounding surfaces outside the recess to allow for the removal of the thin S / D epitaxy material layers. 300rexposed to HCl vapor. During exposure to the HCl vapor, part of the S / D epitaxy material is also removed (e.g., etched) from the partially manufactured S / D epitaxy structure 100. However, since the S / D epitaxy material is located on the recessed part 300r S / D epitaxy material remains on the part after the HCl vapor exposure step, where it is thicker on one surface and thinner on other. 300r Back. After exposure to HCl vapor, the exposed surfaces of the partially manufactured S / D epitaxy structure 100 are chlorine-terminated as explained above.

[0045] Subsequently, the partially fabricated S / D epitaxy structure 100 is subjected to hydrogen treatment with molecular hydrogen or ion-free hydrogen radicals, allowing the Cl-terminated surfaces to be converted into H-terminated surfaces. In some embodiments, when the precursor and reaction gases are reintroduced and the growth of the S / D epitaxy structure 100 is thus continued, the H-terminated surfaces promote the growth of facets. 100f (e.g., they increase the growth rate towards

[111] (GR)

[111] ) compared to the growth rate in the direction of

[100] (e.g. GR)

[100] )). Thus, the growth mode of the S / D epitaxy structure 100 shifts from GR.

[100] > > GR

[111] to GR

[100] < < GR[ 111] In some embodiments, GR[ 111] Due to the H treatment described above, approximately 5 to 10 times higher than GR

[100] .

[0046] The above process steps – precursor action, HCl vapor action, and H treatment – ​​can be repeated in N cycles, thus achieving the desired results. Fig. 7 generates the hexagonal S / D epitaxy structure 100 shown. In some embodiments, the duration of the H treatment (also referred to as the "exposure time") in each cycle N is between about 1 s and about 100 s (e.g., about 10 s). In some embodiments, the exposure time in one cycle may be the same as in other cycles or may differ from it. For example, the H treatment may last about 10 s in one cycle and about 10 s in a subsequent cycle, longer than about 10 s, or less than about 10 s. The dashed lines in Fig. Figure 7 depicts the S / D epitaxic structure 100 in different growth phases. The growth process for the S / D epitaxic structure 100 is terminated when d1 and d2 are in Fig. 1D greater than or equal to approximately 2 nm and W SD between approximately 5 nm and approximately 100 nm.

[0047] In some embodiments, the process parameters of the hydrogen treatment, such as the exposure time, the hydrogen dose, and the plasma power, can be used to adjust the angle θ between the in Fig. 1D shown facets 100f can be used. For example, the angle θ can increase with each cycle of increasing exposure time to the H-treatment.

[0048] The steps of precursor action, HCl vapor action, and H treatment are carried out sequentially in N cycles, as explained above. In some embodiments, N is required to generate the Fig. The hexagonal S / D epitaxy structure shown in Figure 7 has 100 more cycles than approximately 9 (e.g., N > 9). Furthermore, each of the N cycles includes a hydrogen treatment with an exposure time between approximately 1 s and approximately 100 s.

[0049] The embodiments described here relate to hexagonal S / D epitaxy structures. These hexagonal S / D epitaxy structures offer advantages over other S / D epitaxy structures (e.g., rhomboid S / D epitaxy structures) because they adequately cover the end portion of the fin structure, even if material loss occurs during subsequent processing steps. In some embodiments, the hexagonal S / D epitaxy structures are grown such that their upper corners, which abut the end portions of the fin structure, are higher than the upper corners of the fin structure. In some embodiments, the corners of the hexagonal S / D epitaxy structures are at least 2 nm higher than the upper corners of the fin structure. In some embodiments, hydrogen treatment is used during the growth of the S / D epitaxy structure to promote the growth of facets parallel to the silicon crystal plane ( 111) to promote. In some embodiments, the H treatment is used after exposure to HCl vapor. During the H treatment, chlorine-terminated surfaces of the S / D epitaxy structure can be converted into hydrogen-terminated surfaces, which increases the growth rate in a structure perpendicular to the silicon crystal plane ( 111 increase in the direction of travel.

[0050] In some embodiments, a structure comprises a substrate with a fin structure, which further comprises a first part and a second part that is taller than the first. The structure also includes an insulating layer on the substrate that covers the lower sidewalls of the second part and the sidewalls of the first part of the fin structure. Furthermore, the structure features an S / D epitaxy structure grown onto the first part of the fin structure such that the distance between a facet of the S / D epitaxy structure near an upper corner of the second part of the fin structure is greater than approximately 2 nm.

[0051] In some embodiments, a method comprises forming a fin structure with a first part and a second part located near the first part, forming a gate structure on the first part of the fin structure, and removing the second part of the fin structure. The method further comprises growing an S / D epitaxy structure on the removed second part of the fin structure, wherein the growth of the S / D epitaxy structure includes applying a precursor and one or more reactant gases to the removed second part of the fin structure to form part of the S / D epitaxy structure. The growth of the S / D epitaxy structure further comprises applying etching chemicals to the part of the S / D epitaxy structure and subjecting the part of the S / D epitaxy structure to hydrogen treatment to improve the growth of the S / D epitaxy structure.

[0052] In some embodiments, a method comprises forming a fin structure on a substrate, forming a gate structure on a portion of the fin structure, and etching portions of the fin structure adjacent to the gate structure. The method further comprises growing an S / D epitaxy structure on the etched portions of the fin structure, wherein the growth of the S / D epitaxy structure includes the partial growth of the S / D epitaxy structure on the etched portions of the fin structure. The growth of the S / D epitaxy structure further comprises applying etching chemicals to the partially grown S / D epitaxy structure to terminate surfaces of the partially grown S / D epitaxy structure with chlorine atoms and treating the partially grown S / D epitaxy structure with hydrogen to increase the growth rate of the partially grown S / D epitaxy structure in a plane perpendicular to a crystal plane ( 111) in the direction running.

[0053] It is understood that the detailed description, and not the summary of the disclosure, should be used to interpret the claims. The summary of the disclosure may present one or more, but not all, embodiments of the present disclosure considered by the inventor(s) and is therefore not intended to limit the accompanying claims in any way.

[0054] The above disclosure provides an overview of features of several embodiments to make the aspects of the present disclosure more understandable to those skilled in the art. It should be clear to those skilled in the art that they can readily use the present disclosure as a starting point for designing or modifying other processes and structures for the same purposes and / or to achieve the same advantages as the embodiments presented here. It should also be clear to those skilled in the art that such equivalent designs do not deviate from the concept and scope of protection of the present disclosure and that they can make various changes, substitutions, and modifications to them without deviating from the concept and scope of protection of the present disclosure. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 63002293

[0001]

Claims

[1] Structure comprising the following: a substrate, a fin structure on the substrate with a first part and a second part that is higher than the first, an insulating layer on the substrate, covering the lower side walls of the second part of the fin structure and the side walls of the first part of the fin structure, and a source / drain epitaxy structure (S / D epitaxy structure) that has grown onto the first part of the fin structure such that a distance between a facet of the S / D epitaxy structure near an upper corner of the second part of the fin structure is greater than about 2 nm. [2] Structure according to claim 1, wherein the facet near the upper corner of the second part of the fin structure is parallel to a crystal plane (111). [3] Structure according to claim 1, wherein the S / D epitaxy structure has a hexagonal shape. [4] Structure according to claim 1, wherein an upper surface of the S / D epitaxy structure is substantially planar and runs parallel to an upper surface of the fin structure. [5] Structure according to claim 1, wherein a side surface of the S / D epitaxy structure touches a side surface of the second part of the fin structure and [6] Structure according to claim 1, wherein a further facet of the S / D epitaxy structure adjoins the facet and forms an angle of more than 70° with the facet. [7] Structure according to claim 1, wherein the width of the S / D epitaxy structure in a direction perpendicular to the crystal plane (110) is between about 5 nm and about 100 nm. [8] Structure according to claim 1, wherein the S / D epitaxy structure comprises an upper surface with a width in a direction perpendicular to a crystal plane (110) which is in the range between about 2 nm and about 80 nm. [9] Structure according to claim 1, further comprising: Spacers on the insulation layer, which lie against the lower side walls of the S / D epitaxic structure, and a gate structure on the second part of the fin structure, wherein the gate structure is adjacent to a part of a side surface of the S / D epitaxy structure that does not overlap a side surface of the second part of the fin. [10] Method comprising the following: Forming a fin structure comprising a first part and a second part located near the first part, Forming a gate structure on the first part of the fin structure, Excluding the second part of the fin structure and Growth of a source / drain epitaxy structure (S / D epitaxy structure) on the excluded second part of the fin structure, wherein the growth of the S / D epitaxy structure comprises the following: Applying a precursor and one or more reaction gases to the removed part of the fin structure to form part of the S / D epitaxy structure, Exposure of corrosive chemicals to the part of the S / D epitaxy structure and Applying hydrogen treatment to the part of the S / D epitaxy structure to improve the growth of the S / D epitaxy structure. [11] Method according to claim 10, wherein the application of the etching chemicals to the part of the S / D epitaxy structure comprises the application of hydrochloric acid vapor to the fin structure for the purpose of removing the S / D epitaxy material from surfaces outside the excluded second part of the fin structure. [12] Method according to claim 10, wherein the application of the hydrogen treatment to the part of the S / D epitaxy structure comprises the application of a hydrogen gas or hydrogen radicals generated by an ion-free remote plasma. [13] Method according to claim 10, wherein the application of the hydrogen treatment to the part of the S / D epitaxy structure comprises converting chlorine-terminated surfaces of the S / D epitaxy structure into hydrogen-terminated surfaces. [14] Method according to claim 10, wherein the growth of the S / D epitaxy structure comprises repeating the growth of the S / D epitaxy structure for more than 9 cycles and the hydrogen treatment for each cycle comprises an exposure time of between about 1 second and about 100 seconds. [15] Method comprising the following: Forming a fin structure on a substrate, Forming a gate structure on part of the fin structure, Etching of parts of the fin structure adjacent to the gate structure and Growth of a source / drain epitaxy structure (S / D epitaxy structure) on the etched parts of the fin structure, wherein the growth of the S / D epitaxy structure comprises the following: partial growth of the S / D epitaxy structure on the etched parts of the fin structure, Exposure of corrosive chemicals to the partially grown S / D epitaxy structure, wherein the corrosive chemicals terminate surfaces of the partially grown S / D epitaxy structure with chlorine atoms, and Treating the partially grown S / D epitaxy structure with hydrogen to increase the growth rate of the partially grown S / D epitaxy structure in a direction perpendicular to a crystal plane (111). [16] Method according to claim 15, wherein the treatment of the partially grown S / D epitaxy structure comprises the application of hydrogen gas or ion-free hydrogen radicals to the partially grown S / D epitaxy structure. [17] Method according to claim 15, wherein the growth of the S / D epitaxy structure comprises forming a hexagonal S / D epitaxy structure with adjoining facets (111) forming an angle of more than about 70°. [18] Method according to claim 15, wherein the growth of the S / D epitaxy structure comprises the growth of a hexagonal S / D epitaxy structure with upper facets (111) that are spaced more than about 2 nm apart from the upper corners of the fin structure which are covered with the gate structure. [19] Method according to claim 15, wherein the treatment of the partially grown S / D epitaxy structure comprises terminating the surfaces of the partially grown S / D epitaxy structure with hydrogen atoms. [20] Method according to claim 15, wherein the treatment of the partially grown S / D epitaxy structure comprises converting the chlorine-terminated surfaces of the partially grown S / D epitaxy structure into hydrogen-terminated surfaces.