Wafer-level packaging of solid-state biosensors, microfluidics and silicon through-hole technology

Abstract

Biosensor system package (200, 3100), comprising: a transistor structure (210) in a semiconductor layer (208) having a front and a back side, wherein the transistor structure (210) has a channel region (219); a multilayer interconnect structure (212) on the front side of the semiconductor layer (208), wherein the transistor structure (210) is electrically connected to the multilayer interconnect structure (212); a support substrate (220) on the multilayer interconnect structure (212); a first substrate through-hole via structure (246) extending through the support substrate (220) and configured to establish an electrical connection between the multilayer interconnect structure (212) and a separate die (250, 250-1, 250-2); a buried oxide layer (206) on the back side of the semiconductor layer (208), wherein the buried oxide layer (206) has an opening (222) on the back side of the channel region (219) and an interface layer (224) covers the back side above the channel region (219); and a microfluidic channel cap structure (228) attached to the buried oxide layer (206), wherein the microfluidic channel cap structure (228) comprises a cap structure substrate (230) with a chamber (244) and a high-k dielectric oxide layer (242) covering a bottom and side walls of the chamber (244).

Description

BACKGROUND

[0001] Biosensors are devices for sensing and detecting biomolecules and operate based on electronic, electrochemical, optical, and mechanical detection principles. Biosensors, which include transistors, are sensors that electrically detect charges, photons, and mechanical properties of biobodies or biomolecules. Detection can occur through the recognition of the bioelements or biomolecules themselves or through interaction and reaction between specific reactants and bioelements / biomolecules. Such biosensors can be manufactured using semiconductor processes, can rapidly convert electrical signals, and are easily applied to integrated circuits (ICs) and microelectromechanical systems (MEMS).

[0002] US 2017 / 0 158 500 A1 and US 2016 / 0 320 337 A1 describe conventional biosensor semiconductor structures. DE 10 2018 124 826 A1 describes a MEMS package and a method for achieving differential pressure adjustment in cavities. US 2011 / 0 244 676 A1 discloses a substrate via structure (TSV structure). BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Aspects of this disclosure are best understood by reference to the following detailed description taken in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various elements are not drawn to scale. Indeed, the dimensions of various elements may be arbitrarily exaggerated or reduced for clarity of illustration. Fig. 1A is a block diagram of an example biosensor system according to some embodiments. Fig. Figure 1B is a schematic diagram of an exemplary biosensor used in a biosensor system of Fig. 1A is used, according to some embodiments. Fig. 2 is a cross-sectional diagram illustrating a biosensor system package according to some embodiments. Fig. 3A and Fig. 3B are flow diagrams illustrating a method for manufacturing the biosensor system package from Fig. 2 illustrate some embodiments. Fig. Figure 3C is a flowchart showing a step of the method of Fig. 3A and Fig. 3B according to some embodiments. Fig. 4 to 24 are cross-sectional diagrams showing the biosensor package obtained after one or more of the steps of the method of Fig. 3A and Fig. 3B, according to some embodiments. Fig. 25A and Fig. 25B are flow diagrams illustrating another method of manufacturing the biosensor system package according to some embodiments. Fig. 26 to 30 are cross-sectional diagrams showing the biosensor package obtained after one or more of the steps of the method of Fig. 25A and Fig. 25B, according to some embodiments. Fig. 31 is a cross-sectional diagram illustrating a biosensor system package according to some embodiments. Fig. 32A and Fig. 32B are flow diagrams illustrating a method for manufacturing the biosensor system package from Fig. 31 according to some embodiments. Fig. 32C is a flowchart illustrating a step of the method of Fig. 32A to 32B according to some embodiments. Fig. 33 to 47 are cross-sectional diagrams showing the biosensor package obtained after one or more of the steps of the method of Fig. 32A and Fig. 32B, according to some embodiments. Fig. 48 is a cross-sectional diagram illustrating a biosensor system package according to some embodiments. DETAILED DESCRIPTION

[0004] The following disclosure provides many different embodiments or examples for implementing various functions of the presented content. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, in the following description, forming a first element or a second element may include embodiments in which the first and second elements are formed in direct contact, and may also include embodiments in which additional elements may be formed between the first and second elements such that the first and second elements need not be in direct contact. Furthermore, this disclosure may repeat reference numbers and / or letters of the various examples.This repetition is for simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations explained.

[0005] Furthermore, spatially relative terms such as "beneath," "underneath," "lower," "above," "upper," and the like may be used herein for convenience of description to describe the relationship of one element or feature to one or more other elements or features as illustrated in the figures. The spatially relative terms are intended to encompass various orientations of the device in use or operation, in addition to the orientation shown in the figures. The device may be oriented differently (rotated 90 degrees or in another orientation), and the spatially relative terms used herein may also be interpreted accordingly.

[0006] In general, the term "BioFET" as used herein refers to a field-effect transistor (FET) comprising a layer of immobilized capture reagents that act as surface receptors to detect the presence of a target analyte of biological origin. A BioFET, in some embodiments, is a field-effect sensor with a semiconductor transducer. One advantage of BioFETs is the expectation of label-free operation. In particular, BioFETs allow the avoidance of costly and time-consuming labeling procedures, such as labeling an analyte with, for example, fluorescent or radioactive probes. The analytes for detection by a BioFET are typically of biological origin, such as—without limitation—proteins, carbohydrates, lipids, tissue fragments, or sections thereof.A BioFET may be a subset of a broader class of FET sensors that can also detect any chemical compound (referred to as a "ChemFET") or any other element, including ions such as protons or metal ions (referred to as an "ISFET"). This disclosure applies to all types of FET-based sensors ("FET Sensor").

[0007] A "capture reagent" as used herein is a molecule or compound capable of binding the target analyte or target reagent and capable of being bound directly or indirectly to a substantially solid material. The capture reagent can be a chemical, and specifically any substance for which a naturally occurring target analyte exists (e.g., an antibody, a polypeptide, DNA, RNA, a cell, a virus, etc.) or for which a target analyte can be prepared, and the capture reagent can bind to one or more target analytes in an assay.

[0008] A "target analyte" as used herein is the substance to be detected in the test sample using the present disclosure. The target analyte can be a chemical, and specifically any substance for which a naturally occurring capture reagent exists (e.g., an antibody, a polypeptide, DNA, RNA, a cell, a virus, etc.) or for which a capture reagent can be prepared, and the target analyte can bind to one or more capture reagents in an assay. The "target analyte" also includes any antigenic substance, antibody, or combination thereof. The target analyte can include a protein, a peptide, an amino acid, a carbohydrate, a hormone, a steroid, a vitamin, a drug (including those administered for therapeutic purposes as well as those administered for illicit purposes), a bacterium, a virus, and metabolites of, or antibodies to, any of the above-mentioned substances.

[0009] A "test sample" as used herein means the composition, solution, substance, gas, or liquid comprising the target analyte to be detected and analyzed using the present disclosure. The test sample may comprise, in addition to the target analyte, other components that have physical properties of a liquid or gas and be of any size or volume, including, for example, in the form of a moving liquid or gas stream. The test sample may comprise any substances other than the target analyte, as long as the other substances do not interfere with the binding of the target analyte to the capture reagent or the specific binding of the first binding member to the second binding member. Examples of test samples include, but are not limited to, naturally occurring and non-naturally occurring samples, or combinations thereof. Naturally occurring test samples may be synthetic or synthesized.Naturally occurring test samples include body or body fluids isolated from anywhere in or on the body of a subject, including, but not limited to, blood, plasma, serum, urine, saliva or sputum, spinal fluid, cerebrospinal fluid, pleural fluid, nipple aspiration, lymph fluid, respiratory, intestinal and genitourinary tract fluid, tear fluid, saliva, breast milk, lymphatic system fluid, semen, cerebrospinal fluid, organ system fluid, ascites fluid, tumor cyst fluid, amniotic fluid, and combinations thereof, as well as environmental samples such as ground or wastewater, soil extracts, air and pesticide residues or food-related samples.

[0010] The detected substances may include, for example, nucleic acids (including DNA and RNA), hormones, various pathogens (including a biological agent that causes disease or suffering in its host, such as a virus (e.g., H7N9 or HIV), a protozoan (e.g., Plasmodium that causes malaria), or a bacterium (e.g., E. coli or Mycobacterium tuberculosis)), proteins, antibodies, various drugs or therapeutics, or other chemical or biological substances, including hydrogen or other ions, non-ionic molecules or compounds, polysaccharides, small chemical compounds such as members of the chemical combinatorial library, and the like. Detected or determined parameters may include, but are not limited to, pH changes, lactose changes, concentration changes, particles per unit time where a liquid flows over the device for a specific time to detect particles (e.g.,sparse particles) and other parameters.

[0011] As used herein, the term "immobilized," when used, for example, in reference to a capture reagent, essentially encompasses the attachment of the capture reagent to a surface at the molecular level. For example, a capture reagent can be immobilized to a surface of the substrate material using adsorption techniques, such as non-covalent interactions (e.g., electrostatic forces, van der Waals forces, and dehydration of hydrophobic interfaces) and covalent bonding techniques in which functional groups or linkers facilitate the attachment of the capture reagent to the surface. The immobilization of a capture reagent to a surface of a substrate material can be based on the properties of the substrate surface, the medium supporting the capture reagent, and the properties of the capture reagent.In some cases, a substrate surface can first be modified to attach functional groups to the surface. The functional groups can then bind to biomolecules or biological or chemical substances to immobilize them.

[0012] Data acquired by biosensors must be sent to storage devices such as dynamic random access memories (DRAMs) on a separate chip (i.e., a die) for data processing. The biosensor chip and the DRAM chip are located at different locations on a printed circuit board (PCB). In a higher-resolution biosensor array (e.g., 1024 x 1024), the routing between the biosensor chip and the DRAM limits the data transfer rate and bandwidth and increases power consumption and data distortion. To increase the bandwidth of the data signal path between the biosensor and the DRAM, the resistance, capacitance, inductance, noise, and distortion of the signal path must be reduced. It is therefore desirable to reduce the physical distance of the signal path between the biosensor and the DRAM to reduce performance and bandwidth issues related to the resistance, capacitance, and inductance of the path.However, there are physical limits to signal path reduction when the biosensor chip and DRAM are located separately on a circuit board.

[0013] According to some embodiments, wafer-level packaging is provided to integrate a biosensor (or biosensor array) with a microfluidic channel cap structure. The microfluidic channel cap structure is fabricated using a complementary metal-oxide-semiconductor (CMOS) compatible process flow. This is a scalable and cost-effective form of manufacturing compared to die-level packaging. By using a through-silicon via (TSV) as the interface between the chips / dies, the signal path between the biosensor array, the DRAM, and the processing chips is minimized as much as possible. This reduces the resistance, capacitance, and inductance in the interconnects between the chips / dies, which in turn reduces power consumption, delay, noise, and distortion, and increases bandwidth.This allows data from biosensor arrays to be analyzed much faster with higher resolution. In one embodiment, the biosensor system package can be connected to a separate chip (using a first TSV structure through the carrier substrate) on the front side. In another embodiment, the biosensor system package can be connected to another separate chip on the back side (using a second TSV structure through the cap structure substrate). In yet another embodiment, the biosensor system package can be connected to a separate chip on the front side (using a first TSV structure through the carrier substrate) and another separate chip on the back side (using a second TSV structure through the cap structure substrate).

[0014] Embodiments of the disclosure can enhance the integration and miniaturization of the biosensor analysis system. Embodiments of the disclosure can also reduce PCB footprint by directly packaging the biosensor (or biosensor array) with the supporting electronics. Additionally, the microfluidic channel can be fabricated directly with the biosensor (or biosensor array) in a compatible process flow.

[0015] Fig. 1A is a block diagram of an example biosensor system 100 according to some embodiments. Fig. 1B is a schematic diagram of an exemplary biosensor 103 used in a biosensor system 100 of Fig. 1A, according to some embodiments. As in Fig. 1A, the exemplary biosensor system 100 may include, among other things, a sensor array 102, a fluid delivery system 104, a readout circuit 106, and a controller 108.

[0016] The sensor array 102 may be equipped with at least one sensor element for detecting a biological or chemical analyte. The sensor array 102 may comprise an array of biosensors (e.g., a biosensor 103 located in Fig. 1B), in which one or more of the biosensors in the array are functionalized to detect a specific target analyte. Different biosensors can be functionalized with different capture reagents to detect different target analytes. The biosensors can be arranged in multiple rows and columns, creating a 2-dimensional array of biosensors. In some embodiments, each row of biosensors is functionalized with a different capture reagent. In some embodiments, each column of biosensors is functionalized with a different capture reagent. In some embodiments, a specific range of rows and columns of biosensors is functionalized with a different capture reagent. Further details on an exemplary biosensor 103 are provided below with reference to Fig. 1B provided.

[0017] The fluid delivery system 104 can deliver one or more fluid samples to the sensor array 102. The fluid delivery system 104 can be a microfluidic well positioned over the sensor array 102 to contain a fluid above the sensor array 102. The fluid delivery system 104 can also include microfluidic channels for delivering various fluids to the sensor array 102. The fluid delivery system 104 can include any number of valves, pumps, chambers, and channels designed to deliver fluid to the sensor array 102.

[0018] The readout circuit 106 is provided to measure signals from the sensors in the sensor array 102 and generate a quantifiable sensor signal indicative of the amount of a particular analyte present in a target solution, according to some embodiments.

[0019] The controller 108 can send and receive electrical signals to both the sensor array 102 and the readout circuit 106 to perform bio- or chemical-sensitive measurements. The controller 108 can also send electrical signals to the fluid delivery system 104, for example, to actuate one or more valves, pumps, or motors. The controller 108 can include one or more processing devices, such as a microprocessor, and can be programmable to control the operation of the readout circuit 106, the sensor array 102, and / or the fluid delivery system 104.

[0020] As in Fig. 1B, the exemplary biosensor 103 may include, among other things, a fluid gate 112, a source region 114, a drain region 116, a sensing film 118, and a channel region 120. The fluid delivery system 104 applies a fluid 122 over the sensing film 118. The fluid 122 may include an analyte that is not displayed. The sensing film 118 may be an electrically and chemically insulating layer separating the fluid 122 from the channel region 120. The sensing film 118 may include, among other things, a layer of a capture reagent. The capture reagent is specific for an analyte and capable of binding the target analyte or reagent. Binding of the analyte results in changes in the electrostatic potential at the surface of the sensor film 118, which in turn leads to an electrostatic gate effect of the biosensor 103 and a measurable change in a current I ds126 between the source and drain electrodes. A voltage applied to the fluid gate 112 can also change the I ds 126 change.

[0021] Wafer-level packaging is used to integrate the biosensor 103 or the biosensor array 102 with a microfluidic channel into a package. Additionally, the chips (i.e., dies) are connected to either an upper or lower portion of the package through a silicon via (TSV). Further details regarding wafer-level packaging and the TSV connection are provided below.

[0022] Fig. 2 is a cross-sectional diagram illustrating a biosensor system package 200 according to some embodiments. Fig. 3A and Fig. 3B are flow diagrams illustrating a method 300 for manufacturing the biosensor system package from Fig. 2 illustrate some embodiments. Fig. 4 to 24 are cross-sectional diagrams showing the biosensor package obtained after one or more of the steps of the method of Fig. 3A and Fig. 3B, according to some embodiments.

[0023] As in Fig. 2, the biosensor system package 200 has a front side (F) and a back side (B). Fig. 2, the biosensor system package 200 includes, among other things, a buried oxide layer (BOX layer) 206 and a semiconductor layer 208, a transistor structure (i.e., an FET) 210, a multilayer interconnect (MLI) structure 212, a carrier substrate 220, a TSV structure 246, a solder bump 248, a separate chip / die (e.g., a RAM and data processing chip) 250, a trench 222, an interface layer (e.g., a high-k material layer) 224, and a microfluidic channel cap structure 228. The separate chip 250 is connected to the TSV structure 246 by solder bump bonding to the front side (F). The microfluidic channel cap structure 228 is attached to the back side (B). The microfluidic channel cap structure 228 includes, among other things, a cap structure 230, a chamber 244, inlet / outlet ports 240', and optionally a high-k oxide material layer 242. The chamber 244 can accommodate liquid samples to be tested.The inlet / outlet ports 240' can be connected to pumps and / or containers via one or more tubes 252 for the inlet and outlet of the liquid samples. Details of the components of the biosensor system package 200 are described below with reference to FIG. Fig. 3A to 3C and 4 to 24.

[0024] As in Fig. 3A and Fig. 3B, method 300 is used to fabricate a biosensor system package. Fig. 3C is a flowchart illustrating a step 320 of method 300 according to some embodiments. It should be noted that additional steps may be provided before, during, and after method 300, and some of the steps described below may be replaced or eliminated for other embodiments of the method. It should also be noted that method 300 is a CMOS-compatible process flow.

[0025] The method 300 begins with step 302, in which a substrate is provided. The substrate may be a semiconductor substrate (e.g., a wafer). The semiconductor substrate may be a silicon substrate. Alternatively, the substrate may comprise another elemental semiconductor such as germanium; a compound semiconductor comprising silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor comprising SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. In one embodiment, Fig. 3A to 3B and Fig. 4 to 38, the substrate is a semiconductor-on-insulator (SOI) substrate 202. The Fig. The SOI substrate 202 shown in Figure 4 includes a bulk silicon layer 204, a buried oxide (BOX) layer 206, and a semiconductor layer 208 (i.e., an active layer 208). The buried oxide layer 206 may be formed by a method such as separation by implanted oxygen (SIMOX) and / or other suitable methods. The semiconductor layer 208 may include doped regions, such as p-wells and n-wells.

[0026] The method then continues to step 304, where a transistor structure is formed on the substrate. The transistor structure (i.e., the FET) may include a gate structure, a source region, a drain region, and a channel region located between the source and drain regions. As in the example of Fig. 4, the source, drain, and / or channel region of FET 210 may be formed on an active region in semiconductor layer 208. FET 210 may be an n-type FET (nFET) or a p-type FET (pFET). For example, the source / drain regions may comprise n-type dopants or p-type dopants, depending on the FET configuration. The gate structure may comprise a gate dielectric layer, a gate electrode layer, and / or other suitable layers. In one embodiment, the gate electrode is polysilicon. Other example gate electrodes are metallic gate electrodes comprising materials such as Cu, W, Ti, Ta, Cr, Pt, Ag, Au; suitable metal compounds such as TiN, TaN, NiSi, CoSi; combinations thereof; and / or other suitable conductive materials. In one embodiment, the gate dielectric is silicon oxide.Other example gate dielectrics include silicon nitride, silicon oxynitride, a high-k dielectric, and / or combinations thereof. Examples of high-k materials include hafnium silicate, hafnium oxide, zirconium oxide, alumina, tantalum pentoxide, hafnium dioxide-alumina (HfO2-Al2O3) alloy, or combinations thereof. The FET 210 can be deposited using typical CMOS processes such as photolithography, ion implantation, and diffusion; deposition including physical vapor deposition (PVD), metal evaporation or sputtering, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atmospheric pressure chemical vapor deposition (APCVD), low-pressure CVD (LPCVD), high-density plasma CVD (HDPCVD), atomic layer deposition (ALD), spin-on coating; Etching, including wet, dry, and plasma etching; and / or other suitable CMOS processes.

[0027] The method 300 then proceeds to step 306, where a multilayer interconnect (MLI) structure is formed over the transistor structure. The MLI structure may include conductive traces, conductive vertical connection accesses (vias), and / or intervening dielectric layers (e.g., interlayer dielectric (ILD) layers). The MLI structure may provide a physical and electrical connection to the transistor (i.e., the FET), as described above with reference to step 304. The conductive traces may include copper, aluminum, tungsten, tantalum, titanium, nickel, cobalt, metal silicide, metal nitride, polysilicon, combinations thereof, and / or other materials, possibly including one or more layers or liners. The intervening dielectric layers (e.g.,The ILD layers can be made of silicon dioxide, fluorinated silicon glass (FGS), SILK (a product of Dow Chemical of Michigan), BLACK DIAMOND (a product of Applied Materials of Santa Clara, California), and / or other suitable insulating materials. The MLI structure can be formed using suitable processes typical for CMOS manufacturing, such as CVD, PVD, ALD, plating, spin-on coating, and / or other processes.

[0028] As in the example from Fig. 4, an MLI structure 212 is deposited on the support substrate 202 and over the FET 210. The MLI structure 212 includes a plurality of conductive traces 214 connected by conductive vias or plugs 216. In one embodiment, the conductive traces 214 comprise aluminum and / or copper. In one embodiment, the vias or plugs 216 comprise tungsten. In another embodiment, the vias or plugs 216 comprise copper. In one embodiment, the intermediate dielectric layers 218 are disposed on the substrate 202 and include the intermediate conductive features of the MLI structure 212. The intermediate dielectric layers 218 may be ILD layers. In another embodiment, the dielectric layer 218 is a single ILD layer. In one embodiment, each of the intermediate dielectric layers 218 comprises silicon oxide.The MLI structure 212 may provide an electrical connection to the gate and / or source / drain of the FET 210. As shown in the example of FIG. Fig. 4, the MLI structure 212 is located at the front side (F), while the substrate 202 is located at the back side (B).

[0029] The method 300 then proceeds to step 308, where a carrier substrate is attached to the front side (F). In other words, the carrier substrate is attached to the MLI structure. The carrier substrate can protect the front side (F) during subsequent steps. In one embodiment, the carrier substrate is bonded to the MLI structure. In another embodiment, the carrier substrate is bonded to the passivation layer formed on the MLI structure. The carrier substrate can be attached by fusion, diffusion, eutectic, and / or other suitable bonding techniques. Example compositions for the carrier substrate include silicon, glass, and quartz. It should be noted that other compositions are possible and fall within the scope of the present disclosure. As in the example of Fig. As shown in Figure 5, a support substrate 220 is attached to the MLI structure 212. In some embodiments, the support substrate 220 may include functionalities such as interconnect features, wafer bonding sites, defined cavities, and / or other suitable features.

[0030] The method 300 then continues to step 310, where the wafer is flipped. As in Fig. 6, the backside (B) is located on the top side. In other words, the bulk silicon layer 204 is located on the top side. The method 300 then proceeds to step 312, where the bulk silicon layer 204 is removed. The removal may be performed by mechanical or chemical means. A mechanical means includes, for example, polishing or grinding, such as chemical mechanical polishing (CMP). The chemical means include wet etching, such as HF / nitric acid / acetic acid (HNA) or tetramethylammonium hydroxide (TMAH), or dry etching, including plasma and non-plasma etching. As in the example of Fig. 7, the bulk silicon layer 204 is Fig. 6 removed. The buried oxide layer 206 is located at the top of the back side (B).

[0031] The method 300 then proceeds to step 314, wherein the buried oxide layer is patterned to form an opening at the backside (B). A photoresist pattern is formed on the buried oxide layer. In some implementations, the photoresist pattern protects a portion of the buried oxide layer from a subsequent non-plasma etch to expose the backside (B) of the biosensor system package 200. In particular, the photoresist pattern protects a portion of the buried oxide layer from the subsequent non-plasma etch to expose the active region of the transistor structure formed in step 304. The non-plasma etch may be a wet or dry etch that does not include plasma. In some implementations, a two-step etching process may be employed to form the opening at the backside (B). The first etch step includes plasma, and the second etch step is a non-plasma etch. As in the example of Fig. As shown in Figure 8, the non-plasma etch forms a trench 222 with a bottom exposing the channel region 219 of the FET 210. To avoid plasma-induced damage (PID) to the exposed surface of the channel region 219, a non-plasma etch is used. In one non-limiting example, the height of the trench 222 may be between 0.3 µm and 1 µm, while the width of the trench 222 may be between 0.5 µm and 200 µm (in some extreme cases). In some embodiments, the sidewall profile of the trench 222 is substantially straight. After the non-plasma etch, the photoresist pattern is removed. A PID-free photoresist removal process such as stripping and ozone ashing may be used.Because the exposed surface of trench 222 and the exposed surface of the channel region of FET 210 are susceptible to plasma-induced damage (PID), some plasma ashing processes may not be able to be used to remove the photoresist pattern.

[0032] The method 300 then proceeds to step 316. In step 316, an interfacial layer is deposited. In one embodiment, the interface is a high-k material layer. The interface is compatible (e.g., friendly) for the binding of biomolecules or bioentities. For example, the interface may include a capture reagent layer, i.e., a layer of capture reagent capable of binding a target analyte in the liquid samples. In some embodiments, the interfacial layer includes multiple layers. For example, the interface may include a dielectric (e.g., a high-k material), a conductive material, and / or another suitable material for incorporating a receptor. Example interfacial materials include high-k dielectric films, metals, metal oxides, dielectrics, and / or other suitable materials.Other examples of exemplary interface layer materials include HfO2, Ta2O5, Pt, Au, W, Ti, Al, Cu, oxides of such metals, SiO2, Si3N4, Al2O3, TiO2, TiN, ZrO2, SnO, SnO2, and / or other suitable materials. The interface layer can be formed by CMOS processes such as physical vapor deposition (PVD) (sputtering), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atmospheric pressure chemical vapor deposition (APCVD), low-pressure CVD (LPCVD), high-density plasma CVD (HDPCVD), or atomic layer CVD (ALCVD). A photoresist structure is formed over the interface to protect a portion of the interface. The portion above the FET channel region is protected. Unprotected portions of the interface layer are removed in a subsequent etching process. The etching process may include any known etching process that includes plasma etching, since the PID sensitive section is protected.The interface completely covers the channel region and may partially cover the source and drain regions. The partial coverage of the source and drain regions can be customized based on the FET design and the area requirements for the interface layer. In some embodiments, the interface may not be patterned and etched, remaining above the respective surfaces of the FET.

[0033] As in the example from Fig. As shown in Figure 8, an interface layer 224 (e.g., a high-k material layer) is formed on the exposed surface of trench 222 and the exposed surface of the active region of FET 210. In addition, the interface layer 224 is deposited over the entire surface of the buried oxide layer 206.

[0034] Alternatively, in step 318, an interface layer is deposited while exposing some bonding sites. The bonding sites are used to bond a microfluidic channel cap structure to the backside (B), which is described in detail below in step 322. Note that whether bonding sites are required depends on the specific bonding requirements. Similar to step 316, the interface layer can be formed using CMOS processes such as PVD (sputtering), CVD, PECVD, APCVD, LPCVD, HDPCVD, or ALCVD. A photoresist structure is formed over the interface to protect a portion of the interface, and the bonding sites are unprotected. Unprotected portions of the interface layer are removed in a subsequent etching process. The etching process can include any known etching process that includes plasma etching, since the PID-sensitive portion is protected.After etching, the photoresist is removed in a PID-free photoresist removal process.

[0035] As in the example from Fig. As shown in Figure 9, the interface layer 224 (e.g., a high-k material layer) is formed on the exposed surface of the trench 222 and the exposed surface of the active region of the FET 210, while exposing two bonding sites 226. In other words, the buried oxide layer 206 is covered by the interface 224 except for the two bonding sites 226. Note that the shape of the bonding sites may vary depending on the shape of the microfluidic channel cap structure.

[0036] The method 300 then proceeds to step 320 where a microfluidic channel cap structure is fabricated. Fig. 3C is a flow diagram illustrating a step 320 of the method 300 according to some embodiments. Step 320 is a CMOS-compatible process flow. In step 352, a cap structure substrate is provided. The cap structure substrate may be a silicon substrate, but other suitable materials may also be used. As in the example of Fig. 10, a silicon substrate 230 is provided.

[0037] In step 354, the cap structure substrate is patterned and etched to predefine a global cavity region. The global cavity region corresponds to the microfluidic channel. A photoresist pattern is formed on the cap structure substrate. The photoresist pattern protects a portion of the cap structure substrate from subsequent etching to predefine the global cavity region. After patterning the cap structure substrate, the global cavity region is defined by etching the cap structure substrate. The etching process may include a wet etch, such as HF / nitric acid / acetic acid (HNA) or tetramethylammonium hydroxide (TMAH), or a dry etch, including plasma and non-plasma etching. The photoresist is then removed. As in the example of Fig. 11, a global cavity region 232 is predefined at the top surface of the cap structure substrate 230.

[0038] In step 356, a hard mask is applied to bonding areas of the cap structure substrate. In some embodiments, the bonding regions of the cap structure substrate correspond to the bonding locations on the buried oxide layer in step 318. Specifically, the bonding regions of the cap structure substrate are adjacent to the bonding locations on the buried oxide layer, and the microfluidic channel cap structure is bonded to the buried oxide layer (or a suitable interlayer bonding layer deposited and patterned on the buried oxide layer), which is described in detail below in step 322. The hard mask may protect the bonding regions from subsequent etching processes. In some embodiments, the hard mask may be made of oxide. In some embodiments, the hard mask may be made of polysilicon. The hard mask is formed using suitable methods such as CVD and / or the like.In a non-limiting example, the thickness of the hard mask ranges from 0.3 µm to 1 µm. As in the example from . Fig. As shown in Figure 12, the hard mask 236 (e.g., oxide hard mask) is applied to the bonding areas 234 of the cap structure substrate 230. The hard mask 236 may protect the bonding areas 234 from subsequent etching processes.

[0039] In step 358, certain regions of the global cavity region are patterned to form inlet / outlet channels. A photoresist pattern is formed on the hard mask, the global cavity region. The photoresist pattern protects the hard mask and a portion of the global cavity region from a subsequent etch to form the inlet / outlet channels. The cap structure substrate is then etched to form the inlet / outlet channels. The etching process may include a wet etch, such as HF / nitric acid / acetic acid (HNA) or tetramethylammonium hydroxide (TMAH), or a dry etch, including plasma and non-plasma etching. The photoresist is then removed. As in the example of Fig. 13, the photoresist pattern 238 is located on the hard mask 236 and a portion of the global cavity region 232. The exposed portion of the global cavity region 232 is etched to form the inlet / outlet channels 240. The photoresist pattern 238 is then removed, and the structure is as in the example of Fig. 14. The entire global cavity region 232, which includes the inlet / outlet channels 240, is exposed, while the bonding areas 234 are covered by the hard mask 236.

[0040] In step 360, the entire global cavity region is etched across the entire surface. Specifically, the entire global cavity region, including the inlet / outlet channels, is uniformly etched back to a specific depth to form the chamber of the microfluidic channel cap structure. On the other hand, the bonding areas covered by the hard mask are protected during the surface etching. Any suitable etching methods, such as wet or dry etching, such as plasma and non-plasma etching, can be used as the surface etching process. As in the example from Fig. As shown in Figure 15, the entire global cavity region 232 of the cap structure substrate 230, such as the inlet and outlet channels 240, is etched to a predefined etch depth ED. The predefined etch depth ED corresponds to the desired height of the chamber 244 of the microfluidic channel cap structure 228.

[0041] Optionally, in step 362, a high-k oxide material layer is deposited on the global cavity region and the hard mask. Step 362 is optional depending on the application. The high-k oxide material layer can be formed using CMOS processes such as PVD (sputtering), CVD, PECVD, APCVD, LPCVD, HDPCVD, or ALCVD. In a non-limiting example, the high-k oxide material layer has a thickness of 2 nm to 3 nm. As in the example of Fig. As shown in Figure 16, the high-k oxide material layer 242 is deposited on the global cavity region 232 (i.e., chamber 244) and the hard mask 236. The high-k oxide material layer 242 covers the bottom and sidewalls of the chamber 244, the bottom and sidewalls of the inlet / outlet channels, and the hard mask 236.

[0042] Optionally, in step 364, the interfacial layer on top of the hard mask is removed. In one embodiment, a photoresist spray coater may be sprayed by a spray coating process to cover the global void region. The photoresist spray coater protects the high-k oxide material layer as the high-k oxide material layer on the hard mask is removed. The interfacial layer on top of the hard mask is removed by suitable methods, such as plasma etching. In one example of a plasma etching process, a gas mixture of oxygen, a fluorine-containing material, and an inert gas is provided, and a high-speed glow discharge current (plasma) of the gas mixture is fired (in pulses) onto the high-k oxide material layer. The spray coating process is used to apply photoresist over a region with deep features.In the spray coating process, fine photoresist droplets are applied to the structure. The angle at which the photoresist droplets are sprayed allows the photoresist to penetrate into the deep trenches and sidewalls.

[0043] In step 366, the hard mask is removed. The hard mask is removed by suitable methods. In one embodiment, the hard mask is removed by wet etching. In some embodiments, the wet etch is a fluorine-containing etch, such as dilute hydrofluoric acid (HF). In some embodiments, the wet etch is an ammonia hydroxide / hydrogen peroxide etch. The wet etch removes the hard mask without significantly removing or damaging the layer of high-k oxide material. As in the example of Fig. As shown in Figure 17, both the optional high-k oxide material layer 242 on the hard mask 236 and the hard mask 236 are removed. The bonding sites 234 are exposed. The bottom and sidewalls of the global cavity region 232 and the inlet and outlet channels 240 are covered with the high-k oxide material layer 242. Thus, the microfluidic channel cap structure 228 is fabricated.

[0044] Looking back on Fig. 3A, the method 300 proceeds to step 322, where the microfluidic channel cap structure is bonded to the backside of the biosensor system package. In particular, the microfluidic channel cap structure is bonded to the buried oxide layer. In some embodiments, the bonding locations of the buried oxide layer are adjacent to the bonding regions of the cap structure substrate. In other embodiments, an interconnect layer deposited and patterned on the buried oxide layer forms an interface with the bonding regions of the cap structure substrate. The microfluidic channel cap structure may be bonded to the backside of the biosensor system package using fusion bonding, eutectic bonding, anodic bonding, and / or other suitable bonding techniques. Fusion bonding utilizes temperature and pressure to bond semiconductor materials.As a non-limiting example, in a room-temperature fusion bonding process, a bonding device forces the microfluidic channel cap structure and the backside of the biosensor system package together. This is followed by an annealing process to increase bond strength. Eutectic bonding uses a metal interlayer capable of creating a eutectic system. Eutectic metals are alloys that, at a specific composition and temperature, transition directly from the solid to the liquid state or vice versa from the liquid to the solid state without undergoing two-phase equilibrium.Since the eutectic temperature can be much lower than the melting temperature of the two or more pure elements, eutectic bonding can offer the advantages of low processing temperatures, low resulting stresses induced in the final assembly, high bond strength, high manufacturing yield, and good reliability. In anodic bonding, the glasses are sealed with either silicon or metal without the introduction of an intermediate layer. As shown in the example in . Fig. As shown in Figure 18, the microfluidic channel cap structure 228 is bonded to the backside (B) of the biosensor system package 200. Specifically, the microfluidic channel cap structure 228 is connected to the buried oxide layer 206. The bonding sites 226 of the buried oxide layer 206 are adjacent to the bonding sites 234 of the cap structure substrate 230.

[0045] The method 300 then continues to step 324, where the wafer is flipped. As in the example of Fig. As shown in Figure 19, the carrier substrate 220, located at the front (F) of the biosensor system package 200, is now at the top. The method 300 then proceeds to step 326, where the carrier substrate is thinned. In one example, the carrier substrate is thinned by grinding. The grinding process may include rotating a disk that holds the biosensor system package lined with a suitable abrasive material. It should be noted that other methods, such as CMP, may also be used. As shown in Fig. As shown in Figure 20, the carrier substrate 220 has been thinned. The thickness of the carrier substrate is selected in accordance with step 328, which is described below.

[0046] The method 300 then proceeds to step 328, where a TSV (through-substrate via) structure is created through the carrier substrate and connected to the MLI structure. The TSV is used to provide electrical connections and heat dissipation for the biosensor system package 200. As in the example of Fig. 21, a TSV structure 246 is created through the carrier substrate 220 and connected to the MLI structure 212. Although in the example in Fig. 21, more than one TSV structure 246 may be formed to penetrate the support substrate 220. The TSV structure 246 includes a liner 246a, a diffusion barrier layer 246b, and a conductive material 246c. In one embodiment, the TSV structure 246 is formed by the following operations. First, a TSV opening extending to a conductive line 214 of the MLI structure 212 is formed by one or more etching processes. After the TSV opening is formed, the liner 246a is formed on the sidewalls of the TSV opening as an insulation layer so that the conductive material 246c of the TSV structure 246 and the support substrate 220 do not directly contact each other. Thereafter, the diffusion barrier layer 246b is conformally formed on the liner 246a and on the bottom of the TSV opening.The diffusion barrier layer 246b is used to prevent the conductive material 246c, which will be formed later, from migrating into undesired regions. After the diffusion barrier layer 246b is formed, the conductive material 246c is used to fill the TSV opening. Afterward, the excess liner 246a, the diffusion barrier layer 246b, and the conductive material 246c located on the outside of the TSV opening are removed by a planarization process, such as a chemical mechanical polishing (CMP) process. Any suitable removal method may be used.

[0047] The liner 246a is made of an insulating material, such as oxides or nitrides. The liner 246a may be formed using a PECVD process or other applicable processes. The liner 246a may be single-layer or multi-layer. In some non-limiting examples, the liner 246a has a thickness in a range of about 100 Å to about 5000 Å. The diffusion barrier layer 246b is made of Ta, TaN, Ti, TiN, or CoW. In some embodiments, the diffusion barrier layer 246b is formed using a PVD process. In some embodiments, the diffusion barrier layer 246b is formed by plating. In some embodiments, the conductive material 246c is made of copper, copper alloy, aluminum, aluminum alloys, or combinations thereof. Alternatively, other applicable materials may be used.The width, depth, and aspect ratio of the TSV structure 246 can be selected under various circumstances. Because the carrier substrate 220 is thinned in step 326, the TSV structure 246 has a relatively small aspect ratio. This eliminates or greatly reduces the void space and extrusion or diffusion problems resulting from a high aspect ratio of the TSV structure. Furthermore, the overall height of the biosensor system package 200 is reduced to meet advanced packaging requirements. This allows the biosensor system package 200 to achieve a small form factor.

[0048] The method 300 then continues to step 330, where the wafer is flipped. As in the example of Fig. 22, the microfluidic channel cap structure 228 is on top, while the TSV structure 246 is on the bottom. The method 300 then proceeds to step 332, where the microfluidic channel cap structure is thinned to form the inlet / outlet ports 240', as in the example of Fig. 23. The microfluidic channel cap structure 228 is thinned by any suitable method, such as grinding and CMP. After thinning the microfluidic channel cap structure 228, the inlet / outlet channels 240 are exposed to form the inlet / outlet ports 240'. Thus, the chamber 244 can be connected to the outside via the inlet / outlet ports 240'.

[0049] Alternatively, in step 334, the microfluidic channel cap structure may first be thinned and then certain areas etched to form the inlet / outlet ports. However, some inlet and outlet channels are not etched due to the photoresist coverage in the etching process and therefore form a second chamber height that is higher than the chamber height (e.g., chamber 244, as shown in Fig. 22). The microfluidic channel cap structure is first thinned by any suitable method such as grinding and CMP. However, the thinning depth is chosen such that the inlet / outlet channels are not exposed after thinning. In an example in which two inlet / outlet channels (e.g., the inlet / outlet channels 240 as shown in Fig. 22), certain areas (e.g., the region above one of the two inlet / outlet channels) are etched to expose one of the two inlet / outlet channels, thus forming an inlet / outlet port. However, the region above the other inlet / outlet channel is not etched and therefore forms a second chamber height. The height of the second chamber is equal to the height of the chamber plus the height of the inlet / outlet channel. The alternative step 334 offers greater flexibility and can be applied to a chamber with two different heights (i.e., the chamber height and the height of the second chamber) compared to step 332.

[0050] The method 300 then proceeds to step 336, where the wafer is flipped over. After the wafer is flipped over, the carrier substrate 220 and the TSV structure 246 are on top. The method 300 then proceeds to step 338, where a separate chip is bonded to the TSV structure. The separate chip can be any chip that acts as a portion of the biosensor system. In one embodiment, the separate chip is a RAM chip. In one embodiment, the separate chip is a data processing chip. In one embodiment, the separate chip is a RAM and a data processing chip. The separate chip can be connected to the TSV structure by suitable methods. In one embodiment, the separate chip is connected to the TSV structure by solder bump bonding. Solder bumps are the small balls of solder (solder balls) that are bonded to contact pads or pads of semiconductor devices.In one example, solder bump bonding includes the following operations: placing one or more solder bumps on the TSV structures; flipping the wafer; aligning the solder bump(s) with the contact pad(s) of the separate die; and reflowing the solder bump(s) in a furnace to create the bond between the TSV structure and the separate die. In other embodiments, the separate die may be connected to the TSV structure by wire bonding. As in the example of FIG. Fig. As shown in Figure 24, a RAM and data processing chip 250 is bonded to the TSV structure 246 by solder bumps (using a solder bump 248), and the wafer is flipped back. Thus, the biosensor system package 200 is fabricated according to method 300.

[0051] Fig. 25A and Fig. 25B are flow diagrams illustrating another method 2500 for manufacturing the biosensor system package according to some embodiments. Fig. 26 to 30 are a cross-sectional diagram illustrating the biosensor package 3000 obtained after one or more of the steps of the method of Fig. 25A and Fig. 25B, according to some embodiments. The method 2500 is the same as the method 300 of Fig. 3A to 3B, however, the TSV structure is fabricated prior to bonding the microfluidic channel cap structure in method 2500. Therefore, for simplicity, some steps of method 2500 are not described in detail because similar steps have been described previously.

[0052] The method 2500 begins in step 2502, which is similar to step 302 in Fig. 3A, a substrate is provided. The substrate may be a semiconductor substrate (e.g., a wafer). In one example, the semiconductor substrate may be an SOI substrate comprising a bulk silicon layer, a buried oxide layer (BOX layer), and a semiconductor layer (i.e., an active layer). The method 2500 then proceeds to step 2504, which is similar to step 304 in Fig. 3A, wherein a transistor structure is formed on the substrate. The transistor structure (i.e., the FET) may include a gate structure, a source region, a drain region, and a channel region located between the source and drain regions. The method 2500 then proceeds to step 2506, which is similar to step 306 in Fig. 3A, wherein an MLI structure is formed over the transistor structure. The MLI structure may include conductive traces, conductive vias, and / or intervening dielectric layers (e.g., ILD layers). The MLI structure may establish a physical and electrical connection to the transistor (i.e., the FET). The method 2500 then proceeds to step 2508, which is similar to step 308 in Fig. 3A, wherein a carrier substrate is attached to the front side (F). In other words, the carrier substrate is attached to the MLI structure. The carrier substrate can protect the front side (F) during subsequent steps. In one embodiment, the carrier substrate is bonded to the MLI structure. The carrier substrate can be attached by fusion, diffusion, eutectic, and / or other suitable bonding methods.

[0053] The method 2500 then continues to step 2510, which is similar to step 326 in Fig. 3B is where the support substrate is thinned. In one example, the support substrate is thinned by grinding. Note that other methods, such as CMP, may also be applied. The thickness of the support substrate is selected in accordance with step 2512, described further below. The method 2500 then proceeds to step 2512, which is similar to step 328, where a TSV structure is created through the support substrate and connected to the MLI structure. The TSV is used to provide electrical connections and heat dissipation for the biosensor system package. In one embodiment, the TSV structure is formed by the following operations. First, a TSV opening extending to a conductive line of the MLI structure is formed by one or more etch processes.After the TSV opening is formed, the liner is formed on the sidewalls of the TSV opening as an insulation layer, preventing the conductive material of the TSV structure from directly contacting the supporting substrate. The diffusion barrier layer is then conformally formed on the liner and on the bottom of the TSV opening. The diffusion barrier layer prevents the conductive material, which will be formed later, from migrating to undesired regions. After the diffusion barrier layer is formed, the conductive material is used to fill the TSV opening. Afterward, the excess liner, the diffusion barrier layer, and the conductive material located on the outside of the TSV opening are removed using a planarization process such as a CMP process.

[0054] As in the example from Fig. 26, the TSV structure 246 is formed by the carrier substrate 220 at the front side (F) and connected to the MLI structure 212. The TSV structure 246 includes the liner 246a, the diffusion barrier layer 246b, and the conductive material 246c. Fig. The SOI substrate 202 shown on the backside (B) of Figure 26 includes a bulk silicon layer 204, the buried oxide layer (BOX layer) 206, and a semiconductor layer 208 (i.e., the active layer 208). The transistor structure (i.e., the FET) 210 is formed in an active region in the semiconductor layer 208.

[0055] The method 2500 then continues to step 2514, where the wafer is flipped over. After step 2514, the bulk silicon layer is on top. The method 2500 then continues to step 2516, which is similar to step 312 in Fig. 3B is where the bulk silicon layer is removed. Removal can be done by mechanical or chemical means. Mechanical means include polishing or grinding, such as CMP. A chemical means is wet or dry etching. As in the example from Fig. 27, the bulk silicon layer 204 is Fig. 26 removed. The buried oxide layer 206 is located at the top of the back side (B).

[0056] The method 2500 then continues to step 2518, which is similar to step 314 in Fig. 3A, wherein the buried oxide layer is patterned to form a backside opening (B). A photoresist pattern is formed on the buried oxide layer. In some embodiments, the photoresist pattern protects a portion of the buried oxide layer from the subsequent non-plasma etch to expose the active region of the transistor structure formed in step 2504. The non-plasma etch may be a wet or dry etch that does not include plasma. In some implementations, a two-step etching process may be employed to form the backside opening (B). The first etch step includes plasma, and the second etch step is a non-plasma etch. As in the example of Fig. As shown in Figure 28, the non-plasma etch forms a trench 222 with a bottom that exposes the channel region of the FET 210. To prevent plasma-induced damage (PID) to the exposed surface of the channel region 219, a non-plasma etch is used.

[0057] The method 2500 then proceeds to step 2520, which is similar to step 316, where an interfacial layer is applied. In one embodiment, the interface is a high-k material layer. The interface is compatible (e.g., friendly) for the binding of biomolecules or bioentities. For example, the interface may represent a binding interface for biomolecules or bioentities. In some embodiments, the interfacial layer comprises multiple layers. For example, the interface may comprise a dielectric (e.g., a high-k material), a conductive material, and / or another suitable material for receiving a receptor. The interfacial layer may be formed using CMOS processes such as PVD (sputtering), CVD, PECVD, APCVD, LPCVD, HDPCVD, or ALCVD. As in the example of Fig. As shown in Figure 28, the interface layer 224 (e.g., a high-k material layer) is formed on the exposed surface of the trench 222 and the exposed surface of the active region of the FET 210. In addition, the interface layer 224 is deposited over the entire surface of the buried oxide layer 206.

[0058] Alternatively, at step 2522, which is similar to step 318 in Fig. 3A, an interface is deposited while exposing some bonding sites. The bonding sites are used to bond a microfluidic channel cap structure to the backside (B), which is described in detail below in step 2524. Note that whether bonding sites are necessary depends on the specific bonding requirements.

[0059] As in the example from Fig. As shown in Figure 28, the interface layer 224 (e.g., a high-k material layer) is formed on the exposed surface of the trench 222 and the exposed surface of the active region of the FET 210. In other words, the buried oxide layer 206 is covered by the interface layer 224. Note that bonding sites may be employed in some embodiments.

[0060] The method 2500 then continues to step 2524, which is similar to step 320 in Fig. 3A. In one embodiment, step 2524 includes steps 352 to 366 of Fig. 3C. Step 2524 is compatible with CMOS processes. The method 2500 then continues to step 2526, which is similar to step 322 in Fig. 3A, wherein the microfluidic channel cap structure is bonded to the backside of the biosensor system package. In particular, the microfluidic channel cap structure is bonded to the buried oxide layer. In other embodiments, an interconnect layer deposited and patterned on the buried oxide layer forms an interface with the bonding regions of the cap structure substrate. The microfluidic channel cap structure can be bonded to the backside of the biosensor system package using fusion bonding, eutectic bonding, anodic bonding, and / or other suitable bonding techniques.

[0061] The method 2500 then proceeds to step 2528, which is similar to step 332, where the microfluidic channel cap structure is thinned to form the inlet / outlet ports. The microfluidic channel cap structure is thinned by any suitable method, such as grinding and CMP. After thinning the microfluidic channel cap structure, the inlet / outlet channels are exposed to form the inlet / outlet ports.

[0062] Alternatively, in step 2530, similar to step 334, the microfluidic channel cap structure may first be thinned and then certain areas etched to form the inlet / outlet ports. However, some inlet and outlet channels are not etched due to the photoresist coverage in the etching process and therefore form a second chamber height that is higher than the chamber height (e.g., chamber 244, as shown in Fig. 29). The microfluidic channel cap structure is first thinned by any suitable method such as grinding and CMP. However, the thinning depth is chosen so that the inlet / outlet channels are not exposed after thinning. In an example where two inlet / outlet channels have been fabricated, certain areas (e.g., the region above one of the two inlet / outlet channels) are etched to expose one of the two inlet / outlet channels, thus forming an inlet / outlet port. However, the region above the other inlet / outlet channel is not etched and therefore forms a second chamber height. The height of the second chamber corresponds to the height of the chamber plus the height of the inlet / outlet channel. Again, the alternative step 2530, which is similar to step 334, offers greater flexibility and can be applied to a chamber with two different heights (i.e.,The height of the chamber and the height of the second chamber can be applied. This allows one chamber to be connected to the outside via the inlet / outlet port. As shown in the example from . Fig. As shown in Figure 29, a microfluidic channel cap structure 228 is bonded to the back side (B). A chamber 244 with two different heights within a cap structure substrate 230 is connected to the outside via an inlet / outlet channel 240'.

[0063] The method 2500 then proceeds to step 2532, where the wafer is flipped. After the wafer is flipped, the carrier substrate and the TSV structure are on top. The method 2500 then proceeds to step 2534, where a separate chip is bonded to the TSV structure. The separate chip may be any chip that acts as a portion of the biosensor system. In one embodiment, the separate chip is a RAM and a data processing chip. The separate chip may be connected to the TSV structure by suitable methods. In one embodiment, the separate chip is connected to the TSV structure by solder bump bonding. As in the example of Fig. As shown in Figure 30, a RAM and data processing chip 250 is bonded to the TSV structure 246 by solder bumps (using a solder bump 248), and the wafer is then flipped back. Thus, the biosensor system package 3000 is manufactured according to method 2500.

[0064] Fig. 31 is a cross-sectional diagram illustrating a biosensor system package 3100 according to some embodiments. Fig. 32A and Fig. 32B are flow diagrams illustrating a method 3200 for manufacturing the biosensor system package from Fig. 31 according to some embodiments. Fig. 32C is a flow diagram illustrating a step of fabricating a microfluidic channel cap structure of the method 3200 of and Fig. 32A to 32B according to some embodiments. Fig. 33 to 47 are a cross-sectional diagram showing the biosensor package obtained after one or more of the steps of the method of Fig. 32A and Fig. 32B, according to some embodiments. It should be noted that Fig. 31 and 33-47 are schematic and not drawn to scale. Unlike the biosensor system package 200 from Fig. 2, a separate chip is connected to the backside (B) and connected to an MLI structure 212 via a via structure 246 through a microfluidic channel cap structure 228. Since many structures and steps are similar to those described above, the differences are emphasized below.

[0065] As in Fig. 31, the biosensor system package 3100 has a front side (F) and a back side (B). Fig. 31, the biosensor system package 3100 includes, among other things, a buried oxide layer (BOX layer) 206 and a semiconductor layer 208, a transistor structure (i.e., an FET) 210, an MLI structure 212, a support substrate 220, a trench 222, three bonding trenches 223, an interface layer (e.g., a high-k material layer) 224, a microfluidic channel cap structure 228, a redistribution layer (RDL) 268, a solder bump 248, and a separate chip (e.g., a RAM and data processing chip) 250. The microfluidic channel cap structure 228 is attached to the backside (B). The microfluidic channel cap structure 228 includes, among other things, a cap structure 230, a chamber 244, inlet / outlet ports 240', a TSV structure 246, a pillar structure 254, two bond rings 256, an oxide layer 258, and a top oxide layer 259. The chamber 244 can accommodate liquid samples to be tested.The inlet / outlet ports 240' can be connected to pumps and / or reservoirs via one or more tubes 252. The separate chip 250 is connected to at least one of the conductive traces on the first metal layer (e.g., conductive traces on the first metal layer "M1") 214 of the MLI structure 212 via the TSV structure 246 and the pillar structure 254. The microfluidic channel cap structure 228 is connected to the conductive traces 214 of the MLI structure 212 via the pillar structure 254 and the bond rings 256. Details of the components of the biosensor system package 3100 are described below with reference to FIG. Fig. 32A to 32C and 33 to 47.

[0066] As in Fig. 32A and Fig. 32B, the method 3200 is used to manufacture a biosensor system package 3100 as shown in Fig. 31. It should be noted that additional steps may be provided before, during, and after method 3200, and some of the steps described below may be replaced or eliminated for further embodiments of the method. Furthermore, it should be noted that method 3200 includes steps that have features of a typical CMOS technology process flow and are therefore only briefly described here.

[0067] The method 3200 begins with step 3202, where a substrate is provided. The substrate includes a bulk silicon layer, a buried oxide layer (e.g., the layer shown in Fig. 31 shown buried oxide layer 206), and a semiconductor layer 208 (e.g. the one shown in Fig. 31). In step 3204, a transistor structure (e.g., a FET 210 as shown in Fig. 31) is formed on the substrate. In step 3206, an MLI structure (e.g., the MLI structure 212 as shown in Fig. 31) is formed over the transistor structure. In step 3208, a carrier substrate (e.g., the one shown in Fig. 31) is attached to the front side (F) of the biosensor system package. In step 3210, the wafer is flipped over. In step 3212, the bulk silicon layer of the substrate is removed. In step 3214, the buried oxide layer of the substrate is patterned to form an opening (e.g., the trench 222 in Fig. 31) on the back side (B) of the biosensor system package. In step 3216, an interface layer (e.g., the one shown in Fig. 31, which in one example is a high-k material layer).

[0068] The method 3200 then continues to step 3218. In step 3218, the interface layer, the buried oxide layer, the semiconductor layer, and the topmost intermediate dielectric layer (e.g., the topmost intermediate dielectric layer 218 as shown in Fig. 31) of the MLI structure is patterned and etched to form bonding trenches (e.g., bonding trenches 223 shown in Fig. 31) for exposing conductor tracks on the first metal layer of the MLI structure and for receiving bonding rings (e.g. those shown in Fig. 31 256 shown bond rings) and a columnar structure (e.g. the one shown in Fig. 31 shown column structure 254).

[0069] The method 3200 then proceeds to step 3220, where a microfluidic channel cap structure is fabricated. In one embodiment, step 3220 includes the steps described in Fig. 32C. In step 3252, a cap structure substrate is provided. In step 3254, an oxide layer is deposited on the cap structure substrate and a nitride layer is deposited on the oxide layer. In the example of Fig. 33, the oxide layer 258 is deposited on the cap structure substrate 230, and the nitride layer 260 is deposited on the oxide layer 258. In one embodiment, the cap structure substrate 230 is a highly doped and conductive silicon substrate. In one embodiment, the thickness of the oxide layer 258 ranges from 100 nm to 300 nm, and the thickness of the nitride layer 260 ranges from 100 nm to 300 nm.

[0070] In step 3256, the oxide layer and the nitride layer are patterned and etched to define regions corresponding to the bonding rings, the pillar structure, and the chamber. In the example from Fig. 34, the oxide layer 258 and the nitride layer 260 are patterned and etched. The defined areas in which the oxide layer 258 and the nitride layer 260 remain correspond to the column structure, the bonding rings, and the chamber, respectively.

[0071] In step 3258, isolation trenches are etched around the area corresponding to the pillar structure. Fig. 35, two isolation trenches 262 are formed around the area corresponding to the pillar structure by dry etching or wet etching. In step 3260, the oxide in the isolation trenches is thermally built up. Thermal oxide is not built up in regions covered by the nitride layer. In one embodiment, the thickness of the thermal oxide is an order of magnitude thicker than that of the oxide layer covered by the nitride. In addition, thermal oxide is built up on all sides of the cap structure substrate. In the example shown in Fig. In the example shown in Figure 36, a (thermal) oxide layer 258 is built up in the insulation trenches 262.

[0072] In step 3262, the nitride layer and the oxide layer are etched back in defined areas. Fig. 37, the cap structure substrate 230 is exposed in defined areas. In step 3264, a polysilicon layer is deposited covering the entire surface. The polysilicon layer in defined areas corresponding to the column structure and the bonding rings later serves as a section of the column structure or the bonding rings. In the example shown in Fig. In the example shown in Figure 38, the polysilicon layer 264 is deposited blanket-like and over both the defined and undefined regions. In one embodiment, the thickness of the polysilicon layer 264 ranges from 3 µm to 5 µm.

[0073] In step 3266, the native oxide of the polysilicon layer is removed, and an interlayer is blanket deposited. The native oxide layer may form when a silicon-containing surface is exposed to ambient conditions or oxygen. The presence of the native oxide of the polysilicon may increase the resistance between the polysilicon and the interlayer, which is undesirable. In one embodiment, the native oxide of the polysilicon layer is removed by wet processes such as treating the native oxide with dilute hydrofluoric acid (HF). The interlayer is made of any material suitable for eutectic bonding. In one embodiment, the interlayer is made of germanium (Ge). In the example of Fig. 39, the intermediate layer 266 is deposited covering the polysilicon layer 264 after removal of the native oxide.

[0074] In step 3268, the regions corresponding to the bond rings and the pillar structure are patterned, and the interlayer and the polysilicon layer in other unpatterned regions are shifted. In the example from Fig. 40, the pillar structure 254 and the bond rings 256 protrude in other unstructured areas after the removal of the interlayer 266 and the polysilicon layer 264. The pillar structure 254 and the bond rings 256 both comprise a portion of the polysilicon layer 264 and a portion of the interlayer 266 on the portion of the polysilicon layer 264. Optionally, the cap structure substrate 230 is etched in the area around the bond rings 256 and in the area corresponding to the chamber.

[0075] In step 3270, the global cavity region is patterned and etched to form the chamber. In the example from Fig. 41, the global cavity region 232 is patterned, and the cap structure substrate 230 is etched in the global cavity region 232 to form the chamber 244. The chamber depth (CD) of the chamber 244 is smaller than the column structure depth (PD) of the column structure 254.

[0076] Optionally, in step 3272, a high-k oxide material layer is deposited on the bottom surface and sidewalls of the chamber. Step 3272 is optional depending on the application. In one embodiment, step 3272 may be performed by depositing the high-k material layer over the entire area and etching the high-k material layer while blocking the chamber area with a photoresist spray coater. In one embodiment, the thickness of the high-k oxide material ranges from 2 nm to 3 nm. In the example of Fig. 42, the high-k oxide material 242 covers the bottom surface and side walls of the chamber 244. This is how the microfluidic channel cap structure 228 is manufactured.

[0077] Looking back on Fig. 32A and Fig. 32B, in step 3222, the microfluidic channel cap structure is bonded to the back of the biosensor system package. In one embodiment, the bonding is performed by eutectic bonding, and the intermediate layers 266 at the top of the column structure and the bonding rings are used to create a eutectic system. As in the example in Fig. As shown in Figure 43, the microfluidic channel cap structure 228 is bonded to the backside (B) of the biosensor system package using eutectic bonding. Specifically, the pillar structure 254 and the bonding rings 256 are housed in bonding trenches 223 and bonded to the first metal layer M1 of the MLI structure 212 on the conductive trace 214. It should be noted that Fig. 47 is not drawn to scale. In a non-limiting example, the depth of the bonding trench is 2 µm; the heights of the pillar structure 254 and the bond rings 256 are both 4 µm; the thickness of the support substrate 220 ranges from 300 µm to 750 µm; the thickness of the MLI structure 212 is 10 µm; the thickness of the cap structure substrate ranges from 500 µm to 750 µm.

[0078] In step 3224, the upper portion of the microfluidic channel cap structure is thinned. The microfluidic channel cap structure may be thinned by any suitable method, such as grinding and CMP. In the example of Fig. 44, after thinning the microfluidic channel cap structure 228, the TSV structure is exposed at the top of the back side (B).

[0079] In step 3226, a top oxide layer is patterned and deposited on the upper portion of the microfluidic channel cap structure to create a contact opening for the pillar structure. In the example in Fig. 45, the upper oxide layer 259 is deposited over the entire upper surface of the cap structure substrate 230, except for a contact opening 270. Thus, the TSV structure 246 is electrically isolated from other portions of the cap structure substrate 230.

[0080] In step 3228, a redistribution layer (RDL) is patterned and deposited over the contact opening. In general, redistribution layers provide a conductive structure that enables a pin-out contact structure for a finished package that differs from the structure of the via structures, thereby allowing greater flexibility in the placement of vias and dies. Redistribution layers include traces and vias, where vias connect an overlying line to an underlying conductive feature. In the example of Fig. 46, the redistribution layer 268 is patterned and deposited over the contact opening 270. The redistribution layer 268 is electrically connected to the highly doped cap structure substrate 230 in the TSV structure 246.

[0081] In step 3230, the upper oxide layer and the cap structure substrate are patterned and etched to form inlet / outlet ports. Certain regions of the upper oxide layer 259 and the cap structure substrate 230 are etched to form one or more inlet and outlet ports. This forms the inlet and outlet ports. In the example of Fig. 47, the inlet / outlet port 240' is formed by etching the upper oxide layer 259 and the cap structure substrate 230 in a specific area within the chamber 244.

[0082] In step 3232, a separate chip is bonded to the redistribution layer. The separate chip can be any chip that acts as a portion of the biosensor system. The separate chip can be connected to the redistribution layer by suitable methods. As in the example of Fig. As shown in Figure 31, a RAM and data processing chip 250 is bonded to the redistribution layer 268 by solder bumps (using a solder bump 248). Thus, the RAM and data processing chip 250 is connected to the MLI structure by the following electrical path: the redistribution layer 268, the cap structure substrate 230, the TSV structure 246, the pillar structure 254, and the conductive trace 214 at the first metal layer. Thus, the biosensor system package 3100 is manufactured according to method 3200.

[0083] Fig. 48 is a cross-sectional diagram illustrating a biosensor system package 4800 according to some embodiments. The biosensor system package 4800 is a combination of the biosensor system package 200 in Fig. 2 and the Biosensor System Package 3100 in Fig. 31. Specifically, the biosensor system package 4800 is connected to a separate chip on the front side (using a first TSV structure through the carrier substrate) and another separate chip on the back side (using a second TSV structure through the cap structure substrate). In other words, a "three-chip-plus-microfluidic" structure is created. The manufacturing method of the biosensor system package 4800 is a combination of the method 300 in Fig. 3A to 3B and the procedure 3200 in Fig. 32A to 32B, and is therefore not described in detail for the sake of simplicity.

[0084] As in Fig. 48, the biosensor system package 4800 has a front side (F) and a back side (B). Fig.48, the biosensor system package 4800 includes, among other things, a buried oxide layer (BOX layer) 206 and a semiconductor layer 208, a transistor structure (i.e., an FET) 210, an MLI structure 212, a support substrate 220, a trench 222, three bonding trenches 223, an interface layer (e.g., a high-k material layer) 224, a microfluidic channel cap structure 228, a redistribution layer (RDL) 268, two solder bumps 248-1 and 248-2, and two separate chips (e.g., a RAM and data processing chip) 250-1 and 250-2. The microfluidic channel cap structure 228 is attached to the backside (B). The microfluidic channel cap structure 228 includes, among other things, a cap structure 230, a chamber 244, inlet / outlet ports 240', a second TSV structure 246-2, a pillar structure 254, two bond rings 256, an oxide layer 258, and a top oxide layer 259. The chamber 244 can accommodate fluid samples to be tested.The inlet / outlet ports 240' can be connected to pumps and / or reservoirs via one or more tubes. The first separate chip 250-1 is connected to the MLI structure 212 via the carrier substrate 220 using the first TSV structure 246-1. The second separate chip 250-2 is connected to at least one of the conductive traces on the first metal layer (e.g., conductive traces on the first metal layer "M1") 214 of the MLI structure 212 via the second TSV structure 246-2 and the pillar structure 254. The microfluidic channel cap structure 228 is connected to the conductive traces 214 of the MLI structure 212 via the pillar structure 254 and the bond rings 256.

[0085] Embodiments according to the disclosure include a biosensor system package.The biosensor system package comprises: a transistor structure in a semiconductor layer having a front side and a back side, wherein the transistor structure comprises a channel region; a multilayer interconnect (MLI) structure at the front side of the semiconductor layer, wherein the transistor structure is electrically connected to the MLI structure; a support substrate on the MLI structure; a first substrate via (TSV) structure extending through the support substrate and configured to provide electrical connection between the MLI structure and a separate die; a buried oxide (BOX) layer at the back side of the semiconductor layer, wherein the buried oxide layer has an opening at the back side of the channel region and an interface layer covers the back side over the channel region; and a microfluidic channel cap structure attached to the buried oxide layer.

[0086] The further embodiments include a biosensor system package. The biosensor system package comprises: a transistor structure in a semiconductor layer having a front side and a back side, wherein the transistor structure comprises a channel region; a multilayer interconnect (MLI) structure on the front side of the semiconductor layer, comprising a first conductive line and a second conductive line on a first metal layer (M1 layer), wherein the transistor structure is electrically connected to the MLI structure; a carrier substrate on the MLI structure; a buried oxide layer (BOX) layer on the back side of the semiconductor layer, wherein the buried oxide layer has an opening, a first bonding trench, and a second bonding trench at the back side of the channel region, and wherein an interface layer covers the back side over the channel region; a microfluidic channel cap structure attached to the first conductive line and the second conductive line;and a second substrate via (TSV) structure extending through the microfluidic channel cap structure and configured to provide electrical connection between the MLI structure and a separate die.;

[0087] The further embodiments comprise a method for manufacturing a biosensor system package. The method comprises: providing a substrate, the substrate comprising a semiconductor layer having a front side and a back side, a buried oxide (BOX) layer on the back side, and a bulk silicon layer on the back side; forming a transistor structure on the substrate, wherein a channel region of the transistor structure is located in the semiconductor layer; forming a multilayer interconnect (MLI) structure on the front side of the semiconductor layer, wherein the MLI structure is electrically connected to the transistor structure; attaching a support substrate to the MLI structure; removing the bulk silicon layer; etching the buried oxide layer to form an opening on the back side over the channel region; depositing an interface layer on the back side over the channel region; fabricating a microfluidic channel cap structure;Connecting the microfluidic channel cap structure to the BOX layer; thinning the support substrate; creating a first through-hole substrate (TSV) structure extending through the support substrate, wherein the first TSV structure is electrically connected to the MLI structure; and thinning the microfluidic channel cap structure to form at least one opening for the inflow and outflow of fluid samples.

Claims

[1] Biosensor system package (200, 3100), comprising: a transistor structure (210) in a semiconductor layer (208) having a front side and a back side, the transistor structure (210) having a channel region (219); a multilayer interconnect structure (212) on the front side of the semiconductor layer (208), wherein the transistor structure (210) is electrically connected to the multilayer interconnect structure (212); a carrier substrate (220) on the multilayer interconnect structure (212); a first substrate via structure (246) extending through the carrier substrate (220) and configured to establish an electrical connection between the multilayer interconnect structure (212) and a separate die (250, 250-1, 250-2); a buried oxide layer (206) on the back side of the semiconductor layer (208), the buried oxide layer (206) having an opening (222) on the back side of the channel region (219) and an interface layer (224) covering the back side over the channel region (219); and a microfluidic channel cap structure (228) attached to the buried oxide layer (206), the microfluidic channel cap structure (228) comprising a cap structure substrate (230) having a chamber (244) and a high-k dielectric oxide layer (242) covering a bottom and sidewalls of the chamber (244). [2] The biosensor system package (200, 3100) of claim 1, wherein the microfluidic channel cap structure (228) is fabricated using a complementary metal oxide semiconductor compatible process flow. [3] Biosensor system package (200, 3100) of claim 1 or 2, wherein the chamber (244) is arranged to receive liquid samples to be tested; and wherein the microfluidic channel cap structure (228) further comprises at least one port (240') connecting the chamber (244) and serving for the inflow and outflow of the liquid samples. [4] The biosensor system package (200, 3100) of any preceding claim, wherein the cap structure substrate (230) has bonding regions that contact bonding sites of the buried oxide layer (206). [5] Biosensor system package (200, 3100) according to one of the preceding claims, wherein the multilayer interconnect structure (212) comprises: a plurality of intermediate dielectric layers (218); a plurality of conductive traces (214), each conductive trace (214) being disposed in one of the plurality of intermediate dielectric layers (218); and a plurality of conductive vertical interconnect access structures (216) connecting the plurality of conductive traces (214). [6] Biosensor system package (200, 3100) of any one of the preceding claims, wherein the first substrate via structure (246) comprises: a conductive material (246c); a liner (246a) that insulates the conductive material (246c) from the carrier substrate (220); and a diffusion barrier layer (246b) between the conductive material (246c) and the lining (246a). [7] Biosensor system package (200, 3100) of any one of the preceding claims, further comprising: the separate die (250, 250-1, 250-2), wherein the separate die (250, 250-1, 250-2) is electrically connected to the first substrate via structure (246) and is configured to process data collected by the transistor structure (210). [8] The biosensor system package (200, 3100) of any preceding claim, wherein the interface layer (224) is a high-k dielectric layer. [9] The biosensor system package (200, 3100) of any preceding claim, wherein the interface layer (224) comprises a layer of a capture reagent capable of binding a target analyte in the liquid samples. [10] Biosensor system package (200, 3100), comprising: a transistor structure (210) in a semiconductor layer (208) having a front side and a back side, the transistor structure (210) having a channel region (219); a multilayer interconnect structure (212) on the front side of the semiconductor layer (208) comprising a first conductive line (214) and a second conductive line (214), wherein the transistor structure (210) is electrically connected to the multilayer interconnect structure (212); a carrier substrate (220) on the multilayer interconnect structure (212); a buried oxide layer (206) on the back side of the semiconductor layer (208), the buried oxide layer (206) having an opening (222) at the channel region (219), a first bonding trench (223) and a second bonding trench (223), and an interface layer (224) covering the back side over the channel region (219); a microfluidic channel cap structure (228) attached to the first conductive trace (214) and to the second conductive trace (214); and a second substrate via structure (246) extending through the microfluidic channel cap structure (228) and configured to establish an electrical connection between the multilayer interconnect structure (212) and a separate die (250, 250-1, 250-2). [11] The biosensor system package (200, 3100) of claim 10, wherein the microfluidic channel cap structure (228) is fabricated using a complementary metal oxide semiconductor compatible process flow. [12] The biosensor system package (200, 3100) of claim 10 or 11, wherein the microfluidic channel cap structure (228) further comprises: a cap structure substrate (230) having a chamber (244) configured to receive liquid samples to be tested; at least one port (240') connecting the chamber (244) and serving for the inflow and outflow of the liquid samples; a pillar structure (254) housed in a first bonding trench (223) and projecting toward the first conductive line (214), the pillar structure (254) being electrically connected to the second substrate via structure (246); and a bonding ring (256) which is accommodated in a second bonding trench (223) and projects in the direction of the second conductor track (214). [13] The biosensor system package (200, 3100) of claim 12, wherein the pillar structure (254) and the bonding ring (256) both comprise a conductive layer and an intermediate layer, the intermediate layer being used for eutectic bonding. [14] The biosensor system package (200, 3100) of claim 13, wherein the conductive layer is made of polysilicon and the intermediate layer is made of germanium. [15] Biosensor system package (200, 3100) of any one of claims 10 to 14, wherein the second substrate via structure (246) comprises: a portion of the cap structure substrate (230), wherein the portion of the cap structure substrate (230) is highly doped; and at least one oxide layer surrounding the portion of the cap structure substrate (230). [16] Biosensor system package (200, 3100) of any one of claims 10 to 15, further comprising: the separate die (250, 250-1, 250-2), wherein the die (250, 250-1, 250-2) is electrically connected to the second substrate via structure (246) and is configured to process data collected by the transistor structure (210). [17] The biosensor system package (200, 3100) of any one of claims 10 to 16, wherein the interface layer (224) is a high-k dielectric layer. [18] A method (300, 2500, 3200) for producing a biosensor system package (200, 3100), comprising: Providing (302, 2502, 3202) a substrate, the substrate comprising a semiconductor layer (208) having a front side and a back side, a buried oxide layer (206) on the back side, and a bulk silicon layer on the back side; Forming (304, 2504 3204) a transistor structure (210) on the substrate, wherein a channel region (219) of the transistor structure (210) is located in the semiconductor layer (208); Forming (306, 2506, 3206) a multilayer interconnect structure (212) on the front side of the semiconductor layer (208), wherein the multilayer interconnect structure (212) is electrically connected to the transistor structure (210); Attaching (308, 2508, 3208) a carrier substrate (220) to the multilayer interconnect structure (212); removing (3212) the bulk silicon layer; etching (3218) the buried oxide layer (206) to form an opening (222) at the back over the channel region (219); depositing (3216) an interface layer (224) on the back side over the channel region (219); Producing (3220) a microfluidic channel cap structure (228); Bonding the microfluidic channel cap structure (228) to the buried oxide layer (206); Thinning (326, 2510) the carrier substrate (220); Creating (328, 2512) a first substrate via structure (246) extending through the carrier substrate (220), wherein the first substrate via structure (246) is electrically connected to the multilayer interconnect structure (212); and Thinning (332, 2528, 3224) the microfluidic channel cap structure (228) to form at least one port (240') for an inflow and outflow of fluid samples; wherein the production of the microfluidic channel cap structure (228) comprises: Providing a cap structure substrate (230); etching the cap structure substrate (230) to predefine a global cavity region corresponding to a chamber (244); Depositing a hard mask on bonding regions of the cap structure substrate (230); Structuring and etching a portion of the global cavity region to form at least one channel corresponding to the at least one port (240'); etching the entire global cavity region to form the chamber (244); and Removing the hard mask.

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