FERROELECTRIC STORAGE DEVICE AND METHOD FOR FORMING THE SAME

Abstract

Ferroelectric storage device (200), comprising: a multilayer stack arranged over a substrate and comprising a plurality of conductive layers formed as conductor tracks (72) and a plurality of dielectric layers (52) which are alternately stacked one above the other; a channel layer (92) penetrating the plurality of conductive layers and the plurality of dielectric layers (52); and a plurality of ferroelectric sections (90) spaced apart between the channel layer (92) and the plurality of conductive layers, wherein the plurality of ferroelectric sections (90) are spaced apart from one another by one or more non-zero distances, and wherein adjacent ones of the ferroelectric sections (90) are separated from one another by the channel layer (92).

Description

STATE OF THE ART

[0001] Semiconductor devices are used in a wide variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers over a semiconductor substrate and patterning the various material layers using lithography and etching techniques to form circuit components and elements thereon.

[0002] By continuously reducing the minimum feature size, which allows more components to be integrated into a given area, the semiconductor industry is continually improving the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). However, the reduction in minimum feature sizes brings with it additional problems that must be addressed.

[0003] EP 3 499 580 A1 discloses a method for fabricating a three-dimensional 3D semiconductor memory device having a plurality of bit cells, each of which comprises a control gate, a memory element, and a channel. The method comprises providing a vertical stack of alternating layers of a first layer type and a second layer type above a substrate. A memory opening is formed by the vertical stack.

[0004] The article FLORENT K. [et al.]: Vertical ferroelectric HfO2 FET based on 3-D NAND architecture: Towards dense low-power memory. In: IEEE International Electron Devices Meeting (IEDM), 2018, pp. 2.5.1–2.5.4, describes a vertical ferroelectric HfO2 field-effect transistor based on a 3-D macaroni NAND architecture.

[0005] Selective deposition of HfO is described in the article HERREGODS, SJF [et al.]: Vapour phase self-assembled monolayers for ALD blocking on 300 mm wafer scale. In: Euro CVD-21-Baltic ALD-15, Linkoping, Sweden, 2017, pp. 2-4. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the present disclosure are best understood by reference to the following detailed description when taken in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not drawn to scale. Indeed, the dimensions of various features may be arbitrarily exaggerated or reduced for clarity of illustration. The Fig. 1A, Fig. 1B and Fig. 1C illustrate a simplified perspective view, a circuit diagram, and a top-down view of a ferroelectric memory device in accordance with some embodiments. The Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10, Fig. 11, Fig. 12, Fig. 13, Fig. 14, Fig. 15A, Fig. 15B, Fig. 16A, Fig. 16B, Fig. 17A, Fig. 17B, Fig. 18A, Fig. 18B, Fig. 19A, Fig. 19B, Fig. 20A, Fig. 20B, Fig. 20C, Fig. 20D, Fig. 20E, Fig. 20F, Fig. 21, Fig. 22, Fig. 23, Fig. 24A, Fig. 24B, Fig. 25A, Fig. 25B, Fig. 26A, Fig. 26B, Fig. 27A, Fig. 27B, Fig. 28A, Fig. 28B, Fig. 28C, Fig. 28D, Fig. 28E, Fig. 29A, Fig. 29B, Fig. 29C, Fig. 29D and Fig. 29E illustrate various views of fabricating an FC memory array in accordance with some embodiments. The Fig. 30A, Fig. 30B and Fig. 30C illustrate various views of a memory array in accordance with alternative embodiments. Fig. 31 illustrates a method of forming a memory array in accordance with some embodiments. DETAILED DESCRIPTION

[0007] The following disclosure provides many different embodiments, or examples, for implementing various features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, only examples. For example, the formation of a first feature over or on top of a second feature in the following description may include embodiments in which the first and second features are formed in direct contact with each other, but may also include embodiments in which additional features may be formed between the first feature and the second feature such that the first and second features may not be in direct contact with each other. Furthermore, the present disclosure may repeat reference numbers and / or characters in the various examples.This repetition is for the purpose of simplicity and clarity, and does not in itself prescribe any relationship between the various embodiments and / or configurations discussed.

[0008] Furthermore, terms of spatial relationships such as "beneath," "below," "low," "above," "upper," and the like may be used herein for the purpose of more conveniently describing the relationship of one element or feature illustrated in the figures to another element or feature. The terms of spatial relationships are intended to encompass various orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be arranged in a different orientation (rotated 90 degrees or in other orientations), and the terms of spatial relationships used herein may thus be interpreted accordingly.

[0009] Various embodiments provide a memory device, such as a 3D memory array. In some embodiments, the 3D memory array is a ferroelectric field-effect transistor (FeFET) memory circuit comprising a plurality of vertically stacked memory cells. In some embodiments, each of the memory cells is considered to be an FeFET, which includes a word line region serving as a gate electrode, a bit line region serving as a first source / drain electrode, and a source line region serving as a second source / drain electrode, a ferroelectric material as a gate dielectric, and an oxide semiconductor (OS) as a channel region. In some embodiments, each of the memory cells is considered to be a thin-film transistor (TFT).

[0010] The Fig. 1A, Fig. 1B and Fig. 1C illustrate examples of a memory array 200 in accordance with some embodiments. Fig. 1A illustrates an example of a portion of a simplified memory array 200 in a partial three-dimensional view; Fig. 1B illustrates a circuit diagram of the memory array 200; and Fig. 1C illustrates a top-down view of the memory array 200 in accordance with some embodiments. The memory array 200 includes a plurality of memory cells 202, which may be arranged in a grid of rows and columns. The memory cells 202 may further be vertically stacked to provide a three-dimensional memory array and thereby increase device density. The memory array 200 may be arranged at the back end of line (BEOL) of a semiconductor die. For example, the memory array may be arranged in the interconnect layers of the semiconductor die, such as above one or more active devices (e.g., transistors) formed on a semiconductor substrate.

[0011] In some embodiments, the memory array 200 is a flash memory array, such as a NOR flash memory array, or the like. In some embodiments, a gate of each of the memory cells 202 is electrically coupled to a corresponding word line (e.g., trace 72), a first source / drain region of each of the memory cells 202 is electrically coupled to a corresponding bit line (e.g., trace 116B), and a second source / drain region of each of the memory cells 202 is electrically coupled to a corresponding source line (e.g., trace 116A) that electrically connects the second source / drain region to ground.The memory cells 202 in a same horizontal row of the memory array 200 may share a common word line, while the memory cells 202 in a same vertical column of the memory array 200 may share a common source line and a common bit line.

[0012] The memory array 200 includes a plurality of vertically stacked conductive lines 72 (e.g., word lines) with dielectric layers 52 disposed between adjacent ones of the conductive lines 72. The conductive lines 72 extend in a direction parallel to a main surface of a substrate disposed thereunder (in the Fig. 1A and Fig. 1B not specifically shown). The conductive traces 72 may have a stepped arrangement such that lower conductive traces 72 are longer and extend laterally beyond endpoints of the upper conductive traces 72. For example, in Fig. 1A illustrates multiple stacked layers of conductive traces 72, with the topmost conductive traces 72 being the shortest and the bottommost conductive traces 72 being the longest. Respective lengths of the conductive traces 72 may extend in a direction toward the underlying substrate. In this way, a portion of each of the conductive traces 72 may be accessible from above the memory array 200, and conductive contacts may be made to contact respective exposed portions of the conductive traces 72.

[0013] The memory array 200 further includes alternating conductive bumps 106 (which are electrically connected, for example, to bit lines) and conductive bumps 108 (which are electrically connected, for example, to source lines). The conductive bumps 106 and 108 may each extend in a direction perpendicular to the conductive lines 72. A dielectric material 98 is disposed between adjacent conductive bumps 106 and 108, insulating them from each other.

[0014] Pairs of conductive bumps 106 and 108, together with a crossing conductive line 72, define boundaries of each of the memory cells 202, and an isolation bump 102 is disposed between adjacent pairs of conductive bumps 106 and 108 and isolates them from each other. In some embodiments, the conductive bumps 108 are electrically coupled to ground. Although Fig. 1A illustrates a particular positioning of the conductive bumps 106 relative to the conductive bumps 108, it should be understood that the positioning of the conductive bumps 106 and 108 may be reversed in other embodiments.

[0015] In some embodiments, the memory device 200 may also include an oxide semiconductor (OS) material as a channel layer 92. The channel layer 92 may provide channel regions for the memory cells 202. For example, if an appropriate voltage (which is, for example, higher than a corresponding threshold voltage (V th ) of a respective memory cell 202) through a respective conductive line 72, a portion of the channel layer 92 crossing the conductive line 72 may allow current to flow from the conductive bumps 106 to the conductive bumps 108 (for example, in the direction indicated by the arrow 206).

[0016] In some embodiments, the memory array 200 may also include ferroelectric portions 90 arranged separately on sidewall surfaces of the conductive lines 72. For example, the ferroelectric portions 90 may include a first ferroelectric portion arranged on a sidewall surface of a first conductive line and a second ferroelectric portion arranged on a sidewall surface of a second conductive line and separate from the first ferroelectric portion. Since the conductive lines 72 are configured to serve as gate electrodes, the ferroelectric portions 90 may serve as gate dielectrics for the memory cells 202. In some embodiments, the ferroelectric portions 90 include a ferroelectric material, such as hafnium oxide, hafnium zirconium oxide, silicon-doped hafnium oxide, or the like.In some embodiments, respective ones of the ferroelectric sections 90 may have a substantially constant width across a height of the section. In some additional embodiments, respective ones of the ferroelectric sections may have a mixed crystalline-amorphous state having a substantially uniform percentage of crystalline structure (e.g., a substantially constant ratio between crystalline state and amorphous state). In some additional embodiments, respective ones of the ferroelectric sections may have a crystalline structure with an orthorhombic phase of greater than 70 mol%, greater than 80 mol% (e.g., between about 80 mol% and about 99 mol%).Having an orthorhombic phase of more than 70 mol% improves a ferroelectricity of the ferroelectric sections 90, and thus improves the performance (e.g., a read window) of respective memory devices.

[0017] According to the invention, adjacent ferroelectric sections 90 are separated from one another by channel layer 92. In some embodiments, channel layer 92 may extend continuously from a sidewall surface of a first ferroelectric section to a sidewall surface of a second ferroelectric section. In some embodiments, channel layer 92 may line sidewall surfaces and horizontally extending surfaces of ferroelectric sections 90 to define channel layer 92 having an uneven and corrugated sidewall profile. In some embodiments, channel layer 92 has a sidewall profile that defines depressions within one side of channel layer 92 between adjacent ferroelectric sections 90. In some embodiments, dielectric material 98 may extend into the depressions.In some embodiments, the channel layer may contact the dielectric layer 52 disposed between adjacent conductive lines.

[0018] The ferroelectric sections 90 can each be polarized in one of two different directions, and the polarization direction can be changed by applying an appropriate voltage differential to the ferroelectric sections 90 and generating a suitable electric field. The polarization can be relatively localized (e.g., typically contained within each of the boundaries of the memory cells 202). Depending on the polarization direction of a particular region of the ferroelectric sections 90, a threshold voltage of a corresponding memory cell 202 varies, and a digital value (e.g., 0 or 1) can be stored.For example, if a region of the ferroelectric sections 90 has a first electrical polarization direction, the corresponding memory cell 202 may have a relatively low threshold voltage, and if the region of the ferroelectric sections 90 has a second electrical polarization direction, the corresponding memory cell 202 may have a relatively high threshold voltage. The difference between the two threshold voltages may be referred to as the threshold voltage shift. A larger threshold voltage shift makes it easier (e.g., less error-prone) to read the digital value stored in the corresponding memory cell 202.

[0019] To perform a write operation to a memory cell 202 in such embodiments, a write voltage is applied to a portion of the ferroelectric sections 90 corresponding to the memory cell 202. In some embodiments, the write voltage is applied, for example, by applying appropriate voltages to a respective conductive line 72 (e.g., the word line) and the corresponding conductive bumps 106 / 108 (e.g., the bit line / source line). In such embodiments, the conductive line 72 is configured to serve as a gate electrode layer, and the conductive bumps 106 / 108 are configured to serve as source / drain regions. By applying the write voltage to the portion of the ferroelectric sections 90, a polarization direction of the region of the ferroelectric sections 90 can be changed.Consequently, the respective threshold voltage of the respective memory cell 202 can also be switched from a low threshold voltage to a high threshold voltage, or vice versa, and a digital value can be stored in the memory cell 202. Since the conductive lines 72 cross the conductive bumps 106 and 108, individual memory cells 202 can be selected for the write operation.

[0020] To perform a read operation on the memory cell 202 in such embodiments, a read voltage (a voltage between the low and high threshold voltages) is applied to the respective conductive line 72 (e.g., the word line). Depending on the polarization direction of the respective ferroelectric portion 90, the memory cell 202 may or may not be turned on. Consequently, the conductive bump 106 may or may not be discharged through the conductive bump 108 (e.g., a source line coupled to ground), and the digital value stored in the memory cell 202 may be determined. Since the conductive lines 72 cross the conductive bumps 106 and 108, individual memory cells 202 can be selected for the read operation.

[0021] Fig. 1A further illustrates reference cross-sections of the memory array 200 used in later figures. Cross-section BB' runs along a longitudinal axis of the conductive lines 72 and in a direction, for example, parallel to the direction of current flow of the memory cells 202. Cross-section CC' runs perpendicular to cross-section BB' and extends through the dielectric materials 98 and the isolation bumps 102. Cross-section DD' runs perpendicular to cross-section BB' and extends through the dielectric materials 98 and the conductive bumps 106. Cross-section EE' runs perpendicular to cross-section BB' and extends through the dielectric materials 98 and the conductive bumps 106. Cross-section FF' runs parallel to cross-section BB' and extends through the dielectric materials 98, the conductive bumps 106, the isolation bumps 102, and the conductive bumps 108.For clarity, the following figures refer to these reference cross-sections.

[0022] In Fig. 2, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p-type or an n-type dopant) or undoped. The substrate 50 may be an integrated circuit die, such as a logic die, a memory die, an ASIC die, or the like. The substrate 50 may be a complementary metal oxide semiconductor (CMOS) die and may be referred to as a CMOS sub-array (CUA). The substrate 50 may be a wafer, such as a silicon wafer. Generally, an SOI substrate is a layer of a semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is provided on a substrate, typically a silicon or glass substrate.Other substrates, such as a multilayer or gradient substrate, may also be used. In some embodiments, the semiconductor material of substrate 50 may include silicon; germanium; a compound semiconductor comprising silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor comprising silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or combinations thereof.

[0023] Fig. 2 further illustrates circuits that may be formed over substrate 50. The circuits include transistors on a top surface of substrate 50. The transistors may include gate dielectric layers 302 over top surfaces of substrate 50 and gate electrodes 304 over gate dielectric layers 302. Source / drain regions 306 are disposed in substrate 50 on opposite sides of gate dielectric layers 302 and gate electrodes 304. Gate spacers 308 are disposed along sidewalls of gate dielectric layers 302 and separate source / drain regions 306 from gate electrodes 304 by appropriate lateral distances.The transistors may comprise fin field effect transistors (FinFETs), nanostructure FETs (e.g., nanosheet, nanowire, wrap-around gate FETs, or the like) (nanoFETs), planar FETs, the like, or combinations thereof, and may be formed by gate-first or gate-last processes.

[0024] A first interlayer dielectric (ILD) 310 surrounds and insulates the source / drain regions 306, the gate dielectric layers 302, and the gate electrodes 304. A second ILD 312 is disposed over the first ILD 310. Source / drain contacts 314 extend through the second ILD 312 and the first ILD 310 and are electrically coupled to the source / drain regions 306. Gate contacts 316 extend through the second ILD 312 and are electrically coupled to the gate electrodes 304. An interconnect structure 320 is disposed over the second ILD 312, the source / drain contacts 314, and the gate contacts 316. The interconnect structure 320 includes one or more stacked dielectric layers 324 and conductive features 322 formed, for example, in the one or more dielectric layers 324.The interconnect structure 320 may be electrically connected to the gate contacts 316 and the source / drain contacts 314 to form functional circuitry. In some embodiments, the functional circuitry formed by the interconnect structure 320 may include logic circuitry, memory circuitry, sense amplifiers, controllers, input / output circuitry, image sensor circuitry, the like, or combinations thereof. Although. Fig. 2 discussed transistors formed over the substrate 50, other active devices (e.g., diodes or the like) and / or passive devices (e.g., capacitors, resistors, or the like) may also be formed as part of the functional circuits.

[0025] In Fig. 3 is a multilayer stack 58 over the structure of Fig. 2. The substrate 50, the transistors, the ILDs 310 and 312, and the interconnect structure 320 may be omitted from the following drawings for the purpose of simplification and clarity. Although the multilayer stack 58 is illustrated as contacting the dielectric layers 324 of the interconnect structure 320, any number of intermediate layers may be disposed between the substrate 50 and the multilayer stack 58. For example, one or more interconnect layers comprising conductive features in insulating layers (e.g., low-k dielectric layers) may be disposed between the substrate 50 and the multilayer stack 58. In some embodiments, the conductive features may be structured to provide power, ground, and / or signal lines for the active devices on the substrate 50 and / or the memory array 200 (see Fig. 1A and Fig. 1B). In some embodiments, one or more interconnect layers having conductive features in insulating layers (e.g., low-k dielectric layers) may be disposed over the multilayer stack 58.

[0026] In Fig. 3, the multilayer stack 58 includes alternating layers of sacrificial layers 53A-53D (collectively referred to as the sacrificial layers 53) and dielectric layers 52A-52E (collectively referred to as the dielectric layers 52). The sacrificial layers 53 may be patterned and replaced in subsequent steps to define conductive lines 72 (e.g., the wordlines). The sacrificial layers 53 may include dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, combinations thereof, or the like. The dielectric layers 52 may include insulating materials such as aluminum oxide, silicon oxide, silicon nitride, silicon oxynitride, combinations thereof, or the like. The sacrificial layers 53 and the dielectric layers 52 include different materials with different etch selectivities.In some embodiments, sacrificial layers 53 include silicon nitride, and dielectric layers 52 include aluminum oxide or silicon oxide. Both sacrificial layers 53 and dielectric layers 52 may be formed using, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), plasma-enhanced CVD (PECVD), or the like.

[0027] Although Fig. 3 illustrates a specific number of sacrificial layers 53 and dielectric layers 52, other embodiments may include a different number of sacrificial layers 53 and dielectric layers 52. Furthermore, while the multilayer stack 58 is illustrated as having dielectric layers as the bottom and top layers, the disclosure is not so limited. In some embodiments, at least one of the top and bottom layers of the multilayer stack 58 is a sacrificial layer.

[0028] The Fig. 4 to 12 are views of intermediate stages of the manufacture of a stepped structure of the memory device 200 in accordance with the invention. Fig. 4 to 12 are along the Fig. 1A shown reference cross-section BB'.

[0029] In Fig. 4, a photoresist 56 is formed over the multilayer stack 58. In some embodiments, the photoresist 56 is formed using a spin-on technique and patterned using an acceptable photolithography technique. Patterning the photoresist 56 may expose the multilayer stack 58 in regions 60 while masking remaining portions of the multilayer stack 58. For example, a topmost layer of the multilayer stack 58 (e.g., the dielectric layer 52E) may be exposed in regions 60.

[0030] In Fig. 5, the exposed portions of the multilayer stack 58 in the regions 60 are etched using the photoresist 56 as a mask. The etching may be any acceptable etching process, such as a dry etch (e.g., a reactive ion etch (RIE), a neutral beam etch (NBE) or the like), a wet etch, the like, or a combination thereof. The etching may be anisotropic. The etching may remove portions of the dielectric layer 52E and the sacrificial layer 53D in the regions 60 and define openings 61. Because the dielectric layer 52E and the sacrificial layer 53D have different material compositions, the etchants used to remove exposed portions of these layers may differ from each other.In some embodiments, sacrificial layer 53D serves as an etch stop layer during the etching of dielectric layer 52E, and dielectric layer 52D serves as an etch stop layer during the etching of sacrificial layer 53D. Consequently, portions of dielectric layer 52E and sacrificial layer 53D may be selectively removed without removing remaining layers of multilayer stack 58, and openings 61 may extend to a desired depth. Alternatively, a timed etch process may be used to terminate the etching of openings 61 after openings 61 reach a desired depth. In the resulting structure, dielectric layer 52D is exposed in regions 60.

[0031] In Fig. 6, the photoresist 56 is trimmed to expose additional portions of the multilayer stack 58. In some embodiments, the photoresist 56 is trimmed using an acceptable removal technique, such as lateral etching. As a result of the trimming, a width of the photoresist 56 is reduced, and portions of the multilayer stack 58 in the regions 60 and the regions 62 may be exposed. For example, upper surfaces of the dielectric layer 52D may be exposed in the regions 60, and upper surfaces of the dielectric layer 52E may be exposed in the regions 62.

[0032] In Fig. 7, portions of the dielectric layer 52E, the sacrificial layer 53D, the dielectric layer 52D, and the sacrificial layer 53C in the regions 60 and the regions 62 have been removed by acceptable etching processes using the photoresist 56 as a mask. The etching may be any acceptable etching process, such as a dry etch (e.g., RIE, NBE, or the like), a wet etch, the like, or a combination thereof. The etching may be anisotropic. The etching may extend the openings 61 further into the multilayer stack 58. Because the sacrificial layers 53D and 53C and the dielectric layers 52E and 52D have different material compositions, the etchants used to remove exposed portions of these layers may differ from each other.In some embodiments, portions of the dielectric layers 52E and 52D in the regions 62 and 60 are removed by using the photoresist 56 as a mask and using the underlying sacrificial layers 53D and 53C as etch stop layers. Thereafter, the exposed portions of the sacrificial layers 53D and 53C in the regions 62 and 60 are removed by using the photoresist 56 as a mask and using the underlying dielectric layers 52D and 52C as etch stop layers. In the resulting structure, the dielectric layer 52C is exposed in the regions 60, and the dielectric layer 52D is exposed in the regions 62.

[0033] In Fig. 8, the photoresist 56 is trimmed to expose additional portions of the multilayer stack 58. In some embodiments, the photoresist 56 is trimmed using an acceptable removal technique, such as lateral etching. As a result of the trimming, a width of the photoresist 56 is reduced, and portions of the multilayer stack 58 in the regions 60, the regions 62, and the regions 64 may be exposed. For example, upper surfaces of the dielectric layer 52C may be exposed in the regions 60; upper surfaces of the dielectric layer 52D may be exposed in the regions 62; and upper surfaces of the dielectric layer 52E may be exposed in the regions 64.

[0034] In Fig. 9, portions of the dielectric layers 52E, 52D, and 52C and the sacrificial layers 53D, 53C, and 53B in the regions 60, the regions 62, and the regions 64 have been removed by acceptable etching processes using the photoresist 56 as a mask. The etching may be any acceptable etching process, such as a dry etch (e.g., RIE, NBE, or the like), a wet etch, the like, or a combination thereof. The etching may be anisotropic. The etching may extend the openings 61 further into the multilayer stack 58. Because the dielectric layers 52C-52E and the sacrificial layers 53B-53D have different material compositions, the etchants used to remove exposed portions of these layers may differ from each other.In some embodiments, portions of the dielectric layers 52E, 52D, and 52C in regions 64, 62, and 60 are removed by using the photoresist 56 as a mask and using the underlying sacrificial layers 53D, 53C, and 53B as etch stop layers. Thereafter, the exposed portions of the sacrificial layers 53D, 53C, and 53B in regions 64, 62, and 60 are removed by using the photoresist 56 as a mask and using the underlying dielectric layers 52D, 52C, and 52B as etch stop layers. In the resulting structure, the dielectric layer 52B is exposed in regions 60; the dielectric layer 52C is exposed in regions 62; and the dielectric layer 52D is exposed in regions 64.

[0035] In Fig. 10, the photoresist 56 is trimmed to expose additional portions of the multilayer stack 58. In some embodiments, the photoresist 56 is trimmed using an acceptable removal technique, such as lateral etching. As a result of the trimming, a width of the photoresist 56 is reduced, and portions of the multilayer stack 58 in the regions 60, the regions 62, the regions 64, and the regions 66 may be exposed. For example, upper surfaces of the dielectric layer 52B may be exposed in the regions 60; upper surfaces of the dielectric layer 52C may be exposed in the regions 62; upper surfaces of the dielectric layer 52D may be exposed in the regions 64; and upper surfaces of the dielectric layer 52E may be exposed in the regions 66.

[0036] In Fig. 11, portions of the dielectric layers 52E, 52D, 52C, and 52B in the regions 60, the regions 62, the regions 64, and the regions 66 have been removed by acceptable etching processes using the photoresist 56 as a mask. The etching may be any acceptable etching process, such as a dry etch (e.g., RIE, NBE, or the like), a wet etch, the like, or a combination thereof. The etching may be anisotropic. The etching may extend the openings 61 further into the multilayer stack 58. In some embodiments, portions of the dielectric layers 52E, 52D, 52C, and 52B in the regions 66, 64, 62, and 60 are removed by using the photoresist 56 as a mask using the underlying sacrificial layers 53D, 53C, 53B, and 53A as etch stop layers.In the resulting structure, sacrificial layer 53A is exposed in region 60; sacrificial layer 53B is exposed in regions 62; sacrificial layer 53C is exposed in regions 64; and sacrificial layer 53D is exposed in regions 66. Thereafter, photoresist 56 can be removed by an acceptable ashing or wet stripping process.

[0037] In Fig. 12, an intermetal dielectric (IMD) 70 is formed over the multilayer stack 58. The IMD 70 may be formed from a dielectric material and may be deposited by any suitable process, such as CVD, PECVD, flowable CVD (FCVD), or the like. The dielectric materials may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), or the like. In some embodiments, the IMD 70 may include an oxide (e.g., silicon oxide or the like), a nitride (e.g., silicon nitride or the like), a combination thereof, or the like. Other dielectric materials formed by any acceptable process may also be used. Thereafter, a removal process is performed to remove excess dielectric material over the multilayer stack 58.In some embodiments, the removal process may be a planarization process, such as chemical mechanical polishing (CMP), an etch-back process, combinations thereof, or the like. The planarization process exposes the multilayer stack 58 such that upper surfaces of the multilayer stack 58 and the IMD 70 are coplanar after completion of the planarization process. The IMD 70 extends along sidewalls of the sacrificial layers 53B-53D and sidewalls of the dielectric layers 52B-52E. Furthermore, the IMD 70 may contact upper surfaces of the sacrificial layers 53A-53D and the dielectric layer 52E.

[0038] As in Fig. 12, an intermediate and basic stage structure has been formed. The intermediate stage structure has alternating layers of sacrificial layers 53 and dielectric layers 52. The sacrificial layers 53 are subsequently replaced by conductor tracks 72, which are in the Fig. 16A and Fig. 16B. Lower conductive traces 72 are longer and extend laterally beyond upper conductive traces 72, and a width of each of the conductive traces 72 increases in a direction toward the substrate 50 (see Fig. 1A and Fig. 30E).

[0039] The Fig. 13 to 16B are views of intermediate stages of fabricating a memory region of the memory array 200 in accordance with some embodiments. Fig. 13 to 16B, the multilayer base stack 58 is patterned to form trenches 86 therethrough, and the sacrificial layers 53 are replaced by conductive features to define the conductive lines 72. The conductive lines 72 may correspond to word lines in the memory array 200, and the conductive lines 72 may further provide gate electrodes for the resulting memory cells of the memory array 200. The Fig. 13, Fig. 14, Fig. 15B and Fig. 16B are along the Fig. 1A shown reference cross-section CC'. The Fig. 15A and Fig. 16A are shown in a three-dimensional partial view.

[0040] In Fig. 13, the photoresist structures 82 and the underlying hardmask structures 80 have been formed over the multilayer stack 58. In some embodiments, a hardmask layer and a photoresist layer are formed sequentially over the multilayer stack 58. The hardmask layer may, for example, include silicon nitride, silicon oxynitride, or the like, which may be applied by CVD, PVD, ALD, PECVD, or the like. The photoresist layer is formed, for example, using a spin-on technique.

[0041] Thereafter, the photoresist layer is patterned to form photoresist structures 82 and trenches 86 between the photoresist structures 82. The photoresist is patterned, for example, using an acceptable photolithography technique. The patterns of the photoresist structures 82 are then transferred to the hardmask layer to form the hardmask structure 80 using an acceptable etching process, such as a dry etch (e.g., RIE, NBE, or the like), a wet etch, the like, or a combination thereof. The etching may be anisotropic. Thus, trenches 86 are formed which extend through the hardmask layer. Thereafter, the photoresist structures 82 may optionally be removed, for example, using an ashing process.

[0042] In the Fig. 14, Fig. 15A and Fig. 15B, the patterns of the hard mask structures 80 are transferred to the multilayer stack 58 using one or more acceptable etching processes, such as a dry etch (e.g., RIE, NBE, or the like), a wet etch, the like, or a combination thereof. The etching process may be performed anisotropic. Thus, the trenches 86 extend through the base multilayer stack 58, and stripe-shaped sacrificial layers 53 and stripe-shaped dielectric layers 52 are defined accordingly. In some embodiments, the trenches 86 extend through the base step structure, and the stripe-shaped step structures are defined accordingly. Then, the hard mask structures 80 may be removed by an acceptable process, such as a wet etching process, a dry etching process, a planarization process, combinations thereof, or the like.

[0043] In the Fig. 15A, Fig. 15B, Fig. 16A and Fig. 16B, the sacrificial layers 53A-53D (collectively referred to as the sacrificial layers 53) are replaced by conductive lines 72A-72D (collectively referred to as the conductive lines 72). In some embodiments, the sacrificial layers 53 are removed by an acceptable process, such as a wet etching process, a dry etching process, or both. Thereafter, conductive lines 72 are filled in the space between two adjacent dielectric layers 52. As shown in the locally enlarged view, each of the conductive lines 72 includes two barrier layers 71 and 75 and a metal layer 73 between the barrier layers 71 and 75. In particular, the barrier layers 71 or 75 are arranged between the metal layer 73 and the adjacent dielectric layer 52. The barrier layers 71 and 75 may prevent the metal layer from diffusing into the adjacent dielectric layers 52.The barrier layers 71 and 75 may also provide the function of increasing the adhesion between the metal layer 73 and the adjacent dielectric layers 52, and in some examples may be referred to as adhesive layers. In some embodiments, both barrier layers and adhesive layers are provided from different materials as needed. The barrier layers 71 and 75 are formed from a first conductive material, such as a metal nitride, such as titanium nitride, tantalum nitride, molybdenum nitride, zirconium nitride, hafnium nitride, or the like. The metal layers 73 may be formed from a second conductive material, such as a metal, such as tungsten, ruthenium, molybdenum, cobalt, aluminum, nickel, copper, silver, gold, alloys thereof, or the like.The barrier layers 71, 75 and the metal layer 73 can each be formed by an acceptable deposition process, such as CVD, PVD, ALD, PECVD, or the like. The first conductive material of the barrier layers 71 and 75 and the second conductive material of the metal layer 73 are further deposited on the sidewalls of the multilayer stack 58 and fill the trenches 86. Thereafter, the first conductive material of the barrier layers 71 and 75 and the second conductive material of the metal layer 73 in the trenches 86 are removed by an etch-back process. An acceptable etch-back process can be performed to remove excess materials from the sidewalls of the dielectric layers 52 and the bottom surfaces of the trenches 86. The acceptable etch-back process includes a dry etch (e.g., RIE, NBE, or the like), a wet etch, the like, or a combination thereof. The acceptable etch-back process can be anisotropic.

[0044] In some embodiments, during the replacement process, the sacrificial layers 53 of the strip-shaped step-like structures are subsequently replaced by conductive traces 72 (see Fig. 1A) replaced.

[0045] The Fig. 17A to 19B illustrate the selective formation of ferroelectric portions 90 in the trenches 86. The Fig. 17A, Fig. 18A and Fig. 19A are shown in a three-dimensional partial view. In the Fig. 17B, Fig. 18B and Fig. 19B are cross-sectional views along the line CC' of Fig. 1A provided.

[0046] In the Fig. 17A and Fig. 17B, ​​a surface treatment 87 is performed on regions 89 between the conductive lines 72 to selectively modify upper surfaces of the dielectric layers 52 such that the surface energy difference between the regions 89 and the conductive lines 72 increases. In some embodiments, the surface treatment 87 is performed to provide surfaces of the regions 89, which exhibit hydrophobicity or superhydrophobicity, with high wettability and low surface energy. The surface treatment 87 can be performed, for example, by a method described as follows.

[0047] Inhibitor portions 88 are selectively formed on the surfaces of the dielectric layers 52 within the regions 89. The inhibitor portions 88 may be referred to as barrier layers that block the surfaces of the dielectric layers 52 to prevent the subsequently formed ferroelectric portions 90 from being deposited on the surfaces of the dielectric layers 52 within the regions 89. In an embodiment in which the dielectric layers 52 are formed from oxide, the inhibitor portions 88 are formed from an organic material that can react with or adsorb to oxide surfaces of the dielectric layers 52. The organic material may, for example, be a self-assembled monolayer (SAM) for surface modification of the dielectric layers 52.The SAM may be a molecular array that can be organized into ordered arrays at the exposed oxide surfaces of the dielectric layers 52. Each molecule of the SAM may have a head group and a tail, with the head group anchoring the molecule to the oxide surfaces of the dielectric layers 52 and the tail preventing the ferroelectric portions 90 from being deposited at the oxide surfaces of the dielectric layers 52.

[0048] In some embodiments, the inhibitor sections 88 are formed from a molecule having a head group. The head group is a metallophilic head group that anchors to the oxide surfaces of the dielectric layers 52. In one embodiment, the metallophilic head group of the molecule contains a phosphorus atom (P), a sulfur atom (S), or the like.

[0049] Consistent with embodiments of the disclosure, the tail of the molecule forming the inhibitor portions 88 is a metallophobic alkyl tail. The metallophobic alkyl tail comprises, for example, an alkyl chain with a large molecular size or a long carbon chain to prevent the ferroelectric portions 90 from being deposited on its surface. In some embodiments, the tail of the molecule is formed from at least 12 backbone atoms, such as 12 carbon atoms. In one embodiment, the tail of the molecule is formed from approximately 18 backbone atoms. The large molecular structure of the SAM may prevent the ferroelectric portions 90 from being deposited on its surface.

[0050] For example, the inhibitor portions 88 may be formed from molecules selected from the group including, but not limited to, an alkanethiol, such as 1-octadecanethiol (ODT), or an alkanephosphonic acid, such as octadecylphosphonic acid (ODPA). In one embodiment, the inhibitor portions 88 are formed from ODT or ODPA, which attach to the oxide-formed dielectric layers 52. The inhibitor portions 88 may have a thickness T1 of approximately 0.1 nm to 2 nm.

[0051] The inhibitor portions 88 can be deposited by a solution-phase process or vapor-phase epitaxy. For example, the inhibitor portions 88 can be deposited by a solution-phase process in a suitable processing environment, such as a balance of acid concentration, solution temperature, and passivation time. In one embodiment, a balanced processing environment comprises ODPA or ODT with a concentration of between 1 mM and 20 mM, a solution temperature between room temperature and 150°C, and / or a passivation time of between 0.5 and 2 hours.

[0052] In the Fig. 18A and Fig. 18B, ferroelectric portions 90 are formed in the trenches 86 above the conductive lines 72. The ferroelectric portions 90 may include ferroelectric portions 90A, 90B, 90C, and 90D disposed separately on sidewall surfaces of the conductive lines 72A, 72B, 72C, and 72D, respectively. In some embodiments, the ferroelectric portions 90 are not deposited on the inhibitor portions 88, so that the regions 89 between the conductive lines 72 are free of ferroelectric portions. In some additional embodiments, the ferroelectric portions are not deposited on the IMD 70 at the bottom of the trenches 86. It has been concluded that the ferroelectric material of the ferroelectric sections 90 can form on different materials (for example, on the conductive traces 72 and the dielectric layers 52) in different thicknesses, different crystal structures and / or different phases.Such differences in the ferroelectric material can lead to differences in the application of various memory devices. By using the inhibitor portions 88 to prevent the ferroelectric material from forming on the dielectric layer 52, the separate ferroelectric portions 90 can be formed to have a uniform (i.e., constant) thickness, crystal structure, and / or phase throughout the ferroelectric portions, improving memory performance.

[0053] The ferroelectric sections 90 may include a material capable of switching between two different polarization directions by applying a suitable voltage difference to the ferroelectric sections 90. For example, the ferroelectric sections 90 include a high-k dielectric material, such as hafnium (Hf)-based dielectric materials or the like. In some embodiments, the ferroelectric sections 90 include hafnium oxide, hafnium-zirconium oxide, silicon-doped hafnium oxide, or the like.

[0054] In some embodiments, the ferroelectric sections 90 may comprise barium titanium oxide (BaTiO3), lead titanium oxide (PbTiO3), lead zirconium oxide (PbZrO3), lithium niobium oxide (LiNbO3), sodium niobium oxide (NaNbO3), potassium niobium oxide (KNbO3), potassium tantalum oxide (KTaO3), bismuth scandium oxide (BiScO3), bismuth iron oxide (BiFeO3), hafnium erbium oxide (Hf1-xErxO), hafnium lanthanum oxide (Hf1-xLaxO), hafnium yttrium oxide (Hf1-xYxO), hafnium gadolinium oxide (Hf1-xGdxO), hafnium aluminum oxide (Hf1-xAlxO), hafnium zirconium oxide (Hf 1-x Zr x O, H 2 O), hafnium titanium oxide (Hf 1-x Ti x O), hafnium tantalum oxide (Hf 1-x Ti x O), or a combination thereof, or the like. In some embodiments, the ferroelectric sections 90 may contain different ferroelectric materials or different types of memory materials.In some embodiments, the method of forming the ferroelectric portions 90 includes performing a suitable deposition technique, such as CVD, PECVD, metal oxide chemical vapor deposition (MOCVD), ALD, RPALD, PEALD, MBD, or the like.

[0055] In some embodiments where the inhibitor portion 88 is formed from an organic material, such as SAM, to prevent the inhibitor portions 88 from breaking due to thermal decomposition, the ferroelectric portions 90 are deposited using a low-temperature deposition process. In an embodiment where the SAM decomposition temperature is between room temperature and 200°C, the ferroelectric portions 90 are deposited at a temperature lower than room temperature to 200°C to reduce the rate of SAM decomposition without significantly damaging the inhibitor portions 88. This allows the inhibitor portions 88 to retain their barrier capabilities throughout the deposition of the ferroelectric portions 90.

[0056] The ferroelectric portion 90 has a thickness T2 equal to or greater than the thickness T1 of the inhibitor portion 88. In some embodiments, the ferroelectric portion 90 has a thickness T2 of approximately 1-20 nm, such as 5-10 nm. Other thickness ranges (e.g., greater than 20 nm or 5-15 nm) may be applicable. In some embodiments, the ferroelectric portion 90 is formed in a fully amorphous state. In alternative embodiments, the ferroelectric portion 90 is formed in a partially crystalline state; that is, the ferroelectric portion 90 is formed in a mixed crystalline-amorphous state and has a certain degree of structural order. In further alternative embodiments, the ferroelectric portion 90 is formed in a fully crystalline state. In some embodiments, the ferroelectric portion 90 is a single layer.In alternative embodiments, the ferroelectric portion 90 is a multilayer structure.

[0057] An annealing process is performed on the ferroelectric sections 90 and the inhibitor sections 88. The temperature range of the annealing process is from approximately 100°C to approximately 400°C so that the ferroelectric sections 90 can acquire a desired crystalline lattice structure and the inhibitor sections 88 can decompose. In some embodiments, the ferroelectric section 90 is converted from an amorphous state to a partially or fully crystalline state during the annealing process. In alternative embodiments, the ferroelectric sections 90 are converted from a partially crystalline state to a fully crystalline state during the annealing process. In this way, the ferroelectric sections 90 can have an orthorhombic crystal phase. In some embodiments, the orthorhombic crystal phase in the ferroelectric sections 90 is greater than 70 mol% (i.e., 70%).In some embodiments, the orthorhombic crystal phase in the ferroelectric sections 90 is greater than 80 mol%. For example, the orthorhombic crystal phase in the ferroelectric sections 90 is between 80 mol% and 99 mol%. After the inhibitor sections 88 have decomposed, sidewall surfaces of the dielectric layers 52 are exposed in regions 89, and two adjacent ferroelectric sections 90 and the dielectric layer 52 therebetween form a transverse groove G.

[0058] The Fig. 20A to 20F illustrate the selective formation of a channel layer 92 over the ferroelectric portions 90 and the dielectric layers 52. Fig. 20A is shown in a three-dimensional partial view. In Fig. 20B is a cross-sectional view along line CC' of Fig. 1A provided. The Fig. 20C, Fig. 20D, Fig. 20E and Fig. 20F represent locally enlarged views in an area A of Fig. 20B.

[0059] In the Fig. 20A and Fig. 20B, a channel layer 92 is deposited in the trenches 86 and the transverse grooves G. The channel layer 92 contains materials suitable for providing channel regions for the memory cells 202 (see Fig. 1A). For example, the channel layer 92 includes an oxide semiconductor (OS), such as zinc oxide (ZnO), indium tungsten oxide (InWO), indium gallium zinc oxide (InGaZnO, IGZO), indium zinc oxide (InZnO), indium tin oxide (ITO), combinations thereof, or the like. In some embodiments, the channel layer 92 includes polycrystalline silicon (poly-Si), amorphous silicon (a-Si), or the like. The channel layer 92 may be deposited by CVD, PVD, ALD, PECVD, or the like.

[0060] The channel layer 92 may extend along sidewalls and bottom surfaces of the trenches 86 and along top surfaces, sidewalls, and bottoms of the transverse grooves G above the ferroelectric sections 90 and dielectric layers 52. In some embodiments, the channel layer 92 may be further deposited on the IMD 70 and along the sidewall of each of the steps of the step structure in the step-shaped region. The channel layer 92 is in contact with top surfaces, sidewall surfaces, and bottom surfaces of the ferroelectric sections 90, as well as sidewall surfaces of the dielectric layers 52. In some embodiments, the channel layer 92 is conformally deposited on the ferroelectric sections 90 and the dielectric layers 52, whereby the channel layer 92 has an uneven and wavy sidewall profile. In some embodiments, both sidewalls SW1 and SW2 of the channel layer 92 are wavy.The sidewall SW2 of the channel layer 92 has transverse grooves H in planes of the dielectric layers 52, as shown in FIGS. Fig. 20C, Fig. 20D and Fig. 20E. The transverse grooves H are recessed toward the dielectric layers 52. In alternative embodiments, a sidewall SW1 of the channel layer 92, which is in contact with the ferroelectric sections 90 and the dielectric layer 52, is wavy, while a sidewall SW2 of the channel layer 92, which is not in contact with the ferroelectric sections 90 and the dielectric layer 52, is substantially straight, as shown in Fig. 20F shown.

[0061] In some embodiments, the channel layer 92 in the transverse groove G has a thickness T3 equal to the thickness T2 of the ferroelectric portion 90, as shown in Fig. 20C. In alternative embodiments, the channel layer 92 in the transverse groove G has a thickness T3 less than the thickness T2 of the ferroelectric portion 90, as shown in Fig. 20D. In alternative embodiments, the channel layer 92 in the transverse groove G has a thickness T3 less than the thickness T2 of the ferroelectric portion 90, as shown in Fig. 20D. In further alternative embodiments, the channel layer 92 in the transverse groove G has a thickness T3 greater than the thickness T2 of the ferroelectric portion 90, as shown in the Fig. 20E and Fig. 20F shown.

[0062] After the channel layer 92 has been deposited, an annealing process (for example, in a temperature range of approximately 300°C to approximately 450°C) may be performed in an oxygen-containing environment to activate the charge carriers of the channel layer 92.

[0063] The Fig. 21 to 24B illustrate the formation of dielectric material 98 and the patterning of the channel layer 92 for the memory cells 202 (see Fig. 1A) in trenches 86. Fig. 24A is shown in a three-dimensional partial view. In the Fig. 21, Fig. 22, Fig. 23 and Fig. 24B are cross-sectional views along the line CC' of Fig. 1A provided.

[0064] In Fig. 21, a dielectric material 98A is deposited in the trenches 86 and the transverse grooves H above the channel layer 92. In some embodiments, the dielectric material 98A includes silicon oxide, silicon nitride, silicon oxynitride, or the like, which may be deposited by CVD, PVD, ALD, PECVD, or the like. The dielectric material 98A may extend along sidewalls and bottom surfaces of the trenches 86 above the channel layer 92. In some embodiments, the dielectric material 98A is optional and may be omitted if desired.

[0065] In Fig. 22, lower portions of the dielectric material 98A and the channel layer 92 in the trenches 86 are removed. The removal process includes an acceptable etching process, such as a dry etch (e.g., RIE, NBE, or the like), a wet etch, the like, or a combination thereof. The etching may be anisotropic. In some embodiments, the upper portions of the dielectric material 98A and the channel layer 92 are removed from the multilayer stack 58. In some embodiments, the removal process includes a combination of photolithography and etching.

[0066] Consequently, the remaining dielectric material 98A and the channel layer 92 may expose portions of the ferroelectric portion 90 at bottom surfaces of the trenches 86. Thus, portions of the channel layer 92 may be separated from each other at opposite sidewalls of the trenches 86, which may improve the insulation between the memory cells 202 of the memory array 200 (see Fig. 1A) improved.

[0067] In Fig. 23, a dielectric material 98B is applied to completely fill the trenches 86. The dielectric material 98B may be formed from one or more materials and by processes the same or similar to those for the dielectric material 98A. In some embodiments, the dielectric material 98B and the dielectric material 98A include different materials. The dielectric materials 98A and 98B are collectively referred to as a dielectric material 98. The dielectric material 98 has an uneven and wavy sidewall profile.

[0068] In the Fig. 24A and Fig. 24B, a removal process is applied to the dielectric materials 98A / 98B, the channel layer 92, and the ferroelectric portion 90 to remove excess materials over the multilayer stack 58. In some embodiments, a planarization process, such as a CMP, an etch-back process, combinations thereof, or the like, may be used. The planarization process exposes the multilayer stack 58 such that top surfaces of the multilayer stack 58 (e.g., the dielectric layer 52E), the ferroelectric portions 90, the channel layer 92, the dielectric material 98, and the IMD 70 are arranged on a plane after completion of the planarization process.

[0069] The Fig. 25A to 28D illustrate intermediate steps in the fabrication of conductive bumps 106 and 108 (e.g., source / drain bumps) in the memory array 200. The conductive bumps 106 and 108 may extend along a direction perpendicular to the conductive lines 72 so that individual cells of the memory array 200 may be selected for read and write operations. Fig. 25A, Fig. 26A, Fig. 27A and Fig. 28A are shown in a three-dimensional partial view. In the Fig. 25B and Fig. 26B are cross-sectional views along the line CC' of Fig. 1A provided. In the Fig. 27B and Fig. 28B are cross-sectional views along the line DD' of Fig. 1A provided. In Fig. Figure 28C is a cross-sectional view along line EE' of Fig. 1A provided. In Fig. Figure 28D is a cross-sectional view along line FF' of Fig. 1A provided. In Fig. 28E is a top-down view of Fig. 1A provided.

[0070] In the Fig. 25A and Fig. 25B, trenches 100 are formed through the channel layer 92 and the dielectric material 98. The trenches 100 may be formed by a combination of photolithography and etching, for example, to remove portions of the dielectric material 98. The trenches 100 may be arranged between opposite sidewalls of the ferroelectric portions 90 and may connect adjacent stacks of memory cells in the memory array 200 (see Fig. 1A) physically separate them.

[0071] In the Fig. 26A and Fig. 26B, isolation bumps 102 are formed in the trenches 100. In some embodiments, an isolation layer is deposited over the multilayer stack 58 to fill the trenches 100. The isolation layer may include, for example, silicon oxide, silicon nitride, silicon oxynitride, or the like, which may be deposited by CVD, PVD, ALD, PECVD, or the like. The isolation layer may extend along sidewalls and bottom surfaces of the trenches 100 above the channel layer 92. After deposition, a planarization process (e.g., CMP, etchback, or the like) may be performed to remove excess portions of the isolation layer.In the resulting structure, top surfaces of the multilayer stack 58 (e.g., the dielectric layer 52E), the ferroelectric portions 90, the channel layer 92, and the isolation bumps 102 may be substantially coplanar (e.g., within typical process variations). In some embodiments, materials of the dielectric material 98 and the isolation bumps 102 may be selected such that they can be selectively etched relative to each other. For example, in some embodiments, the dielectric material 98 includes oxide, and the isolation bumps 102 include nitride. In some embodiments, the dielectric material 98 includes nitride, and the isolation bumps 102 include oxide. Other materials are also possible.

[0072] In the Fig. 27A and Fig. 27B, trenches 104 are formed for the subsequently formed conductive bumps 106 and 108. The trenches 104 are formed by patterning the dielectric material 98, for example, with a combination of photolithography and etching. In some embodiments, as in Fig. 27A, a photoresist 118 is formed over the multilayer stack 58, the dielectric material 98, the isolation bumps 102, the channel layer 92, and the ferroelectric portion 90. In some embodiments, the photoresist 118 is patterned by an acceptable photolithography technique to define openings 120. Each of the openings 120 may expose the corresponding isolation bump 102 and two separate regions of the dielectric material 98 adjacent to the isolation bump 102. In this way, each of the openings 120 may define a pattern of a conductive bump 106 and an adjacent conductive bump 108 separated from each other by the isolation bumps 102.

[0073] Subsequently, portions of the dielectric material 98 exposed through the openings 120 may be removed by an acceptable etching process, such as a dry etch (e.g., RIE, NBE, or the like), a wet etch, the like, or a combination thereof. The etching may be anisotropic. The etching process may use an etchant that etches the dielectric material 98 without significantly etching the isolation bumps 102. As a result, the isolation bumps 102 may not be significantly removed even though they have been exposed through the openings 120. Structures of the trenches 104 may correspond to the conductive bumps 106 and 108 (see Fig. 28A and Fig. 28B). After the trenches 104 have been patterned, the photoresist 118 can be removed, for example, by ashing.

[0074] In the Fig. 28A and Fig. 28E, the trenches 104 are filled with a conductive material to form the conductive bumps 106 and 108. The conductive material may include copper, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, ruthenium, aluminum, combinations thereof, or the like, which may be formed, for example, using CVD, ALD, PVD, PECVD, or the like. After the conductive material is deposited, planarization (e.g., CMP, etchback, or the like) may be performed to remove excess portions of the conductive material, thereby forming the conductive bumps 106 and 108.In the resulting structure, top surfaces of the multilayer stack 58 (e.g., dielectric layer 52E), the ferroelectric portions 90, the channel layer 92, the conductive bumps 106, and the conductive bumps 108 may be substantially coplanar (e.g., within typical process variations). In some embodiments, the conductive bumps 106 correspond to and are electrically connected to the bit lines in the memory array, and the conductive bumps 108 correspond to and are electrically connected to the source lines in the memory array 200.

[0075] The conductive bumps 106 and 108 penetrate the conductive traces 72 and the dielectric layers 52 of the multilayer stack 58. In some embodiments, the conductive bumps 106 and 108 have uneven and wavy sidewall profiles. The conductive bump 106 or 108 has first portions P1 and second portions P2, as shown in Fig. 28C. The first sections P1 are arranged in the same planes as the dielectric layers 52. The second sections P2 are arranged in the same planes as the conductive lines 72. The first sections P1 and the second sections P2 have different widths. In some embodiments, the first section P1 has a first width W1 that is greater than a second width W2 of the second section P2. The channel layer 92 is sandwiched between the first sections P1 and the dielectric layers 52 and sandwiched between the second sections P2 and the ferroelectric sections 90. In some embodiments, the channel layer 92 is in contact with the first sections P1 and the dielectric layers 52 and in contact with the second sections P2 and the ferroelectric sections 90.

[0076] Thus, the stacked memory cells 202 can be formed in the memory array 200 as shown in Fig. 1A. Each of the memory cells 202 includes a gate electrode (e.g., a portion of a corresponding conductive line 72), a gate dielectric (e.g., a portion of a corresponding ferroelectric portion 90), a channel region (e.g., a portion of a corresponding channel layer 92), and source / drain bumps (e.g., portions of the corresponding conductive bumps 106 and 108). The isolation bumps 102 isolate adjacent memory cells 202 in a same column and on a same vertical plane. The memory cells 202 may be arranged in an array of vertically stacked rows and columns.

[0077] The Fig. 29A, Fig. 29B, Fig. 29C and Fig. 29D illustrate the formation of conductive traces 116A, 116B, and 116C for the memory array 200. Fig. 29A illustrates a perspective view of the memory assembly 200; Fig. Figure 29B illustrates a cross-sectional view of the memory array 200 along line DD' of Fig. 1A; Fig. Figure 29C illustrates a top-down view of the memory array 200 of Fig. 29A; Fig. Figure 29D is a cross-sectional view along line EE' of Fig. 1A; and Fig. Figure 29E is a cross-sectional view of the device taken along line BB' of Fig. 1A.

[0078] In the Fig. 29A, Fig. 29B, Fig. 29C, Fig. 29D and Fig. 29E, an IMD 74 is formed on upper surfaces of the multilayer stack 58 (e.g., the dielectric layer 52E), the ferroelectric portions 90, the channel layer 92, the conductive bumps 106, and the conductive bumps 108, and the IMD 70. Conductive contacts 110, 112, and 114 are formed on the conductive lines 72, the conductive bumps 106, and the conductive bumps 108, respectively.

[0079] The IMD 74 may be formed from a dielectric material and may be deposited by any suitable process, such as CVD, PECVD, flowable CVD (FCVD), or the like. The dielectric materials may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), a low-k dielectric material, or the like. In some embodiments, the IMD 74 may include an oxide (e.g., silicon oxide or the like), a nitride (e.g., silicon nitride or the like), a combination thereof, or the like. Other dielectric materials formed by any acceptable process may also be used. Thereafter, a removal process is applied to the IMD 74 to remove excess dielectric material over the multilayer stack 58 and the IMD 70.In some embodiments, the removal process may be a planarization process, such as chemical mechanical polishing (CMP), an etch-back process, combinations thereof, or the like.

[0080] In some embodiments, the stepped shape of the conductive lines 72 may provide a surface on each of the conductive lines 72 upon which the conductive contacts 110 may land. In some embodiments, forming the conductive contacts 110 may include patterning openings in the IMD 74 and the IMD 70 to expose portions of the conductive lines 72, for example, using a combination of photolithography and etching. A liner (not shown), such as a diffusion barrier layer, an adhesion layer, or the like, and a conductive material are formed in the openings. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may include copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like.A planarization process, such as CMP, can be performed to remove excess material from the surfaces of the ILM 74. The remaining liner and conductive material form the conductive contacts 110 in the openings.

[0081] As also shown by the perspective view of Fig. 29A, conductive contacts 112 and 114 may also be formed on conductive bumps 106 and conductive bumps 108, respectively. The conductive contacts 112, 114, and 110 may be electrically connected to conductive traces 116A, 116B, and 116C, respectively, which connect the memory array to underlying / overlying circuitry (e.g., control circuitry) and / or signal, power, and ground lines in the semiconductor die. As shown in Fig. 30D, for example, conductive contacts 110 may extend through IMD 74 and IMD 70 to electrically connect conductive traces 116C to conductive traces 72. Other conductive contacts or vias may be formed through IMD 74 to electrically connect conductive traces 116A and 116B to the underlying active devices on the substrate. In alternative embodiments, routing and / or power lines to and from the memory array may be provided by an interconnect structure formed over memory array 200 in addition to or instead of interconnect structure 320. Consequently, memory array 200 may now be completed.

[0082] Although the embodiments of the Fig. 1A to 29D illustrate a specific structure for the conductive bumps 106 and 108, other configurations are also possible. For example, in these embodiments, the conductive bumps 106 and 108 have a staggered structure. However, in other embodiments, the conductive bumps 106 and 108 are all aligned in a same row of the array, as in the ferroelectric memory array 200A of FIG. Fig. 30A, Fig. 30B and Fig. 30C shown. The Fig. 30A, Fig. 30B and Fig. 30C illustrate examples of a memory array 200A in accordance with alternative embodiments. Fig. 30A illustrates a perspective view of the memory assembly 200A; Fig. Figure 30B is a cross-sectional view of the device taken along line HH' of Fig. 30A; and Fig. Figure 30C illustrates a top-down view of the memory array 200A.

[0083] Fig. 31 illustrates a method of forming a ferroelectric memory device in accordance with some embodiments. Although the method has been illustrated and / or described as a sequence of steps or events, it should be understood that the method is not limited to the illustrated order or steps. Therefore, in some embodiments, the steps may be performed in different orders than those illustrated and / or may be performed concurrently. Further, in some embodiments, the illustrated steps or events may be divided into multiple steps or events that may be performed at different times or concurrently with other steps or sub-steps. In some embodiments, some illustrated steps or events may be omitted, and other non-illustrated steps or events may be performed.

[0084] In step S300, a multilayer stack is formed over a substrate. The multilayer stack includes a plurality of alternately stacked dielectric layers and conductive layers and includes a trench penetrating the dielectric layers and conductive layers. Fig. 4 to Fig. 16B illustrate various views according to some embodiments of step S300.

[0085] In step S302, a plurality of ferroelectric sections are selectively formed. The plurality of ferroelectric sections are separately formed on sidewall surfaces of the plurality of conductive layers. In some embodiments, selectively forming a plurality of ferroelectric sections comprises performing a surface treatment on the plurality of dielectric layers; and depositing the plurality of ferroelectric layers on the sidewalls of the plurality of conductive layers. The surface treatment comprises selectively forming a plurality of inhibitor sections on the sidewall surfaces of the plurality of dielectric layers. The plurality of inhibitor sections comprises a plurality of self-assembled monolayers. The plurality of self-assembled monolayers contains, for example, an alkanethiol, an alkanephosphonic acid, or a combination thereof.The majority of self-assembled monolayers contain 1-octadecanethiol (ODT) or octadecylphosphonic acid (ODPA). After the majority of ferroelectric sections have been deposited, an annealing process is performed to remove the majority of self-assembled monolayers. Fig. 17A to Fig. 19B illustrate various views according to some embodiments of step S302.

[0086] At step S304, a channel layer is formed on the plurality of ferroelectric portions. Fig. 20A to Fig. 20F illustrate various views according to some embodiments of step S304.

[0087] In some embodiments of the disclosure, inhibitor portions are selectively formed on the sidewall surfaces of the multilayer stack of dielectric layers, and thus ferroelectric portions are separately disposed on the conductive layers of the multilayer stack. Since the sidewall surfaces of the dielectric layers are blocked by the inhibitor portions, a ferroelectric material hardly forms on the sidewall surfaces of the dielectric layers. Therefore, the problem of different growth rates of the ferroelectric material on the dielectric layers and the conductive layers, as well as the different proportion of the orthogonal phase of the ferroelectric material on the dielectric layers and the conductive layers, can be solved.Furthermore, since the ferroelectric material does not form on the dielectric layers, the ferroelectric material on the conductive layers is not suppressed by the ferroelectric material on the dielectric layers, which facilitates the formation of the orthorhombic phase and increases the proportion of the orthorhombic phase. With the method of the disclosure, the proportion of the orthorhombic phase of the ferroelectric material on the sidewall surfaces of the conductive layers can be precisely controlled, so that the method of the disclosure can be applied to the high-density 3D memory structure in a small HZO active area. Furthermore, since the disclosed method is a low-temperature process, it can be integrated into the BEOL for embedded memory applications.

[0088] In the above embodiments, the ferroelectric memory device is formed by a "staircase-first process" in which the stepped structure is formed before the memory cells are formed. However, the disclosure is not limited thereto. In other embodiments, the ferroelectric memory device may be formed by a "staircase-last process" in which the stepped structure is formed after the memory cells are formed.

[0089] In the above embodiments, the gate electrodes (e.g., word lines) are formed by applying sacrificial dielectric layers followed by replacing the sacrificial dielectric layers with conductive layers. However, the disclosure is not limited thereto. In other embodiments, the gate electrodes (e.g., word lines) may be formed in the first phase without requiring the replacement step.

[0090] The present disclosure contemplates numerous variations of the above examples. It should be understood that different embodiments may have different advantages, and that no particular advantage is necessarily required for any embodiment.

[0091] In accordance with some embodiments of the invention, a ferroelectric memory device comprises a multilayer stack disposed over a substrate and comprising a plurality of alternately stacked conductive layers and dielectric layers; a channel layer penetrating the plurality of conductive layers and the plurality of dielectric layers; and a plurality of ferroelectric sections spaced apart between the channel layer and the plurality of conductive layers, the plurality of ferroelectric sections being vertically separated from each other by a non-zero pitch.

[0092] In accordance with alternative embodiments of the invention, a device comprises a semiconductor substrate, a first memory cell over the semiconductor substrate, and a second memory cell over the first memory cell. The first memory cell comprises a first thin-film transistor. The first thin-film transistor comprises: a first ferroelectric portion on a sidewall of a first conductive line; and a first channel region of a first channel layer around a top surface, a sidewall, and a bottom surface of the first ferroelectric portion. A conductive bump extends vertically along the sides of the first memory cell and the second memory cell, the first ferroelectric portion and the first channel region being laterally disposed between the first conductive line and the conductive bump.

[0093] In accordance with further alternative embodiments of the invention, a method of forming a ferroelectric memory device comprises forming a multilayer stack comprising a plurality of dielectric layers and a plurality of conductive layers stacked alternately over a substrate, wherein sidewalls of the plurality of dielectric layers and the plurality of conductive layers define a trench penetrating therethrough; selectively forming a plurality of ferroelectric sections separately on sidewalls of the plurality of conductive layers; forming a channel layer on the plurality of ferroelectric sections and the sidewalls of the plurality of dielectric layers; and forming a conductive bump along sidewalls of the channel layer.

Claims

[1] Ferroelectric storage device (200), comprising: a multilayer stack arranged over a substrate and comprising a plurality of conductive layers formed as conductor tracks (72) and a plurality of dielectric layers (52) which are alternately stacked one above the other; a channel layer (92) penetrating the plurality of conductive layers and the plurality of dielectric layers (52); and a plurality of ferroelectric sections (90) spaced apart between the channel layer (92) and the plurality of conductive layers, wherein the plurality of ferroelectric sections (90) are spaced apart from one another by one or more non-zero distances, and wherein adjacent ones of the ferroelectric sections (90) are separated from one another by the channel layer (92). [2] The ferroelectric memory device (200) of claim 1, wherein the channel layer (92) has an uneven and wavy sidewall profile. [3] The ferroelectric memory device (200) of claim 1 or 2, wherein the channel layer (92) is in contact with a plurality of upper surfaces, a plurality of lower surfaces, and a plurality of sidewall surfaces of the plurality of ferroelectric sections (90). [4] The ferroelectric memory device (200) of claim 3, wherein the channel layer (92) is further in contact with the plurality of dielectric layers (52). [5] The ferroelectric memory device (200) of any preceding claim, wherein the plurality of ferroelectric sections (90) have a crystalline structure with an orthorhombic phase between 80 mol% and 99 mol%. [6] Device (200) comprising: a semiconductor substrate; a first memory cell (202) above the semiconductor substrate, the first memory cell (202) comprising a first thin-film transistor, the first thin-film transistor comprising: a first ferroelectric portion (90) on a sidewall of a first conductive track (72); and a first channel region of a first channel layer (92) around a top surface, a sidewall and a bottom surface of the first ferroelectric section (90); a second memory cell (202) above the first memory cell (202); and a conductive bump (106) extending vertically along the sides of the first memory cell (202) and the second memory cell (202), wherein the first ferroelectric portion (90) and the first channel region are arranged laterally between the first conductive line (72) and the conductive bump (106), wherein the second memory cell (202) comprises a second thin-film transistor, and the second thin-film transistor comprises: a second conductor track (72) arranged over the first conductor track (72) and separated from the first conductor track (72) by a dielectric layer (52); a second ferroelectric portion (90) on a sidewall of a second conductor track (72); and a second channel region of the channel layer (92) around a top surface, a sidewall, and a bottom surface of the second ferroelectric section (90), wherein adjacent ones of the ferroelectric sections (90) are separated from each other by the channel layer (92). [7] The device (200) of claim 6, wherein the channel layer (92) extends continuously to contact the top surfaces, the sidewalls, and the bottom surfaces of the first ferroelectric portion (90) and the second ferroelectric portion (90). [8] The device (200) of claim 6 or 7, wherein the conductive bump (106) comprises: a first region on a side wall of the first channel region; and a second region on a side wall of the second channel region of the channel layer, wherein the first region and the second region have smaller widths than a third region arranged vertically therebetween. [9] The device (200) of any one of claims 6 to 8, wherein the first ferroelectric portion (90) has a crystalline structure with an orthorhombic phase between 80 mol% and 99 mol%. [10] A method of forming a ferroelectric memory device (200), comprising: Forming a multilayer stack comprising a plurality of dielectric layers (52) and a plurality of conductive layers (72) arranged alternately over a substrate, wherein sidewalls of the plurality of dielectric layers (52) and the plurality of conductive layers (72) define a trench (86) penetrating therethrough; selectively forming a plurality of ferroelectric sections (90) separately on the sidewalls of the plurality of conductive layers (72); Forming a channel layer (92) on the plurality of ferroelectric sections (90) and the sidewalls of the plurality of dielectric layers (52); and Forming a conductive bump (106) along sidewalls of the channel layer (92). [11] The method of claim 10, wherein selectively forming a plurality of ferroelectric sections (90) comprises: performing a surface treatment on sidewall surfaces of the plurality of dielectric layers (52); and Applying the plurality of ferroelectric sections (90) to the side walls of the plurality of conductive layers (72). [12] The method of claim 11, wherein performing the surface treatment comprises selectively forming a plurality of inhibitor portions (88) on the sidewall surfaces of the plurality of dielectric layers (52). [13] The method of claim 12, wherein the plurality of inhibitor portions (88) comprise a plurality of self-assembling monolayers. [14] The method of claim 13, wherein the plurality of self-assembling monolayers contains an alkanethiol, an alkanephosphonic acid, or a combination thereof. [15] The method of claim 13 or 14, wherein the plurality of self-assembling monolayers contains 1-octadecanethiol, ODT, or octadecylphosphonic acid, ODPA. [16] The method of any one of claims 13 to 15, further comprising an annealing process for removing the plurality of self-assembled monolayers after depositing the plurality of ferroelectric sections (90).

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