Storage array source / drain electrode structures and methods

Abstract

Memory cell (202) comprising: a thin-film transistor (204) over a semiconductor substrate (50), the thin-film transistor (204) comprising: a memory film (90) contacting a word line (72); and an oxide semiconductor layer, OS layer (92), contacting a source line (108) and a bit line (106), wherein the memory film (90) is arranged between the OS layer (92) and the word line (72), wherein the source line (108) and the bit line (106) each comprise a first conductive material (150) contacting the OS layer (92), and wherein the first conductive material (150) has a work function that is less than 4.6 eV; and a dielectric (98) separating the source line (108) and the bit line (106) from each other, wherein the OS layer (92) comprises: a first polycrystalline region (92') at an interface (152) between the OS layer (92) and the source line (108); and a second polycrystalline region (92') at an interface (152) between the OS layer (92) and the bit line (106), wherein the first polycrystalline region (92') comprises a metal oxide, wherein a metal element of the first polycrystalline region (92') is the same as a metal element of the first conductive material (150).

Description

BACKGROUND

[0001] Semiconductor memory is used in integrated circuits for electronic applications, including, for example, radios, televisions, cell phones, and personal computing devices. Semiconductor memory includes two major categories: volatile memory; the other is non-volatile memory. Volatile memory includes random-access memory (RAM), which can be further divided into two subcategories: static random-access memory (SRAM) and dynamic random-access memory (DRAM). SRAM and DRAM are both volatile because they lose the information they store when power is removed.

[0002] On the other hand, data can be stored on non-volatile memory. One type of non-volatile semiconductor memory is ferroelectric random access memory (FeRAM or FRAM). Advantages of FeRAM include its fast read / write speed and small size.

[0003] Prior art relating to the subject matter of the invention can be found, for example, in US 2011 / 0 215 317 A1, US 2010 / 0 133 601 A1, WO 2018 / 136 734 A1, US 2011 / 0 180 796 A1, US 2020 / 0 185 411 A1, the document SZE, SM; NG, KK: Physics of Semiconductor Devices. Third Edition. Hoboken, New Jersey: WILEY-INTERSCIENCE, 2007. P. 137. - ISBN 978-0-471-14323-9, WO 2020 / 027 532 A1 and WO 2019 / 152 226 A1.

[0004] The invention is defined by the main claim and the subordinate claim. Further embodiments of the invention are recited in the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Aspects of this disclosure are best understood by reference to the following detailed description taken in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not drawn to scale. Indeed, the dimensions of various features may be arbitrarily exaggerated or reduced for clarity of illustration. Fig. 1A, Fig. 1B and Fig. 1C illustrate a perspective view, a circuit diagram, and a top view of a memory array according to some embodiments. Fig. 2, Fig. 3A, Fig. 3B, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10, Fig. 11, Fig. 12A, Fig. 12B, Fig. 13, Fig. 14, Fig. 15, Fig. 16, Fig. 17A, Fig. 17B, Fig. 18A, Fig. 18B, Fig. 19A, Fig. 19B, Fig. 20, Fig. 21, Fig. 22, Fig. 23A, Fig. 23B, Fig. 23C, Fig. 24A, Fig. 24B, Fig. 25A, Fig. 25B, Fig. 26A, Fig. 26B, Fig. 27A, Fig. 27B, Fig. 28, Fig. 29A, Fig. 29B, Fig. 30A, Fig. 30B, Fig. 30C and Fig. 30D illustrate various views for fabricating a memory array according to some embodiments. Fig. Figure 27C illustrates characteristics of a device according to some embodiments. Fig. 31A, Fig. 31B, Fig. 31C illustrate various views of a memory array according to some embodiments. Fig. 32A, Fig. 32B, Fig. 32C, Fig. 33A, Fig. 33B, Fig. 33C, Fig. 34A, Fig. 34B, Fig. 34C, Fig. 35A, Fig. 35B and Fig. 35C illustrate a memory array according to some embodiments. DETAILED DESCRIPTION

[0006] The following disclosure provides many different embodiments or examples of implementing various features of the invention. Specific examples of components and arrangements are described below to simplify this disclosure. For example, in the following description, forming a first element or a second element may include embodiments in which the first and second elements are formed in direct contact, and may also include embodiments in which additional elements may be formed between the first and second elements such that the first and second elements need not be in direct contact. Furthermore, this disclosure may repeat reference numbers and / or letters of the various examples. This repetition is for simplicity and clarity and does not, in itself, dictate a relationship between the various embodiments and / or configurations explained.

[0007] Furthermore, spatially relative terms such as "beneath," "underneath," "lower," "above," "upper," and the like may be used herein for convenience of description to describe the relationship of one element or feature to one or more other elements or features as illustrated in the figures. The spatially relative terms are intended to encompass various orientations of the device in use or operation, in addition to the orientation shown in the figures. The device may be oriented differently (rotated 90 degrees or in another orientation), and the spatially relative terms used herein may also be interpreted accordingly.

[0008] Various embodiments provide a 3D memory array with a plurality of vertically stacked memory cells. Each memory cell includes a thin-film transistor (TFT) having a word line region serving as a gate electrode, a bit line region serving as a first source / drain electrode, and a source line region serving as a second source / drain electrode. Each TFT further includes an insulating memory film (e.g., as a gate dielectric) and an oxide semiconductor channel (OS) region.

[0009] Fig. 1A, Fig. 1B and Fig. 1C illustrate examples of a memory array according to some embodiments. Fig. 1A illustrates an example of a portion of the memory array 200 in a three-dimensional view; Fig. 1B illustrates a circuit diagram of the memory array 200; and Fig. 1C illustrates a top view of the memory array 200 according to some embodiments. The memory array 200 includes a plurality of memory cells 202 that may be arranged in a grid of rows and columns. The memory cells 202 may be further stacked vertically to provide a three-dimensional memory array, thereby increasing device density. The memory array 200 may be disposed in the back-end-of-line (BEOL) of a semiconductor die. For example, the memory array may be disposed in the interconnect layers of the semiconductor die, such as above one or more active devices (e.g., transistors) formed on a semiconductor substrate. In some embodiments, the memory array may be disposed in a top metal layer of the interconnect layers, such as above all other interconnect layers in the semiconductor die.In other embodiments, the memory array may be arranged in an intermediate metal layer of the interconnect layers, and the semiconductor die may, for example, comprise further interconnect layers above and below the memory array.

[0010] In some embodiments, the memory array 200 is a flash memory array, such as a NOR flash memory array or the like. Each memory cell 202 may include a thin-film transistor (TFT) 204 with an insulating memory film 90 as a gate dielectric. In some embodiments, a gate of each TFT 204 is electrically coupled to a respective word line, a first source / drain region of each TFT 204 is electrically coupled to a respective bit line, and a second source / drain region of each TFT 204 is electrically coupled to a respective source line that electrically couples the second source / drain region to ground. The memory cells 202 in a same horizontal row of the memory array 200 may share a common word line, while the memory cells 202 in a same vertical column of the memory array 200 may share a common source line and a common bit line.

[0011] The memory array 200 includes a plurality of vertically stacked conductive lines 72 (e.g., word lines) with dielectric layers 52 disposed between adjacent ones of the conductive lines 72. The conductive lines 72 extend in a direction parallel to a significant surface of an underlying substrate (in Fig. 1A and Fig. 1B). The conductive lines 72 may have a staircase configuration such that lower conductive lines 72 are longer than upper conductive lines 72 and extend laterally beyond their endpoints. For example, in Fig. 1A illustrates multiple stacked layers of conductive lines 72, with the topmost conductive lines 72 being the shortest and the bottommost conductive lines 72 being the longest. Respective lengths of the conductive lines 72 may increase in a direction toward the underlying substrate. In this manner, a portion of each of the conductive lines 72 may be accessible from above the memory array 200, and conductive contacts may be made to an exposed portion of each of the conductive lines 72.

[0012] The memory array 200 further includes a plurality of conductive lines 106 (e.g., bit lines) and conductive lines 108 (e.g., source lines). The conductive lines 106 and 108 may each extend in a direction perpendicular to the conductive lines 72. A dielectric 98 is disposed between and insulates adjacent conductive lines 106 and the conductive lines 108.

[0013] Pairs of conductive lines 106 and 108, along with an intersecting conductive line 72, define boundaries of each memory cell 202, and a dielectric 102 is disposed between and insulates adjacent pairs of conductive lines 106 and 108. In some embodiments, conductive lines 108 are electrically coupled to ground. Although Fig. 1A illustrates a particular placement of the conductive lines 106 with respect to the conductive lines 108, it should be noted that the placement of the conductive lines 106 and 108 may be reversed in other embodiments.

[0014] In some embodiments, the conductive lines 106 and 108 may be formed from a material that reduces contact resistance in the memory cells 202. For example, in some embodiments, the conductive lines 106 and 108 may comprise a material with a low work function (e.g., less than 4.6). As a portion of forming the conductive lines 106 and 108, an annealing process may be performed to form a polycrystalline, metal-containing region in the channel region at a boundary between the OS layer 92 and the conductive lines 106 and 108. Therefore, the polycrystalline region contacting the conductive lines 106 and 108 may be a low-resistivity region, regardless of the phase (e.g., crystalline or amorphous) of the remaining portions of the OS layer 92, thereby reducing contact resistance in the TFTs 204.In some embodiments, conductive lines 106 and 108 may comprise a low-resistivity copper-based alloy with a reduced tendency to oxidize (e.g., less susceptible to oxidation than pure copper). In embodiments where conductive lines 106 and 108 comprise a low-resistivity copper-based alloy, current driving in TFTs 204 may be further improved.

[0015] In some embodiments, at least portions of the conductive lines 106 and 108 in contact with the OS layer 92 may be a low work function material capable of inducing surface metallization of the OS layer 92 and reducing contact resistance at interfaces between the OS layer 92 and the conductive lines 106 / 108. In some embodiments, the conductive lines 106 and 108 may comprise an alloy at an interface with the OS layer 92, and an alloy may have low resistivity with a reduced tendency to oxidize (e.g., less susceptible to oxidation than pure copper). Various embodiments may achieve advantages.For example, as a portion of forming the conductive lines 106 / 108, an annealing process may be performed to form a polycrystalline metal oxide region in the OS layer 92 at an interface between the OS layer 92 and the conductive lines 106 and 108. The polycrystalline regions may be formed by the interaction between the low work function material and the OS layer 92, which is triggered by the annealing process. Therefore, the polycrystalline region contacting the conductive lines 106 / 108 may be a low-resistivity region, regardless of the phase (e.g., crystalline or amorphous) of the remaining portions of the OS layer 92, thereby reducing contact resistance. In embodiments where the conductive lines 106 and 108 comprise a low-resistivity copper-based alloy, current drive may be further improved.

[0016] As explained above, the memory array 200 may also include an oxide semiconductor (OS) layer 92. The OS layer 92 may provide channel regions for the TFTs 204 of the memory cells 202. For example, if a suitable voltage (e.g., higher than a respective threshold voltage (V th ) of a corresponding TFT 204) through a corresponding conductive line 72, a region of the OS layer 92 that intersects the conductive line 72 may allow current to flow from the conductive lines 106 to the conductive lines 108 (e.g., in the direction indicated by arrow 206). The OS layer 92 may have a relatively low hydrogen concentration, such as in a range of approximately 10 20 up to approx. 10 22Atoms per cubic centimeter as measured by time-of-flight secondary ion mass spectrometry (ToF-SIMS) analysis. Therefore, the stability of TFTs 204 can be improved compared to TFTs with OS layers, which have a higher concentration of hydrogen.

[0017] A memory film 90 is disposed between the conductive lines 72 and the OS layer 92, and the memory film 90 may provide gate dielectrics for the TFTs 204. In some embodiments, the memory film 90 comprises a ferroelectric material, such as hafnium oxide, hafnium zirconium oxide, silicon-doped hafnium oxide, or the like. Accordingly, the memory array 200 may also be referred to as a ferroelectric random access memory (FERAM) array. Alternatively, the memory film 90 may have a multilayer structure including a layer of SiN x between two SiO xlayers (e.g. an ONO structure), another ferroelectric material, another type of storage layer (e.g. capable of storing a bit) or the like.

[0018] In embodiments where the memory film 90 comprises a ferroelectric material, the memory film 90 can be polarized in one of two different directions, and the polarization direction can be changed by applying a suitable voltage difference across the memory film 90 and generating a suitable electric field. The polarization can be relatively localized (e.g., generally included in each boundary of the memory cells 202), and a continuous region of the memory film 90 can extend across multiple memory cells 202. Depending on the polarization direction of a particular region of the memory film 90, a threshold voltage of a corresponding TFT 204 varies, and a digital value (e.g., 0 or 1) can be stored.For example, if a region of the storage film 90 has a first electrical polarization direction, the corresponding TFT 204 may have a relatively low threshold voltage, and if the region of the storage film 90 has a second electrical polarization direction, the corresponding TFT 204 may have a relatively high threshold voltage. The difference between the two threshold voltages may be referred to as the threshold voltage shift. A larger threshold voltage shift makes it easier (e.g., less error-prone) to read the digital value stored in the corresponding memory cell 202.

[0019] To perform a write operation of a memory cell 202 in such embodiments, a write voltage is applied across a portion of the memory film 90 corresponding to the memory cell 202. The write voltage can be applied, for example, by applying appropriate voltages to a corresponding conductive line 72 (e.g., the word line) and the corresponding one of the conductive lines 106 / 108 (e.g., the bit line / source line). By applying the write voltage across the portion of the memory film 90, a polarization direction of the region of the memory film 90 can be changed. This also allows the corresponding threshold voltage of the corresponding TFT 204 to be switched from a low threshold voltage to a high threshold voltage or vice versa, and a digital value can be stored in the memory cell 202.Since the conductive lines 72 intersect the conductive lines 106 and 108, individual memory cells 202 can be selected for the write operation.

[0020] To perform a read operation on memory cell 202, a read voltage is applied to the corresponding conductive line 72 (e.g., the word line / gate electrodes of TFT 204), and a current is applied to a corresponding conductive line 106 (e.g., the bit line). The read voltage may be between the low and high threshold voltages of TFT 204. Depending on the polarization direction of the corresponding region of FE material 90, TFT 204 of memory cell 202 may or may not be turned on. Therefore, conductive line 106 may or may not be discharged through conductive line 108 (e.g., a source line coupled to ground), and the digital value stored in memory cell 202 can be determined. Since the conductive lines 72 intersect the conductive lines 106 and 108, individual memory cells 202 can be selected for the read operation.

[0021] Fig. 1A further illustrates reference cross-sections of the memory array 200 used in later figures. Cross-section BB' extends along a longitudinal axis of the conductive lines 72 and in a direction, for example, parallel to the direction of current flow of the TFTs 204. Cross-section CC' is perpendicular to cross-section BB' and parallel to a longitudinal axis of the conductive lines 72. Cross-section CC' extends through the conductive lines 106. Cross-section DD' is parallel to cross-section CC' and extends through the dielectric 102. Successive figures refer to these reference cross-sections for clarity.

[0022] In Fig. 2, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, an insulator substrate (SOI substrate), or the like, which may be doped (e.g., with a p- or n-type dopant) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Generally, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulating layer is provided on a substrate, typically silicon or a glass substrate. Other substrates, such as a multilayer or gradient substrate, may also be used.In some embodiments, the semiconductor material of substrate 50 may comprise silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or combinations thereof.

[0023] Fig. 2 further illustrates circuits that may be formed over substrate 50. The circuits include active devices (e.g., transistors) at a top surface of substrate 50. The transistors may include gate dielectric layers 202 over top surfaces of substrate 50 and gate electrodes 204 over gate dielectric layers 202. Source / drain regions 206 are disposed in substrate 50 on opposite sides of gate dielectric layers 202 and gate electrodes 204. Gate spacers 208 are formed from gate electrodes 204 by appropriate lateral spacing along sidewalls of gate dielectric layers 202 and separated from source / drain regions 206. In some embodiments, the transistors may be planar field-effect transistors (FETs), fin field-effect transistors (finFETs), nanofield-effect transistors (nanoFETs), or the like.

[0024] A first ILD 210 surrounds and insulates the source / drain regions 206, the gate dielectric layers 202, and the gate electrodes 204, and a second ILD 212 is located over the first ILD 210. Source / drain contacts 214 extend through the second ILD 212 and the first ILD 210 and are electrically coupled to the source / drain regions 206, and gate contacts 216 extend through the second ILD 212 and are electrically coupled to the gate electrodes 204. An interconnect structure 220 comprising one or more stacked dielectric layers 224 and conductive features 222 formed in one or more dielectric layers 224 is located above the second ILD 212, the source / drain contacts 214 and the gate contacts 216. Although Fig. 2 illustrates two stacked dielectric layers 224, it should be noted that the interconnect structure 200 may include any number of dielectric layers 224 in which conductive features 222 are disposed. The interconnect structure 220 may be electrically connected to the gate contacts 216 and the source / drain contacts 214 to form functional circuits. In some embodiments, the functional circuits formed by the interconnect structure 220 may include logic circuits, memory circuits, sense amplifiers, controllers, input / output circuits, image sensor circuits, the like, or combinations thereof. Although Fig. 2 discusses transistors formed over the substrate 50, other active devices (e.g., diodes or the like) and / or passive devices (e.g., capacitors, resistors, or the like) may be formed as a portion of the functional circuitry.

[0025] In Fig. 3A and Fig. 3B is a multilayer stack 58 over the structure of Fig. 2. The substrate 50, the transistors, the ILDs, and the interconnect structure 120 may be omitted from subsequent drawings for the sake of simplicity and clarity. Although the multilayer stack 58 is illustrated as contacting the dielectric layers 224 of the interconnect structure 220, any number of intermediate layers may be disposed between the substrate 50 and the multilayer stack 58. For example, the multilayer stack 58 may be located over the interconnect structure 220, and one or more additional interconnect layers including conductive features in insulation layers (e.g., low-k dielectric layers) may be disposed between the substrate 50 and the multilayer stack 58.In some embodiments, the conductive features may be patterned to provide power, ground, and / or signal lines to the active devices on the substrate 50 and / or the memory array 200 (see . Fig. 1A and Fig. 1B).

[0026] The multilayer stack 58 includes alternating layers of conductive lines 72A-D (collectively referred to as conductive layers 54) and dielectric layers 52A-C (collectively referred to as dielectric layers 52). The conductive layers 54 may be patterned in subsequent steps to define the conductive lines 72 (e.g., word lines). The conductive layers 54 may comprise a conductive material such as copper, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, ruthenium, aluminum, combinations thereof, or the like, and the dielectric layers 52 may comprise an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, combinations thereof, or the like.The conductive layers 54 and dielectric layers 52 may each be formed using, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), plasma-enhanced CVD (PECVD), or the like. Although . Fig. 3A and Fig. 3B illustrate a particular number of conductive layers 54 and dielectric layers 52, other embodiments may include a different number of conductive layers 54 and dielectric layers 52.

[0027] Fig. 4 to 12B are views of intermediate stages in the fabrication of a staircase structure of the memory array 200 according to some embodiments. Fig. 4 to 11 and 12B are illustrated along reference cross section BB', which is Fig. 1 is illustrated. Fig. 12A is illustrated in a three-dimensional view.

[0028] In Fig. 4, a photoresist 56 is formed over the multilayer stack 58. As discussed above, the multilayer stack 58 may include alternating layers of the conductive layers 54 (labeled 54A, 54B, 54C, and 54D) and the dielectric layers 52 (labeled 52A, 52B, and 52C). The photoresist 56 may be formed using a spin-on technique.

[0029] In Fig. 5, the photoresist 56 is patterned to expose the multilayer stack 58 in regions 60 while masking remaining portions of the multilayer stack 58. For example, the topmost layer of the multilayer stack 58 (e.g., the conductive layer 54D) may be exposed in the regions 60. The photoresist 56 may be patterned using acceptable photolithography techniques.

[0030] In Fig. 6, the exposed portions of the multilayer stack 58 in the regions 60 are etched using the photoresist 56 as a mask. The etching may be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), the like, or a combination thereof. The etching may be anisotropic. The etching may remove portions of the conductive layer 54D and dielectric layer 52C in the regions 60 and define openings 61. Because the conductive layer 54D and dielectric layer 52C have different material compositions, etchants used to remove exposed portions of the layers may be different. In some embodiments, the dielectric layer 52C acts as an etch stop layer during etching of the conductive layer 54D, and the conductive layer 54C acts as an etch stop layer during etching of the dielectric layer 52C.Therefore, portions of conductive layer 54E and conductive layer 54D can be selectively removed without removing remaining layers of multilayer stack 58, and openings 61 can be extended to a desired depth. Alternatively, a timed etch process can be used to stop etching openings 61 after openings 61 reach a desired depth. In the resulting structure, conductive layer 54C is exposed in regions 60.

[0031] In Fig. 7, the photoresist 56 is trimmed to expose further portions of the multilayer stack 58. The photoresist may be trimmed using appropriate photolithography techniques. By trimming, a width of the photoresist 56 is reduced, and portions of the multilayer stack 58 in regions 60 and 62 may be exposed. For example, a top surface of the conductive layer 54C may be exposed in regions 60, and a top surface of the conductive layer 54D may be exposed in regions 62.

[0032] In Fig. 8, portions of the conductive layer 54D, the dielectric layer 52C, the conductive layer 54C, and the dielectric layer 52B in the regions 60 and 62 are removed by acceptable etching processes using the photoresist 56 as a mask. The etching may be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), the like, or a combination thereof. The etching may be anisotropic. The etching may extend the openings 61 further into the multilayer stack 58. Because the conductive layers 54D / 54C and the dielectric layers 52C / 52B have different material compositions, etchants used to remove exposed portions of the layers may be different.In some embodiments, the dielectric layer 52C acts as an etch stop layer during the etching of the conductive layer 54D; the conductive layer 52C acts as an etch stop layer during the etching of the conductive layer 54D; the dielectric layer 52B acts as an etch stop layer during the etching of the conductive layer 54C; and the conductive layer 54B acts as an etch stop layer during the etching of the dielectric layer 54B. Therefore, portions of the conductive layers 54D / 54C and the dielectric layer 52C / 52B can be selectively removed without removing remaining layers of the multilayer stack 58, and the openings 61 can be extended to a desired depth. Furthermore, during the etching process, unetched portions of the conductive layers 54 and dielectric layers 52 act as a mask for underlying layers and due to a previous pattern of the conductive layer 54D and dielectric layer 52C (see . Fig. 7) can be transferred to the underlying conductive layer 54C and dielectric layer 52B. In the resulting structure, the conductive layer 54B is exposed in regions 60 and the conductive layer 54C is exposed in regions 62.

[0033] In Fig. 9, the photoresist 56 is trimmed to expose further portions of the multilayer stack 58. The photoresist may be trimmed using appropriate photolithography techniques. By trimming, a width of the photoresist 56 is reduced, and portions of the multilayer stack 58 in regions 60, 62, and 64 may be exposed. For example, a top surface of the conductive layer 54B may be exposed in regions 60; a top surface of the conductive layer 54C may be exposed in regions 62; and a top surface of the conductive layer 54D may be exposed in regions 64.

[0034] In Fig. 10, portions of the conductive layers 54D, 54C, and 54B in the regions 60, 62, and 64 are removed by acceptable etching processes using the photoresist 56 as a mask. The etching may be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), the like, or a combination thereof. The etching may be anisotropic. The etching may extend the openings 61 further into the multilayer stack 58. In some embodiments, the dielectric layer 52C acts as an etch stop layer during the etching of the conductive layer 54D; the dielectric layer 52B acts as an etch stop layer during the etching of the conductive layer 54C; and the dielectric layer 54A acts as an etch stop layer during the etching of the conductive layer 54B.Therefore, portions of the conductive layers 54D, 54C, and 54B can be selectively removed without removing remaining layers of the multilayer stack 58, and the openings 61 can be extended to a desired depth. Furthermore, during the etching process, each of the dielectric layers 52 acts as a mask for underlying layers and due to a prior pattern of the dielectric layers 52C / 52B (see FIG. Fig. 9) can be transferred to the underlying conductive layers 54C / 54B. In the resulting structure, the dielectric layer 52A is exposed in regions 60; the dielectric layer 52B is exposed in regions 62; and the dielectric layer 52C is exposed in regions 64.

[0035] In Fig. 11, the photoresist 56 may be removed, such as by an acceptable ash or wet stripping process. Thus, a stair structure 68 is formed. The stair structure includes a stack of alternating conductive layers 54 and dielectric layers 52. Lower conductive layers 54 are wider and extend laterally past upper conductive layers 54, with a width of each of the conductive layers 54 increasing in a direction toward the substrate 50. For example, the conductive layer 54A may be longer than the conductive layer 54B; the conductive layer 54B may be longer than the conductive layer 54C; and the conductive layer 54C may be longer than the conductive layer 54D. Therefore, in subsequent processing steps, conductive contacts may be made from above the stair structure 68 to each of the conductive layers 54.

[0036] In Fig. 12, an intermetal dielectric (IMD) 70 is deposited over the multilayer stack 58. The IMD 70 may be formed from a dielectric and may be formed by any suitable process, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. Dielectrics may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped silicate glass (BPSG), undoped silicate glass (USG), or the like. Other insulating materials formed by an acceptable process may be used. The IMD 70 extends along sidewalls of the conductive layers 54 as well as sidewalls of the dielectric layers 52. Further, the IMD 70 may contact top surfaces of each of the dielectric layers 52.

[0037] As further stated in Fig. As illustrated in Figure 12, a stripping process is then applied to the IMD 70 to remove excess dielectric over the multilayer stack 58. In some embodiments, a planarization process, such as chemical mechanical polishing (CMP), an etch-back process, combinations thereof, or the like, may be used. The planarization process exposes the multilayer stack 58 so that the top surfaces of the multilayer stack 58 and IMD 70 are flat after completion of the planarization process.

[0038] Fig. 13 to 17B are views of intermediate stages in the fabrication of the memory array 200 according to some embodiments. In Fig. 13 to 17B, the multilayer stack 58 is formed, and trenches are formed in the multilayer stack 58, defining the conductive lines 72. The conductive lines 72 may correspond to word lines in the memory array 200, and the conductive lines 72 may further provide gate electrodes for the resulting TFTs of the memory array 200. Fig. 17A is illustrated in a three-dimensional view. Fig. 13 to 16 and 17B are illustrated along reference cross section CC', which is Fig. 1A is illustrated.

[0039] In Fig. 13, a hard mask 80 and a photoresist 82 are deposited over the multilayer stack 58. The hard mask layer 80 may comprise, for example, silicon nitride, silicon oxynitride, or the like, which may be deposited by CVD, PVD, ALD, PECVD, or the like. The photoresist 82 may be formed, for example, using a spin-on technique.

[0040] In Fig. 14, the photoresist 82 is patterned to form trenches 86. The photoresists can be patterned using appropriate photolithography techniques. For example, the photoresist 82 can be exposed to light for patterning. After the exposure process, the photoresist 82 can be developed to form exposed or unexposed portions of the photoresist, depending on whether a negative or positive resist is used, thereby defining a patterning of the trenches 86.

[0041] In Fig. 15, a pattern of photoresist 82 is transferred to hard mask 84 using an acceptable etching process, such as wet or dry etching, reactive ion etching (RIE), neutral beam etching (NBE), the like, or a combination thereof. The etching may be anisotropic. Thus, trenches 86 are formed that extend through hard mask 84. Photoresist 82 may be removed, for example, by an ash process.

[0042] In Fig. 16, a pattern of the hard mask 84 is transferred to the multilayer stack 58 using one or more acceptable etching processes, such as wet or dry etching, reactive ion etching (RIE), neutral beam etching (NBE), the like, or a combination thereof. The etching processes may be anisotropic. For example, trenches 86 extend through the multilayer stack 58, and the conductive lines 72 (e.g., word lines) are formed from the conductive layers 54. By etching trenches 86 through the conductive layers 54, adjacent conductive lines 72 may be separated from each other. Subsequently, Fig. 17A and Fig. 17B, ​​the hard mask 84 may then be removed by an acceptable process, such as a wet etching process, a dry etching process, a planarization process, combinations thereof, or the like. Due to the stair-step shape of the multilayer stack 58 (see, e.g., Fig. 12), the conductive lines 72 may have different lengths that increase in a direction toward the substrate 50. For example, the conductive lines 72A may be longer than the conductive lines 72B; the conductive lines 72B may be longer than the conductive lines 72C; and the conductive lines 72C may be longer than the conductive lines 72D.

[0043] Fig. 18A to 23C illustrate the formation and patterning of channel regions for the TFTs 204 (see Fig. 1A) in trenches 86. Fig. 18A, Fig. 18A and Fig. 23A are illustrated in a three-dimensional view. In Fig. 18B, Fig. 19B, Fig. 20, Fig. 21, Fig. 22A, Fig. 22B and Fig. 23B are cross-sectional views along line CC' of Fig. 1A provided. Fig. Figure 23C illustrates a corresponding top view of the TFT structure.

[0044] In Fig. 18A and Fig. 18B, a memory film 90 is conformally deposited in the trenches 86. The memory film 90 may comprise a material capable of storing a bit, such as a material capable of switching between two different polarization directions by applying a suitable voltage difference across the memory film 90. For example, the polarization of the memory film 90 may change due to an electric field resulting from the application of the voltage difference.

[0045] For example, the memory film 90 may be a high-k dielectric, such as a hafnium-based (Hf-based) dielectric or the like. In some embodiments, the memory film 90 comprises a ferroelectric material, such as hafnium oxide, hafnium zirconium oxide, silicon-doped hafnium oxide, or the like. In other embodiments, the memory 90 may have a multilayer structure including a layer of SiN x comprises, between two SiO x-layers (e.g., an ONO structure). In yet other embodiments, the memory film 90 may comprise another ferroelectric material or another type of memory material. The memory film 90 may be deposited by CVD, PVD, ALD, PECVD, or the like to extend along sidewalls and a bottom surface of the trenches 86. After the memory film 90 is deposited, an annealing step (e.g., at a temperature range of about 300°C to about 600°C) may be performed to achieve a desired crystalline phase, improve film quality, and reduce film-related defects / impurities for the memory film 90. Further, in some embodiments, the annealing step may be below 400°C to meet a BEOL heat budget and reduce defects that may result in other features from high-temperature annealing processes.

[0046] In Fig. 19A and Fig. 19B, the OS layer 92 is conformally deposited in the trenches 86 over the storage film 90. The OS layer 92 comprises a material suitable for providing a channel region for a TFT (e.g., TFTs 204, see Fig. 1A). In some embodiments, the OS layer 92 comprises an indium-containing material, such as In x Ga y Zn zMO, where M can be Ti, Al, Ag, Si, Sn, or the like. X, Y, and Z can each be a value between 0 and 1. In other embodiments, a different semiconductor material can be used for the OS layer 92. The OS layer 92 can be deposited by CVD, PVD, ALD, PECVD, or the like. The OS layer 92 can extend along sidewalls and a bottom surface of the trenches 86 above the FE layer 90. After the OS layer 92 is deposited, an annealing step (e.g., at a temperature range of about 300°C to about 450°C) can be performed in an oxygen-related ambient to activate the charge carriers of the OS layer 92.

[0047] In Fig. 20, a dielectric 98A is deposited on sidewalls and a bottom surface of trenches 86 and over OS layer 92. Dielectric 98A may comprise, for example, silicon oxide, silicon nitride, silicon oxynitride, or the like, which may be deposited by CVD, PVD, ALD, PECVD, or the like.

[0048] In Fig. 21, lower portions of the dielectric 98A in the trenches 86 are removed, for example, using a combination of photolithography and etching. The etching may be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), the like, or a combination thereof. The etching may be anisotropic.

[0049] Below, as well as through Fig. 21, the dielectric 98A may be used as an etch mask to etch through a lower portion of the OS layer 92 in the trenches 86. The etch may be any acceptable etch process, such as reactive ion etching (RIE), neutral beam etching (NBE), the like, or a combination thereof. The etch may be anisotropic. Etching the OS layer 92 may expose portions of the memory film 90 at a lower surface of the trenches 86. Thus, portions of the OS layer 92 may be separated from each other at opposite sidewalls of the trenches 86, providing insulation between the memory cells 202 of the memory array 200 (see Fig. 1A) improved.

[0050] In Fig. 22A and Fig. 22B, another dielectric 98B may be deposited to fill remaining portions of the trenches 86. The dielectric 98B may comprise, for example, silicon oxide, silicon nitride, silicon oxynitride, or the like, which may be deposited by CVD, PVD, ALD, PECVD, or the like. In some embodiments, the dielectric 98B may have the same material composition and be formed using the same process as the dielectric 98A. Alternatively, the dielectric 98B may have a different material composition and / or be formed by a different process than the dielectric 98A.

[0051] In Fig. 23A to 23C, a removal process is then applied to the dielectric 98, the OS layer 92, and the memory film 90 to remove excess material over the multilayer stack 58. In some embodiments, a planarization process, such as chemical mechanical polishing (CMP), an etch-back process, combinations thereof, or the like, may be used. The planarization process exposes the multilayer stack 58 so that the top surface of the multilayer stack 58 is flat after completion of the planarization process. Fig. Figure 23C illustrates a corresponding top view of the structure shown in Fig. 23A is illustrated.

[0052] Fig. 24A to 29B illustrate intermediate steps of fabricating the conductive lines 106 and 108 (e.g., source lines and bit lines) in the memory array 200. The conductive lines 106 and 108 may further provide source / drain electrodes for TFTs 204 in the memory array (see Fig. 1A to 1C). Conductive lines 106 and 108 may comprise a material with a relatively low work function capable of inducing area metallization of OS layer 92 to reduce contact resistance in TFTs 204. Conductive lines 106 and 108 may extend along a direction perpendicular to conductive lines 72 so that individual cells of memory array 200 can be selected for read and write operations. Fig. 24A, Fig. 25A, Fig. 26A and Fig. Figure 27A illustrates a cross-sectional view along cross section CC' of Fig. 1A; Fig. 24B, Fig. 25B, Fig. 26B, Fig. 27B, Fig. 28 and Fig. 29B illustrate a corresponding plan view; and Fig. 29A illustrate a cross-sectional view along cross section DD' of the Fig. 1A.

[0053] In Fig. 24A and Fig. 24B, trenches 100 are patterned through the dielectric 98 (including dielectric 98A and dielectric 98B). Patterning the trenches 100 can be performed, for example, by a combination of photolithography and etching. The trenches 100 can be arranged between opposite sidewalls of the OS layer 92 and expose a top surface of the storage film 90 through the OS layer 92.

[0054] In Fig. 25A and Fig. 25B, a conductive material 150 is formed in the trenches 100 on sidewalls of the OS layer 92. The conductive material 150 may have a relatively low work function, such as a work function of less than about 4.6. For example, the conductive material 150 may comprise titanium, iridium, ruthenium, a conductive oxide (e.g., a ceramic material such as LaNiO, InSnO, InZnO, CdSnO, aluminum-doped ZnO, F-SnO, or the like), or the like. It has been observed that when the conductive material 150 has a low work function (e.g., in the above range), the conductive material 150 is capable of inducing surface metallization of the OS layer 92 to reduce contact resistance at the interfaces between the OS layer 92 and the conductive material 150. It has further been observed that by providing a conductive material 150 with a low work function (e.g.,less than 4.6), a barrier height between the conductive material 150 and the OS layer 92 can be reduced and the electron tunneling speed can be increased. The conductive material 150 can be deposited by CVD, PVD, ALD, PECVD, or the like.

[0055] After the conductive material 150 is deposited, an annealing process may be performed to induce surface metallization of the OS layer 92 at the interfaces 152 between the OS layer 92 and the conductive material 150. In some embodiments, the annealing process may take place at a temperature of at least approximately 300°C, which is sufficient to induce surface metallization of the OS layer 92. The annealing process may form a polycrystalline region 92' at the interfaces 152 between the OS layer 92 and the conductive material 150. For example, the polycrystalline region 92' may be formed by a reaction between the InO acomponent of the OS layer 92 and the metal component of the conductive material 150 (hereinafter referred to as M'). The reaction can be expressed by equations (1) and (2), where a and b are each integers between 0 and 1, and Vo represents film-generated defects (e.g., oxygen vacancies and / or defects in the film). InO a + M' → M'O b + InO a-b + Vo (1) Vo →Vo 2+ + 2e - (2)

[0056] As stated above, the polycrystalline region may comprise a metal oxide, and a metal element of the metal oxide may be the same as a metal element of the conductive material 150. A thickness of the polycrystalline region 92' (e.g., a depth in the OS layer 92 into which the polycrystalline region 92' extends) may, in some embodiments, be in a range of about 1 nm to about 10 nm or in a range of about 1 nm to about 5 nm. It has been observed that by having a relatively thin polycrystalline region (e.g., in the above ranges), electrons can more easily tunnel across the boundary between the conductive material 150 and the OS layer 92. In other embodiments, the polycrystalline region may have a different thickness. A remainder of the OS layer 92 (e.g., outside the polycrystalline region 92') may remain at the same crystalline level as before the annealing process. For example, the rest of OS layer 92 may remain amorphous.

[0057] As also in Fig. 25A and Fig. 25B, a removal process is then applied to the conductive material 150 to remove excess material over the multilayer stack 58. In some embodiments, a planarization process such as a CMP, an etch-back process, combinations thereof, or the like may be used. The planarization process exposes the multilayer stack 58 such that the top surfaces of the multilayer stack 58, the memory film 90, the OS layer 92, and the conductive material 150 are planar after completion of the planarization process.

[0058] Fig. 26A to 27B illustrate manufacturing steps in which central portions of the conductive material are replaced by another conductive material. Therefore, the conductive lines 106 and 108 (see Fig. 28) comprise two different materials (e.g., the conductive material 150 and the conductive material 156, as described below). The steps described in Fig. 26A to 27B are optional and may be omitted in some embodiments. In such embodiments, the conductive lines 106 and 108 may comprise only the conductive material 150, as shown by Fig. 31A to 31C illustrated.

[0059] In Fig. 26A and Fig. 26B, trenches 154 are patterned through the conductive material 150. Patterning the trenches 154 may be performed, for example, through a combination of photolithography and etching. The trenches 154 may be disposed between opposing sidewalls of the conductive material 150, and remaining portions of the conductive material 150 may be disposed between the trenches 100 and the OS layer 92. The trenches 154 extend through the conductive material 150 and the OS layer 92 to expose the underlying memory film 90.

[0060] In Fig. 27A and Fig. 27B, a conductive material 156 is deposited to fill the trenches 154. The conductive material 156 may be disposed and contact opposing portions of the conductive material 150. In some embodiments, the conductive material 156 may have a relatively low work function, such as a work function of less than about 5 eV. For example, the conductive material 156 may include TiN, W, Ti, MoTi, CuMgAl, Ru, Al, Ta, TaN, CuMn, CuAlZn, combinations thereof, or the like. The conductive material 156 may be deposited by CVD, PVD, ALD, PECVD, or the like. It has been observed that by providing a conductive material 156 with a low work function (e.g., in the above range), a barrier height between the conductive material 156 and the conductive material 150 / the OS layer 92 can be reduced and the electron tunneling speed can be increased.After deposition, a planarization process such as CMP, an etch-back process, combinations thereof, or the like may be used. The planarization process exposes the multilayer stack 58, so that the top surfaces of the multilayer stack 58, the memory film 90, the OS layer 92, the conductive material 150, and the conductive material 156 are flat after completion of the planarization process.

[0061] By forming the conductive material 150 and the polycrystalline regions 92' in the OS layer 92 with low work functions (e.g., less than approximately 4.6), electrons can tunnel directly from the conductive material 156 through the conductive material 150 and across the channel regions of the OS layer 92. For example, due to the formation of the conductive material according to various embodiments, the OS layer 92 may include a low-resistivity region (e.g., the polycrystalline regions 92') regardless of the phase of the OS layer 92 (e.g., crystalline or amorphous). Therefore, the contact resistance may be reduced. This reduced resistance and improved electron tunneling is illustrated by the bandgap diagram 300 of Fig. 27C, which shows a conduction band (E C ), a valence band (E V ), a Femi-level (E F ) and a vacuum energy level (E VAC) of the conductive material 156, the conductive material 150, and the OS layer 92. The valence band and the conduction band are the bands closest to the Fermi level and determine the electrical conductivity of the material. Furthermore, the valence band is the highest range of electron energies in which electrons are normally present at absolute zero temperature, while the conduction band is the lowest range of empty electron states. Furthermore, the conductive material 150 and / or the conductive material 156 may be less susceptible to unwanted oxidation than, for example, pure copper. Thus, a reduction in device performance due to oxidation can be avoided.

[0062] In Fig. 28, trenches 158 are patterned through the conductive material 150, the conductive material 156, and the OS layer 92. The patterning of the trenches 158 may be performed, for example, by a combination of photolithography and etching. The trenches 158 may be disposed between opposing sidewalls of the storage film 90. Therefore, the conductive lines 106 and 108 are defined from remaining portions of the conductive material 150 and the conductive material 156. Each of the conductive lines 106 is separated from an adjacent conductive line 108 by the dielectric 98, and pairs of the conductive lines 106 / 108 are separated by the trenches 158. Discrete portions of the OS layer 92 extend continuously from a respective conductive line 106 to a respective conductive line 108.The conductive lines 106 may correspond to bit lines in the memory array, and the conductive lines 108 may correspond to source lines in the memory array 200. Furthermore, the conductive lines 106 / 108 may be source / drain electrodes for TFTs 204 (see . Fig. 29A and Fig. 29B) in the memory array 200.

[0063] In Fig. 29A and Fig. 29B, a dielectric 102 is deposited in the trenches 158 and fills them. Fig. Figure 29B illustrates a cross-sectional view of line DD' in Fig. 29A. The dielectric layer 102 may comprise, for example, silicon oxide, silicon nitride, silicon oxynitride, or the like, which may be deposited by CVD, PVD, ALD, PECVD, or the like. The dielectric layer 102 may extend along extended sidewalls and a bottom surface of the trenches 86 above the storage film 92. After deposition, a planarization process (e.g., a CMP, etch-back, or the like) may be performed to remove excess portions of the dielectric 102. In the resulting structure, top surfaces of the multilayer stack 58, the storage film 90, the OS layer 92, the dielectric 102, and the conductive lines 106 / 108 may be substantially planar (e.g., within process variations).

[0064] Thus, stacked TFTs 204 may be formed in the memory array 200. Each TFT 204 includes a gate electrode (e.g., a portion of a corresponding conductive line 72), a gate dielectric (e.g., a portion of a corresponding memory film 90), a channel region (e.g., a portion of a corresponding OS layer 92), and source and drain electrodes (e.g., portions of corresponding ones of the conductive lines 106 and 108). The dielectric 102 isolates adjacent TFTs 204 in a same column and on a same vertical plane. The TFTs 204 may be arranged in an array of vertically stacked rows and columns.

[0065] In Fig. 30A, Fig. 30B, Fig. 30C and Fig. 30D, the contacts 110 are made with the conductive lines 72, the conductive lines 106 and the conductive lines 108. Fig. 30A illustrates a perspective view of the memory array 200; Fig. 30B illustrates a top view of the memory array 200; Fig. Figure 30C illustrates a cross-sectional view of the device and the underlying substrate along line 30C'-30C' of Fig. 28A; and Fig. Figure 30D illustrates a cross-sectional view of the device along line BB' of Fig. 1A. In some embodiments, the stair-step shape of the conductive lines 72 may provide a surface on each of the conductive lines 72 for the conductive contacts 110 terminating thereon. Forming the contacts 110 may include patterning openings in the IMD 70 and the dielectric layers 52 to expose portions of the conductive layers 54, for example, using a combination of photolithography and etching. A liner (not shown), such as a diffusion barrier layer, an adhesive layer, or the like, and a conductive material are formed in the openings. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process, such as CMP, may be performed to remove excess material from a surface of the IMD 70.The remaining lining and the conductive material form the contacts 110 in the openings.

[0066] As also shown by the perspective view of Fig. 30A, conductive contacts 112 and 114 may also be made with the conductive lines 106 and the conductive lines 108, respectively. The conductive contacts 110, 112, and 114 may be electrically connected to the conductive lines 116A, 116B, and 116C, respectively, which connect the memory array to underlying / overlying circuitry (e.g., control circuitry) and / or signal, power, and ground lines in the semiconductor die. For example, conductive vias 118 may extend through the IMD 70 to electrically connect the conductive lines 116C to the underlying circuitry of the interconnect structure 220 and the active devices on the substrate 50, as shown in Fig. 30C. Other conductive vias may be formed through the IMD 70 to electrically connect the conductive lines 116A and 116B to the underlying circuitry of the interconnect structure 220. In alternative embodiments, routing and / or power lines to and from the memory array may be provided through an interconnect structure formed over the memory array 200, in addition to or instead of the interconnect structure 220. Accordingly, the memory array 200 may be terminated.

[0067] Fig. 31A, Fig. 31B and Fig. 31C illustrate a cross-sectional view of a memory array 220 according to alternative embodiments. Fig. Figure 31A illustrates a cross-sectional view along cross section CC' of the Fig. 1A and Fig. 31B; Fig. 31B illustrates a corresponding plan view and Fig. Figure 31C illustrates a cross-sectional view along cross section DD' of the Fig. 1A and Fig. 31B. The memory array 200 may be substantially the same as the memory array, in which like reference numerals indicate like elements formed by like processes. However, in the memory array 220, the conductive material 156 (see Fig. 29B) and the steps described in Fig. 26A to 27B are omitted. Therefore, the conductive lines 106 and 108 are made of a low work function conductive material 150. The conductive material 150 may be similar to that described above, with a low work function (e.g., less than 4.6), for reduced resistivity between the conductive lines 106 / 108 and the OS layer 92. Furthermore, a polycrystalline region 92' may be formed in the OS layer 92 at the interface with the conductive material 150, for example, by an annealing process.

[0068] Fig. 32A to 35C illustrate intermediate steps of forming conductive lines 106 and 108 in a memory array 250 according to some alternative embodiments. Memory array 250 may be the same as memory array 200, in which like reference numerals indicate like elements formed by like processes, unless otherwise noted. Fig. 32A to 35C, figures with end “A” illustrate a 3D view; figures with end “B” illustrate a plan view and figures with end “C” illustrate a corresponding cross-sectional view parallel to the line CC' of Fig. 1A.

[0069] In Fig. 32A, Fig. 32B and Fig. 32C, the trenches 100 are structured by the OS layer 92 and the dielectric 98 (including the dielectric 98A and the dielectric 98B). Fig. 32C illustrates a cross-sectional view of line CC' in Fig. 32B. The patterning of the trenches 100 may be performed, for example, by a combination of photolithography and etching. The trenches 100 may be arranged between opposite sidewalls of the memory film 90, and the trenches 100 may be physically separate adjacent stacks of memory cells in the memory array 200 (see Fig. 1A). Furthermore, the trenches 100 may have a stepped configuration in a plan view (see Fig. 32B). Alternatively, the trenches 100 may be aligned in a similar manner as illustrated above for memory array 200.

[0070] In Fig. 33A, Fig. 33B and Fig. 33C, a dielectric 102 is deposited in the trenches 100 and fills them. Fig. Figure 33C illustrates a cross-sectional view of line CC' in Fig. 33B. The dielectric layer 102 may comprise, for example, silicon oxide, silicon nitride, silicon oxynitride, or the like, which may be deposited by CVD, PVD, ALD, PECVD, or the like. The dielectric layer 102 may extend 92 along extended sidewalls and a bottom surface of the trenches 86 above the OS layer. After deposition, a planarization process (e.g., a CMP, etch-back, or the like) may be performed to remove excess portions of the dielectric 102. In the resulting structure, top surfaces of the multilayer stack 58, the memory film 90, the OS layer 92, and the dielectric 102 may be substantially planar (e.g., within process variations). In some embodiments, materials of the dielectrics 98 and 102 may be selected such that they can be selectively etched relative to each other.For example, in some embodiments, dielectric 98 is an oxide and dielectric 102 is a nitride. In some embodiments, dielectric 98 is a nitride and dielectric 102 is an oxide. Other materials are possible.

[0071] In Fig. 34A, Fig. 34B and Fig. 34C, trenches 104 for the conductive lines 106 and 108 are structured. Fig. Figure 34C illustrates a cross-sectional view of line CC' in Fig. 34B. The trenches 104 are patterned, for example, by patterning the dielectric 98 (including the dielectric 98A and the dielectric 98C) using a combination of photolithography and etching.

[0072] For example, a photoresist 118 may be deposited over the multilayer stack 58, the dielectric 98, the dielectric 102, the OS layer 92, and the memory film 90. The photoresist 118 may be formed, for example, using a spin-on technique. The photoresist 118 is defined to define openings 120. Each of the openings 120 may overlap a corresponding region of the dielectric 102, and each of the openings 120 may further partially expose two separate regions of the dielectric 98. For example, each opening 120 may expose one region of the dielectric 102; partially expose a first region of the dielectric 98; and partially expose a second region of the dielectric 98 that is separated from the first region of the dielectric 98 by the region of the dielectric 102.Thus, each of the openings 120 can define a pattern of a conductive line 106 and an adjacent conductive line 108 separated by the dielectric 102. The photoresists can be patterned using appropriate photolithography techniques. For example, the photoresist 82 can be exposed to light for patterning. After the exposure process, the photoresist 82 can be developed to expose exposed or unexposed portions of the photoresist, depending on whether a negative or positive resist is used, thereby defining a pattern of the mold openings 120.

[0073] Subsequently, portions of the dielectric 98 that were exposed through the openings 120 may be removed, for example, by etching. The etching may be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), the like, or a combination thereof. The etching may be anisotropic. The etching process may use an etchant that etches the dielectric 98 without significantly etching the dielectric 102. Therefore, while the openings 120 expose the dielectric 102, the dielectric 102 may not be significantly removed. A structure of the trenches 104 may correspond to the conductive lines 106 and 108 (see Fig. 35A, Fig. 35B and Fig. 35C). For example, a portion of dielectric 98 may remain between each pair of trenches 104, and dielectric 102 may be disposed between adjacent pairs of trenches 104. After trenches 104 are patterned, photoresist 118 may be removed, for example, by ashing.

[0074] In Fig. 35A, Fig. 35B and Fig. 35C, the trenches 104 are filled with a conductive material to form the conductive lines 106 and 108. Fig. Figure 35C illustrates a cross-sectional view of line CC' in Fig. 35B. The conductive lines 106 and 108 may each comprise a conductive material, such as a copper-based alloy or a copper-aluminum-based alloy with a subordinate metal having high oxidizability (e.g., Zn, Si, Mg, Ca, Ni, Co, Mo, Ti, W). For example, in some embodiments, the conductive lines 106 and 108 may comprise an alloy of Cu (or CuAl) and Zn, Si, Mg, Ca, Ni, Co, Mo, Ti, W, or the like. A percentage of the subordinate metal in the conductive lines 106 and 108 may range from about 0.1 at% to about 10 at%. It has been observed that by including the subordinate metal in the above amount, the conductive lines 106 and 108 can obtain a low resistivity (e.g., less than about 10 mΩ per cm) even after annealing at a temperature of about 300 °C to about 500 °C in a nitrogen (N2) environment for one hour.Thus, conductive lines 106 and 108 can be more robust and able to withstand subsequent processing because their material is less susceptible to oxidation or copper diffusion than pure metal. The copper-based alloy can also improve current driving in TFTs 204.

[0075] After the conductive lines 106 and 108 have been deposited, planarization (e.g., a CMP, etch-back, or the like) may be performed to remove excess portions of the conductive material and thereby form the conductive lines 106 and 108. In the resulting structure, upper surfaces of the multilayer stack 58, the memory film 90, the OS layer 92, the conductive lines 106, and the conductive lines 108 may be substantially planar (e.g., within process variations). The conductive lines 106 may correspond to bit lines in the memory array, and the conductive lines 108 may correspond to source lines in the memory array 200. Although Fig. 35C illustrates a cross-sectional view showing only the conductive lines 106, a cross-sectional view of the conductive lines 108 may be similar.

[0076] Thus, stacked TFTs 204 may be formed in the memory array 200. Each TFT 204 includes a gate electrode (e.g., a portion of a corresponding conductive line 72), a gate dielectric (e.g., a portion of a corresponding memory film 90), a channel region (e.g., a portion of a corresponding OS layer 92), and source and drain electrodes (e.g., portions of corresponding ones of the conductive lines 106 and 108). The dielectric 102 isolates adjacent TFTs 204 in a same column and on a same vertical plane. The TFTs 204 may be arranged in an array of vertically stacked rows and columns. Subsequent processing similar to that described above may be performed to form interconnections from the conductive lines 72, 106, and 108 to the underlying circuitry of the device and result in a structure similar to that described above. Fig. 30A to 30D.

[0077] Various embodiments provide a 3D memory array with vertically stacked memory cells. The memory cells each comprise a TFT with a memory film, gate dielectric, and an oxide semiconductor channel region. The TFT includes source / drain electrodes, which also serve as source lines and bit lines in the memory array. In some embodiments, the source lines and bit lines in the memory array may be formed from a material that reduces contact resistance in the memory cells.

[0078] For example, in some embodiments, the source lines and bit lines may comprise a low work function material (e.g., less than 4.6). As a portion of forming the source lines and bit lines, an annealing process may be performed to form a polycrystalline, metal-containing region in the channel region at a boundary between the channel region and the source and bit lines. Therefore, the polycrystalline region contacting the source / bit lines may be a low-resistivity region, regardless of the phase (e.g., crystalline or amorphous) of the remaining portions of the channel region, thereby reducing contact resistance in the TFTs. In some embodiments, the source / bit lines may comprise a low-resistivity copper-based alloy with a reduced tendency to oxidize (e.g., less susceptible to oxidation than pure copper).In embodiments where the source / bit lines comprise a low resistivity copper-based alloy, current driving may be further improved.

Claims

[1] Memory cell (202) comprising: a thin-film transistor (204) over a semiconductor substrate (50), the thin-film transistor (204) comprising: a memory film (90) contacting a word line (72); and an oxide semiconductor layer, OS layer (92), contacting a source line (108) and a bit line (106), wherein the memory film (90) is arranged between the OS layer (92) and the word line (72), wherein the source line (108) and the bit line (106) each comprise a first conductive material (150) contacting the OS layer (92), and wherein the first conductive material (150) has a work function that is less than 4.6 eV; and a dielectric (98) separating the source line (108) and the bit line (106) from each other, wherein the OS layer (92) comprises: a first polycrystalline region (92') at an interface (152) between the OS layer (92) and the source line (108); and a second polycrystalline region (92') at an interface (152) between the OS layer (92) and the bit line (106), wherein the first polycrystalline region (92') comprises a metal oxide, wherein a metal element of the first polycrystalline region (92') is the same as a metal element of the first conductive material (150). [2] The memory cell of claim 1, wherein the first conductive material (150) comprises LaNiO, InSnO, InZnO, CdSnO, Al-doped ZnO, or F-SnO. [3] The memory cell of claim 1 or 2, wherein the source line (108) and the bit line (106) each comprise a second conductive material (156) on a side of the first conductive material (150) opposite the OS layer (92), the second conductive material (156) being different from the first conductive material (150). [4] The memory cell of claim 3, wherein the second conductive material (156) comprises TiN, W, Ti, MoTi, CuMgAl, Ru, Al, Ta, TaN, CuMn or CuAlZn. [5] The memory cell of any one of the preceding claims 1 to 4, wherein a thickness of the first polycrystalline region (92') is in a range of 1 nm to 10 nm. [6] A memory cell according to any one of the preceding claims, wherein the first conductive material (150) extends continuously from the OS layer (92) to a second OS layer (92), and the second OS layer (92) is located on a side of the first conductive material (150) opposite the OS layer (92). [7] Method comprising: Structuring a first trench extending through a first conductive line (72); depositing a storage film (90) along sidewalls and a bottom surface of the first trench; Depositing an oxide semiconductor layer, OS layer (92), over the memory film (90), the OS layer (92) extending along sidewalls and the bottom surface of the first trench; Depositing a first dielectric (98A) over and in contact with the OS layer (92); Patterning a second trench (100) extending through the first dielectric (98A); Depositing a first conductive material (150) in the second trench (100); and Annealing the first conductive material (150) and the OS layer (92) to form a polycrystalline region (92') at an interface (152) between the OS layer (92) and the first conductive material (150), wherein annealing the first conductive material (150) and the OS layer (92) causes a reaction between an indium oxide component of the OS layer (92) and a metal component of the first conductive material (150) such that the polycrystalline region (92') comprises a metal oxide. [8] The method of claim 7, wherein the first conductive material (150) comprises TiN, W, Ti, MoTi, CuMgAl, Ru, Al, Ta, TaN, CuMn or CuAlZn. [9] The method of claim 7 or 8, wherein annealing the first conductive material (150) and the OS layer (92) comprises annealing the first conductive material (150) and the OS layer (92) at a temperature of at least 300°C. [10] The method of any one of the preceding claims 7 to 9, further comprising: after annealing the first conductive material (150), structuring a third trench through the first conductive material (150), wherein remaining portions of the first conductive material (150) are arranged on opposite sidewalls of the third trench; and filling the third trench with a second conductive material (156) different from the first conductive material (150). [11] The method of claim 10, wherein the second conductive material (156) comprises TiN, W, Ti, MoTi, CuMgAl, Ru, Al, Ta, TaN, CuMn, CuAlZn. [12] Method according to one of the preceding claims 7 to 11, further comprising: structuring a fourth trench through the first conductive material (150); and filling the fourth trench with a second dielectric.

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