DRIVER CIRCUIT

Abstract

Driver circuit (1) of a power device (51, 52) comprising: an internal power supply (11); a set-side pulse generation circuit (13a) and a reset-side pulse generation circuit (13b) connected to the internal power supply (11) and receiving a logic input signal, wherein the set-side pulse generation circuit (13a) generates a set signal when it detects that the logic input signal changes from a first logic level to a second logic level, wherein the reset-side pulse generation circuit (13b) generates a reset signal when it detects that the logic input signal changes from the second logic level to the first logic level; a set-side level shift circuit (21a) that generates a level-shifted set signal by shifting a level of the set signal; a reset-side level shift circuit (21b) that generates a level-shifted reset signal by shifting a level of the reset signal; a control circuit that turns on the power device (51, 52) in response to the level-shifted set signal and turns off the power device (51, 52) in response to the level-shifted reset signal; and a securing circuit (15) which, based on the logic input signal, secures a first state in which the power device (51, 52) is turned off when the logic input signal is at the first logic level, and ensures a second state in which the power device (51, 52) is turned on when the logic input signal is at the second logic level.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority from Japanese Patent Application No. JP 2019-043 760 A, filed on March 11, 2019, the entire disclosure of which is hereby incorporated by reference. BACKGROUNDTechnical field

[0002] The present disclosure relates to a driver circuit that drives a power device. Description of the state of the art

[0003] US 9 621 151 B2 discloses a driver IC having an annular termination region and a first region and a second region arranged outside and inside the termination region on a layout, respectively. A sense MOS, which is arranged between a floating terminal and a first sense node and driven by a power supply voltage, is formed in the termination region. A fault detection circuit, which detects the presence of a fault when a voltage of the first sense node is higher than a decision voltage determined in advance during a period in which a low-side driver drives a low-side transistor to an ON state, is formed in the first region.

[0004] As disclosed in International Patent Application Publications Nos. WO 2016 / 163142 A1 and WO 2016 / 009719 A1, a half-bridge circuit includes first and second power switching devices connected in series between a high-potential terminal and a low-potential terminal of a power supply, and a node between the first power switching device and the second power switching device is coupled to a load such as a motor. The load is controlled by turning the first power switching device on and off and by turning the second power switching device on and off complementarily to the first power switching device. The second power switching device is turned on and off by being controlled by a low-side control circuit that operates by using the potential of the low-potential terminal of the power supply as the reference potential.The first power switching device is turned on and off by being controlled by a high-side control circuit that operates by using the potential of the node between the first power switching device and the second power switching device as the reference potential.

[0005] A level shift circuit is coupled to a preceding stage of the high-side control circuit, and a pre-stage circuit is coupled to a preceding stage of the level shift circuit. The high-side control circuit and the level shift circuit operate at high voltage, and the pre-stage circuit operates at low voltage. The pre-stage circuit generates a pulsed set signal and reset signal based on external logic input signals, and the level shift circuit shifts the levels of the set signal and reset signal. The high-side control circuit generates the drive signal based on the level-shifted set signal and reset signal and switches the first power switching device on and off according to the drive signal.

[0006] When the first and second power switching devices are switched between an on and off state, the potential of the node between the first power switching device and the second power switching device falls below the potential of the low-potential terminal of the power supply due to the inductance of the load, and the voltage at the node may become negative. When such a negative voltage is generated, the operation of the pre-stage circuit is unstable, so the set signal and the reset signal are not stably output from the pre-stage circuit. Even if the voltage at the node recovers from such a negative voltage state and returns to normal, the levels of the set signal and the reset signal may become erroneous, and the high-side control circuit may malfunction.

[0007] The present disclosure is based on the above-mentioned problems, and an object of the present disclosure is to operate a control circuit that normally drives a power device even after a negative voltage is generated at a node coupled to the power device. SUMMARY

[0008] A main aspect of the present disclosure for achieving an object described above is a driver circuit according to claim 1. Further aspects of the present disclosure are subject of the dependent claims, the drawings and the following description of embodiments.

[0009] According to one aspect of the present disclosure, it is possible for a control circuit that drives a power switching device to operate normally. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 is a diagram showing a driver circuit, an output circuit, a load, and an external power supply. Fig. 2 is a timing diagram illustrating, on a time axis, relationships among a high-side input signal, a low-side input signal, a set signal, a level-shifted set signal, a reset signal, a level-shifted reset signal, an output of a latch circuit, and an output signal. Fig. Figure 3 is a diagram illustrating an external power supply and a pre-stage circuit of the driver circuit. Fig. 4 is a timing diagram illustrating relationships between a high-side input signal and the states of switching devices on a time axis. Fig. 5 is a timing diagram showing, on a time axis, relationships between voltages at nodes, an input signal, an output signal, and output signals of pulse generation circuits after a high-side power switching device is switched from the on-state to the off-state. Fig. 6 is a timing diagram showing, on a time axis, relationships between voltages at nodes, an input signal, an output signal, and output signals of pulse generation circuits after a high-side power switching device is switched from the off state to the on state. DETAILED DESCRIPTION

[0010] The description of this specification and the accompanying drawings show at least the following things. ======== Design =========

[0011] An embodiment of the present disclosure will be described below with reference to the drawings. Note that various limitations technically preferred for implementing the present disclosure will be added to an embodiment described below. Therefore, the present disclosure is not limited to the following embodiments and illustrated examples. <<<1. Rough diagram of the driver and output circuit>>>

[0012] Fig. 1 is a diagram showing a driver circuit 1, an output circuit 5, a load 9, and an external power supply 4. Fig. 2 is a timing chart illustrating relationships among an input signal HIN, an input signal LIN, a set signal set, a level-shifted set signal setdrn, a reset signal res, a level-shifted reset signal resdrn, an output of a latch circuit 222, and an output signal HO.

[0013] The external power supply 4 generates a constant DC voltage and outputs the DC voltage to the driver circuit 1.

[0014] The external power supply 4 is coupled to a capacitor 4a with a large capacitance. Thus, noise generated in the driver circuit 1, the output circuit 5, and the like is removed by the capacitor 4a, so that the external power supply 4 is not affected by the noise. Accordingly, the output voltage of the external power supply 4 is stable.

[0015] The driver circuit 1 is operated by receiving the high-side input signal HIN and the low-side input signal LIN from a microcomputer (not shown). The input signal HIN and the input signal LIN are logical input signals that repeatedly alternate between a first logical level and a second logical level. In this description, the first logical level refers to a low level, and the second logical level refers to a high level.

[0016] The input signal HIN and the input signal LIN are usually in a complementary relationship. Specifically, when the input signal HIN is high, the input signal LIN is low, and when the input signal HIN is low, the input signal LIN is high.

[0017] Note that the microcomputer is not affected by noise generated in the driver circuit 1, the output circuit 5, and the like. Accordingly, the microcomputer stably outputs the input signal HIN and the input signal LIN.

[0018] When the driver circuit 1 drives the output circuit 5 based on the high-side input signal HIN and the low-side input signal LIN, the output circuit 5 repeatedly and alternately switches the state of the load 9 between a voltage application state in which voltage of a high-voltage DC power supply 8 is applied to the load 9 and a ground voltage application state in which a ground voltage is applied to the load 9.

[0019] The output circuit 5 includes power switching devices 51, 52 that form a half-bridge. The power switching devices 51 and 52 are N-channel power MOSFETs, but can also be power devices such as IGBTs or bipolar transistors. The power switching devices 51 and 52 are connected in series between a high-potential output terminal and a low-potential output terminal of the high-voltage DC power supply 8. A node N1 between the power switching device 52 and the low-potential output terminal of the high-voltage DC power supply 8 is grounded, and the node N1 leads to a reference potential. A node N2 between the power switching device 51 and the power switching device 52 is coupled to one end of the load 9. The other end of the load 9 is grounded. The node N2 is coupled to a low-potential output terminal of a high-side DC power supply 6.

[0020] The driver circuit 1 switches the power switching device 51 on and off based on the high-side input signal HIN. Furthermore, the driver circuit 1 switches the power switching device 52 on and off complementarily to the power switching device 51 based on the low-side input signal LIN. When the power switching device 51 is on and the power switching device 52 is off, the potential of the node N2 leads to the output voltage of the high-voltage DC power supply 8, and the load 9 enters the voltage application state. When the power switching device 51 is off and the power switching device 52 is on, the potential of the node N2 leads to the reference potential, and the load 9 enters the ground voltage application state. Accordingly, the potential of the node N2 can vary between the reference potential and the output voltage of the high-voltage DC power supply 8.It should be noted that after a dead time, the load 9 transitions from the voltage applied state to the ground voltage applied state. During the dead time, the two power switching devices 51, 52 are turned off to prevent short-circuit and through-current in the high-voltage DC power supply 8. Similarly, after a dead time, the load 9 transitions from the ground voltage applied state to the voltage applied state. <<<2. Driver circuit configuration>>>

[0021] The driver circuit 1 includes a pre-stage circuit 10, a terminal stage circuit 20 and the low-side control circuit 40.

[0022] The driver circuit 1 is designed as a single chip. However, the driver circuit 1 can also be configured such that the pre-stage circuit 10 and the terminal stage circuit 20 are housed in the same chip, and the low-side control circuit 40 is housed in a different chip. Alternatively, the driver circuit 1 can also be configured such that the pre-stage circuit 10 and the low-side control circuit 40 are housed in the same chip, and the terminal stage circuit 20 is housed in a different chip. The driver circuit 1 can also be configured such that the terminal stage circuit 20 and the low-side control circuit 40 are housed in the same chip, and the pre-stage circuit 10 is housed in a different chip.As a further alternative, the driver circuit 1 can be configured such that the pre-stage circuit 10, the terminal stage circuit 20 and the low-side control circuit 40 are each housed in separate chips.

[0023] The pre-stage circuit 10 operates at low voltage, and the terminal stage circuit 20 operates at high voltage.

[0024] The pre-stage circuit 10 includes an internal power supply 11, an input circuit 12, a pulse generation circuit 13, and a buffer circuit 14. The terminal stage circuit 20 includes a level shift circuit 21, a high-side control circuit 22, and the diodes 28 and 29. <<< 2-1. Low-side control circuit>>>

[0025] The low-side control circuit 40 is powered by a low-side DC power supply 7 and receives the input signal LIN from the microcomputer. The low-side control circuit 40 switches the power switching device 52 on and off complementarily to the power switching device 51 based on the input signal LIN. <<< 2-2. Internal Power Supply >>>>

[0026] The internal power supply 11 is supplied with power from the external power supply 4 and generates a constant DC voltage from the energy of the external power supply 4, which is lower than the output voltage of the external power supply 4. The internal power supply 11 outputs the DC voltage to the input circuit 12 and the pulse generation circuit 13. <<< 2-3. Input circuit>>>>

[0027] Fig. 3 is a diagram illustrating the input circuit 12, the pulse generation circuit 13, the buffer circuit 14, and an input control state securing circuit 15. Fig. 4 is a timing chart illustrating relationships between the states of the switching devices 133a, 134a, 133b, and 134b of the pulse generating circuit 13, the states of the switching devices 151a, 152a, 151a, and 151b of the input control state ensuring circuit 15, and the input signal HIN.

[0028] The input circuit 12 includes a comparator 121 and a noise filter 122. The comparator 121 compares a reference voltage Ref generated by the internal power supply 11 and the level of the input signal HIN. If the level of the input signal HIN is higher than the reference voltage Ref, the output signal of the comparator 121 is high. If the level of the input signal HIN is lower than the reference voltage Ref, the output signal of the comparator 121 is low.

[0029] The noise filter 122 is, for example, a low-pass filter. The noise filter 122 removes noise in the output signal of the comparator 121. The output signal whose noise is removed by the noise filter 122 is the output signal of the input circuit 12, and this output signal is fed into the pulse generation circuit 13. If a delay in the input circuit 12 is ignored, the output signal of the input circuit 12 is synchronous with the input signal HIN. <<< 2-4. Pulse generation circuit>>>>

[0030] The pulse generation circuit 13 includes a set-side pulse generation circuit 13a and a reset-side pulse generation circuit 13b. When the output signal of the input circuit 12 changes from low to high, the set-side pulse generation circuit 13a generates a pulse and outputs the set signal set (see Fig. 2), whose level is high when this pulse is generated, and whose level is low when this pulse disappears. When the output signal of the input circuit 12 changes from high to low, the reset-side pulse generation circuit 13b further generates a pulse and outputs the reset signal res (see Fig. 2) whose level is high when this pulse is generated and whose level is low when this pulse disappears. The time at which the level of the set signal set is high is shifted in time from the time at which the level of the reset signal res is high. The set signal set and the reset signal res are input to the level shift circuit 21 of the terminal stage circuit 20.

[0031] The set-side pulse generation circuit 13a includes a set-side edge detection circuit 131a, an inverter 132a, a switching device (third switching device) 133a, a switching device (fourth switching device) 134a, and a set-side Zener diode (set-side clamping device) 135a. The reset-side pulse generation circuit 13b includes a reset-side edge detection circuit 131b, an inverter 132b, a switching device (seventh switching device) 133b, a switching device (eighth switching device) 134b, and a reset-side Zener diode (reset-side clamping device) 135b.

[0032] The set-side edge detection circuit 131a generates a pulse when a rising edge is detected, after which the output signal of the input circuit 12 changes from low to high. The set-side edge detection circuit 131a outputs a signal to an inverter 132a whose level is high when the pulse is generated and whose level is low when the pulse disappears. The inverter 132a inverts the output signal of the set-side edge detection circuit 131a and outputs the inverted signal to the gates of the switching device 133a and the switching device 134a.

[0033] Switching device 133a is a P-channel MOSFET, and switching device 134a is an N-channel MOSFET. The source of switching device 133a is coupled to the internal power supply 11, the drain of switching device 133a is coupled to the drain of switching device 134a, and the source of switching device 134a is grounded, thereby providing the reference potential.

[0034] The set-side Zener diode 135a is coupled between a node N3 and ground in a reverse-biased manner. In other words, the cathode of the set-side Zener diode 135a is coupled to node N3, and the anode of the set-side Zener diode 135a is coupled to ground, thus forming the reference potential. Note that the breakdown voltage (e.g., 5.5 V) of the set-side Zener diode 135a is higher than the output voltage (e.g., 5 V) of the internal power supply 11 and lower than the output voltage (e.g., 30 V) of the internal power supply 4. Accordingly, the set-side Zener diode 135a clamps the voltage at node N3, which is coupled to the gate of the set-side level shift switching device 211a described later, to the breakdown voltage such that the voltage at node N3 does not rise higher than necessary.

[0035] When the output signal of the inverter 132a is low, that is, when the input signal HIN rises, the switching device 133a is turned on and the switching device 134a is turned off (see Fig. 4). Thus, the voltage of the internal power supply 11 is applied to node N3, and the voltage at node N3 becomes high. When the output signal of inverter 132a is high, switching device 133a is turned off, and switching device 134a is turned on. Thus, the voltage at node N3 becomes low, which serves as a reference potential. The voltage at node N3 is output as the set signal set.

[0036] The reset-side edge detection circuit 131b generates a pulse when a falling edge is detected, after which the output signal of the input circuit 12 changes from high to low. The reset-side edge detection circuit 131b outputs a signal to an inverter 132b whose level is high when the pulse is generated and whose level is low when the pulse disappears. The inverter 132b inverts the output signal of the reset-side edge detection circuit 131b and outputs the inverted signal to the gates of the switching device 133b and the switching device 134b.

[0037] Switching device 133b is a P-channel MOSFET, and switching device 134b is an N-channel MOSFET. The source of switching device 133b is coupled to the internal power supply 11, the drain of switching device 133b is coupled to the drain of switching device 134b, and the source of switching device 134b is grounded, thereby providing the reference potential.

[0038] The reset-side Zener diode 135b is coupled between a node N4 and ground in a reverse-biased manner. In other words, the cathode of the reset-side Zener diode 135b is coupled to the node N4, and the anode of the reset-side Zener diode 135b is coupled to ground, thereby forming the reference potential. Note that the breakdown voltage (for example, 5.5 V) of the reset-side Zener diode 135b is the same as that of the set-side Zener diode 135a. Accordingly, the reset-side Zener diode 135b clamps the voltage at node N4, which is coupled to the gate of the reset-side level-shift switching device 211b described later, to the breakdown voltage, such that the voltage at node N4 does not rise higher than necessary.

[0039] When the output signal of the inverter 132b is low, that is, when the input signal HIN falls, the switching device 133b is turned on and the switching device 134b is turned off (see Fig. 4). Thus, the voltage of the internal power supply 11 is applied to node N4, and the voltage at node N4 becomes high. When the output signal of inverter 132b is high, switching device 133b is turned off, and switching device 134b is turned on. Thus, the voltage at node N4 becomes low, which serves as the reference potential. <<< 2-5. Level shift circuit and clamping diodes>>>

[0040] As in Fig. 1, the level shift circuit 21 includes a set-side level shift circuit 21a and a reset-side level shift circuit 21b. The set-side level shift circuit 21a shifts the DC level of the set signal set output by the set-side pulse generation circuit 13a while inverting the set signal set, and outputs the inverted set signal as the level-shifted set signal setdrn to the high-side control circuit 22 (see Fig. 2). Furthermore, the reset-side level shift circuit 21b shifts the DC level of the reset signal res output by the reset-side pulse generation circuit 13b while inverting the reset signal res, and outputs the inverted reset signal res to the high-side control circuit 22 as the level-shifted reset signal resdrn (see Fig. 2).

[0041] The set-side level shift circuit 21a includes a set-side level shift switching device 211a and a resistor 212a. The reset-side level shift circuit 21b includes a reset-side level shift switching device 211b and a resistor 212b.

[0042] The level-shifting switching devices 211a and 211b are N-channel MOSFETs with high voltage withstand capability, but may also be IGBTs, bipolar transistors, or the like. The threshold voltage (for example, 1.5 V) of the set-side level-shifting circuit 211a is set lower than the breakdown voltage (for example, 5.5 V) of the set-side Zener diode 135a, and the threshold voltage of the reset-side level-shifting circuit 211b is set lower than the breakdown voltage of the reset-side Zener diode 135b. The threshold voltage refers to a gate-source voltage when the level-shifting switching device 211a or 211b is turned on. Note that when the level shift switching device 211a or 211b is a bipolar transistor, the threshold voltage is a voltage (for example, 0.7 V) when the bipolar transistor is turned on.

[0043] Resistor 212a and set-side level shift switching device 211a are connected in series between the high-potential output terminal of high-side DC power supply 6 and ground. Specifically, the drain of set-side level shift switching device 211a is coupled to the high-potential output terminal of high-side DC power supply 6 via resistor 212a, and the source of set-side level shift switching device 211a is coupled to ground.

[0044] Resistor 212b and reset-side level-shift switching device 211b are connected in series between the high-potential output terminal of high-side DC power supply 6 and ground. Specifically, the drain of reset-side level-shift switching device 211b is coupled to the high-potential output terminal of high-side DC power supply 6 via resistor 212b, and the source of reset-side level-shift switching device 211b is coupled to ground.

[0045] An anode of diode 28 is coupled to node N2, and a cathode of diode 28 is coupled to node N5 between resistor 212a and set-side level shift switching device 211a. Since diode 28 clamps the potential of node N5 to the potential of node N2, the reference voltage at node N5 is the potential of N2. This prevents an overvoltage from being injected into high-side control circuit 22.

[0046] An anode of diode 29 is coupled to node N2, and a cathode of diode 29 is coupled to node N6 between resistor 212b and reset-side level-shift switching device 211b. Since diode 29 clamps the potential of node N6 to the potential of node N2, the reference voltage at node N6 is the potential of node N2. This prevents an overvoltage from being injected into high-side control circuit 22.

[0047] The gate of the set-side level-shift switching device 211a is coupled to the output terminal of the set-side pulse generation circuit 13a, that is, the node N3 between the switching device 133a and the switching device 134a. The set signal set output by the set-side pulse generation circuit 13a is input to the gate of the set-side level-shift switching device 211a. The set-side level-shift switching device 211a is turned on and off based on the set signal set. When the set-side level-shift switching device 211a is turned off, the drain voltage (voltage at node N5) is raised to the high level by the high-side DC power supply 6. When the set-side level-shift switching device 211a is turned on, the voltage at node N5 is lowered to the low level by the ground.The voltage at node N5 is fed into the high-side control circuit 22 as the level-shifted set signal setdrn.

[0048] The gate of the reset-side level-shift switching device 211b is coupled to the output terminal of the reset-side pulse generation circuit 13b, that is, the node N4 between the switching device 133b and the switching device 134b. The reset signal res output by the reset-side pulse generation circuit 13b is input to the gate of the reset-side level-shift switching device 211b. The reset-side level-shift switching device 211b is turned on and off based on the reset signal res. When the reset-side level-shift switching device 211b is turned off, the voltage at node N6 is raised to the high level by the high-side DC power supply 6. When the reset-side level-shift switching device 211b is turned on, the voltage at node N6 is lowered to the low level by the ground.The voltage at node N6 is fed into the high-side control circuit 22 as the level-shifted reset signal res.

[0049] The time at which the level-shifted set signal setdrn is low is shifted in time from the time at which the level-shifted reset signal resdrn is low. <<< 2-6. High-side control circuit>>>

[0050] The high-side control circuit 22 generates the output signal HO based on the level-shifted set signal setdrn and the level-shifted reset signal resdrn, and outputs the output signal HO to the gate of the power switching device 51. The high-side control circuit 22 thereby turns the power switching device 51 on and off. When the level-shifted set signal setdrn is low and the level-shifted reset signal resdrn is high, the high-side control circuit 22 causes the output signal HO to be high. When both the level-shifted set signal setdrn and the level-shifted reset signal resdrn are low or high, the high-side control circuit 22 maintains the level of the output signal HO. When the level-shifted set signal setdrn is high and the level-shifted reset signal resdrn is low, the high-side control circuit 22 causes the output signal HO to be low.

[0051] The high-side control circuit 22 includes a protection circuit 221, a latch circuit 222 and a high-side driver 223.

[0052] The voltage of the high-side DC power supply 6 is applied to the protection circuit 221 with respect to the potential of node N2. The protection circuit 221 also receives the level-shifted set signal setdrn and the level-shifted reset signal resdrn. The protection circuit 221 controls the latch circuit 222 based on the level-shifted set signal setdrn and the level-shifted reset signal resdrn. As shown in Fig. As illustrated in Figure 2, the protection circuit 221 outputs a high-level signal to the latch circuit 222 when the level-shifted set signal setdrn is low and the level-shifted reset signal resdrn is high. When the level-shifted set signal setdrn is high and the level-shifted reset signal resdrn is low, the protection circuit 221 outputs a low-level signal to the latch circuit 222. When both the level-shifted set signal setdrn and the level-shifted reset signal resdrn are low or high, the protection circuit 221 causes the output to have a high impedance.

[0053] The output voltage of the high-side DC power supply 6 with respect to the potential of node N2 is fed into the latch circuit 222. The latch circuit 222 is controlled according to the output of the protection circuit 221. When the output of the protection circuit 221 (the input of the latch circuit 222) is high or low, the latch circuit 222 stores the output value and outputs it. When the output of the protection circuit 221 changes to high impedance, the latch circuit 222 retains and outputs the value stored immediately before the output of the protection circuit 221 changes to high impedance.

[0054] Let's assume a case where driver circuit 1 is normal. When the level-shifted set signal setdrn is low and the level-shifted reset signal resdrn is high, the output of latch circuit 222 is high. Furthermore, when both the level-shifted set signal setdrn and the level-shifted reset signal resdrn are low, the output of latch circuit 222 is held high. When the level-shifted set signal setdrn is high and the level-shifted reset signal resdrn is low, the output of latch circuit 222 is low. Furthermore, when both the level-shifted set signal setdrn and the level-shifted reset signal resdrn are low, the output of latch circuit 222 is held low.

[0055] In addition, when the potentials at nodes N5 and N6 change, dv / dt noise is caused by parasitic capacitances of level-shifting switching devices 211a and 211b, etc., so that currents flow through level-shifting switching devices 211a and 211b simultaneously. This causes both the level-shifted set signal setdrn and the level-shifted reset signal resdrn to erroneously go low. Accordingly, the output of protection circuit 221 is at a high impedance, and the level of the output of latch circuit 222 is maintained.

[0056] The high-side driver 223 is inputted with the output voltage of the high-side DC power supply 6 with respect to the potential of node N2. The high-side driver 223 also receives the output of the latch circuit 222. The high-side driver 223 generates the output signal HO according to the output of the latch circuit 222 and outputs the output signal HO to the gate of the power switching device 51. Specifically, the high-side driver 223 causes the output signal HO to be low when the output of the latch circuit 222 is low and causes the output signal HO to be high when the output of the latch circuit 222 is high.

[0057] Note that the components of the high-side control circuit 22 may be those disclosed in Japanese Patent Publication No. 3429937. <<< 2-7. Buffer circuit>>>>

[0058] As in the Fig. 1 and Fig. 3, the output voltage of the external power supply 4 is fed into the buffer circuit 14.

[0059] The buffer circuit 14 outputs a signal that is non-inverted with respect to the input signal HIN and a signal that is inverted with respect to the input signal HIN to the input control state ensuring circuit 15.

[0060] The buffer circuit 14 contains inverters 141 and 142.

[0061] The input signal HIN is input to inverter 141. Inverter 141 inverts the input signal HIN and outputs the signal inverted with respect to the input signal HIN to inverter 142 and the input control state ensuring circuit 15. Inverter 142 inverts the output of inverter 141 and outputs a signal that is non-inverted with respect to the input signal HIN to the input control state ensuring circuit 15.

[0062] It should be noted that the output signal of the input circuit 12 can be fed into the buffer circuit 14 instead of the input signal HIN. <<< 2-8. Input Control State Protection Circuit>>>

[0063] The output voltage of the external power supply 4 is fed into the input control state ensuring circuit 15.

[0064] The input control state ensuring circuit 15 includes a set-side input control state ensuring circuit 15a and a reset-side input control state ensuring circuit 15b.

[0065] In the set-side input control state ensuring circuit 15a, when the input signal HIN is high, the voltage at the output terminal of the set-side pulse generation circuit 13a, that is, the voltage at node N3 between the switching device 133a and the switching device 134a, is pulled up by the external power supply 4 based on the output of the inverter 141 of the buffer circuit 14. Furthermore, in the set-side input control state ensuring circuit 15a, when the input signal HIN is low, the voltage at node N3 is pulled down by grounding based on the output of the inverter 141 of the buffer circuit 14. Here, the pulling up and pulling down of the voltage at node N3 has no influence on the operation of turning on and off the set-side level shift switching device 211a performed by the set-side pulse generation circuit 13a.

[0066] In the reset-side input control state ensuring circuit 15b, when the input signal HIN is low, the voltage at the output terminal of the reset-side pulse generating circuit 13b, that is, the voltage at node N4 between the switching device 133b and the switching device 134b, is pulled up by the external power supply 4 based on the output signal of the inverter 142 of the buffer circuit 14. Furthermore, in the reset-side input control state ensuring circuit 15b, when the input signal HIN is high, the voltage at node N4 is pulled down by grounding based on the output signal of the inverter 142 of the buffer circuit 14. The pulling up and pulling down of the voltage at node N4 does not affect the operation of turning on and off the reset-side level shift switching device 211b performed by the reset-side pulse generating circuit 13b.

[0067] The set-side input control state ensuring circuit 15a includes the switching device (first switching device) 151a, the switching device (second switching device) 152a, and a set-side resistor 153a. The reset-side input control state ensuring circuit 15b includes the switching device (fifth switching device) 151b, the switching device (sixth switching device) 152b, and a reset-side resistor 153b. The switching devices 151a and 151b are P-channel MOSFETs, and the switching devices 152a and 152b are N-channel MOSFETs.

[0068] The source of switching device 151a is coupled to external power supply 4. Set-side resistor 153a is coupled between the drain of switching device 151a and the drain of switching device 152a. The source of switching device 152a is grounded and thus forms the reference potential. The gates of switching device 151a and switching device 152a are coupled to the output terminal of inverter 141 of buffer circuit 14. The node between set-side resistor 153a and switching device 152a is coupled to the output terminal of set-side pulse generation circuit 13a, that is, node N3 between switching device 133a and switching device 134a.

[0069] The source of switching device 151b is coupled to external power supply 4. Reset-side resistor 153b is coupled between the drain of switching device 151b and the drain of switching device 152b. The source of switching device 152b is grounded, thereby forming the reference potential. The gates of switching device 151b and switching device 152b are coupled to the output terminal of inverter 142 of buffer circuit 14. The node between reset-side resistor 153b and switching device 152b is coupled to the output terminal of reset-side pulse generation circuit 13b, that is, node N4 between switching device 133b and switching device 134b.

[0070] The output signal of inverter 141 is input to the gates of switching devices 151a and 152a, thereby turning switching device 151a on and off in phase with the input signal HIN, and turning switching device 152a on and off complementarily to switching device 151a. When the input signal HIN is high, that is, when the output signal of inverter 141 is low, switching device 151a is on, and switching device 152a is off. Accordingly, the voltage at the output terminal (that is, node N3) of set-side pulse generation circuit 13a is pulled up by external power supply 4. When the input signal HIN is low, that is, when the output signal of inverter 141 is high, switching device 151a is off, and switching device 152a is on.Accordingly, the voltage at the output terminal of the set-side pulse generation circuit 13a is pulled down by grounding.

[0071] Assuming that the on-state resistance value of the switching device 133a is R133a [Ω], the resistance value of the set-side resistor 153a is R153a [Ω], and the on-state resistance value of the switching device 151a is R151a [Ω], expression (1) is as follows: [Expression 1] R133a< <R153a+R151a

[0072] Thus, when switching devices 133a and 151a are turned on and switching devices 134a and 152a are turned off, the voltage at node N3 is determined by the voltage of internal power supply 11 and the on-state resistance of switching device 133a, essentially unaffected by external power supply 4. In other words, the level of set signal set, which is high, is only slightly pulled up by external power supply 4. Accordingly, no overvoltage occurs at the gate of set-side level-shift switching device 211a.

[0073] Furthermore, assuming that the on-state resistance value of the switching device 134a is R134a [Ω], the output voltage value of the external power supply 4 is VCC [V], and the threshold voltage value of the set-side level shift switching device 211a is VTHa [V], expression (2) is as follows: [Expression 2] VTHa>R134aR134a+R153a+R151aVCC

[0074] Therefore, when switching devices 134a and 151a are turned on and switching devices 133a and 152a are turned off, the voltage at node N3 is lower than the threshold voltage of the set-side level-shift switching device 211a, even if the voltage at node N3 is pulled up by the external power supply 4. Accordingly, the set-side level-shift switching device 211a is turned off. Note that the set-side resistor 153a does not need to be present as long as the on-state resistance of the switching device 151a is sufficiently large. This results in R153a=0 in the two expressions above.

[0075] The output signal of inverter 142 is input to the gates of switching devices 151b and 152b, thereby turning on and off switching device 151b in phase with the input signal HIN, and turning on and off switching device 152b complementarily to switching device 151b. When the input signal HIN is high, that is, when the output signal of inverter 142 is high, switching device 152b is on, and switching device 151b is off. Accordingly, the voltage at the output terminal (that is, node N4) of reset-side pulse generation circuit 13b is pulled down by grounding. Furthermore, when the input signal HIN is low, that is, when the output signal of inverter 142 is low, switching device 152b is off, and switching device 151b is on.Accordingly, the voltage at the output terminal of the reset-side pulse generation circuit 13b is pulled up by the external power supply 4.

[0076] Here, assuming that the on-state resistance value of the switching device 133b is R133b [Ω], the resistance value of the reset-side resistor 153b is R153b [Ω], the on-state resistance value of the switching device 151b is R151b [Ω], the on-state resistance value of the switching device 134b is R134b [Ω], the output voltage value of the external power supply 4 is VCC [V], and the threshold voltage value of the reset-side level shift switching device 211b is VTHb [V], expressions (3) and (4) are as follows: [Expression 3] R133b< <R153b+R151b [Expression 4] VTHb>R134bR134b+R153b+R151bVCC

[0077] According to Expression (3), when the switching devices 133b and 151b are turned on and the switching devices 134b and 152b are turned off, the level of the reset signal res, which is high, is only slightly pulled up by the external power supply 4. Accordingly, no overvoltage occurs at the gate of the reset-side level-shift switching device 211b.

[0078] Furthermore, according to expression (4), when switching devices 134b and 151b are turned on and switching devices 133b and 152b are turned off, the voltage at node N4 is lower than the threshold voltage of the reset-side level-shift switching device 211b, even if the voltage at node N4 is pulled up by the external power supply 4. Accordingly, the reset-side level-shift switching device 211b is turned off. Note that the reset-side resistor 153b does not need to be present as long as the on-state resistance of the switching device 151b is sufficiently large. This results in R153b=0 in the above two expressions.

[0079] The operating delay time of the combination of the above-mentioned buffer circuit 14 and the set-side input control state ensuring circuit 15a is shorter than the operating delay time of the combination of the input circuit 12 and the set-side pulse generating circuit 13a. This is because the noise filter 122 of the input circuit 12 is a low-pass filter, and the output signal of the noise filter 122 is delayed with respect to the input signal.

[0080] Similarly, the operation delay time of the combination of the above-mentioned buffer circuit 14 and the reset-side input control state securing circuit 15b is smaller than the operation delay time of the combination of the input circuit 12 and the reset-side pulse generating circuit 13b. <<<3. Case where a negative voltage is generated>>>

[0081] As shown in the diagrams of the Fig. 5 and Fig. As illustrated in Figure 6, the voltage at node N2 may become negative under the influence of the inductance of load 9 and dv / dt after the power switching devices 51 and 52 are switched on and off, that is, after the input signal HIN and the output signal HO rise or fall. Also, in the case where external noise, such as a three-phase current, a lighting surge, and an ESD surge, occurs, the voltage at node N2 may become negative.

[0082] When the voltage at node N2 becomes negative, the operation of the pre-stage circuit 10 becomes unstable under the influence of the terminal stage circuit 20. In particular, the internal power supply 11 does not operate normally, and the input circuit 12 and the pulse generation circuit 13 also do not operate normally. More specifically, the output voltage from the internal power supply 11 drops, and the output of the pulse generation circuit 13 may become a high-impedance state. In such a case, the output signals of the set-side pulse generation circuit 13a and the reset-side pulse generation circuit 13b (set signal set, reset signal res) are unstable. Accordingly, the output signals of the set-side pulse generation circuit 13a and the reset-side pulse generation circuit 13b become indeterminate when the voltage at node N2 returns from the negative voltage state to the normal state.

[0083] However, the microcomputer and external power supply 4, which output the input signals HIN, are not affected by the terminal stage circuit 20. That is, even if the voltage at node N2 becomes negative, the microcomputer and external power supply 4 operate normally. Thus, the buffer circuit 14, the set-side input control state ensuring circuit 15a, and the reset-side input control state ensuring circuit 15b, to which the voltage of the external power supply 4 is input, operate normally. Accordingly, the high-side control circuit 22 does not malfunction when node N2 returns from the negative voltage state to the normal state, even if the output signals of the set-side pulse generation circuit 13a and the reset-side pulse generation circuit 13b are unstable.Thus, even after returning to the normal state, the output signal HO of the high-side control circuit 22 remains in the state before the negative voltage appeared at node N2. This will be described in more detail below. <<< 3-1. Case where the output signal HO is low>>>

[0084] When the input signal HIN falls, the output signal of the reset-side pulse generation circuit 13b (reset signal res) temporarily goes high, and then both output signals of the reset-side pulse generation circuit 13b and the set-side pulse generation circuit 13a (set signal set) go low (see Fig. 2). Accordingly, the output signal HO of the high-side control circuit 22 goes low.

[0085] Then, after the power switching devices 51 and 52 are switched on and off, when the voltage at node N2 is as shown in Fig. 5 illustrates, due to the effects of the inductance of the load 9 and dv / dt or the effects of external noise and the like, the switching device 152a turns on even though the output signal of the set-side pulse generation circuit 13a is unstable. Thus, the voltage at the output terminal (i.e., node N3) of the set-side pulse generation circuit 13a is pulled down by grounding. This causes the output signal HO of the high-side control circuit 22 to remain high without turning on the set-side level shift switching device 211a. Furthermore, since the switching device 151b turns on, the voltage at the output terminal (i.e., node N4) of the reset-side pulse generation circuit 13b is pulled up by the external power supply 4.Accordingly, the output signal of the reset-side pulse generation circuit 13b is unstable, causing the output signal HO of the high-side control circuit 22 to remain low regardless of whether the reset-side level shift switching device 211b is turned on or not.

[0086] After that, the voltage at node N2 returns from the negative voltage level to the normal state, and the internal power supply 11, the input circuit 12, and the pulse generation circuit 13 return to their original states. In this case, since the switching device 152a is turned on, the voltage at the output terminal of the set-side pulse generation circuit 13a is pulled down by grounding. Thus, the output signal HO of the high-side control circuit 22 remains low without the set-side level shift switching device 211a being turned on, even if the output signal of the set-side pulse generation circuit 13a is unstable at the time of returning to the original state. Furthermore, since the switching device 151b is turned on, the voltage at the output terminal of the reset-side pulse generation circuit 13b is pulled up by the external power supply 4.Accordingly, the output signal HO of the high-side control circuit 22 remains low regardless of whether the reset-side level-shift switching device 211b is turned on or not, even if the output signal of the reset-side pulse generation circuit 13b is unstable. Note that, here, the case where the reset-side level-shift switching device 211b is turned on represents, for example, the case where the switching device 134b is off and the voltage at node N4 is pulled up, resulting in the breakdown voltage of the reset-side Zener diode 135b. On the other hand, the case where the reset-side level-shift switching device 211b is off indicates, for example, that the switching device 134b is turned on and the voltage at node N4 is lower than the threshold voltage.

[0087] Here, as described above, the operation delay time of the combination of the buffer circuit 14 and the set-side input control state ensuring circuit 15a is shorter than the operation delay time of the combination of the input circuit 12 and the set-side pulse generating circuit 13a. Thus, the voltage at node N3 is influenced by the output of the set-side input control state ensuring circuit 15a before the output signal of the set-side pulse generating circuit 13a becomes unstable or indeterminate. Accordingly, the erroneous operation of the set-side level shift switching device 211a can be prevented. <<< 3-2. Case where the output signal HO is high >>>

[0088] After the input signal HIN rises, the output signal HO of the high-side control circuit 22 is high when both the output signals of the reset-side pulse generation circuit 13b and the set-side pulse generation circuit 13a (set signal set) are low. In this case, when the voltage at node N2, as shown in Fig.6 illustrates, due to the effects of external noise and the like, the switching device 152b turns on even though the output signal of the reset-side pulse generation circuit 13b is unstable. This causes the voltage at the output terminal of the reset-side pulse generation circuit 13b to be pulled down by grounding. Accordingly, the output signal HO of the high-side control circuit 22 remains high without the reset-side level shift switching device 211b turning on. Subsequently, even when the voltage at node N2 returns to the normal state from the negative voltage state, the switching device 152a turns on, and thus the voltage at the output terminal of the reset-side pulse generation circuit 13b is pulled down by grounding.Accordingly, even if the output of the reset-side pulse generation circuit 13b is unstable at the time of returning to the original state, the output signal HO of the high-side control circuit 22 remains high without turning on the reset-side level-shift switching device 211b. Furthermore, since the switching device 151a is turned on, the voltage at the output terminal of the set-side pulse generation circuit 13a is pulled up by the external power supply 4. Thus, the output signal HO of the high-side control circuit 22 remains high regardless of whether the set-side level-shift switching device 211a is turned on or not, when the voltage at node N2 is in the negative voltage state and then returns to the normal state.It should be noted that whether the set-side level shift switching device 211a is turned on or not depends on the state of the switching device 134a, similarly to whether the reset-side level shift switching device 211b is turned on or not. <<<4. Brief description>>>>

[0089] (1) When the voltage at node N2 becomes negative, the internal power supply 11, the input circuit 12, and the pulse generation circuit 13 may no longer operate normally. However, the buffer circuit 14 and the input control state assurance circuit 15 operate normally thanks to the external power supply 4 and the input signal HIN. Accordingly, the following advantageous effects (2) to (5) are obtained.

[0090] (2) When the input signal HIN is low, the voltage at the output terminal (i.e., node N3) of the set-side pulse generation circuit 13a is pulled low by grounding. Thus, even if the voltage at node N2 becomes negative, the set-side level shift switching device 211a is not turned on. Accordingly, the output signal HO of the high-side control circuit 22 remains low.

[0091] (3) When the input signal HIN is high, the voltage at the output terminal (i.e., node N4) of the reset-side pulse generation circuit 13b is pulled low by grounding. Thus, even if the voltage at node N2 becomes negative, the reset-side level shift switching device 211b is not turned on. Accordingly, the output signal HO of the high-side control circuit 22 remains high.

[0092] (4) When the input signal HIN is low, the voltage at the output terminal of the reset-side pulse generation circuit 13b is pulled up by the external power supply 4. Thus, even if the voltage at node N2 becomes negative, the reset-side level shift switching device 211b is likely to be turned on. Accordingly, the output signal HO of the high-side control circuit 22 remains low.

[0093] (5) When the input signal HIN is high, the voltage at the output terminal of the set-side pulse generation circuit 13a is pulled up by the external power supply 4. Thus, even if the voltage at node N2 becomes negative, the set-side level shift switching device 211a is likely to be turned on. Accordingly, the output signal HO of the high-side control circuit 22 remains high.

[0094] (6) Assume that the internal power supply 11, the input circuit 12, and the pulse generation circuit 13 are operating normally. Even if the voltage at the output terminal of the set-side pulse generation circuit 13a is boosted by the external power supply 4, the voltage at the output terminal of the set-side pulse generation circuit 13a does not exceed the withstand voltage of the set-side level-shift switching device 211a when the set signal set is high. This is because the above expression (1) is satisfied. Similarly, since the above expression (3) is satisfied, the voltage at the output terminal of the reset-side pulse generation circuit 13b does not exceed the withstand voltage of the reset-side level-shift switching device 211b when the reset signal res is high.

[0095] (7) Assume that the internal power supply 11, the input circuit 12, and the pulse generation circuit 13 are operating normally. Even if the voltage at the output terminal of the set-side pulse generation circuit 13a is pulled up by the external power supply 4 when the set signal set is low, the voltage at the output terminal of the set-side pulse generation circuit 13a does not exceed the withstand voltage of the set-side level-shift switching device 211a, and the set-side level-shift switching device 211a is turned off. This is because the above expression (2) is satisfied. Similarly, since the above expression (4) is satisfied, the reset-side level-shift switching device 211b is turned off when the reset signal res is low.

[0096] (8) While the voltage at node N2 is negative, and when the internal power supply 11, the input circuit 12, and the pulse generation circuit 13 are not operating normally, both switching devices 133a and 134a may be turned off. In this case, when the output signal causes the switching device 151a to turn on and the switching device 152a to turn off, the voltage at the output terminal of the set-side pulse generation circuit 13a is clamped by the set-side Zener diode 135a so that the breakdown voltage of the set-side Zener diode 135a is not exceeded. As a result, an overvoltage is not applied to the gate of the set-side level-shift switching device 211a, so that the set-side level-shift switching device 211a can be prevented from being destroyed.Also, when the internal power supply 11, the input circuit 12, and the pulse generation circuit 13 are not operating normally and the switching device 151b is turned on and the switching device 152b is turned off, no overvoltage is applied to the gate of the reset-side level-shift switching device 211b, so that the reset-side level-shift switching device 211b can be prevented from being destroyed.

[0097] (9) The operation delay time of the combination of the buffer circuit 14 and the input control state ensuring circuit 15 is shorter than the operation delay time of the combination of the input circuit 12 and the pulse generating circuit 13. Thus, the voltages at nodes N3 and N4 are affected by the output of the input control state ensuring circuit 15 before the output signal of the pulse generating circuit 13 becomes unstable or indeterminate due to the voltage at node N2 becoming negative. Accordingly, the erroneous operation of the level shift switching devices 211a and 211b can be prevented. <<<5. Modified Examples>>>>

[0098] It should be noted that the above-described embodiments were presented for the purpose of facilitating understanding of the present disclosure and are not intended to interpret the present disclosure in a limiting manner. Furthermore, the present disclosure may be modified or improved without departing from the spirit of the disclosure, and equivalents of the present disclosure are naturally incorporated into the present disclosure.

[0099] For example, the input circuit 12 may include a delay circuit to cause the delay time of the input circuit 12 and the pulse generation circuit 13 to be longer than the delay time of the buffer circuit 14 and the input control state ensuring circuit 15.

Claims

[1] Driver circuit (1) of a power device (51, 52) comprising: an internal power supply (11); a set-side pulse generation circuit (13a) and a reset-side pulse generation circuit (13b) connected to the internal power supply (11) and receiving a logic input signal, wherein the set-side pulse generation circuit (13a) generates a set signal when it detects that the logic input signal changes from a first logic level to a second logic level, wherein the reset-side pulse generation circuit (13b) generates a reset signal when it detects that the logic input signal changes from the second logic level to the first logic level; a set-side level shift circuit (21a) that generates a level-shifted set signal by shifting a level of the set signal; a reset-side level shift circuit (21b) that generates a level-shifted reset signal by shifting a level of the reset signal; a control circuit that turns on the power device (51, 52) in response to the level-shifted set signal and turns off the power device (51, 52) in response to the level-shifted reset signal; and a securing circuit (15) which, based on the logic input signal, secures a first state in which the power device (51, 52) is turned off when the logic input signal is at the first logic level, and ensures a second state in which the power device (51, 52) is turned on when the logic input signal is at the second logic level. [2] Driver circuit (1) according to claim 1, wherein the securing circuit (15) includes: a set-side securing circuit (15a) which pulls down an output voltage of the set-side pulse generating circuit (13a) using a reference potential when the logic input signal is at the first logic level; and a reset-side securing circuit (15b) that pulls down an output voltage of the reset-side pulse generating circuit (13b) using the reference potential when the logic input signal is at the second logic level. [3] Driver circuit (1) according to claim 2, wherein the set-side securing circuit (15a) pulls up the output voltage of the set-side pulse generating circuit (13a) using an external power supply (4) when the logic input signal is at the second logic level, and the reset-side securing circuit (15b) pulls down an output voltage of the reset-side pulse generating circuit (13b) using the external power supply (4) when the logic input signal is at the first logic level. [4] Driver circuit (1) according to claim 3, wherein the setting-side securing circuit (15a) includes: a first switching device (151a) coupled to the external power supply (4), wherein the first switching device (151a) is configured to be switched on when the logic input signal is at the second logic level and switched off when the logic input signal is at the first logic level, and a second switching device (152a) connected in series with the first switching device (151a) via a set-side resistor (153a) between the reference potential and the external power supply (4), wherein the second switching device (152a) is configured to be switched on and off complementarily to the first switching device (151a) based on the logic input signal; and a node between the set-side resistor (153a) and the second switching device (152a) coupled to an output of the set-side pulse generation circuit (13a). [5] Driver circuit (1) according to claim 4, wherein the setting-side pulse generation circuit (13a) contains the following: a set-side edge detection circuit (131a) which detects that the logic input signal changes from the first logic level to the second logic level, a third switching device (133a) coupled to the internal power supply (11), the third switching device (133a) being configured to be switched on and off based on an output signal of the set-side edge detection circuit (131a), and a fourth switching device (134a) connected in series with the third switching device (133a) between the reference potential and the internal power supply (11), wherein the fourth switching device (134a) is configured to be switched on and off complementarily to the third switching device (133a) based on the output signal of the set-side edge detection circuit (131a); and a node (N3) between the third switching device (133a) and the fourth switching device (134a) coupled to the node between the set-side resistor (153a) and the second switching device (152a), wherein the set-side pulse generation circuit (13a) outputs to the set-side level shift circuit (21a) a voltage at the node (N3) between the third switching device (133a) and the fourth switching device (134a) as the set signal. [6] The driver circuit (1) according to claim 5, wherein an on-state resistance value of the third switching device (133a) is smaller than a sum of an on-state resistance value of the first switching device (151a) and a resistance value of the set-side resistor (153a). [7] The driver circuit (1) according to claim 5 or 6, wherein the set-side level shift circuit (21a) includes a set-side level shift switching device (211a) coupled between a high-side power supply (6) and the reference potential, the set-side level shift switching device (211a) being configured to be turned on and off based on the set signal, and the set-side level shift circuit (21a) outputs to the high-side control circuit (22) a voltage at a terminal of the set-side level shift switching device (211a) connected to the high-side power supply (6) as the level-shifted set signal. [8] The driver circuit (1) according to claim 7, wherein the output voltage of the set-side pulse generating circuit (13a) when the first switching device (151a) and the fourth switching device (134a) are turned on and the second switching device (152a) and the third switching device (133a) are turned off is lower than a threshold voltage of the set-side level shift switching device (211a). [9] The driver circuit (1) according to claim 7 or 8, wherein a threshold voltage of the set-side level shift switching device (211a) is greater than a product obtained by multiplying a quotient obtained by dividing an on-state resistance value of the fourth switching device (134a) by a sum of the on-state resistance value of the fourth switching device (134a), a resistance value of the set-side resistor (153a), and an on-state resistance value of the first switching device (151a) by a voltage of the external power supply (4). [10] The driver circuit (1) according to any one of claims 7 to 9, wherein the set-side pulse generating circuit (13a) further comprises a set-side clamping device (135a) that clamps a voltage at the node (N3) between the third switching device (133a) and the fourth switching device (134a) to a voltage lower than a predetermined voltage. [11] Driver circuit (1) according to claim 10, wherein the set-side clamping device (135a) is a set-side Zener diode coupled to the node (N3) between the third switching device (133a) and the fourth switching device (134a) in a reverse-biased manner, the specified voltage is a breakdown voltage of the set-side Zener diode, and a threshold voltage of the set-side level shift switching device (211a) is lower than the breakdown voltage of the set-side Zener diode. [12] Driver circuit (1) according to one of claims 3 to 11, wherein the reset-side securing circuit (15b) includes: a fifth switching device (151b) coupled to the external power supply (4), wherein the fifth switching device (151b) is configured to be switched on when the logic input signal is at the first logic level and switched off when the logic input signal is at the second logic level, and a sixth switching device (152b) connected in series with the fifth switching device (151b) via a reset-side resistor (153b) between the reference potential and the external power supply (4), wherein the sixth switching device (152b) is configured to be switched on and off complementarily to the fifth switching device (151b) based on the logic input signal; and a node between the reset-side resistor (153b) and the sixth switching device (152b) coupled to an output of the reset-side pulse generation circuit (13b). [13] A driver circuit (1) according to claim 12, wherein the reset-side pulse generation circuit (13b) includes: a reset-side edge detection circuit (131b) which detects that the logic input signal changes from the second logic level to the first logic level, a seventh switching device (133b) coupled to the internal power supply (11), wherein the seventh switching device (133b) is configured to be turned on and off based on an output signal of the reset-side edge detection circuit (131b), and an eighth switching device (134b) connected in series with the seventh switching device (133b) between the reference potential and the internal power supply (11), wherein the eighth switching device (134b) is configured to be turned on and off complementarily to the seventh switching device (133b) based on the output signal of the reset-side edge detection circuit (131b); and a node (N4) between the seventh switching device (133b) and the eighth switching device (134b) coupled to the node (N4) between the reset-side resistor (153b) and the sixth switching device (152b), wherein the reset-side pulse generation circuit (13b) outputs to the reset-side level shift circuit (21b) a voltage at the node (N4) between the seventh switching device (133b) and the eighth switching device (134b) as the reset signal. [14] The driver circuit (1) according to claim 13, wherein an on-state resistance value of the seventh switching device (133b) is smaller than a sum of an on-state resistance value of the fifth switching device (151b) and a resistance value of the reset-side resistor (153b). [15] Driver circuit (1) according to claim 13 or 14, wherein the reset-side level shift circuit (21b) includes a reset-side level shift switching device (211b) coupled between a high-side power supply (6) and the reference potential, wherein the reset-side level shift switching device (211b) is configured to be turned on and off based on the reset signal, and the reset-side level shift circuit (21b) outputs to the control circuit a voltage at a terminal of the reset-side level shift switching device (211b) connected to the high-side power supply (6) as the level-shifted reset signal. [16] The driver circuit (1) according to claim 15, wherein the output voltage of the reset-side pulse generating circuit (13b) when the fifth switching device (151b) and the eighth switching device (134b) are turned on and the sixth switching device (152b) and the seventh switching device (133b) are turned off is lower than a threshold voltage of the reset-side level shift switching device (211b). [17] The driver circuit (1) according to claim 15 or 16, wherein a threshold voltage of the reset-side level-shift switching device (211b) is greater than a product obtained by multiplying a quotient obtained by dividing an on-state resistance value of the eighth switching device (134b) by a sum of the on-state resistance value of the eighth switching device (134b), a resistance value of the reset-side resistor (153b), and an on-state resistance value of the fifth switching device (151b) by a voltage of the external power supply (4). [18] The driver circuit (1) according to any one of claims 15 to 17, wherein the reset-side pulse generating circuit (13b) further comprises a reset-side clamping device (135b) that clamps a voltage at the node between the seventh switching device (133b) and the eighth switching device (134b) to a voltage lower than a predetermined voltage. [19] The driver circuit (1) according to claim 18, wherein the reset-side clamping device (135b) further includes a reset-side Zener diode coupled to the node between the seventh switching device (133b) and the eighth switching device (134b) in a reverse-biased manner, the predetermined voltage is a breakdown voltage of the reset-side Zener diode, and a threshold voltage of the reset-side level-shifting switching device (211b) is lower than the breakdown voltage of the reset-side Zener diode.

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