Integrated circuit with a resistor network

Abstract

Integrated circuit in the form of an analog convolution plane of a neural network or an analog matrix multiplier, with at least one resistor network (100) having at least two memory cells (200a, 200d) for storing a resistance characteristic value, each having a first contact pair (104a / 106a, 104a / 106b) connected to a source electrode and a drain electrode of a transistor (201) designed as a field-effect transistor, in which a ferroelectric capacitance (203) is electrically connected in series between the front-gate electrode of the transistor (201) and the second contact (109) of the second contact pair, or of a transistor (201) designed as a ferroelectric field-effect transistor or of a transistor (201) designed as a charge-trap transistor, which is part of one of the memory cells (200a, 200d), and is configured toin at least one operating mode, providing an electrical resistance corresponding to the stored resistance characteristic value, wherein first contacts (104a) of the first contact pair of each of the two memory cells (200a, 200d) are directly connected to each other, and second contacts (106a, 106b) of the first contact pair (104a / 106a, 104a / 106b) of each of the two memory cells (200a, 200d) are electrically independent of each other, wherein the memory cells (200a, 200d) each have a second contact pair (108a / 109a, 108a / 109b) which is connected to a front-gate electrode of the transistor (201) and a back-gate electrode of the transistor (201), is electrically independent of the first contact pair (104a / 106a, 104a / 106b), and which is arranged such that by means of suitable electrical Signals via this second contact pair (108a / 109a, 108a / 109b) allow the stored electrical resistance characteristic of the respective memory cell (200a, 200d) to be reversibly changed,at least the two memory cells (200) are each configured to be able to be switched between at least three different memory states by means of suitable electrical signals via the second contact pair (108 / 109).

Description

[0001] The invention relates to the field of integrated circuits with a resistor network with variable resistances, in particular when used as an analog convolution layer of a neural network and / or as an analog matrix multiplier.

[0002] Resistor networks with variable resistances are known and are used in analog matrix multiplication or as a convolution layer in an analog neural network. These have memory cells, each with a single contact pair, through which both a read and a write operation takes place. A ferroelectric memory in RAM structure is known from WO 00 / 77855 A1. Patent EP 3 382 565 B1 discloses a device with selective noise tolerance that uses a neural network.

[0003] WO 2017 / 151192 A1 deals with a non-volatile memory with temperature monitoring.

[0004] The invention is based on the object of providing a circuit with a flexibly and quickly configurable resistor network.

[0005] This object is achieved according to the invention by the features of the main claim.

[0006] The features contained in the subclaims enable advantageous further developments and improvements.

[0007] The integrated circuit according to the invention has at least one resistance network. The resistance network comprises at least two memory cells, each for storing a resistance characteristic, which each have a first contact pair connected to a source electrode and a drain electrode of a transistor designed as a field-effect transistor, in which a ferroelectric capacitance is electrically connected in series between the front gate electrode of the transistor and the second contact of the second contact pair, of a transistor designed as a ferroelectric field-effect transistor or a charge-trap transistor, which is part of one of the memory cells, and is configured to provide an electrical resistance corresponding to the stored resistance characteristic in at least one operating mode.wherein first contacts of the respective first contact pair of the two memory cells are directly connected to one another, and second contacts of the respective first contact pair of the two memory cells are electrically independent of one another. The memory cells each have a second contact pair that is connected to a front gate electrode of the transistor and a back gate electrode of the transistor, is electrically independent of the first contact pair, and is arranged such that the stored electrical resistance value of the respective memory cell can be reversibly changed by means of suitable electrical signals via this second contact pair. At least two of the memory cells are each configured to be switched between at least three different memory states by means of suitable electrical signals via the respective second contact pair.

[0008] This makes it possible, in particular, to read and / or write memory cells of the resistance network (weight values) independently of one another. Furthermore, it is possible to set weight values ​​while the resistance network is being read virtually simultaneously, i.e., for example, with a delay or a time interval of less than a maximum of 100 µs, for example, less than 10 µs, advantageously less than 1 µs, particularly advantageously less than 100 ns, preferably less than 10 ns.

[0009] A "resistor network" is understood, for example, to be an interconnection of memory cells for storing electrical resistors, which has at least one input contact group with at least one, for example at least two, advantageously at least four, preferably at least eight input contacts (bit line), and at least one output contact group with at least one, for example at least two, advantageously at least four, preferably at least eight output contacts (word line). For example, for each combination of input and output contacts, exactly one memory cell is provided, which connects them to one another by means of their first contact pair.In alternative embodiments, however, it is also possible for the memory elements to be arranged and connected to one another in such a way that they form branched paths between the input contacts and the output contacts, so that at least some of the memory cells each belong to at least two different, in particular shortest, connection paths between different combinations of input and output contacts.

[0010] For example, the first contacts of the first contact pair of the two memory cells are connected to a single / common input contact and the second contacts of the first contact pair are connected to different output contacts.

[0011] In the context of this document, a "memory cell for storing a resistance characteristic value" is to be understood as an electrical assembly that is suitable for providing an electrical resistance corresponding to the resistance characteristic value across the first contact pair as a function of the stored resistance characteristic value. Assigning the resistance characteristic value to the corresponding resistance can be, in particular, solely temperature-dependent. For example, assigning the resistance characteristic value to the corresponding resistance depends on an electrical signal, in particular an electrical voltage, present across the second contact pair. One, in particular a further, memory cell can be configured to be able to assume only a single memory state, in particular at least two, advantageously at least three, preferably at least eight memory states.For example, the memory cell is configured to assume any resistance value on a quasi-continuous or continuous spectrum. Depending on the type of memory cell, the resistance value can be a resistance value, a digital storage value, or an analog storage value. An analog storage value can, for example, be represented by the value of a physical quantity, such as an electrical charge, an electrical polarization, and / or a magnetic polarization. The resistance network can, in principle, be composed of memory cells of different types, for example, from different electrical components and / or with different possible storage states. Advantageously, all memory cells are of the same type, which in particular simplifies production of the resistance network and can enable small dimensions.

[0012] Preferably, at least the two memory cells are configured to store different resistance values ​​in at least one operating state. Advantageously, the memory cells are configured to be switched or switched between different storage states by means of a charge via the second contact pair.

[0013] In particular, the smallest resistance value that can be set / stored in the memory cells is at least 100 Ω, advantageously at least 1 kΩ, particularly advantageously at least 10 kΩ. For example, the largest resistance value that can be set / stored in the memory cell is a maximum of 100 TΩ, in particular a maximum of 10 TΩ, advantageously a maximum of 1 TΩ.

[0014] The term "directly connected" refers in particular to the fact that two contacts are electrically connected to each other, in particular solely via conductive material, regardless of the external wiring state and / or operating mode. In particular, the electrical impedance of a direct connection, preferably frequency-independent, is a maximum of 10 3 V / A, preferably maximum 10 2V / A, preferably a maximum of 20 V / A. In particular, an ohmic resistance between the contacts is less than 100%, in particular less than 10%, advantageously less than 1%, of a smallest electrical resistance that can be set via the memory cells. In particular, a connection between the contacts is free of switching elements that are switched differently depending on the operating state and / or ohmic resistances that are greater than that of a pure connecting line. For example, it is possible to arrange switching elements between the contacts which, however, are always switched to conducting regardless of the operating mode when the resistor network is in operation. The contacts are preferably connected directly to one another by means of metallically conductive material or doped, in particular highly doped, semiconductor material.

[0015] The term "electrically independent" refers in particular to the fact that two contacts are electrically separated from each other in at least one operating state (external wiring state). In particular, an ohmic resistance between the two contacts is greater than 10 3 Ω, preferably greater than 10 5 Ω, preferably greater than 10 7 Ω. It is possible to place a large resistor between the contacts, for example, to divert fault currents. Preferably, at least one area along the shortest electrical path between the two contacts is free of electrically conductive material. Advantageously, the two contacts are not directly connected to each other.

[0016] The fact that the stored electrical resistance value of the respective memory cell is “reversibly changeable” should be understood, for example, to mean that a resistance value can be changed from a first state (a first value) to a second state (a second value), in particular by a first electrical signal or a first electrical signal sequence via the second contact pair, and can be changed from the second state back to the first state by means of a second electrical signal or a second electrical signal sequence via the second contact pair.

[0017] For example, it is possible to adjust resistance values ​​(weights) stored in the two memory cells while an input signal to be evaluated, such as a current or a voltage, is applied to the input contacts and an output signal, such as a current or a voltage, is output via the output contacts. For example, output signals are consistent and / or usable again within less than 1 µs, in particular less than 100 ns, advantageously less than 10 ns, after a disturbance in the resistance network by adjusting one of the stored resistance values. In particular, this allows for high dynamics and / or adaptability to be achieved.

[0018] According to a further embodiment, it is proposed that first contacts of the respective second contact pair of the two memory cells are directly connected to one another and second contacts of the respective second contact pair of the two memory cells are independent of one another.

[0019] For example, the resistor network has at least one selection input group with at least one, for example at least two, advantageously at least four, preferably at least eight selection inputs (source line), and at least one selection output group with at least one, for example at least two, advantageously at least four, preferably at least eight selection outputs (bulk line / main line / return line). For example, for each combination of selection inputs and selection outputs, exactly one memory cell is provided, which connects them to one another via their second contact pair.

[0020] In particular, the first contacts of the second contact pair of the two memory cells are connected to a single / common selection input and the second contacts of the second contact pair are connected to different selection outputs.

[0021] For example, a high degree of independence of the memory cells can be achieved when setting the resistance values.

[0022] In a further embodiment, it is proposed that the resistor network has at least one third memory cell for storing a resistance characteristic value, which has a first contact pair which is designed to provide an electrical resistance corresponding to the stored resistance characteristic value, wherein a first contact of the first contact pair of the third memory cell is independent of the first contacts of the first contact pair of the two memory cells and wherein a second contact of the first contact pair of the third memory cell is directly connected to the second contact of the first contact pair of one of the two memory cells and is independent of the second contact of the first contact pair of the other of the two memory cells.

[0023] A larger number of memory cells allows for greater flexibility in the use of the resistor network. Furthermore, more input contacts can be connected to more output contacts.

[0024] For example, the respective first contacts of the first contact pair of the two memory cells are connected to a different input contact than the first contact of the first contact pair of the third memory cell and the second contact of the first contact pair of the third memory cell is connected to an output contact that is the same as the second contact of the first contact pair of one of the two memory cells, but to a different output contact than the second contact of the first contact pair of the other of the two memory cells.

[0025] Preferably, the respective first contacts of the second contact pair of the two memory cells are connected to a different selection input than the first contact of the second contact pair of the third memory cell, and the second contact of the second contact pair of the third memory cell is connected to a same selection output as the second contact of the second contact pair of one of the two memory cells, but to a different selection output than the second contact of the second contact pair of the other of the two memory cells.

[0026] According to a further embodiment, it is proposed that at least one, advantageously at least a majority, for example at least 80%, advantageously at least 90%, preferably all, of the memory cells, in particular at least the two and for example at least the third memory cell, has or is formed by at least one transistor designed as a ferroelectric field-effect transistor.

[0027] A ferroelectric field-effect transistor is understood to be, for example, a field-effect transistor whose gate insulation to the source-drain channel is formed by a ferroelectric dielectric.

[0028] This makes it possible to achieve a long retention time for the stored values.

[0029] Alternatively or additionally, it is possible for at least one of the memory cells to comprise or be formed by a field-effect transistor and a ferroelectric capacitance, in particular a capacitor with a ferroelectric dielectric, wherein the gate contact of the field-effect transistor is coupled to the ferroelectric capacitance.

[0030] Alternatively or additionally, it is possible that at least one of the memory cells has or is formed by a charge trap transistor.

[0031] Alternatively or additionally, it is possible for at least one of the memory cells to be formed as a group of resistance structures with a selection unit, in particular a selection transistor, wherein the selection unit determines one of the resistance structures that is connected between the first contact pair. According to an alternative, these resistance structures can be combined to form a resulting resistance by suitable connection using the selection unit in series and / or parallel.

[0032] The proposed memory cells can be manufactured using different manufacturing technologies, such as nanosheet technology (nanolayer transistors), GAA technology (gate-all-around transistor), FinFET technology, FDSOI technology (fully depleted silicon on insultor transistor), high-K metal gate technology or polysilicon oxynitride gate technology.

[0033] In a further embodiment, it is proposed that the memory cells are each configured to either provide the electrical resistance corresponding to the stored resistance value (memory cell is activated) or to block it (memory cell is deactivated) depending on a voltage applied across the second contact pair across the first contact pair.

[0034] This makes it possible to provide a flexible resistor network. In particular, the topology of the resistor network can be changed with little effort without losing the memory state of the memory cell.

[0035] The term "blocking" the memory cells above the first contact pair should be understood, for example, to mean that a resistance is provided between the contacts that is at least as great, in particular at least 10 times as great, advantageously at least 1000 times as great, as the maximum resistance that can be provided by the memory cell in an unlocked state due to the different possible resistance values. In particular, the memory cell is in a non-conductive state between the contacts.

[0036] In particular, the memory cells are configured to provide the electrical resistance corresponding to the stored resistance value across the first contact pair when a first voltage is present between the contacts of the second contact pair of the respective memory cell. For example, the memory cells are configured to block the electrical resistance corresponding to the stored resistance value across the first contact pair when at least one second voltage is present between the contacts of the first contact pair, which is of a smaller magnitude and the same polarity as the first voltage or which is of the opposite polarity of the first voltage and of any desired magnitude. For example, the first voltage and the second voltage differ by at least 0.5 V, in particular by at least 1 V. Advantageously, the first voltage and the second voltage differ, in particular at least in their magnitude, from voltages used to change the stored resistance value.

[0037] Furthermore, it is possible that, at least during a read operation via the resistor network, i.e., in particular, when the input contacts are energized, a reference potential of the contacts of the second contact pair is shifted by a reference voltage (bias voltage) relative to a reference potential of the contacts of the first contact pair. This can, for example, ensure reliable operation of resistor networks manufactured in particularly voltage-sensitive technology areas.

[0038] The at least two memory cells are each configured to be switched between at least three, in particular at least eight, different memory states by means of suitable electrical signals via the respective second contact pair. Advantageously, the memory cells are configured to assume quasi-continuous resistance values ​​(memory values).

[0039] In particular, a high degree of flexibility can be achieved in an application of the resistance network.

[0040] It is further proposed that the resistor network have a plurality, for example at least 6, in particular at least 10, advantageously at least 20, preferably at least 60, of further memory cells for storing resistance values, which each have a first contact pair which is designed to provide an electrical resistance corresponding to the stored resistance value in at least one operating mode and which are arranged together with the two memory cells in rows and columns of a grid. For example, the grid has at least 2, in particular at least 4, advantageously at least 8, preferably at least 32 rows. For example, the grid has at least 2, in particular at least 4, advantageously at least 8, preferably at least 32 columns. Advantageously, the number of columns is equal to the number of rows in order to enable high flexibility.Alternatively, the number of columns differs from the number of rows. In particular, each row of the grid is assigned an input contact of the input contact group. For example, each column of the grid is assigned an output contact of the output contact group. Each column of the grid can be assigned a selection input of the selection input group. For example, each column of the grid is assigned a selection output of the selection output group. Advantageously, the resistor network has at least one memory cell for each combination of columns and rows of the grid, which connects the input and output contacts corresponding to the columns and rows by means of their respective first contact pair and / or which connects the selection inputs and selection outputs corresponding to the columns and rows by means of their respective second contact pair.

[0041] In particular, by appropriately controlling the selection inputs and / or selection outputs, in particular activation and / or deactivation of the memory cells, an adaptation of the topology and / or the dimension of the matrix given by the grid can be achieved, wherein, for example, one or more entire rows and / or one or more entire columns of memory cells are excluded from an evaluation (transformation of the input signals into output signals).

[0042] In further embodiments, it is possible that at least some of the grid positions (combinations of columns and rows) are free of memory cells.

[0043] This makes it possible, for example, to carry out complex and / or extensive operations with the resistance network.

[0044] Furthermore, an integrated circuit, in particular an analog convolution layer of a neural network or an analog matrix multiplier, is proposed, which has at least one resistance network according to the invention.

[0045] Resistor networks according to the invention are particularly suitable for analog convolution and / or matrix multiplication, where matrix factors and / or weights change little or not at all between repeated applications. In particular, significant digital computing power can be saved.

[0046] For example, the integrated circuit comprises at least one analog-to-digital converter configured to convert analog output signals at the output contacts of the resistor network into digital signals / data. For example, the integrated circuit comprises at least one digital-to-analog converter configured to convert digital input signals into analog input signals and to route them to the input contacts of the resistor network.

[0047] For example, the integrated circuit has at least one further resistance network, wherein output contacts of the (first) resistance network are connected, in particular directly, to input contacts of the second resistance network, wherein at least one of the resistance networks deviates from a grid-shaped configuration in each case.

[0048] It is advantageously proposed that the integrated circuit has a first selection unit which is connected to the first contacts of the respective second contact pair of the memory cells and is designed to connect a subset of the first contacts to a first activation contact and to connect a complementary set of the first contacts to a first deactivation contact as a function of a specification.

[0049] For example, it is proposed that the integrated circuit has a second selection unit which is connected to the second contacts of the respective second contact pair of the memory cells and is designed to connect a subset of the second contacts to a second activation contact and to connect a complementary set of the second contacts to a second deactivation contact as a function of a specification.

[0050] For example, at least in one selection operating mode, an electrical potential applied to the first activation contact is lower than an electrical potential applied to the second deactivation contact. At least in one selection operating mode, an electrical potential applied to the second activation contact can be lower than an electrical potential applied to the first activation contact. In particular, at least in one selection operating mode, an electrical potential applied to the first deactivation contact is lower than an electrical potential applied to the second activation contact. Depending on the technical / structural implementation (in particular doping) of the memory cells, it is possible that the order of the potentials of the activation and deactivation contacts is reversed.In particular, a potential difference between the activation contacts of the two selection units is selected such that an activation voltage of between 0 V and 1 V, in particular of 0.5 V, drops across the contacts of the memory cells connected to the activation contacts. In particular, a potential difference between the respective activation contact of one selection unit and the respective deactivation contact of the other selection unit is selected such that a deactivation voltage of between 0.3 V and 1.5 V, in particular between 0.5 V and 1 V, in particular of 0.75 V, drops across the memory cells connected to these contacts. In particular, a potential difference between the respective deactivation contacts of the two selection units is selected such that a voltage of a maximum of 5 V, in particular a maximum of 4 V, advantageously a maximum of 3 V, preferably a maximum of 2 V, drops across the correspondingly connected memory cells.In particular, the potential differences at the activation and deactivation contacts are selected to be higher (for example, by up to 15 V) than the target voltages that are ultimately to be applied to the memory cells in order to compensate for increased conduction resistances, in particular due to conduction through doped substrates.

[0051] For example, the first selection unit is configured, at least in a set operating mode, to connect a subset of the first contacts of the second contact pair of the memory cells to a first set contact. The second selection unit can be configured, at least in a set operating mode, to connect a subset of the second contacts of the second contact pair of the memory cells to a second set contact. In particular, the set contacts are identical to the respective activation contact or to the respective deactivation contact. Alternatively, it is possible for the respective set contact to be independent of the respective activation contact and the respective deactivation contact. In particular, the set contacts are configured to deliver electrical signals for changing the memory states of the memory cells.

[0052] A “complementary set of the first / second contacts” should be understood here, for example, as the subset of the first / second contacts that are not connected to the first / second activation contact and, for example, are also not connected to the first setting contact.

[0053] In particular, the selection unit comprises at least one group of switching elements, each of which is configured to connect the selection inputs of the resistance network independently of one another either to the activation contact or to the deactivation contact, depending on a control signal.

[0054] It is further proposed that the integrated circuit comprise at least one temperature sensor configured to monitor a temperature of the resistor network, and that the integrated circuit comprise at least one control unit configured to adapt stored resistance values ​​of the memory cells of the resistor network to a changed temperature. For example, electrical resistances corresponding to the stored resistance values ​​are temperature-dependent.For example, the actuating unit is configured, particularly after a temperature change has been detected, to adjust stored resistance values ​​of the storage elements such that a resulting new resistance assigned to the new resistance value at least substantially corresponds to an old resistance corresponding to the old resistance value before the temperature change, i.e., in particular, is at least closer to the old resistance than the resistance adjusted by the changed temperature corresponding to the old resistance value. In particular, the new resistance deviates from the old resistance by a maximum of 10%, advantageously a maximum of 5%, preferably a maximum of 2%. In particular, resulting resistances of the storage cells are kept temperature-independent by changed stored resistance values.Alternatively, the integrated circuit is configured to adjust the stored resistance values ​​upon a temperature change such that their relationships to one another are kept at least substantially constant, i.e., with a maximum deviation of 10 percent of the original value. Alternatively, the output signal of the word line can also be adjusted. A ferroelectric field-effect transistor can preferably be used for this purpose.

[0055] In particular, high temperature stability can be achieved.

[0056] Embodiments of the invention are illustrated in the drawings and are described below with reference to Fig. 1 to 8 are explained in more detail. They show: Fig. 1 a schematic representation of a section of a resistor network with memory cells; Fig. 2 shows an embodiment of a memory cell of a resistor network; Fig. 3 an alternative embodiment of a memory cell of a resistor network; Fig. 4a)- c) Characteristics of a memory cell of a resistor network; Fig. 5 a schematic 3D representation of an implementation of a resistor network; Fig. 6 a first sectional view through the resistance network along a section plane A in Fig. 5; Fig. 7 a second sectional view through the resistance network along a section plane B in Fig. 5; and Fig. 8 a schematic representation of an integrated circuit with a resistor network.

[0057] Fig. Figure 1 shows a section of a resistor network 100 with a plurality of memory cells 200. The section comprises nine memory cells 200, each for storing a resistance characteristic. The memory cells 200 each have a first contact pair configured to provide an electrical resistance corresponding to the stored resistance characteristic in at least one operating mode.

[0058] The memory cells 200 are arranged in a grid. The grid has 32 rows and 32 columns, although networks of any size are possible. The grid in the section shown has 3 rows and 3 columns.

[0059] First contacts 104a, 104b, and 104c of the first contact pair of memory cells 200a, 200d, 200g, 200b, 200e, 200h, and 200c, 200f, 200i, respectively, arranged in the same row, are each connected to one another. The first contacts 104a, 104b, and 104c each form an input contact of an input contact group 105.

[0060] Second contacts 106a, 106b, 106c of the first contact pair of the memory cells 200a, 200d, 200g, 200b, 200e, 200h, 200c, 200f, 200i, which are arranged in a same row, are each electrically independent of each other.

[0061] The memory cells 200 each have a second contact pair that is electrically independent of the first contact pair. The second contact pair is arranged such that the stored electrical resistance value of the respective memory cell 200 can be reversibly changed by means of suitable electrical signals.

[0062] First contacts 108a, 108b, and 108c of the second contact pair of memory cells 200a, 200d, 200g, 200b, 200e, 200h, and 200c, 200f, 200i, respectively, arranged in the same row, are each connected to one another. The first contacts 108a, 108b, and 108c each form a selection input of a selection input group 110.

[0063] Second contacts 109a, 109b, and 109c of the second contact pair of memory cells 200a, 200d, 200g, 200b, 200e, 200h, and 200c, 200f, 200i, respectively, arranged in the same row, are each electrically independent of one another. The second contacts 109a, 109b, and 109c each form a selection output of a selection output group 120.

[0064] First contacts 104a, 104b, and 104c of the first contact pair of memory cells 200a, 200b, 200c, 200d, 200e, 200f, and 200g, 200h, 200i, respectively, which are arranged in the same column, are each electrically independent of one another. The first contacts 104a, 104b, and 104c each form an output contact of an input contact group 105.

[0065] Second contacts 106a, 106b, and 106c of the first contact pair of memory cells 200a, 200b, 200c, 200d, 200e, 200f, and 200g, 200h, 200i, respectively, arranged in the same row, are each connected to one another. The second contacts 106a, 106b, and 106c each form an output contact of an output contact group 107.

[0066] First contacts 108a or 108b or 108c of the second contact pair of the memory cells 200a, 200b, 200c, or 200d, 200e, 200f, or 200g, 200h, 200i, which are arranged in a same column, are each electrically independent of each other.

[0067] Second contacts 109a, 109b, and 109c of the second contact pair of memory cells 200a, 200b, 200c, 200d, 200e, 200f, and 200g, 200h, 200i, respectively, arranged in the same row, are each connected to each other. The first contacts 109a, 109b, and 109c each form a selection input of a selection input group 110.

[0068] The memory cells 200 are each configured to either provide or block the electrical resistance corresponding to the stored resistance value across the first contact pair, depending on a voltage applied across the second contact pair.

[0069] In Fig. Figure 2 shows an electrical diagram of the memory cells 200 of the resistor network 100. The memory cells 200 each have a transistor 201 embodied as a ferroelectric field-effect transistor (FeFET). Recurring features are provided with identical reference numerals in this figure as well as in the following figures. A back-gate electrode of the transistor 201 forms the first contact 108 of the second contact pair of the memory cell 200. A front-gate electrode of the transistor 201 forms the second contact 109 of the second contact pair of the memory cell 200. The source and drain electrodes of the transistor 201 form the first and second contacts 104, 106 of the first contact pair, respectively.

[0070] According to an alternative embodiment, the transistor 201 is formed by a charge trap transistor instead of a ferroelectric field effect transistor.

[0071] Fig. 3 illustrates an electrical diagram of an alternative embodiment of the memory cells 200. The memory cell 200 comprises a transistor 201 embodied as a field-effect transistor. Furthermore, the memory cell 200 comprises a ferroelectric capacitance 203, which is electrically arranged or connected in series between the front gate electrode of the transistor 201 and the second contact 109 of the second contact pair. A back gate electrode of the transistor 201 forms the first contact 108 of the second contact pair of the memory cell 200. The source and drain electrodes of the transistor 201 each form the first and second contacts 104, 106 of the first contact pair. Alternatively, it is also possible for the ferroelectric capacitance to be arranged between the back gate electrode of the transistor 201 and the first contact of the second contact pair.

[0072] In Fig. 4, an upper diagram a) and a middle diagram b) show a set of characteristic curves of the memory cells 200 designed as ferroelectric field-effect transistors. A source-drain current I d depending on a gate-bulk voltage V gfor different storage states of the memory cell 200. The variable resistance characteristic is the electrical polarization of the ferroelectric material. By means of suitable electrical signals via the second contact pair, the memory cell 200 can be switched between a multitude of values ​​across a quasi-continuous spectrum. The signals for changing the stored resistance characteristic are designed as pulses or pulse sequences. The extent to which the resistance characteristic changes as a result of a pulse depends in particular on the pulse amplitude, the pulse duration, and the pulse frequency. In the lower diagram c), for example, the source-drain current I dacross the memory cell 200 as a function of a number N of pulses applied. Diagrams a) and b) differ in that the pulses have reversed polarity and thus (with each additional pulse) the resistance characteristic and thus the characteristic curve changes in a different direction. Using a signal pulse or a signal pulse sequence, the state of the FeFET can be changed step by step from one extreme state to another. The amplitude of this pulse is greater than the read voltage of the FeFET. Furthermore, there are several possibilities for this pulse sequence. Three example possibilities are the repeated sequence of identical pulses, repeated sequence with a change in the pulse width, and repeated sequence with a change in the pulse amplitude.

[0073] When using a ferroelectric field-effect transistor (FeFET), the activation and deactivation potentials (voltages) in the resistor network can be determined based on the two extreme states, each characterized by a rectified polarization along the gate stack. The activation or read voltage of the source lines (difference between the first and second activation potential) should be in the range where the difference in the transfer characteristics of the two states is large (in the given example, the Fig. 4 about 0.5V), but at the same time this voltage should be chosen as low as possible in order to avoid disturbing the state of this memory cell or other memory cells.

[0074] The deactivation voltage of the bulk and source lines should each be selected in a range where the current of both transfer curves is low or negligible. At the same time, the voltage should be selected as close as possible to the read voltage to avoid disturbance of the states due to an increased voltage in areas where both the source and bulk lines see the deactivation voltage. Furthermore, it should be noted that in the case of the bulk lines, a large portion of the voltage does not drop across the transistor. Therefore, the deactivation voltage must be selected so that the voltage drop across the transistor is sufficient for switch-off. If it is not possible to conduct such a high voltage across the bulk lines in the selected technology node, this can be compensated for by a bias voltage applied to both the source and bulk lines.It should be noted that the bias voltage of the source and bulk lines is different and must be selected so that the voltage drop across the transistor does not change.

[0075] Fig. Figure 5 shows, in a schematic three-dimensional representation, the topology of an implementation of a resistor network according to the invention on a semiconductor substrate 202. The semiconductor substrate 202 is divided into columns by shallow trenches 231a, 231b and into rows by deep trenches 230a, 230b, 230c. The deep trenches 230a, 230b, 230c are formed as double trenches, so that each row is surrounded by its own pair of deep trenches 230a, 230b, 230c. In each cell region corresponding to a row-column combination, a memory cell 200a, 200b, 200c, 200d, 200e, 200f is formed in and on the semiconductor substrate 202. The cell regions each have a size of approximately 300 nm by 300 nm. In each cell region, a front gate insulation made of ferroelectric dielectric 210a, 210d is applied to the semiconductor substrate 202 between and partially over two similarly doped source / drain regions 204a, 206a and 204d, 210b of the cell region (see FIG.. Fig. 6 and Fig. 7). Since the source and drain of a FET are topologically interchangeable, regions that can function as source or drain regions are referred to as source / drain regions in this description - it is assumed here that a FET has two source / drain regions, and that one of these regions ultimately serves as the source and the other as the drain.

[0076] The front gate insulations of the memory cells 200a, 200b, 200c and 200d, 200e, 200f of a same column are each arranged such that front gate electrodes arranged thereon are contacted by means of a first linear conductor track in a first conductor layer level and vias. The first conductor track, together with the front gate electrode and the vias, forms the second contact 109a and 109b of the second contact pair. First source / drain regions 204a of the memory cells 200a, 200b, 200c and 200d, 200e, 200f arranged in a same column are each contacted per column by a second linear conductor track and vias. The second conductor track is routed parallel to the first conductor track and in the first conductor layer level, or alternatively in a further conductor layer level. Second source / drain regions 206a, 206d of the memory cells 200a, 200d, or 200b, 200e, respectively, arranged in the same row.200c, 200f are each connected per row by a third straight track and vias. The third tracks are routed orthogonally skew to the first tracks in a second conductor layer level. The third tracks are routed orthogonally skew to the second tracks. The first, second, and third tracks form a crossbar array.

[0077] The semiconductor substrate 202 has a basic doping 208a, 208b, 208c between the deep trenches 230a, 230b, 230c of a row. The basic doping 208a, 208b, 208c extends beneath the shallow trenches 231a, 231b. The basic doping 208a, 208b, 208c of a row forms a back-gate contact of the transistor for each memory cell 200a, 200d, or 200b, 200e, or 200c, 200f of the row. The basic doping 208a, 208b, 208c is interrupted by the deep trenches 230a, 230b, 230c, so that the basic dopings 208a, 208b, 208c of the different rows are electrically isolated from each other. The deep trenches 230a, 230b, 230c extend somewhat deeper into the semiconductor substrate 202 than the basic doping 208a, 208b, 208c. Additionally, the semiconductor substrate 202 is undoped in a region between the deep trenches 230a, 230b, 230c of different rows, or alternatively, doped opposite to the basic doping 208a, 208b, 208c.Instead of double trenches, it is alternatively possible for the deep trenches to extend significantly further into the substrate than the basic doping 208a, 208b, 208c.

[0078] At one edge of the grid, the basic doping 208a, 208b, 208c of each row is contacted via front-side electrodes with fourth conductive tracks arranged in the first or, alternatively, the second or, alternatively, the further conductive layer level. The fourth conductive tracks form the first contact 108a, 108b, 108c, respectively, of the second contact pair of the memory cells 200a, 200d, 200b, 200e, 200c, 200f, respectively.

[0079] As in Fig. 6, a first sectional view of the topology of the resistor network along section plane A, the basic doping 208a, 208b, 208c at the beginning and at the end of a row is also separated from the rest of the semiconductor substrate 202 by a deep trench 230a, 230b, 230c. The basic doping 208a, 208b, 208c is surrounded by the deep trench 230a, 230b, 230c. Furthermore, as in Fig. 6, an additional shallow trench may be provided between a contact surface of the back-gate contact and a contact surface of the first source / drain region 204a. Regardless of the fact that in Fig. 6 shows only two memory cells in a row, any number of memory cells can be provided per row. The basic doping 208a, 208b, 208c extends accordingly far (to the left) without being interrupted by deep trenches.

[0080] A further sectional view of the topology of the resistance network along the section plane B is shown in Fig. 7 shown.

[0081] In Fig. 8 shows an integrated circuit 300 according to the invention, in particular an analog convolution layer of a neural network or an analog matrix multiplier, with a resistor network 100 according to the invention.

[0082] The integrated circuit 300 has a first selection unit 310, which is connected to the first contacts 108 of the second contact pair of the memory cells 200 and is designed to connect a subset of the first contacts 108 to a first activation contact and to connect a complementary set of the first contacts 108 to a first deactivation contact depending on a specification 342.

[0083] The integrated circuit 300 has a second selection unit 320, which is connected to the second contacts 109 of the second contact pair of the memory cells 200 and is designed to connect a subset of the second contacts 109 to a second activation contact and to connect a complementary set of the second contacts 109 to a second deactivation contact depending on the specification 342.

[0084] The integrated circuit 300 has an actuating unit 340 configured to generate specifications 342 for the selection units 310, 320. The actuating unit 340 is configured to generate electrical signals that are transmitted by means of the selection units 310, 320 to certain of the memory cells 200 of the resistor network 100 (e.g., to individual ones or to all of them) at second contacts 108, 109 of the memory cells 200 in order to change a respectively stored resistance value or storage state of the memory cells 200. The actuating unit 340 is configured to provide different potentials that are conducted to the second contact pair of the memory cells 200 by means of the first and second activation and deactivation contacts of the selection units 310, 320.

[0085] For example, each selection input of resistor network 100 can be connected to the first activation contact to supply an activation potential to the first contacts 108 of the second contact pairs, and each selection output of resistor network 100 can be connected to the second activation contact to supply an activation potential (e.g., a ground potential or a reference potential (bias)) to the second contacts 109 of the second contact pair, so that all memory cells 200 of resistor network 100 are active. If an input signal 350 (input signal) is applied via each of the input contacts (bit lines), an output signal 352 can be taken from all output contacts. The states of the memory elements are retained (i.e., are not lost).

[0086] In a further operating variant, it is possible for the memory cells 200 of selected columns to be deactivated. For example, if only the memory cells 200g, 200h, 200i of the third column are to be deactivated, the associated second contacts 109c of the second contact pair (i.e., the third selection output) are connected to the second deactivation contact and thus to a second deactivation potential by means of the second selection unit 320, while the associated second contacts 109a, 109b of the remaining memory cells 200a, 200b, 200c, and 200d, 200e, 200f are connected to the second activation contact. If an input signal 350 is now applied to all input contacts, a third output contact (Wordline) remains without a signal, regardless of the resistance values ​​stored in the memory cells 200, since the memory cells 200a, 200b, 200c of the third column are blocked.It is also possible to deactivate multiple columns of the resistor network 100 by connecting the corresponding bulk lines to the second deactivation potential. The states of the memory elements are retained (i.e., are not lost).

[0087] Furthermore, it is possible for the memory cells 200 of selected rows to be deactivated. For example, if the memory cells 200c, 200f, 200i of the third row are to be deactivated, the associated first contacts 108c of the respective second contact pair (i.e., the third selection input) are connected to the first deactivation contact and thus to a first deactivation potential by means of the first selection unit 310, while the associated first contacts 108a, 108b of the remaining memory cells 200a, 200d, 200g, and 200b, 200e, 200h are connected to the first activation contact. If input signals 350 are now applied to all input contacts, the output signals 352 at the output contacts remain independent of an input signal 350 at the third input contact (regardless of the resistance values ​​stored in the memory cells 200), since the memory cells 200a, 200d, 200g of the third row are blocked.It is also possible to deactivate multiple rows of the resistor network 100 by connecting the corresponding source lines to the first deactivation potential. The states of the memory elements are retained (i.e., are not lost).

[0088] Furthermore, it is possible for several rows and / or several columns to be deactivated simultaneously, so that only partial areas, down to individual memory cells 200, of the resistor network 100 are active. In this way, it is possible to read out individual memory cells 200. In order to control a selected, contiguous area in the resistor network, the respective deactivation voltage (deactivation potential) of the source lines or bulk lines can be applied to all unused lines. The remaining resistor network can be operated independently of the other lines like a standalone network. The states of the deactivated memory elements are retained and therefore not lost. To read out the state of an individual memory cell, the respective activation voltage is applied to the source or bulk line connected to the memory element.All other lines are connected to the corresponding deactivation voltages (deactivation potentials). By applying a readout or input signal to the corresponding bit line of the memory element (memory cell), the output signal can be read out on the connected word line and compared with the associated state. In an analogous case, instead of the activation voltage, the signal for changing the memory state can also be applied to the source line in the form of a pulse. This makes it possible to change the state of an individual memory element without causing interference with the other memory elements.

[0089] The integrated circuit 300 includes a temperature sensor 344 configured to monitor a temperature of the resistor network 100. The control unit 340 is configured to adapt stored resistance values ​​of the memory cells 200 of the resistor network 100 to a changed temperature.

[0090] The actuating unit 340 has a cycle counter 346 and a refresh unit 348. The cycle counter 346 monitors how many input signals have been passed through the input contact group 105 and the resistor network 100. The refresh unit 346 is configured to clear the resistor network 100 and reset the stored values ​​of the memory cells 200 (weight values) after a predetermined / determinable number of input signals has been reached.

[0091] The resistor network 100 weights the input signals 350 according to the electrical resistances or weights provided by the memory cells 200 and combines them according to a matrix multiplication to form output signals 352.

[0092] Weights of the storage cells 200 are set by the actuating unit 340 based on external specifications 345.

[0093] Furthermore, the integrated circuit 300 has a digital-to-analog converter 351 which is configured to convert digital input signals 350 into analog input signals and to forward them to the input contact group 105.

[0094] Furthermore, the integrated circuit 300 has an analog-to-digital converter 353 which is configured to convert the analog output signals at the contacts of the output contact group 107 into digital output signals 352.

[0095] Depending on the application, the converters 351, 353 can also be omitted.

[0096] Read and write accesses are therefore completely separated. The first contact pairs are used for reading, i.e., the analog calculation of vector-matrix multiplication or convolution operations. The second contact pairs are used for writing the resistance values ​​or weight values. Furthermore, the second contact pairs are used for the targeted deactivation / activation of the respective memory element.

[0097] The project leading to this application has received funding from the ECSEL Joint Undertaking (JU) under grant agreement No. 826655. The JU receives support from the European Union's Horizon 2020 research and innovation program and from Belgium, France, Germany, the Netherlands, and Switzerland.

Claims

[1] Integrated circuit in the form of an analog convolution layer of a neural network or an analog matrix multiplier, with at least one resistance network (100) with at least two memory cells (200a, 200d) for storing a resistance characteristic value each, which each have a first contact pair (104a / 106a, 104a / 106b) which is connected to a source electrode and a drain electrode of a transistor (201) designed as a field-effect transistor, in which a ferroelectric capacitor (203) is electrically connected in series between the front gate electrode of the transistor (201) and the second contact (109) of the second contact pair, or of a transistor (201) designed as a ferroelectric field-effect transistor or of a transistor (201) designed as a charge-trap transistor, which is part of one of the memory cells (200a, 200d), and is designed to is,to provide an electrical resistance corresponding to the stored resistance value in at least one operating mode, wherein first contacts (104a) of the respective first contact pair of the two memory cells (200a, 200d) are directly connected to one another and second contacts (106a, 106b) of the respective first contact pair (104a / 106a, 104a / 106b) of the two memory cells (200a, 200d) are electrically independent of one another, wherein the memory cells (200a, 200d) each have a second contact pair (108a / 109a, 108a / 109b) which is connected to a front gate electrode of the transistor (201) and a back gate electrode of the transistor (201), is electrically independent of the first contact pair (104a / 106a, 104a / 106b) and is arranged such that by means of suitable electrical signals via this second contact pair (108a / 109a, 108a / 109b) the stored electrical resistance value of the respective memory cell (200a, 200d) can be reversibly changed,at least the two memory cells (200) are each configured to be switched between at least three different memory states by means of suitable electrical signals via the respective second contact pair (108 / 109). [2] Integrated circuit according to claim 1, characterized by that first contacts (108a) of the respective second contact pair of the two memory cells (200a, 200d) are directly connected to one another and second contacts (109a, 109b) of the respective second contact pair (108a / 109a, 108a / 109b) of the two memory cells (200a, 200d) are independent of one another. [3] Integrated circuit according to claim 1 or 2, characterized byat least one third memory cell (200b) for storing a resistance characteristic value, which has a first contact pair (104b, 106a) which is designed to provide an electrical resistance corresponding to the stored resistance characteristic value, wherein a first contact (104b) of the first contact pair of the third memory cell is independent of the first contacts (104a) of the first contact pair (104a / 106a, 104a / 106b) of the two memory cells (200a, 200d) and wherein a second contact (106a) of the first contact pair of the third memory cell (200b) is directly connected to the second contact (106a) of the first contact pair (104a / 106a) of one of the two memory cells (200a) and is independent of the second contact (106b) of the first contact pair of the other of the two memory cells (200b). [4] Integrated circuit according to claim 1 to 3, characterized bythat the memory cells (200) are each configured, depending on a voltage applied across the second contact pair (108 / 109), to either provide the electrical resistance corresponding to the stored resistance characteristic value across the first contact pair (104 / 106) or to block it. [5] Integrated circuit according to one of claims 1 to 4, characterized by a plurality of further memory cells (200b, 200c, 200e, 200f, 200g, 200h, 200i) for storing resistance values, each having a first contact pair (104 / 106) which is designed to provide an electrical resistance corresponding to the stored resistance value in at least one operating mode and which are arranged together with the two memory cells (200a, 200d) in rows and columns of a grid. [6] Integrated circuit according to claim 1, characterized bya first selection unit (310) which is connected to the first contacts (108) of the second contact pair (108 / 109) of the memory cells (200) and is designed to connect a subset of the first contacts (108) to a first activation contact and to connect a complementary set of the first contacts (108) to a first deactivation contact depending on a specification (342). [7] Integrated circuit according to claim 1, characterized by at least one temperature sensor (344) configured to monitor a temperature of the resistance network (100), and at least one actuating unit (340) configured to adapt stored resistance values ​​of the memory cells (200) of the resistance network (200) to a changed temperature.

Images