Power semiconductor device and manufacturing process for this

Abstract

comprising a power semiconductor device: • a heat radiating plate (1); • an insulating substrate (3) which is connected in a connection region (12) on an upper surface of the heat-radiating plate (1) by means of a connecting material (2) which contains a plurality of elements with different solidification points; • a semiconductor element (5) mounted on an upper surface of the insulating substrate (3); and • a metal wire (8w) which is connected in the connection region (12) on the upper surface of the heat radiating plate (1) such that the metal wire (8w) surrounds the semiconductor element (5) in a top view.

Description

Background of the invention; Field of the invention

[0001] The present invention relates to the suppression of a shrinkage cavity in a power semiconductor device. Description of the state of the art

[0002] A shrinkage cavity in an interconnect material within a power semiconductor device posed a problem. When the solidification points of the multiple elements contained in an interconnect material differ, and an earlier solidified element is pulled through a later solidified metal, a crack forms. This phenomenon is called a shrinkage cavity. In a lead-free solder, for example, which contains tin as the main component, the pure tin solidifies earlier at 232°C, and subsequently, the eutectic component of the additive element solidifies later. For example, tin-ag-copper solidifies at 217°C. Metal shrinks upon solidification, tin solidifies earlier, is pulled, and cracks occur. Not only does the creation of the shrinkage cavity affect heat dissipation, but a wire interconnect failure, such as a chip crack, is caused by the creation of the shrinkage cavity during wire joining.For this reason, suppression of a shrinkage cavity is necessary.

[0003] Japanese patent JP 5665786 B2 discloses a method for suppressing a shrinkage cavity by subjecting a back copper pattern of an insulating substrate to a depression processing. However, the depressions created by the method of Japanese patent JP 5665786 B2 form vacancies, and insulation is not ensured. Furthermore, in a case where the semiconductor element is placed on depressions due to design constraints regarding the layout of the semiconductor element (chip), the heat dissipation effect of the semiconductor element is reduced by the vacancies. Therefore, the problem is that depressions for suppressing a shrinkage cavity cannot be provided in the outer edge region of the semiconductor element.Additionally, it is necessary that the semiconductor element be placed away from the outer edge region of the insulating substrate, which impairs the degree of freedom in the design.

[0004] Publication JP 2019-110 317 A discloses a power semiconductor unit comprising an insulating substrate with a conductive layer at least on a front surface of the insulating substrate, a wire protrusion arranged on the conductive layer, a semiconductor element placed on the wire protrusion, and a solder layer for bonding the conductive layer and the semiconductor element to the conductive layer, and / or a base plate, a plurality of wire protrusions arranged on the base plate, an insulating substrate placed on the wire protrusions and having a conductive layer at least on a rear surface of the insulating substrate, and a solder layer for bonding the conductive layer of the insulating substrate to the base plate, wherein an alloy consisting of a material of the wire protrusions and a material of the solder layer,is formed at an interface between each of the wire protrusions and the solder layer.

[0005] Document US 2016 / 0113107A1 describes a power module comprising a substrate, a power chip, an interconnect, and at least one spacer. The substrate contains a circuit-structured layer. The power chip is connected to the circuit-structured layer by the interconnect. The spacer is located between the circuit-structured layer and the power chip to keep the power chip away from the circuit-structured layer.

[0006] The publication JP H11-186 331 A discloses a semiconductor device that standardizes the thickness of a solder joint between an insulating substrate and a metal plate. The insulating substrate and the metal plate are joined via the solder joint. This creates several protrusions that regulate the thickness of the solder joint. The protrusions consist of a non-solderable material. In a power module, a chip is soldered onto an insulating substrate, which in turn is fixed to a copper plate. An aluminum nitride conductor layer with copper patterns is located between the copper plate and the chip. A protrusion made of a non-solderable metal wire segment is formed in a solder joint connecting the aluminum nitride to the copper plate.The projection and the resulting cavity are formed at a desired location, and the projection is metal-bonded to the copper plate via a metal connection. Summary

[0007] The technology of the present invention consists of suppressing a shrinkage cavity without affecting the layout or insulation performance of the semiconductor element in a power semiconductor device.

[0008] The problem underlying the invention is solved according to the invention in a power semiconductor device by the features of claim 1 and in a manufacturing method for a power semiconductor device by the features of claim 5. Advantageous embodiments are the subject of the respective dependent claims.

[0009] The power semiconductor device according to the present invention comprises a heat-radiating plate, an insulating substrate, and a semiconductor element. The insulating substrate is attached in a connection region on an upper surface of the heat-radiating plate by means of a bonding material having a plurality of elements with different solidification points. The semiconductor element is mounted on the upper surface of the insulating substrate. A metal wire is connected in the connection region on the upper surface of the heat-radiating plate, such that the metal wire surrounds the semiconductor element in a top view.

[0010] According to the power semiconductor device of the present invention, the expansion of the shrink cavity is suppressed because the interfacial tension in the bonding material in contact with the heat sink plate and the metal wire is a force in the opposite direction to the shrinking force of the bonding material, which expands the shrink cavity. As a result, the shrink cavity is prevented from expanding directly beneath the semiconductor element; therefore, the wire connection is properly formed on the upper surface of the semiconductor element. Furthermore, no depressions are formed on the insulating substrate; therefore, the degrees of freedom regarding the layout or the insulating performance of the semiconductor element are not affected.

[0011] The manufacturing process of the power semiconductor device of the present invention comprises connecting a metal wire to an upper surface of a heat-radiating plate, connecting an insulating substrate to an upper surface of the heat-radiating plate by means of a solder containing a plurality of elements with different solidification points, and mounting a semiconductor element on an upper surface of the insulating substrate, in which the metal wire is connected in a connection region which is connected to the insulating substrate on the upper surface of the heat-radiating plate, such that the metal wire surrounds the semiconductor element in a top view.

[0012] According to the manufacturing process of the power semiconductor device of the present invention, the shrinkage cavity is prevented from expanding directly beneath the semiconductor element; therefore, the wire connection is properly formed on the upper surface of the semiconductor element. Furthermore, no depressions are formed on the insulating substrate; therefore, the degrees of freedom with respect to the layout or the insulating performance of the semiconductor element are not affected.

[0013] These and other tasks, features, aspects and advantages of the present invention will become clearer with reference to the following detailed description of the present invention in conjunction with the accompanying figures. Brief description of the characters Fig. 1A and Fig. 1B are configuration diagrams of a power semiconductor device of an underlying technology; Fig. Figure 2 is a cross-sectional view illustrating the power semiconductor device of the underlying technology, in which depressions are formed on a metal pattern of a lower surface of an insulating substrate; Fig. Figure 3 is a cross-sectional view illustrating a power semiconductor device according to embodiment 1. Fig. 4A and Fig. 4B are diagrams illustrating a manufacturing process of the power semiconductor device according to embodiment 1; Fig. 5A and Fig. 5B are diagrams illustrating a manufacturing process of the power semiconductor device according to embodiment 1; Fig. 6A and Fig. Figure 6B shows diagrams illustrating a manufacturing process of the power semiconductor device according to embodiment 1; Fig. 7A and Fig. Figure 7B shows diagrams illustrating a manufacturing process of the power semiconductor device according to embodiment 1; Fig. 8A and Fig. Figure 8B shows diagrams illustrating a manufacturing process of the power semiconductor device according to embodiment 1; Fig. 9A and Fig. Figure 9B are diagrams illustrating a manufacturing process of the power semiconductor device according to embodiment 1; Fig. 10A and Fig. Figure 10B shows diagrams illustrating a manufacturing process of the power semiconductor device according to embodiment 1; Fig. Figure 11 is a perspective view illustrating a state in which a wire connection is formed on the upper surface of the heat-radiating plate; Fig. 12A and Fig. 12B are diagrams illustrating the connection spacing and loop height of the wire connection; Fig. Figure 13 is a cross-sectional view illustrating a state in which a perpendicular is formed on the upper surface of the heat-radiating plate; Fig. Figure 14 is a cross-sectional view illustrating a state in which the perpendicular flows under the loop; Fig. Figure 15 is an enlarged view of a significant part of Fig. 14; Fig. 16 is a diagram illustrating a shrinkage force generated in the vertical plane in the power semiconductor device of the underlying technology; Fig. Figure 17 is a diagram illustrating a relationship between the shrinkage force and the tension of the perpendicular under a loop; Fig. Figure 18 is a diagram illustrating a shrinkage force generated in the vertical plane in the power semiconductor device of embodiment 1; and Fig. 19A and Fig. Figure 19B are diagrams illustrating a condition in which a crack in the solder is created in the power semiconductor device of the underlying technology. Description of preferred embodiments<A. Zugrundeliegende Technik>

[0014] The Fig. 1A and Fig. Figure 1B illustrates a configuration of the power semiconductor device 100A of a first underlying technology. Fig. 1A is a top view of the 100A power semiconductor device, and Fig. Figure 1B is a cross-sectional view of the 100A power semiconductor device.

[0015] The power semiconductor device 100A comprises a heat-radiating plate 1, an insulating substrate 3, and a semiconductor element 5. The insulating substrate 3 has a configuration in which an insulating base material 32 is inserted between a metal pattern 31 of a lower surface and a metal pattern 33 of an upper surface. For example, the metal pattern 31 of the lower surface and the metal pattern 33 of the upper surface are made of copper, and the insulating base material 32 is made of silicon nitride. The metal pattern of the lower surface 31 of the insulating substrate 3 is connected to the upper surface of the heat-radiating plate 1 by means of a solder 2. A plurality of semiconductor elements 5 are connected to the upper surface of the metal pattern 33 of the upper surface by means of a solder 4. The solder 2 and the solder 4 are examples of bonding materials.

[0016] A wire connection 6 is formed on the upper surface of the semiconductor element 5. The wire connection 6 has a configuration in which connection sections 6b and a connecting wire 6w are provided between the connection sections 6b. The semiconductor element 5 is a switching element that controls electrical power and requires heat dissipation. In addition to silicon (Si), a wide-bandgap semiconductor such as SiC or GaN is used as the semiconductor material for the semiconductor element 5.

[0017] Lot 2 contains Sn as its main component. Fig. Figure 1 illustrates a condition in which a shrinkage cavity 7 is created in the solder 2 below the end section of the insulating substrate 3. A problem arises in that the wire connection 6 is not properly formed in a region 10 of the semiconductor element 5, because the ultrasonic vibration is not transmitted at the time of wire connection due to the shrinkage cavity 7 immediately below region 10.

[0018] Fig. Figure 2 is a cross-sectional view of a power semiconductor device 100B of a second underlying technology. The solder 4, the semiconductor element 5, and the wire connection 6 are shown in Fig. 2 not illustrated. The power semiconductor device 100B differs from the power semiconductor device 100A of the first underlying technology in that a recess 311 is formed on the metal pattern 31 of the lower surface of the insulating substrate 3.

[0019] The recess 311 suppresses the formation of the shrinkage cavity 7 in the solder 2. However, the recess 311 has an unfilled section 312 in which the solder 2 is not filled and a bubble is enclosed. In a case where the semiconductor element 5 is located on the end section of the metal pattern 33 of the upper surface, the recess 311 cannot be formed to avoid a reduction in heat dissipation. Even if the heat dissipation condition is met and the recess 311 is formed, the high-altitude insulation performance is reduced due to the reduction in insulation performance caused by the unfilled section 312.

[0020] Therefore, in the embodiment 1 described below, a shrinkage cavity in the solder 2, which contains Sn as the main component, is suppressed without affecting the layout or the insulation performance of the semiconductor element 5. <B. Ausführungsform 1><B-1. Übersicht>

[0021] Fig. Figure 3 is a cross-sectional view illustrating a power semiconductor device 101 according to embodiment 1. The power semiconductor device 101 differs from the power semiconductor device 100A of the first underlying technology in that the wire connection 8 is formed on the upper surface of the heat-radiating plate 1. <B-2. Herstellungsprozess>

[0022] The manufacturing process of the power semiconductor device 101 is described below with reference to the Fig. 4A to 10B described. The Fig. 4A, Fig. 5A, Fig. 6A, Fig. 7A, Fig. 8A, Fig. 9A, and Fig. 10A are top views and the Fig. 4B, Fig. 5B, Fig. 6B, Fig. 7B, Fig. 8B, Fig. 9B, and Fig. 10B are cross-sectional views.

[0023] First, as in the Fig. 4A and Fig. Figure 4B illustrates the preparation of a heat-radiating plate 1. A region of the upper surface of the heat-radiating plate 1, onto which the solder 2 will be applied in a later step, is designated as the joining region 12. The heat-radiating plate 1 is formed from a Cu base plate, and a resist is applied in a region 11 that differs from the joining region 12 of the heat-radiating plate 1. In contrast, no resist is applied in the joining region 12, and the joining region 12 is pure Cu. However, the joining region 12 may be coated with Ni.

[0024] As in the Fig. 5A and Fig. As illustrated in Figure 5B, the wire connection 8 is next formed in the connection region 12 on the upper surface of the heat-radiating plate 1, along each side of the outer edge area of ​​the connection region 12.

[0025] Then, as in the Fig. 6A and Fig. As illustrated in Figure 6B, the plumb line 2 is attached to the connection region 12 on the upper surface of the heat-radiating plate 1.

[0026] Next, as in the Fig. 7A and Fig. As illustrated in Figure 7B, the insulating substrate 3 is connected to the heat-radiating plate 1 by means of the solder 2.

[0027] Then, as in the Fig. 8A and Fig. As illustrated in Figure 8B, the solder 4 is attached to the upper surface of the metal pattern 33 of the upper surface of the insulating substrate 3.

[0028] Next, as in the Fig. 9A and Fig. Figure 9B illustrates a multitude of semiconductor elements 5 connected to the metal pattern 33 of the upper surface of the insulating substrate 3 by means of the solder 4. Fig. Figures 6A to 9B illustrate a state in which the solder 2 has not yet wetted the connecting wire of the wire connection 8.

[0029] Then, as in the Fig. 10A and Fig. As illustrated in Figure 10B, the solder 2 wets the connecting wire of the wire connection 8 and enters under the loop of the connecting wire. <B-3. Verbindungsdraht>

[0030] Fig. Figure 11 is a perspective view illustrating a state in which the wire connection 8 is formed on the upper surface of the heat-radiating plate 1. The wire connection 8 is formed in the connection region 12 on the upper surface of the heat-radiating plate 1, along each side of the outer edge region of the connection region 12.

[0031] As in the Fig. 12A and Fig. As illustrated in Figure 12B, the wire connection comprises 8 connection sections 8b and a connecting wire 8w between the connection sections 8b. The connecting wire 8w contains Cu or Ag as its main component. The connecting wire 8w reacts with the solder 2, which contains Sn as its main component, so that an intermetallic compound is formed.

[0032] The diameter of the 8w connecting wire is 200 µm or more and 500 µm or less. A distance between the in Fig. The connection sections 8b illustrated in 12A are 1.0 mm or more. The height b of the loops formed by the connecting wire 8w, which are shown in Fig. As illustrated in Figure 12B, the thickness is 0.1 mm or more. By meeting these conditions, the solder 2 is allowed to enter under the loops of the connecting wire 8w.

[0033] Fig. Figure 13 is a cross-sectional view illustrating the state immediately after the solder 2 has been attached to the upper surface of the heat-radiating plate 1. The molten solder 2 wets the connecting wire 8w, which is made of Ag or Cu, and flows under the loops formed by the connecting wire 8w, as shown in Fig. 14 is illustrated. Fig. 15 is an enlarged view of Fig. 14 of a loop of the connecting wire 8w.

[0034] The solder 2 is then cooled, solidifies, and shrinks. Without the wire connection 8 formed on the upper surface of the heat-radiating plate 1, the shrinkage cavity 7 expands due to the shrinkage force of the solder 2, as indicated by the arrows in Fig. 16 is indicated. In the power semiconductor device 101, the interfacial tension of the solder 2, which is indicated by the left-pointing arrow in Fig. 17 is marked, however, a reaction force to the shrinkage force of the perpendicular 2, which is indicated by the arrow pointing to the right. As in Fig. As illustrated in Figure 18, the shrinkage cavity 7 is therefore prevented from expanding into the interior of the wire connection 8.

[0035] As in the Fig. 5A, Fig. As illustrated in Figure 5B, or Figure 11, the wire connection 8 is formed in the connection region 12 on the upper surface of the heat-radiating plate 1 along the outer edge of the connection region 12. This ensures that the wire connection 8 surrounds the semiconductor element 5 in a top view. As described above, the shrink cavity 7 does not extend into the interior of the wire connection 8; therefore, the wire connection 6 is properly formed on the upper surface of the semiconductor element 5 without the shrink cavity 7 extending directly beneath the semiconductor element 5.

[0036] By adding Lot 2, as in Fig. As illustrated in Figure 14, and furthermore, if it is possible to enter under the loops of the connecting wire 8w, the solder 2 will have a thickness equal to the height b of the loops. By defining the height b of the loops, the thickness of the solder 2 can therefore be determined with respect to a desired thickness.

[0037] The linear coefficients of thermal expansion differed between the insulating substrate 3 and the heat-radiating plate 1 due to material differences. For example, if the material of the heat-radiating plate 1 is Cu, the linear coefficient of thermal expansion of the heat-radiating plate 1 is 16.2. If the material of the insulating base material 32 is silicon nitride, and the material of the metal pattern 31 of the lower surface and the material of the metal pattern 33 of the upper surface are Cu, the linear coefficient of thermal expansion of the entire insulating substrate 3 is 6.2. Therefore, stress occurs in the solder 2 during the temperature cycle test due to the difference in the coefficient of thermal expansion between the insulating substrate 3 and the heat-radiating plate 1, and, as shown in the Fig. 19A and Fig. As illustrated in Figure 19B, a crack 9 is created in the horizontal direction. The crack 9 extends from the end section towards the interior of the perpendicular 2. Fig. 19A is the position where crack 9 has spread the most, marked by reference numeral 9a.

[0038] In contrast, the wire connection 8 in the power semiconductor device 101 of embodiment 1 is formed along all sides of the connection region 12 of the heat-radiating plate 1 with respect to the insulating substrate 3, and the intermetallic connection is formed between the connecting wire 8w and the solder 2. The intermetallic compound is, for example, Cu6Sn5, Cu3Sn, or Ag3Sn. As a result, the crack 9 is suppressed during the temperature cycle test because the solder 2 resists the stress, which, as described above, is generated due to the difference in the coefficient of thermal expansion between the insulating substrate 3 and the heat-radiating plate 1. That is, the power semiconductor device 101 exhibits crack resistance in the temperature cycle test. <B-4. Effekt>

[0039] The power semiconductor device 101 according to embodiment 1 comprises the heat-radiating plate 1, the insulating substrate 3, which is connected in the connection region 12 on the upper surface of the heat-radiating plate 1 by means of the solder 2, which is a connecting material having a plurality of elements with different solidification points, the semiconductor element 5, which is mounted on the upper surface of the insulating substrate 3 and the connecting wire 8w, which is a metal wire that is connected in the connection region 12 on the upper surface of the heat-radiating plate 1 such that the connecting wire 8w surrounds the semiconductor element 5 in a top view.This prevents the shrink cavity 7 from expanding, as an interfacial tension arises in the solder 2, which is in contact with the heat-dissipating plate 1 and the connecting wire 8w. This tension exerts a force in the opposite direction to the shrink force of the solder 2, which expands the shrink cavity 7. Consequently, the shrink cavity 7 is prevented from expanding directly beneath the semiconductor element 5; this ensures that the wire connection 6 forms properly on the upper surface of the semiconductor element 5. Furthermore, no depressions are formed on the insulating substrate 3; therefore, the degrees of freedom regarding the layout or the insulating performance of the semiconductor element are not affected.

[0040] In the power semiconductor device 101 according to embodiment 1, the connecting wire 8w is preferably connected along all sides of the outer edge region of the connection area 12 on the upper surface of the heat-radiating plate 1. As a result, the shrinkage cavity 7 is prevented from expanding directly below the semiconductor element 5; this ensures that the wire connection 6 is properly formed on the upper surface of the semiconductor element 5.

[0041] In the power semiconductor device 101 according to embodiment 1, the connection spacing of the connecting wire 8w is preferably 1.0 mm or more, and the loop height of the connecting wire 8w is preferably 0.1 mm or more. Such conditions allow the solder 2 to enter under the loop of the connecting wire 8w.

[0042] In the power semiconductor device 101 according to embodiment 1, the connecting wire 8w contains Cu or Ag as its main component, and the solder 2, which is a bonding material, contains Sn as its main component. Consequently, the solder 2 reacts with the connecting wire 8w, forming an intermetallic bond. This suppresses the horizontally generated crack 9 during the temperature cycle test, as the solder 2 resists the stress generated by the difference in the coefficient of linear thermal expansion between the heat-radiating plate 1 and the insulating substrate 3.

[0043] A manufacturing method for the power semiconductor device according to embodiment 1 comprises connecting the connecting wire 8w, which is a metal wire, to the upper surface of the heat-radiating plate 1; connecting the insulating substrate 3 to the upper surface of the heat-radiating plate 1 by means of the solder 2, which contains a plurality of elements with different solidification points; mounting the semiconductor element 5 onto the upper surface of the insulating substrate 3; and wherein the connecting wire 8w is connected in the connection region to which the insulating substrate 3 is connected on the upper surface of the heat-radiating plate 1, such that the connecting wire 8w surrounds the semiconductor element 5 in a top view. As a result, the shrinkage cavity 7 is prevented from expanding directly below the semiconductor element 5; thereby, the wire connection 6 is properly formed on the upper surface of the semiconductor element 5.Furthermore, no depressions are formed on the insulating substrate 3; therefore, the degree of freedom with respect to the layout or the insulation performance of the semiconductor element is not affected.

Claims

[1] comprising a power semiconductor device: • a heat radiating plate (1); • an insulating substrate (3) which is connected in a connection region (12) on an upper surface of the heat-radiating plate (1) by means of a connecting material (2) which contains a plurality of elements with different solidification points; • a semiconductor element (5) mounted on an upper surface of the insulating substrate (3); and • a metal wire (8w) which is connected in the connection region (12) on the upper surface of the heat radiating plate (1) such that the metal wire (8w) surrounds the semiconductor element (5) in a top view. [2] Power semiconductor device according to claim 1, wherein the metal wire (8w) is connected along an entire outer edge region of the connection region (12) on the upper surface of the heat radiating plate (1). [3] Power semiconductor device according to claim 1 or 2, wherein • a connection distance of the metal wire (8w) is 1.0 mm or more, and • the loop height of the metal wire (8w) is 0.1 mm or more. [4] Power semiconductor device according to any one of claims 1 to 3, wherein • the metal wire (8w) contains Cu or Ag as the main component, and • the connecting material (2) contains Sn as the main component. [5] comprising a manufacturing process of a power semiconductor device: • Connecting a metal wire (8w) to an upper surface of a heat-radiating plate (1); • Connecting an insulating substrate (3) in an upper surface of the heat-radiating plate (1) by means of a connecting material (2) which contains a plurality of elements with different solidification points; and • Mounting a semiconductor element (5) on an upper surface of the insulating substrate (3), wherein • the metal wire (8w) in a connection region (12), to which the insulating substrate (3) is connected on the upper surface of the heat-radiating plate (1), is connected in such a way that the metal wire (8w) surrounds the semiconductor element (5) in a top view.

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