Three-dimensional storage device and manufacturing method thereof

Abstract

A three-dimensional memory device comprising: a first stack structure (ST) comprising first stack layers and first insulating layers (112) alternately stacked on a substrate (100) along a vertical direction (Z), each of the first stack layers comprising a first gate layer (118), a first ferroelectric layer (120), and a first channel layer (122), the first gate layer, the first ferroelectric layer, and the first channel layer each extending along a horizontal direction (Y) perpendicular to the vertical direction, and the first ferroelectric layer being disposed between the first gate layer and the first channel layer;a second stack structure (ST) laterally spaced from the first stack structure (ST) and comprising second stack layers and second insulating layers (112) alternately stacked on the substrate (100) along the vertical direction (Z), each of the second stack layers comprising a second gate layer (118), a second ferroelectric layer (120), and a second channel layer (122), the second gate layer, the second ferroelectric layer, and the second channel layer each extending along the horizontal direction (Y), the second ferroelectric layer being disposed between the second gate layer and the second channel layer, and the first gate layer (118) and the second gate layer being disposed between the first ferroelectric layer (120) and the second ferroelectric layer;first conductive pillars (126) extending along the vertical direction (Z), laterally separated from each other, and in contact with the first channel layer (122) of each of the first stack layers; second conductive pillars (126) extending along the vertical direction (Z), laterally separated from each other, and in contact with the second channel layer (122) of each of the second stack layers; and a dielectric wall (128) disposed between the first stack structure (ST) and the second stack structure (ST), the dielectric wall being disposed between the first gate layer (118) of each of the first stack layers and the second gate layer (118) of each of the second stack layers.

Description

BACKGROUNDThe industry for semiconductor integrated circuit (IC) has undergone exponential growth. Technological advances in IC materials and design have produced generations of ICs that have become smaller and more complex from generation to generation circuits. In the course of IC evolution, the functional density (e.g., the number of devices connected per chip area) has generally been increased, while the geometry size (e.g., the smallest component (or line) that may be achieved by a fabrication process) has been decreased. This downsizing process generally offers advantages in that production efficiency is increased and the costs associated therewith are decreased.However, such downsizing has also increased complexity in processing and manufacturing ICs, and similar developments in IC processing and manufacturing are required to realize these advances. For example, three-dimensional (3D) memory devices have been presented that are intended to replace planar memory devices. However, the 3D memory device is not satisfactory in every respect. Additional problems to be solved occur.US 2020 / 0 026 990 A1 describes a system for performing a sum-of-products function, the system including a storage device and a control unit. The memory device includes a 3D array including a plurality of memory cells having programmable conductivities arranged in nodes of a plurality of cell body lines and gate lines, a gate driver coupled to the gate lines and applying control gate voltages in combination with the programmable conductivities to correspond to the weights of terms in the sum-of-products function, an input driver configured to apply voltages to the memory cells corresponding to input variables, a plurality of input lines connecting the cell body lines to the input driver, a sense circuit configured to sense currents flowing through the memory cells and corresponding to the terms in the sum-of-products function, and a buffer circuit, which is used to store the terms. The control unit is for controlling the storage device which sums the terms in the sum-of-products function. US 2011 / 0 294 290 A1 describes a 3D semiconductor memory device having a stacked structure including a plurality of conductive structures, an active pillar penetrating the stacked structure, and a data storage structure between the active pillar and the conductive structures, the active pillar including a vertical semiconductor structure penetrating the stacked structure and protruding semiconductor structures between the vertical semiconductor structure and the data storage structure, the protruding semiconductor structures having a different crystalline structure from that of the vertical semiconductor structure.BRIEF DESCRIPTION OF THE DRAWINGSAspects of the present disclosure may best be understood from the following detailed description taken in conjunction with the accompanying drawings. It should be appreciated that, in accordance with practice in the industry, various features are not drawn to scale. Indeed, the dimensions of the various features may be arbitrarily increased or reduced for clarity of explanation. FIGS. 1A to 11A are schematic plan views of structures manufactured at various stages of a manufacturing method of a three-dimensional memory device according to some embodiments of the disclosure. FIGS. 1B to 11B are schematic cross-sectional views taken along lines A-A' as shown in FIGS. 1A to 11A. FIGS. 4C to 11C are schematic plan views taken along lines B-B' as shown in FIGS. 4B to 11B. FIG. 12 is an equivalent circuit diagram of the three-dimensional memory device as illustrated in FIGS. 11A, 11B, and 11C. FIG. 13 is a schematic cross-sectional view of a semiconductor structure according to some embodiments of the disclosure. FIG. 14 is a schematic top view of a three-dimensional memory device according to some alternative embodiments of the present disclosure. FIG. 15 is a schematic top view of a three-dimensional memory device according to some alternative embodiments of the present disclosure. FIG. 16 is a schematic top view of a three-dimensional memory device according to some alternative embodiments of the present disclosure.DETAILED DESCRIPTIONThe following disclosure provides many different embodiments and examples for implementing different features of the provided subject matter. To simplify the present disclosure, specific examples of components and arrangements will be described below. These are, of course, only examples. For example, the formation of a first feature over or on a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, but may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Further, reference numerals may be repeated in the various examples of the present disclosure. This repetition is for convenience and clarity and does not fundamentally dictate a relationship between the various embodiments and / or configurations discussed.Further, for convenience of description herein, spatially relative terms such as "below," "below," "downward," "above," "above," "upward," and the like may be used to describe the relationship of one element or feature to another element or feature as illustrated in the drawings. The spatially relative terms are intended to include other orientations of the device during use or operation in addition to the orientation as illustrated in the drawings. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative terms used herein may also be interpreted accordingly.Among the various nonvolatile memories, the ferroelectric field effect transistor (FeFET) is a promising candidate for high density and low power consumption applications. Due to its field controlled operation, the FeFET has advantages such as non-destructive read-out, high programming / erasing speed, and low power consumption. Further, the FeFET has attracted more attention because of its high scalability and high CMOS compatibility. In order to achieve an even higher density, a three-dimensional (3D) vertical structure is proposed. Generally, polysilicon is used as the channel material. However, there are some challenges with the polysilicon channel, such as low charge carrier mobility on the very thin polysilicon channel and a low dielectric constant interface layer between the ferroelectric material and the polysilicon. Due to the capacitance discontinuity between the low dielectric constant barrier layer and the ferroelectric material, a large voltage is applied to the barrier layer during operation. This ultimately leads to a break-through of the boundary layer and thus to a failure of service life. Further, the interface layer having a low dielectric constant increases the trapping of charges, resulting in a problem of threshold voltage shift, thereby impairing the reliability.To overcome the foregoing challenges, an FeFET with an oxide semiconductor channel is proposed. The oxide semiconductor channel is suitable for fast access speeds in a very thin body because of its high charge carrier mobility.FIGS. 1A to 11A are schematic plan views of structures manufactured at various stages of a manufacturing method of a three-dimensional memory device 10 according to some embodiments of the disclosure. FIGS. 1B to 11B are schematic cross-sectional views taken along lines A-A' as shown in FIGS. 1A to 11A. FIGS. 4C to 11C are schematic plan views taken along lines B-B' as shown in FIGS. 4B to 11B.Referring to FIGS. 1A and 1B, a multilayer stack 110 is formed on the substrate 100. The multilayer stack 110 includes insulating layers 112 and sacrificial layers 114. As shown in FIG. 1B, the insulating layers 112 and the sacrificial layers 114 are alternately stacked on the substrate 100 along a direction Z. In detail, the insulating layers 112 are spaced apart from each other along the direction Z by the sacrificial layers 114. From another perspective, each sacrificial layer 114 is between an underlying insulating layer 112 and an overlying insulating layer 112. Further, the sacrificial layers 114 are replaced with gate layers 118 in the subsequent steps described below with reference to FIGS. 9A-9C and 10A-10C. While three insulating layers 112 and two sacrificial layers 114 are shown in FIG. 1B for illustrative purposes, those skilled in the art will appreciate that the number of insulating layers 112 and the number of sacrificial layers 114 may be more than shown in FIG. 1B and may be determined as needed and / or design layout.In some embodiments, the material of the insulating layers 112 has sufficient etch selectivity with respect to the material of the sacrificial layers 114 such that the insulating layers 112 may remain substantially intact during removal of the sacrificial layers 114 in the subsequent step described with reference to FIGS. 9A-9C. In some embodiments, the insulating layers 112 include silicon oxide while the sacrificial layers 114 are made of silicon nitride. However, it is within the skill of the art to select other suitable materials for the insulating layers 112 and the sacrificial layers 114 according to process requirements. In some alternative embodiments, the material of the insulating layers 112 may be selected from silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borosilicate glass (BSG), or boron doped phosphosilicate glass (BPSG), and the material of the sacrificial layers 114 may be selected from silicon oxide, silicon oxynitride, PSG, BSG, or BPSG. In some embodiments, the insulating layers 112 include the same dielectric material, such as silicon oxide. However, the embodiments of the present disclosure are not limited thereto. In some alternative embodiments, the insulating layers 112 thereof may include different dielectric materials. Similarly, in some embodiments, sacrificial layers 114 include the same dielectric material, such as silicon nitride. However, the embodiments of the present disclosure are not limited thereto. In some alternative embodiments, the sacrificial layers 114 may include different dielectric materials therefrom. In some embodiments, the method of forming each of the insulating layers 112 and each of the sacrificial layers 114 includes a deposition process, such as a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process.In some embodiments, the substrate 100 is an etch stop layer formed over a complementary metal oxide semiconductor (CMOS) integrated circuit. In these embodiments, the material of the substrate 100 has sufficient etch selectivity with respect to the materials in the multilayer stack 110. In these embodiments, the material of the substrate 100 includes silicon carbide, silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon oxide, or silicon nitride. In those embodiments where the insulating layers 112 and the sacrificial layers 114 include silicon oxide and silicon nitride, the material of the substrate 100 is formed of silicon carbide. However, the disclosure is not limited thereto. In some alternative embodiments, the substrate 100 is a semiconductor wafer or a semiconductor on insulator (SOI) wafer.In some embodiments, the insulating layers 112 have a thickness t 1 along the direction Z of about 15 nm to about 90 nm and the sacrificial layers 114 have a thickness t 2 of about 15 nm to about 90 nm. In some embodiments, the insulating layers 112 are formed with a different thickness than the sacrificial layers 114. In some alternative embodiments, the insulating layers 112 are formed to the same thickness as the sacrificial layers 114. For example, the thickness t 2 of the sacrificial layers 114 is about 10% to about 50% greater or less than the thickness t 1 of the insulating layers 112. In some embodiments, the multilayer stack 110 has a total height h 1 along the direction Z of about 1000 nm to about 10000 nm.Referring to FIGS. 2A and 2B, trenches TR 1 are formed in the multilayer stack 110. As illustrated in FIG. 2B, the trenches TR 1 penetrate the multilayer stack 110 along the direction Z. That is, the trenches TR 1 vertically extend in the multilayer stack 110. In the illustrated embodiment, the trenches TR 1 vertically extend through all layers (e.g., all insulating layers 112 and all sacrificial layers 114) of the multilayer stack 110 and expose the substrate 100. That is, the bottom surfaces of the trenches TR 1 are defined by the substrate 100. In other words, the substrate 100 is exposed at the bottom surfaces of the trenches TR 1. However, the disclosure is not limited thereto. In some alternative embodiments, the trenches TR 1 extend vertically through some, but not all, layers of the multilayer stack 110. For example, the trenches TR 1 may vertically extend through all the sacrificial layers 114 and expose the lowermost insulating layer 112. While three trenches TR 1 are illustrated in FIGS. 2A and 2B for illustrative purposes, those skilled in the art will understand that the number of trenches TR 1 may be greater than that illustrated in FIGS. 2A and 2B and may be determined as needed and / or design layout.As shown in the plan view of FIG. 2A, the trenches TR 1 vertically penetrating the multilayer stack 110 extend laterally along a direction Y perpendicular to the direction Z and are arranged along a direction X perpendicular to the direction Y and to the direction Z. Thus, the multilayer stack 110 is cut into a plurality of stripe portions by the trenches TR. In such cases, the plurality of strip portions will be referred to below as the remaining portions of the multilayer stack 110. Further, after forming the trenches TR 1, each remaining portion of the multilayer stack 110 is arranged between two adjacent trenches TR 1 along the direction X, i.e. two adjacent remaining portions of the multilayer stack 110 are spaced apart from each other by a respective trench TR 1. In some embodiments, the remaining portions of the multilayer stack 110 have a width w 1 of about 50 nm to about 200 nm along the direction X and further have the height h 1, as discussed with reference to FIGS. 1A and 1B. In some embodiments, the trenches TR 1 have a width w 2 of about 50 nm to about 200 nm along the direction X. The aspect ratio (AR) of each remaining portion of the multilayer stack 110 is the ratio of the height h 1 to the width of the narrowest feature of the remaining portion of the multilayer stack 110, which is the width w 1 in this processing step. Further, the trenches TR 1 expose the side surfaces of the remaining portions of the multilayer stack 110, as illustrated in FIG. 2B. That is, the sidewalls of the trenches TR 1 are defined by the remaining portions of the multilayer stack 110. In the illustrated embodiment, the trenches TR 1 completely expose the side surfaces of the remaining portions of the multilayer stack 110. That is, the trenches TR 1 expose the side surfaces of all layers (for example, all the insulating layers 112 and all the sacrificial layers 114) in the remaining portions of the multilayer stack 110. However, the disclosure is not limited thereto. In some alternative embodiments, the trenches TR 1 partially expose the side surfaces of the remaining portions of the multilayer stack 110. In some embodiments, the side surfaces of the insulating layers 112 are substantially coplanar or flush with the side surfaces of the sacrificial layers 114 in the current step.In some embodiments, the method of forming the trenches TR 1 includes a lithography process and an etching process (for example, an anisotropic etching process). Since the substrate 100 has a sufficient etch selectivity with respect to the materials in the multilayer stack 110, the substrate 100 may remain substantially intact during the etching process. In some embodiments in which the substrate 100 includes silicon carbide, the insulating layers 112 include silicon oxide, and the sacrificial layers 114 include silicon nitride, the trenches TR 1 are formed by dry etching using a fluorine-based gas (for example, C 4F 6) mixed with hydrogen (for example, H 2) or oxygen (for example, O 2).Referring to FIGS. 3A and 3B, the sacrificial layers 114 in the remaining portions of the multilayer stack 110 are recessed laterally opposite the insulating layers 112 in the remaining portions of the multilayer stack 110. As shown in FIG. 3B, portions of the sacrificial layers 114 exposed by the trenches TR 1 are removed to form recesses R. Each of the recesses R is formed between two adjacent insulating layers 112. Each of the recesses R is connected (for example, spatially continuous) to the respective trench TR 1. From another viewpoint, as illustrated in FIG. 3B, the side surfaces of the sacrificial layers 114 are exposed through the recesses R and the trenches TR 1, and the exposed side surfaces of the sacrificial layers 114 are no longer coplanar with the exposed side surfaces of the insulating layers 112 but are recessed laterally from the exposed side surfaces of the insulating layers 112. While the exposed side surfaces of the sacrificial layers 114 are depicted as straight in FIG. 3B, the side surfaces may be concave or convex.In some embodiments, a method for laterally recessing the sacrificial layers 114 includes an etching process, such as an isotropic etching process. During such an etching process, the insulating layers 112 may be hardly etched because they have sufficient etching selectivity to the sacrificial layers 114. That is, the etching process used to form the recesses R is selective to the material of the sacrificial layers 114 (e.g., the material of the sacrificial layers 114 is selectively etched at a faster rate than the material of the insulating layers 112). Viewed from another aspect, the substrate 100 may remain substantially intact during such an etching operation, as the substrate 100 has sufficient etch selectivity to the materials in the multilayer stack 110. In some embodiments in which the substrate 100 is formed of silicon carbide, the insulating layers 112 are formed of silicon oxide, and the second sacrificial layers 114 are formed of silicon nitride, the trenches TR 1 are extended to the recesses R by wet etching using phosphoric acid (for example, H 3PO 4). However, the embodiments of the disclosure are not limited thereto. In some alternative embodiments, dry etching may be used that selectively acts on the material of sacrificial layers 114.After manufacture, each of the recesses R has a depth d 1 that extends beyond the sidewalls of the insulating layers 112 along the direction X. By means of time-controlled etching processes, the etching of the recesses R can be stopped after the recesses R have reached a desired depth d 1. In some embodiments, the depth d 1 of the recesses R is about 5 nm to about 20 nm. From another viewpoint, the width of the sacrificial layers 114 is reduced by forming the recesses R. In some embodiments, after the recesses R are formed, each of the sacrificial layers 114 has a width w 3 of about 20 nm to about 100 nm along the direction X. As mentioned above, the aspect ratio (AR) of each remaining portion of the multilayer stack 110 is the ratio of the height h 1 to the width of the narrowest feature of the remaining portion of the multilayer stack 110, which is the width w 3 in this processing step. The formation of the recesses R thus increases the aspect ratio of each remaining portion of the multilayer stack 110.Referring to FIGS. 4A, 4B, and 4C, ferroelectric layers 120 are formed in the recesses R. In detail, as shown in FIGS. 4B and 4C, each of the ferroelectric layers 120 is formed within one of the recesses R in a one-to-one relationship. The ferroelectric layer 120 is formed to cover or contact the side surface of the respective sacrificial layer 114 exposed by the respective recess R. Thus, the adjacent ferroelectric layers 120 are laterally spaced apart from each other along the direction X in each remaining portion of the multilayer stack 110 by the respective sacrificial layer 114. As shown in FIG. 4B, one of the sacrificial layers 114 and the associated ferroelectric layers 120 in each remaining portion of the multilayer stack 110 are substantially on the same plane. When elements are described herein as being on a "substantially same plane", these elements are formed at substantially the same height. Viewed from another viewpoint, as shown in FIG. 4B, the ferroelectric layers 120 are each embedded between two adjacent insulating layers 112. In other words, the ferroelectric layers 120 are vertically spaced apart from each other along the direction Z by the respective insulating layer 112.In some embodiments, the ferroelectric layers 120 are formed by the following steps. First, a ferroelectric material is formed over the substrate 100 to fill the recesses R between the insulating layers 112. In some embodiments, the ferroelectric material not only fills the recesses R, but also covers the side surfaces of the insulating layers 112 exposed by the trenches TR 1, the upper surface of the uppermost insulating layer 112, and the upper surface of the substrate 100 exposed by the trenches TR 1. In some embodiments, the method of forming the ferroelectric material includes a deposition process, such as a CVD process or an ALD process. Thereafter, the portions of the ferroelectric material covering the side surfaces of the insulating layers 112 exposed by the trenches TR1, the upper surface of the uppermost insulating layer 112 and the upper surface of the substrate 100 exposed by the trenches TR1 are removed to form the ferroelectric layers 120 separated from each other and not connected to each other. In some embodiments, the method of removing some portions of the ferroelectric material includes performing an isotropic etching process. However, the disclosure is not limited thereto. In some alternative embodiments, an anisotropic etching process is performed, followed by performing an isotropic etching process to remove some portions of the ferroelectric material.In some embodiments, the ferroelectric layers 120 include a ferroelectric material capable of switching between two different polarization directions by applying appropriate voltage differences across the ferroelectric layers 120. For example, the polarization of a ferroelectric layer 120 changes due to an electric field resulting from the applied voltage difference. In some embodiments, the ferroelectric material of the ferroelectric layers 120 includes hafnium zirconium oxide (e.g., HZO), silicon-doped hafnium oxide (e.g., HSO), hafnium silicon oxide (e.g., HfSiO), hafnium lanthanum oxide (e.g., HfLaO), hafnium oxide (e.g., HfO2), hafnium zirconium oxide (e.g., HfZrO2), zirconium oxide (e.g., ZrO2), or HfO2doped with lanthanum (e.g., La), yttrium (e.g., Y), silicon (e.g., Si), or germanium (e.g., Ge). However, the disclosure is not limited thereto. In some alternative embodiments, the ferroelectric material of the ferroelectric layers 120 may be a high-k dielectric material, such as a hafnium (Hf) based dielectric material or the like. For example, the ferroelectric material may be a hafnium-containing compound such as hafnium zirconium oxide (e.g., HfZnO), hafnium aluminum oxide (e.g., HfAlO), hafnium lanthanum oxide (e.g., HfLaO), hafnium cerium oxide (e.g., HfCeO), hafnium gadolinium oxide (e.g., HfGO), hafnium silicon oxide (e.g., HfSiO), hafnium zirconium lanthanum oxide (e.g., HfZrLaO), hafnium zirconium gadolinium oxide (e.g., HfZrGO), hafnium zirconium yttrium oxide (e.g., HfZrYO), hafnium zirconium cerium oxide (e.g., HfZrNbO), hafnium zirconium strontium oxide (for example, HfZrNbO), or the like. In addition, the hafnium-containing compound may be doped with some dopants, such as lanthanum (e.g., La), yttrium (e.g., Y), silicon (e.g., Si), germanium (e.g., Ge), cerium (e.g., Ce), gadolinium (e.g., Gd), strontium (e.g., Sr), or the like, or a combination thereof. By doping the hafnium-containing compound with these dopants, an orthorhombic lattice structure can be achieved in the ferroelectric layers 120. In some embodiments, the hafnium-containing compound having the orthorhombic lattice structure has a desired ferroelectric property to achieve the switchable property of the ferroelectric layers 120 in the memory device. Further, by including the dopants, an orthorhombic lattice structure in the ferroelectric layers 120 may be achieved relatively easily (e.g. at a lower temperature) and the ferroelectric layers 120 may be formed within the relatively low thermal budget of BEOL (back-end-of-line) processes (e.g. at a temperature that does not damage FEOL (front-end-of-line) features).As shown in the top view of FIG. 4C, the ferroelectric layers 120 extend laterally along the direction Y. In some embodiments, the ferroelectric layers 120 have a thickness t 3 (see, e.g., FIG. 4B ) that substantially corresponds to the thickness t 2 of the sacrificial layers 114 (see, e.g., FIG. 4B ) along the direction Z. In some embodiments, the thickness t 3 of the ferroelectric layers 120 is about 3 nm to about 15 nm. In some embodiments, the ferroelectric layers 120 have a width w 4 along the direction X (see, e.g., FIG. 4C ) that is less than the depth d 1 of the recess R (see, e.g., FIG. 4B ). This means that the recesses R are partially occupied by the respective ferroelectric layers 120. Timed etch processes may be used to stop the etching of the ferroelectric layers 120 after the ferroelectric layers 120 have reached a desired width w 4. In some embodiments, the width w 4 of the ferroelectric layers 120 along the direction X is about 3 nm to about 15 nm.Further, referring to FIGS. 4B and 4C, channel layers 122 are formed in the recesses R. In detail, as shown in FIGS. 4B and 4C, each of the channel layers 122 is formed in a one-to-one relationship within one of the recesses R. The channel layer 122 is formed to cover or contact the side surface of the respective ferroelectric layer 120 exposed by the corresponding recess R. Thus, the respective channel layers 122 in each remaining portion of the multilayer stack 110 are laterally spaced apart from each other by the respective ferroelectric layers 120 along the direction X and by the respective sacrificial layer 114. Further, as shown in FIG. 4B, one of the sacrificial layers 114, the respective ferroelectric layers 120, and the respective channel layers 122 in each remaining portion of the multilayer stack 110 are substantially on a same plane. From another viewpoint, as shown in FIG. 4B, the channel layers 122 are each embedded between two adjacent insulating layers 112. In other words, the channel layers 122 are vertically spaced apart from each other along the direction Z by the respective insulating layers 112.In some embodiments, the channel layers 122 are formed by the following steps. First, a channel material is formed over the substrate 100 to fill the recesses R between the insulating layers 112. In some embodiments, the channel material not only fills the recesses R, but also covers the side surfaces of the insulating layers 112 exposed by the trenches TR 1, the upper surface of the uppermost insulating layer 112, and the upper surface of the substrate 100 exposed by the trenches TR 1. In some embodiments, the method of forming the channel material includes a deposition process, such as a CVD process or an ALD process. Thereafter, the portions of the channel material covering the side surfaces of the insulating layers 112 exposed by the trenches TR 1, the upper surface of the uppermost insulating layer 112, and the upper surface of the substrate 100 exposed by the trenches TR 1 are removed to form the channel layers 122 separated from each other and not connected to each other. In some embodiments, the method of removing some portions of the channel material includes performing an anisotropic etching process.In some embodiments, the channel material of the channel layers 122 includes a metal oxide (or an oxidic semiconductor), such as an indium-based oxide material (e.g., indium gallium zinc oxide (e.g., IGZO)). Other suitable materials for the channel layers 122 include zinc oxide (e.g., ZnO), indium tungsten oxide (e.g., InWO), tungsten oxide (e.g., WO), tantalum oxide (e.g., TaO), and molybdenum oxide (e.g., MoO).As shown in the top view of FIG. 4C, the channel layers 122 extend laterally along the direction Y and the ferroelectric layers 120 are arranged between the respective channel layer 122 and the respective sacrificial layer 114. In some embodiments, the channel layers 122 have a thickness t 4 (see, e.g., FIG. 4B ) that substantially corresponds to the thickness t 2 of the sacrificial layers 114 (see, e.g., FIG. 4B ) along the direction Z. In some embodiments, the thickness t 4 of the channel layers 122 is about 5 nm to about 15 nm. In some embodiments, the channel layers 122 have a width w 5 along the direction X (see, e.g., FIG. 4C ) that is less than the depth d 1 of the recess R (see, e.g., FIG. 4B ). In some embodiments, the width w 5 of the channel layers 122 along the direction X is about 5 nm to about 15 nm.In some embodiments, as shown in FIG. 4B, the side surface of each channel layer 122 exposed by the respective trench TR 1 is substantially coplanar or planar with the side surfaces of the adjacent insulating layers 112 exposed by the respective trench TR 1. In such cases, the sum of the width w 4 of the ferroelectric layers 120 (see, e.g., FIG. 4C ) and the width w 5 of the channel layers 122 (see, e.g., FIG. 4C ) is substantially equal to the depth d 1 of the recess R. However, the disclosure is not limited thereto. In some alternative embodiments, the side surface of each channel layer 122 exposed by the respective trench TR 1 is slightly recessed from the side surfaces of the adjacent insulating layers 112 exposed by the respective trench TR 1 by a non-zero distance. The non-zero distance is, for example, about 1 nm to about 5 nm.Referring to FIGS. 5A, 5B, and 5C, after the formation of the channel layers 122, dielectric walls 124 are formed to fill the trenches TR 1. As shown in FIGS. 5A, 5B, and 5C, the dielectric walls 124 are in contact with the side surfaces of the insulating layers 112 exposed by the trenches TR 1 and the side surfaces of the channel layers 122 exposed by the trenches TR 1. In embodiments in which the side surface of each channel layer 122 exposed by the respective trench TR 1 is substantially coplanar or planar with the side surfaces of the adjacent insulating layers 112 exposed by the respective trench TR 1, the side surface of the dielectric wall 124 in contact with the side surfaces of the insulating layers 112 and the side surface of the channel layer 122 exposed by the respective trench TR 1 has a substantially planar profile. In some embodiments, as shown in FIGS. 5A, 5B, and 5C, each side surface of the dielectric wall 124 is in contact with the side surfaces of the insulating layers 112 and the side surface of the channel layers 122 exposed by the respective trench TR 1 substantially straight. However, the disclosure is not limited thereto. In embodiments in which the side surface of each channel layer 122 exposed by the respective trench TR 1 is slightly recessed from the side surfaces of the adjacent insulating layers 112 exposed by the respective trench TR 1, the side surface of the dielectric wall 124 that is in contact with the side surfaces of the insulating layers 112 and the side surface of the channel layers 122 exposed by the respective trench TR 1 has an uneven profile. In such cases, the dielectric walls 124 may have laterally protruding portions in contact with the side surfaces of the respective channel layers 122.In some embodiments, as shown in FIG. 5B, the lower surfaces of the dielectric walls 124 are in contact with the upper surface of the substrate 100 exposed by the trenches TR 1. However, the disclosure is not limited thereto. In embodiments where the trenches TR 1 extend vertically through some, but not all, layers of the multilayer stack 110, the bottom surfaces of the dielectric walls 124 are in contact with the remaining portions of the multilayer stack 110.In some embodiments, the dielectric walls 124 are formed by the following steps. After the formation of the channel layers 122, a dielectric material is formed to fill the trenches TR 1. The dielectric material may include silicon nitride, silicon oxide, silicon oxynitride, phosphosilicate glass (PSG), borosilicate glass (BSG), boron doped phosphosilicate glass (BPSG), or the like, or a combination thereof, and may be formed by a suitable deposition process, such as a CVD process or an ALD process. After the dielectric material is formed, a planarization process, such as a chemical mechanical planarization (CMP) process, an etching process, or a combination thereof, may be performed to remove portions of the dielectric material outside the trenches TR 1. In some embodiments, the portions of the dielectric material removed by the planarization process are over the top surface of the top insulating layer 112. That is, the planarization process exposes the multilayer stack 110 such that the top surface of the multilayer stack 110 (e.g., the top surface of the uppermost insulating layer 112) and the top surfaces of the remaining portions of the dielectric material are substantially coplanar or planar with each other after completion of the planarization process. The remaining portions of the dielectric material in the trenches TR 1 form the dielectric walls 124.As shown in the top view of FIG. 5C, the dielectric walls 124 extend laterally along the direction Y and each of the channel layers 122 is disposed between the respective dielectric wall 124 and the respective ferroelectric layer 120. In some embodiments, the dielectric walls 124 (see, e.g., FIG. 5C ) have a height h 2 that substantially corresponds to the overall height h 1 of the multilayer stack 110 (see, e.g., FIG. 5C ) along the direction Z. In some embodiments, the height h2of the dielectric walls 124 is about 1000 nm to about 10000 nm. In some embodiments, the dielectric walls 124 (see, e.g., FIG. 5B ) have a width w 6 that substantially corresponds to the width w 2 of the trenches TR 1 (see, e.g., FIG. 5B ) along the direction X. In some embodiments, the width w 6 of the dielectric walls 124 is about 50 nm to about 200 nm.Referring to FIGS. 6A, 6B, and 6C, through holes TH are formed in the dielectric walls 124, the insulating layers 112, and the channel layers 122. As shown in FIGS. 6A, 6B, and 6C, each through hole TH penetrates through the respective dielectric wall 124, the respective insulating layers 112, and the respective channel layers 122 along the direction Z to expose the substrate 100. That is, each through hole TH extends vertically through the respective dielectric wall 124, the respective insulating layers 112, and the respective channel layers 122. Further, as shown in FIG. 6C, the through holes TH penetrate the channel layers 122 to separate the channel layers 122, so that each of the channel layers 122 is present as a discontinuous channel layer. However, the disclosure is not limited thereto. In some alternative embodiments, the through-holes TH may penetrate the channel layers 122 without separating the channel layers 122. In such cases, each of the channel layers 122 is further a continuous channel layer. Further, as shown in FIG. 6B, the side surfaces of the ferroelectric layers 120 in contact with the channel layers 122 are exposed through the through holes TH after forming the through holes TH. However, the disclosure is not limited thereto. In embodiments where the vias TH penetrate the channel layers 122 without separating the channel layers 122, the ferroelectric layers 120 are not exposed through the vias TH.In some embodiments, the through holes TH are laterally separated from each other. As shown in FIGS. 6A, 6B, and 6C, the through holes TH disposed in the same dielectric wall 124 are laterally separated from each other by the dielectric wall 124, the respective insulating layers 112, and the respective channel layers 122. From another viewpoint, as shown in FIGS. 6A and 6C, the through holes TH are arranged separately from each other so as to have a plurality of columns extending along the direction Y and so that two adjacent columns of the through holes TH are spaced apart from each other along the direction X. The through holes TH in the same column are laterally separated from each other by the respective dielectric wall 124, the respective insulating layers 112, and the respective channel layers 122. The vias TH in one of the adjacent columns of vias TH disposed in the same dielectric wall 124 are laterally separated by the dielectric wall 124 from the vias TH in another adjacent column.In some embodiments, the through holes TH are formed by a lithography process and an etching process. A mask pattern, for example a patterned photoresist, may be formed over the multilayer stack 110. The etching process may then be performed using the mask pattern as an etch mask to remove portions of the dielectric walls 124, the insulating layers 112 and the channel layers 122 to form the through openings TH. After the etching process is completed, the mask pattern (e.g., the patterned photoresist) may be removed by a suitable removal process such as ashing or stripping. In some embodiments, the etching process is an anisotropic etching process.Referring to FIGS. 7A, 7B, and 7C, conductive pillars 126 are formed to fill the through holes TH. As shown in FIGS. 7A, 7B, and 7C, each conductive pillar 126 penetrates through the respective dielectric wall 124, the respective insulating layers 112, and the respective channel layers 122 along the direction Z and reaches the upper surface of the substrate 100 exposed through the respective through hole TH. That is, each conductive pillar 126 extends vertically through the respective dielectric wall 124, the respective insulating layers 112, and the respective channel layers 122. In some embodiments, each conductive pillar 126 is formed to be in lateral contact with a respective channel layer 122 via more than one side surface. In the illustrated embodiment, as shown in FIG. 6C, in which the through holes TH cut off the channel layers 122 to expose the side surfaces of the ferroelectric layers 120, two side surfaces of each conductive pillar 126 filling the respective through hole TH are in lateral contact with one of the respective channel layers 122. From another viewpoint, the conductive pillars 126 filling the through holes TH are in contact with the side surfaces of the ferroelectric layers 120 exposed through the respective through holes TH. However, the disclosure is not limited thereto. In embodiments where the through holes TH penetrate the channel layers 122 without cutting off the channel layers 122, portions of each conductive pillar 126 are embedded in the respective channel layers 122. In such cases, three side surfaces of each conductive pillar 126 filling the respective through hole TH are in lateral contact with a respective channel layer 122. While sixteen conductive pillars 126 are shown in FIG. 7A for illustrative purposes, those skilled in the art will appreciate that the number of conductive pillars 126 may be greater than that shown in FIG. 7A and may be determined as needed and / or design layout.In some embodiments, the conductive pillars 126 are laterally separated from each other. As shown in FIGS. 7A, 7B, and 7C, the conductive pillars 126 disposed in the same dielectric wall 124 are laterally separated from each other by the dielectric wall 124, the respective insulating layers 112, and the respective channel layers 122. Viewed from another viewpoint, as shown in FIGS. 7A and 7C, the conductive pillars 126 are arranged in an array of rows and columns separately from each other. In detail, the conductive pillars 126 are arranged apart from each other to have multiple columns extending along the direction Y, and adjacent columns of the conductive pillars 126 are spaced apart from each other along the direction X. The conductive pillars 126 in the same column are laterally separated from each other by the respective dielectric wall 124, the respective insulating layers 112, and the respective channel layers 122. The conductive pillars 126 in an adjacent column of the conductive pillars 126 disposed in the same dielectric wall 124 are laterally separated from the conductive pillars 126 in another adjacent column by the dielectric wall 124.In some embodiments, the conductive pillars 126 are formed by the following steps. After the via holes TH are formed, a conductive material is formed to fill the via holes TH. The conductive material may include copper, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, ruthenium, aluminum, combinations thereof, or the like, and may be formed by a deposition process (e.g., a CVD process or a physical vapor deposition (PVD) process), a plating process, or a combination thereof. After the formation of the conductive material, a planarization process, such as a CMP process, an etching process, or a combination thereof, may be performed to remove portions of the conductive material outside the through holes TH. In some embodiments, the portions of the conductive material removed by the planarization process overlie the top surface of the uppermost insulating layer 112 and the top surfaces of the dielectric walls 124. That is, the planarization process exposes the multilayer stack 110 and the dielectric walls 124 such that the top surface of the multilayer stack 110 (e.g., the top surface of the uppermost insulating layer 112), the top surfaces of the dielectric walls 124, and the top surfaces of the remaining portions of the conductive material are substantially coplanar or planar with each other after completion of the planarization process. The remaining portions of the conductive material in the through holes TH form the conductive pillars 126.After the conductive pillars 126 are formed in contact with the channel layers 122, the sacrificial layers 114 are then replaced with gate layers 118 by a replacement process that will be described in more detail with reference to FIGS. 8A to 10A, 8B to 10B, and 8C to 10C.Referring to FIGS. 8A, 8B, and 8C, trenches TR 2 are formed in the multilayer stack 110. In the illustrated embodiment, the trenches TR 2 penetrate the remaining portions of the multilayer stack 110 that are present along the direction Z after the recesses R are formed (as described with reference to FIGS. 3A and 3B ). In order to avoid ambiguity and to simplify the discussion, the remaining portions of the multilayer stack 110 that are present after the recesses R are formed will be referred to as the remaining portions of the multilayer stack 110 in the following explanation. In detail, each of the trenches TR 2 is formed in one of the remaining portions of the multilayer stack 110 in a one-to-one relationship. From a different viewpoint, each of the trenches TR 2 in the illustrated embodiment vertically extends through all layers (e.g., all insulating layers 112 and all sacrificial layers 114) of the respective remaining portion of the multilayer stack 110 to expose the substrate 100. That is, each remaining portion of the multilayer stack 110 may be considered to be separated into two half parts by the respective trench TR 2. However, the disclosure is not limited thereto. In some alternative embodiments, the trenches TR 2 extend vertically through some, but not all, layers of the remaining portions of the multilayer stack 110. For example, the trenches TR 2 may extend through all the sacrificial layers 114 and expose the lowermost insulating layer 112.As shown in the plan view of FIG. 8A and the plan view of FIG. 8C, the trenches TR 2 extend laterally along the direction Y and are arranged along the direction X. Further, the two half parts of each remaining portion of the multilayer stack 110 are laterally spaced apart from each other by one of the trenches TR 2 after the formation of the trenches TR 2. In some embodiments, the trenches TR 2 have a width w 7 along the direction X (see, for example, FIG. 8B ) of about 5 nm to about 20 nm. That is, the two half parts of each remaining portion of the multilayer stack 110 are laterally spaced apart from each other by the separation distance equal to the width w 7 of the respective trench TR 2. Further, as shown in FIG. 8B, the trenches TR 2 expose the remaining sacrificial layers 114 in each half of the remaining portions of the multilayer stack 110.In some embodiments, the method of forming the trenches TR 2 includes a lithography process and an etching process (for example, an anisotropic etching process). Since the substrate 100 has a sufficient etch selectivity to the materials in the multilayer stack 110, the substrate 100 may remain substantially intact during the etching process. In some embodiments in which the substrate 100 is formed of silicon carbide, the insulating layers 112 are formed of silicon oxide, and the sacrificial layers 114 are formed of silicon nitride, the trenches TR 2 are formed by dry etching using a fluorine-based gas (for example, C 4F 6) mixed with hydrogen (for example, H 2) or oxygen (for example, O 2). In some embodiments, the etching process for forming the trenches TR 2 may be similar to the etching process for forming the trenches TR 1 as described with reference to FIGS. 2A and 2B.Referring to FIGS. 9A, 9B, and 9C, the remaining sacrificial layers 114 are selectively removed to form gaps G between the insulating layers 112. Because the ferroelectric layers 120, the dielectric walls 124, and the conductive pillars 126 are connected to the insulating layers 112, the ferroelectric layers 120, the dielectric walls 124, and the conductive pillars 126 may support the insulating layers 112 and prevent the insulating layers 112 from breaking down after removing the remaining sacrificial layers 114. In some embodiments, the method of removing the remaining sacrificial layers 114 includes an isotropic etch process. Since the substrate 100, the insulating layers 112 and the ferroelectric layers 120 may have a sufficient etch selectivity to the sacrificial layers 114, the sacrificial layers 114 may be selectively removed during such an isotropic etch process.Referring to FIGS. 10A, 10B, and 10C, gate layers 118 are formed in the gaps G previously occupied by the sacrificial layers 114. In other words, the previously present sacrificial layers 114 in each half of the remaining portions of the multilayer stack 110 are replaced with the gate layers 118. After the gate layers 118 are formed, stack structures ST each including the insulating layers 112 and the gate layers 118 alternately stacked on the substrate 100 are formed. That is, after performing the replacement process on the remaining portions of the multilayer stack 110, as described with reference to FIGS. 8A to 10A, 8B to 10B, and 8C to 10C, the remaining portions of the multilayer stack 110 are transformed into the stack structures ST. In detail, as shown in FIGS. 8B and 10B, each remaining portion of the multilayer stack 110 is formed into two stack structures ST after performing the replacement process. Since the sacrificial layer 114, the respective ferroelectric layers 120, and the respective channel layers 122 in each remaining portion of the multilayer stack 110 are substantially on the same plane as described with reference to FIGS. 4A, 4B, and 4C, the gate layer 118 occupying the place of the sacrificial layer 114 in the stack structure ST is substantially on the same plane with the respective ferroelectric layers 120 and the respective channel layers 122.In some embodiments, the stack structures ST are laterally spaced apart from each other. In detail, as shown in FIGS. 10A, 10B, and 10C, two adjacent stack structures ST on opposite sides of one of the trenches TR 2 are laterally spaced apart from each other by this one of the trenches TR 2. In some embodiments, the two adjacent stack structures ST on opposite sides of one of the trenches TR 2 are laterally spaced apart from each other by the separation distance equal to the width w 7 of the trench TR 2, as described above with reference to FIGS. 8A, 8B, and 8C. Further, as shown in FIGS. 10A, 10B, and 10C, two adjacent stack structures ST on opposite sides of one of the dielectric walls 124 are laterally spaced apart from each other by the one of the dielectric walls 124, the respective ferroelectric layers 120, the respective channel layers 122, and the respective conductive pillars 126. As shown in the plan view of FIG. 10A and the plan view of FIG. 10C, the stack structures ST extend laterally along the direction Y and are arranged along the direction X. In some embodiments, the gate layers 118 have a thickness t 5 (see, for example, FIG. 10B ) that substantially corresponds to the thickness t 3 of the ferroelectric layers 120 along the direction Z. In some embodiments, the thickness t 5 of the gate layers 118 is about 15 nm to about 90 nm. In some embodiments, the gate layers 118 have a width w 8 along the direction X (see, for example, FIG. 10C ) of about 10 nm to about 50 nm.In some embodiments, each of the gate layers 118 is formed in a one-to-one relationship within one of the gaps G. As shown in FIGS. 10B and 10C, the gate layer 118 is formed to cover or contact the side surface of the ferroelectric layer 120 exposed by the respective gap G. In some embodiments, the side surfaces of the gate layers 118 exposed by the trenches TR 2 are substantially coplanar or planar with the side surfaces of the adjacent insulating layers 112 exposed by the trenches TR 2, as shown in FIG. 10B. However, the disclosure is not limited thereto. In some alternative embodiments, the side surface of each gate layer 118 exposed by the respective trench TR 2 is slightly recessed from the side surfaces of the adjacent insulating layers 112 exposed by the respective trench TR 2 by a non-zero distance. The non-zero distance is, for example, about 1 nm to about 5 nm.In some embodiments, the gate layers 118 are formed by the following steps. First, a gate material is formed over the substrate 100 to fill the trenches TR 2 and the gaps G between the insulating layers 112. In some embodiments, the gate material not only fills the gaps G and the trenches TR 2, but also covers the upper surfaces of the uppermost insulating layers 112 in the stack structures ST, the upper surfaces of the conductive pillars 126, and the upper surfaces of the dielectric walls 124. In some embodiments, the method of forming the gate material includes a deposition process, such as a CVD process or an ALD process. The gate material may include copper, tungsten, cobalt, aluminum, tungsten nitride, ruthenium, silver, gold, rhodium, molybdenum, nickel, cadmium, zinc, alloys thereof, combinations thereof, or the like. Thereafter, the portions of the gate material not covered by the insulating layers 112 in the stack structures ST are removed by an etching process such as an anisotropic etching process. The remaining portions of the conductive material form the gate layers 118. In other words, the insulating layers 112 in the stack structures ST may serve as shielding masks during the etching process and the patterning of the conductive material may be considered a self-aligned process. In some alternative embodiments, barrier layers may be formed between the gate layers 118 and the adjacent insulating layers 112 to prevent the metal elements of the gate layers 118 from diffusing into the adjacent insulating layers 112. The barrier layers may also have a function to increase adhesion between the gate layers 118 and the adjacent insulating layers 112, and may be referred to as adhesion layers in some examples. The barrier layers may include a metal nitride such as titanium nitride, tantalum nitride, molybdenum nitride, zirconium nitride, or hafnium nitride. In some other embodiments, the barrier layers and the gate layers 118 include conductive materials different from each other. For example, the gate layers 118 are formed of tungsten and the barrier layers are formed of titanium nitride.Referring to FIGS. 11A, 11B, and 11C, dielectric walls 128 are formed to fill the trenches TR 2. As shown in FIGS. 11A, 11B, and 11C, the dielectric walls 128 are in contact with the side surfaces of the insulating layers 112 exposed by the trenches TR 2 and the side surfaces of the gate layers 118 exposed by the trenches TR 2. In embodiments in which the side surface of each gate layer 118 exposed by the respective trench TR 2 is substantially coplanar or planar with the side surfaces of the adjacent insulating layers 112 exposed by the respective trench TR 2, the side surface of the dielectric wall 128 in contact with the side surfaces of the insulating layers 112 and the side surface of the gate layer 118 exposed by the respective trench TR 1 has a substantially planar profile. In some embodiments, as shown in FIGS. 11A, 11B, and 11C, the side surface of the dielectric wall 128 in contact with the side surfaces of the insulating layers 112 and the side surface of the gate layer 118 exposed by the respective trench TR 2 is substantially straight. However, the disclosure is not limited thereto. In embodiments in which the side surface of each gate layer 118 exposed by the respective trench TR 2 is slightly recessed from the side surfaces of the adjacent insulating layers 112 exposed by the respective trench TR 2, the side surface of the dielectric wall 128 in contact with the side surfaces of the insulating layers 112 and the side surface of the gate layers 118 exposed by the respective trench TR 2 has an uneven profile. In such cases, the dielectric walls 128 may have laterally protruding portions in contact with the side surfaces of the respective gate layers 118. In some embodiments, as shown in FIG. 11B, the lower surfaces of the dielectric walls 128 are in contact with the upper surface portion of the substrate 100 exposed by the trenches TR 2. However, the disclosure is not limited thereto. In some alternative embodiments, the bottom surfaces of the dielectric walls 128 are not in contact with the top surface portion of the substrate 100 exposed by the trenches TR 2. For example, the lower surfaces of the dielectric walls 128 may be in contact with the lowermost insulating layer 112.In some embodiments, the dielectric walls 128 are formed by the following steps. A dielectric material is formed to fill the trenches TR 2. The dielectric material may include silicon nitride, silicon oxide, silicon oxynitride, phosphosilicate glass (PSG), borosilicate glass (BSG), boron doped phosphosilicate glass (BPSG), or the like, or a combination thereof, and may be formed by a suitable deposition process such as a CVD process or an ALD process. After the dielectric material is formed, a planarization process such as a chemical mechanical planarization (CMP) process, an etching process, or a combination thereof may be performed to remove portions of the dielectric material outside the trenches TR 2. In some embodiments, the portions of the dielectric material removed by the planarization process are over the top surfaces of the top insulating layers 112 in the stack structures ST. That is, the planarization process exposes the stack structures ST such that the top surfaces of the stack structures ST (e.g., the top surfaces of the uppermost insulating layers 112) and the top surfaces of the remaining portions of the dielectric material are substantially coplanar or planar with each other after completion of the planarization process. The remaining portions of the dielectric material in the trenches TR 2 form the dielectric walls 128.As shown in the plan view of FIG. 11C, the dielectric walls 128 extend laterally along the direction Y. Further, as shown in the plan view of FIG. 11C, each of the dielectric walls 128 is disposed between two adjacent stack structures ST. That is, two adjacent stack structures ST on opposite sides of one of the dielectric walls 128 are laterally separated from each other by the one of the dielectric walls 128. In some embodiments, the dielectric walls 128 have a width w 9 along the direction X (see, e.g., FIG. 11B ) that substantially corresponds to the width w 7 of the trench TR 2 (see, e.g., FIG. 8B ) described with reference to FIGS. 8A to 8C. In some embodiments, the width w 9 of the dielectric walls 128 is about 5 nm to about 20 nm.To this end, the three-dimensional storage device 10 according to some embodiments of the present disclosure is formed. Referring to FIGS. 11A, 11B, and 11C, the three-dimensional memory device 10 includes the stack structures ST laterally spaced apart from each other, each of the stack structures ST having the insulating layers 112 and the gate layers 118 alternately stacked on the substrate 100. In detail, the stack structures ST are laterally spaced apart from each other by dielectric walls (e.g., the dielectric walls 124 and the dielectric walls 128). Further, the three-dimensional memory device 10 also includes the ferroelectric layers 120 between two adjacent insulating layers 112 in each of the stack structures ST, the channel layers 122 between two adjacent insulating layers 112 in each of the stack structures ST, and the conductive pillars 126 vertically penetrating the dielectric walls 124, which are laterally separated from each other and are in contact with the channel layers 122 in each of the stack structures ST. As shown in FIGS. 11B and 11C, one of the gate layers 118 in each stack structure ST lies substantially in the same plane as one of the ferroelectric layers 120 and one of the channel layers 122. That is, a gate layer 118, a ferroelectric layer 120, and a channel layer 122 in each stack structure ST are collectively disposed between the same underlying insulating layer 112 and the same overlying insulating layer 112. Therefore, the gate layer 118, the ferroelectric layer 120, and the channel layer 122, which are substantially on the same plane, may be collectively referred to as a stack layer of the stack structure ST. Therefore, the stack structure ST may be considered to include stack layers (each including a gate layer 118, a ferroelectric layer 120, and a channel layer 122) and insulating layers 112 alternately stacked on the substrate 100.As shown in FIG. 11C, a portion of the gate layer 118, portions of the ferroelectric layer 120 and the channel layer 122 that are in the same stack layer as the gate layer 118 and laterally adjacent to the portion of the gate layer 118, and portions of the two adjacent conductive pillars 126 that are laterally adjacent to the portion of the gate layer 118 in each of the stack structures ST form a field effect transistor (FET) that serves as a memory cell MC. That is, the memory cell MC may be considered to include a pair of the conductive pillars 126, a channel layer 122, a ferroelectric layer 120, and a gate layer 118. In a memory cell MC, one of the pair of conductive pillars 126 serves as a source terminal of the memory cell MC, and another one of the pair of conductive pillars 126 serves as a drain terminal of the memory cell MC. Dipole moments in opposite directions can be stored in the ferroelectric layer 120. Thus, the FET has different threshold voltages from each other, which correspond to the dipole moments. Thus, the FET may be identified as being in a respective logic state. In these embodiments, the memory cell MC is a ferroelectric FET.As shown in FIGS. 11B and 11C, the stack layers (each including a gate layer 118, a ferroelectric layer 120, and a channel layer 122) stacked in each stack structure ST along the direction Z (for example, the vertical direction) and portions of pairs of the conductive pillars 126 adjacent to the stack layers form a stack of memory cells MC. Further, as shown in FIGS. 11A, 11B, and 11C, a plurality of stacks of the memory cells MC are arranged along the direction X (for example, the horizontal direction) and the direction Y (for example, the horizontal direction). That is, the multiple stacks of the memory cells MC are arranged separately from each other in an array of rows and columns. In detail, the multiple stacks of the memory cells MC are arranged apart from each other to have multiple columns along the direction Y and multiple rows along the direction X.As shown in FIGS. 11B and 11C, each of the channel layers 122 is shared by the respective column of memory cells MC along the direction Y, and thus conductive channels of these memory cells MC are formed in different portions of the channel layer 122. Further, as shown in FIGS. 11B and 11C, laterally adjacent memory cells MC on opposite sides of one of the dielectric walls 128 are separated from each other by the one of the dielectric walls 128. That is, the gate layers 118 of the laterally adjacent memory cells MC on opposite sides of one of the dielectric walls 128 are physically and electrically separated from each other. In other words, the laterally adjacent memory cells MC have two separate, independent gate layers 118 on opposite sides of one of the dielectric walls 128. Consequently, the interference between the laterally adjacent memory cells on opposite sides of one of the dielectric walls 128 in the three-dimensional memory device 10 can be effectively prevented. Further, as shown in FIGS. 11B and 11C, laterally adjacent memory cells MC on opposite sides of one of the dielectric walls 124 are separated from each other by the one of the dielectric walls 124. That is, the pairs of conductive pillars 126 in the laterally adjacent memory cells MC on opposite sides of one of the dielectric walls 124 are physically and electrically separated from each other. In other words, the laterally adjacent memory cells MC on opposite sides of one of the dielectric walls 124 each have their own pairs of source and drain terminals. Consequently, the interference between the laterally adjacent memory cells on opposite sides of one of the dielectric walls 124 in the three-dimensional memory device 10 can be effectively prevented.Although not illustrated, the three-dimensional memory device 10 further includes bit lines and source lines electrically connected to the conductive pillars 126. The pair of conductive pillars 126 in each stack of memory cells MC is connected to one of the bit lines and one of the source lines. In some embodiments, the bit lines and the source lines extend along the direction X. In some embodiments, the conductive pillars 126 in adjacent stacks of memory cells MC may be connected to different bit lines and different source lines. Thus, the memory cells MC in adjacent stacks of memory cells MC may be controlled by different bit lines and different source lines, whereby noise between the memory cells MC in adjacent stacks of memory cells MC may be reduced. In embodiments where the conductive pillars 126 in adjacent stacks of memory cells MC are connected to different bit lines and different source lines, the bit lines and the source lines are disposed on opposite sides of the substrate 100. For example, the source lines extend below the substrate 100, while the bit lines extend above the stack structures ST. Another example is that the source lines extend above the stack structures ST, while the bit lines extend below the substrate 100. However, the disclosure is not limited thereto. In some alternative embodiments, the bit lines and the source lines may be disposed on the same side of the substrate 100. In such cases, the bit lines and the source lines are alternately arranged along the direction Y, each of the bit lines is electrically connected to the conductive pillars 126 in the same row, and each of the source lines is electrically connected to the conductive pillars 126 in the same row, and each of the bit lines and each of the source lines are perpendicular to the stack patterns ST.While the steps of the method are illustrated and described as a series of acts or events, the illustrated order of such acts or events is not to be considered limiting. Further, not all illustrated methods or steps are required to implement one or more embodiments of the present disclosure.FIG. 12 is an equivalent circuit diagram of the three-dimensional memory device as illustrated in FIGS. 11A, 11B, and 11C.Referring to FIGS. 11B, 11C, and 12, the gate layers 118 in each stack structure ST as illustrated in FIGS. 11B and 11C serve as word lines WL as shown in FIG. 12. Each word line WL connects the gate terminals G of the respective column of memory cells MC along the direction Y. Further, as illustrated in FIGS. 11B and 11C, each pair of conductive pillars 126 in one of the memory cells MC separately connects to the source and drain terminals S, D of the memory cells MC stacked along the direction Z as illustrated in FIG. 12. As shown in FIG. 12, the gate terminals G of each stack of the memory cells MC are each connected to one of the word lines WL. As shown in FIG. 12, the gate terminals G of the adjacent stacks of the memory cells MC are connected to different word lines WL, respectively. Further, the source terminals S of each stack of the memory cells MC are connected to each other by one of the respective pair of conductive pillars 126, and the drain terminals D of each stack of the memory cells MC are connected to each other by another one of the respective pair of conductive pillars 126. In other words, the channels CH are connected in parallel between the source and drain terminals S, D of each stack of the memory cells MC. Thus, each stack of the memory cells MC may be considered to be connected to each other by a NOR flash configuration, and the three-dimensional memory device 10 may be referred to as a three-dimensional NOR memory device.FIG. 13 is a schematic cross-sectional view illustrating a semiconductor structure 20 according to some embodiments of the disclosure.Referring to FIGS. 11A-11C and 13, the semiconductor structure 20 shown in FIG. 13 includes the three-dimensional memory device 10 as described with reference to FIGS. 11A-11C. In the embodiments where the substrate 100 of the three-dimensional memory device 10 is an etch stop layer, a CMOS integrated circuit LC may be underlying the substrate 100, and the CMOS integrated circuit LC may also be referred to as a CUA (CMOS under array). Although not illustrated, the gate layers 118 and the conductive pillars 126 may be routed to the CMOS integrated circuit LC, and the three-dimensional memory device 10 may be controlled by the CMOS integrated circuit LC.In some embodiments, the CMOS integrated circuit LC is formed on a semiconductor substrate 200. The semiconductor substrate 200 may be a semiconductor wafer or an SOI (Semiconductor on Insulator) wafer. The CMOS integrated circuit LC may include active devices formed on a surface region of the semiconductor substrate 200. In some embodiments, the active devices include MOS (Metal Oxide Semiconductor) transistors 202. The MOS transistors 202 may each include a gate structure 204 formed over the semiconductor substrate 200. In some embodiments, the gate structure 204 includes a gate electrode 206, a gate dielectric layer 208, and a gate spacer 210. The gate dielectric layer 208 may extend between the gate electrode 206 and the semiconductor substrate 200 and may or may not further cover a sidewall of the gate electrode 206. The gate spacer 210 may laterally surround the gate electrode 206 and the gate dielectric layer 208. Further, the MOS transistor 202 may include source / drain regions 212. The source / drain regions 212 may be formed in the semiconductor substrate 200 and are located on opposite sides of the gate structure 204. In some embodiments, the source / drain regions 212 may be epitaxial structures and protrude from a surface of the semiconductor substrate 200. It should be appreciated that while MOS transistors 202 are depicted as planar MOS transistors forming conductive channels (not shown) along the surface of semiconductor substrate 200, MOS transistors 202 may alternatively be fin-like MOS transistors (or referred to as FinFET), Gate All Around (GAA-FETs), or the like.In some embodiments, the CMOS integrated circuit LC further includes dielectric layers 214 stacked on the semiconductor substrate 200, and includes contact plugs 216 and interconnects 218 formed in the stack of dielectric layers 214. A lowermost dielectric layer 214 may laterally surround the gate structures 204 and cover the source / drain regions 212. Some of the contact plugs 216 may penetrate the lowermost of the dielectric layers 214 to form an electrical connection to the source / drain regions 212, while others of the contact plugs 216 are on the gate structures 204 and may form an electrical connection to the gate electrodes 206 of the gate structures 204. The interconnects 218 may extend onto the contact plugs 216 and are electrically connected to the contact plugs 216. The interconnects 218 may include conductive lines and conductive vias. The conductive lines each lie on one of the dielectric layers 214, while the conductive vias each penetrate one or more of the dielectric layers 214 and are electrically connected to one or more of the conductive lines.In some embodiments, the three-dimensional memory device 10 is disposed on the stack of dielectric layers 214. In these embodiments, the gate layers 118 and the conductive pillars 126 of the three-dimensional memory device 10 may be routed through conductive paths (not shown) to the interconnects 218 in the stack of dielectric layers 214 that extend through the substrate 100 and the top of the dielectric layers 214. For example, the gate layers 118 (or referred to as word lines) may be routed to word line drivers formed by some of the active devices interconnected by a portion of the interconnects 218, and the conductive pillars 126 may be routed to sense amplifiers formed by other of the active devices interconnected by another portion of the interconnects 218.FIG. 14 is a schematic top view of a three-dimensional storage device 30 in accordance with some alternative embodiments of the present disclosure. The three-dimensional storage device 30 illustrated in FIG. 14 is similar to the three-dimensional storage device 10 illustrated in FIG. 11C. Therefore, the same reference numerals are used to refer to the same or similar elements, and the detailed description thereof will be omitted here. The differences between the three-dimensional storage device 30 illustrated in FIG. 14 and the three-dimensional storage device 10 illustrated in FIG. 11C will be described below.Referring to FIG. 14, the three-dimensional memory device 30 further includes insulators 300 penetrating the dielectric walls 124, the insulating layers 112, and the channel layers 122 along the direction Z. In detail, each insulator 300 extends vertically through the respective dielectric wall 124, the respective insulating layers 112, and the respective channel layers 122. As shown in FIG. 14, each insulator 300 extends laterally to separate two adjacent channel layers 122 on opposite sides of the respective dielectric wall 124 along the direction X. That is, the insulator 300 extends laterally along the direction X between two adjacent stack structures ST at opposite sides of the respective dielectric wall 124. Further, as shown in FIG. 14, the insulator 300 is formed along the direction Y between the laterally adjacent memory cells MC in the column of the memory cells MC. That is, the channel layers 122 of the laterally adjacent memory cells MC in each column of memory cells MC are physically and electrically separated from each other along the direction Y. In other words, the laterally adjacent memory cells MC in each column of memory cells MC along the direction Y comprise two separate, independent channel layers 122. Consequently, the interference between the laterally adjacent memory cells in each column of memory cells MC along the direction Y in the three-dimensional memory device 30 can be effectively prevented. From another viewpoint, as shown in FIG. 14, the pair of conductive pillars 126 in each memory cell MC is disposed between two adjacent insulators 300 along the direction Y. Further, since the insulator 300 extends laterally between two adjacent columns of the memory cells MC on opposite sides of the respective dielectric wall 124 along the direction X, two pairs of conductive columns 126 in two adjacent memory cells MC are disposed on opposite sides of one of the dielectric walls 124 along the direction Y between the same two adjacent insulators 300. While nine insulators 300 are shown in FIG. 14 for illustrative purposes, those skilled in the art will appreciate that the number of insulators 300 may be more than shown in FIG. 14 and may be determined as needed and / or design layout.In the illustrated embodiment, the insulators 300 do not extend laterally through the ferroelectric layers 120 along the direction X. Different portions of the ferroelectric layer 120 may be independently polarized from each other, and thus the ferroelectric layer 120 may function to store values even if adjacent portions of the ferroelectric layer 120 corresponding to the laterally adjacent memory cells MC in each column of memory cells MC along the direction Y are not physically and electrically separated from each other. However, the disclosure is not limited thereto. In some alternative embodiments, each insulator 300 further extends laterally to separate the ferroelectric layers 120 at opposite sides of the respective dielectric wall 124 along the direction X.In some embodiments, the insulators 300 are laterally separated from each other. As shown in FIG. 14, the insulators 300 are separately arranged and have a plurality of columns along the direction Y, and adjacent columns of the insulators 300 are spaced apart from each other along the direction X. In the illustrated embodiment, the insulators 300 are laterally separated from the conductive pillars 126. However, the disclosure is not limited thereto. In some alternative embodiments, the insulators 300 may contact the conductive pillars 126.In some embodiments, the method of manufacturing the insulators 300 includes the following steps. First, after forming the conductive pillars 126, as described with reference to FIGS. 7A, 7B, and 7C, trenches penetrating the dielectric walls 124, the insulating layers 112, and the channel layers 122 along the direction Z are formed using a lithography process and an etching process. A mask pattern, for example a patterned photoresist, may be formed over the multilayer stack 110. The etching process may then be performed using the mask pattern as an etch mask to remove portions of the dielectric walls 124, the insulating layers 112 and the channel layers 122 to form the trenches. After the etching process is completed, the mask pattern (e.g., the patterned photoresist) may be removed by a suitable removal process such as ashing or stripping. In some embodiments, the etching process is an anisotropic etching process. Next, a dielectric material is formed to fill the trenches. The dielectric material may include silicon oxide, silicon nitride, silicon oxynitride, tetraethylorthosilicate (TEOS) oxide, undoped silicate glass, borophosphosilicate glass (BPSG), fused silica (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), low-k dielectric material, other suitable dielectric material, or combinations thereof. Exemplary Iok-k dielectric materials are FSG, carbon doped silicon oxide, Black Diamond® (Applied Materials, Santa Clara, California), xerogel, aerogel, amorphous fluorinated carbon, parylene, benzocyclobutene (BCB), SiLK™ (Dow Chemical, Midland, Michigan), polyimide, other low-k dielectric materials, or combinations thereof. The low-k dielectric material used in the insulators 300 between adjacent memory cells MC is capable of reducing the crosstalk or the coupling interference between the adjacent memory cells MC, thereby increasing the performance and reliability of the three-dimensional memory device 30. The dielectric material may be formed by a suitable deposition method, such as a CVD method or an ALD method. After the formation of the dielectric material, a planarization process, such as a CMP process, an etching process, or a combination thereof, may be performed to remove portions of the dielectric material outside of the trenches. In some embodiments, the portions of the dielectric material removed by the planarization process overlie the top surface of the uppermost insulating layer 112, the top surfaces of the dielectric walls 124, and the top surfaces of the conductive pillars 126. That is, the planarization process exposes the multilayer stack 110, the dielectric walls 124, and the conductive pillars 126 such that the top surface of the multilayer stack 110 (e.g., the top surface of the uppermost insulating layer 112), the top surfaces of the dielectric walls 124, the top surfaces of the conductive pillars 126, and the top surfaces of the remaining portions of the dielectric material are substantially coplanar or planar with each other after completion of the planarization process. The remaining portions of the dielectric material in the trenches form the insulators 300. However, the disclosure is not limited thereto. In some alternative embodiments, the step of forming the insulators 300 may precede the step of forming the conductive pillars 126.FIG. 15 is a schematic top view of a three-dimensional memory device according to some alternative embodiments of the present disclosure. The three-dimensional storage device 40 illustrated in FIG. 15 is similar to the three-dimensional storage device 10 illustrated in FIG. 11C. Therefore, the same reference numerals are used to refer to the same or similar elements, and the detailed description thereof will be omitted here. The differences between the three-dimensional storage device 40 illustrated in FIG. 15 and the three-dimensional storage device 10 illustrated in FIG. 11C will be described below.Referring to FIG. 15, the conductive pillars 126 in the three-dimensional memory device 40 penetrate the dielectric walls 124 along the direction Z without penetrating the channel layers 122. That is, the conductive pillars 126 in each memory cell MC are laterally separated from the respective ferroelectric layer 120 by the respective channel layers 122. From another viewpoint, as shown in FIG. 15, each conductive pillar 126 is formed so as to be in lateral contact with one of the respective channel layers 122 via a side surface. Further, as shown in FIG. 15, the conductive pillars 126 disposed in the same dielectric wall 124 are laterally separated from each other by the dielectric wall 124. Further, although not illustrated, the three-dimensional memory device 40 may further include insulators between the laterally adjacent memory cells MC along the direction Y, as described with reference to FIG. 14.In the foregoing embodiments with reference to Figs. 1-15, the conductive pillars 126 in the same row of the array are all aligned with each other. However, the disclosure is not limited thereto. In some alternative embodiments, the conductive pillars 126 may be arranged in an offset configuration from one another. Hereinafter, other configurations of the three-dimensional storage device will be discussed in conjunction with FIG. 16.FIG. 16 is a schematic top view of a three-dimensional memory device according to some alternative embodiments of the present disclosure. The three-dimensional storage device 50 illustrated in FIG. 16 is similar to the three-dimensional storage device 10 illustrated in FIG. 11C. Therefore, the same reference numerals are used to refer to the same or similar elements, and the detailed description thereof will be omitted here. The differences between the three-dimensional storage device 50 illustrated in FIG. 16 and the three-dimensional storage device 10 illustrated in FIG. 11C will be described below.Referring to FIG. 16, the conductive pillars 126 are formed in the three-dimensional memory device 50 in an offset configuration from each other. In detail, the columns of the conductive pillars 126 are alternately offset from each other along the same direction (e.g., the direction Y). For example, even columns of the conductive pillars 126 are offset from odd columns of the conductive pillars 126 along the direction Y. In some embodiments, as shown in FIG. 16, the columns of the conductive pillars 126 are alternately offset from each other along the direction Y by a substantially identical offset amount. In addition, although not illustrated, the three-dimensional memory device 50 further includes bit lines and source lines electrically connected to the conductive pillars 126. In embodiments in which columns of the conductive pillars 126 are alternately offset from each other, the conductive pillars 126 in adjacent stacks of memory cells MC may be connected to different bit lines and different source lines. In some embodiments, the source lines and the bit lines all extend over the stack structures ST. However, the disclosure is not limited thereto. In some alternative embodiments, the bit lines and the source lines are disposed on opposite sides of the substrate 100. Further, although not illustrated, the three-dimensional memory device 50 may further include insulators between the laterally adjacent memory cells MC along the direction Y, as described with reference to FIG. 14.The invention is defined by the main claim and the subordinate claims. The dependent claims represent further embodiments of the invention.

Claims

A three-dimensional memory device comprising: a first stack structure (ST) comprising first stack layers and first insulating layers (112) alternately stacked on a substrate (100) along a vertical direction (Z), wherein each of the first stack layers comprises a first gate layer (118), a first ferroelectric layer (120) and a first channel layer (122), wherein the first gate layer, the first ferroelectric layer and the first channel layer each extend along a horizontal direction (Y) perpendicular to the vertical direction, and wherein the first ferroelectric layer is arranged between the first gate layer and the first channel layer; a second stack structure (ST) laterally spaced from the first stack structure (ST) and comprising second stack layers and second insulating layers (112) alternately stacked on the substrate (100) along the vertical direction (Z), each of the second stack layers comprising a second gate layer (118), a second ferroelectric layer (120) and a second channel layer (122), wherein the second gate layer, the second ferroelectric layer and the second channel layer each extend along the horizontal direction (Y), wherein the second ferroelectric layer is disposed between the second gate layer and the second channel layer, and wherein the first gate layer (118) and the second gate layer are disposed between the first ferroelectric layer (120) and the second ferroelectric layer; first conductive pillars (126) extending along the vertical direction (Z) are laterally separated from each other and are in contact with the first channel layer (122) of each of the first stack layers; second conductive pillars (126) extending along the vertical direction (Z) are laterally separated from each other and are in contact with the second channel layer (122) of each of the second stack layers; and a dielectric wall (128) disposed between the first stack structure (ST) and the second stack structure (ST), the dielectric wall being disposed between the first gate layer (118) of each of the first stack layers and the second gate layer (118) of each of the second stack layers.The three-dimensional memory device of claim 1, wherein the first conductive pillars (126) penetrate the first channel layer (122) of each of the first stack layers along the vertical direction (Z), and wherein the second conductive pillars (126) penetrate the second channel layer (122) of each of the second stack layers along the vertical direction.The three-dimensional memory device of claim 1 or 2, wherein the first conductive pillars (126) are in contact with the first ferroelectric layer (120) of each of the first stack layers, and wherein the second conductive pillars (126) are in contact with the second ferroelectric layer (120) of each of the second stack layers.The three-dimensional memory device of any preceding claim, wherein the first conductive pillars (126) are laterally separated from each other by the first channel layer (122) of each of the first stack layers, and wherein the second conductive pillars (126) are laterally separated from each other by the second channel layer (122) of each of the second stack layers.The three-dimensional memory device of claim 1 or 2, wherein the first conductive pillars (126) are laterally separated from the first ferroelectric layer (120) of each of the first stack layers by the first channel layer (122) of each of the first stack layers, and wherein the second conductive pillars (126) are laterally separated from the second ferroelectric layer (120) of each of the second stack layers by the second channel layer (122) of each of the second stack layers.The three-dimensional memory device according to any one of the preceding claims, further comprising: first insulators (300) penetrating the first channel layer (122) of each of the first stack layers along the vertical direction (Z) and being laterally separated from each other; and second insulators (300) penetrating the second channel layer (122) of each of the second stack layers along the vertical direction (Z) and being laterally separated from each other.The three-dimensional memory device of claim 6, wherein two of the first conductive pillars (126) are disposed between two adjacent first insulators (300), and wherein two of the second conductive pillars (126) are disposed between two adjacent second insulators (300).The three-dimensional memory device according to any one of claims 1 to 5, wherein the first channel layer (122) extends continuously in the horizontal direction (Y) between adjacent first conductive pillars (126), and the second channel layer (122) extends continuously in the horizontal direction (Y) between adjacent second conductive pillars (126).A three-dimensional memory device comprising: a first stack structure (ST) and a second stack structure (ST) disposed on a substrate (100) and laterally spaced apart from each other, wherein the first stack structure comprises first insulating layers (112) and first gate layers (118) alternately stacked on the substrate, and wherein the second stack structure comprises second insulating layers and second gate layers (118) alternately stacked on the substrate; a dielectric wall (124) disposed on the substrate (100) and between the first stack structure (ST) and the second stack structure (ST); first ferroelectric layers (120) arranged between the dielectric wall (124) and the first gate layers (118), each of the first ferroelectric layers being arranged between two adjacent first insulating layers (112); first channel layers (122) arranged between the dielectric wall (124) and the first ferroelectric layers (120), each of the first channel layers being arranged between two adjacent first insulating layers (112); second ferroelectric layers (120) arranged between the dielectric wall (124) and the second gate layers (118), each of the second ferroelectric layers being arranged between two adjacent second insulating layers (112); second channel layers (122) arranged between the dielectric wall (124) and the second ferroelectric layers (120), each of the second channel layers being arranged between two adjacent second insulating layers (112); first conductive pillars (126) penetrating the dielectric wall (124), being laterally separated from each other and being in contact with the first channel layers (122); and second conductive pillars (126) penetrating the dielectric wall (124), being laterally separated from each other and being in contact with the second channel layers (122).The three-dimensional memory device of claim 9, wherein the dielectric wall (124) is in contact with side surfaces of the first insulating layers (112), side surfaces of the second insulating layers (112), side surfaces of the first channel layers (122), and side surfaces of the second channel layers (122).The three-dimensional memory device of claim 10, wherein side surfaces of the first gate layers (118) are laterally recessed from the side surfaces of the first insulating layers (112), and wherein the first ferroelectric layers (120) are in contact with the respective side surfaces of the first gate layers; and wherein the side surfaces of the second gate layers (118) are laterally recessed from the side surfaces of the second insulating layers (112), and wherein the second ferroelectric layers (120) are in contact with the respective side surfaces of the second gate layers.The three-dimensional memory device of any of claims 9 to 11, wherein each of the first gate layers (118), each of the second gate layers (118), each of the first ferroelectric layers (120), each of the first channel layers, each of the second ferroelectric layers (120), and each of the second channel layers extend laterally along a first direction (Y) above the substrate (100), and wherein the dielectric wall (124), each of the first conductive pillars (126), and each of the second conductive pillars (126) extend vertically along a second direction (Z) perpendicular to the first direction.The three-dimensional memory device of claim 12, wherein the first conductive pillars (126) penetrate the dielectric wall (124) and the first channel layers (122) along the second direction (Z), and wherein the second conductive pillars (126) penetrate the dielectric wall and the second channel layers (122) along the second direction.The three-dimensional memory device of claim 12, wherein the first conductive pillars (126) penetrate the dielectric wall (124) along the second direction (Z) without penetrating the first channel layers (122), and wherein the second conductive pillars (126) penetrate the dielectric wall along the second direction without penetrating the second channel layers (122).The three-dimensional memory device according to any one of claims 12 to 14, further comprising: insulators (300) disposed on the substrate (100), penetrating through the dielectric wall (124), the first channel layers (122), and the second channel layers (122) along the second direction (Z), and extending laterally along a third direction (X) perpendicular to the first direction (Y) and the second direction (Z) between the first stack structure (ST) and the second stack structure (ST).The three-dimensional memory device according to claim 15, wherein two of the first conductive pillars (126) and two of the second conductive pillars (126) are disposed between two adjacent insulators (300) along the first direction (Y).A method comprising: forming a multilayer stack (110) on a substrate (100), the multilayer stack having insulating layers (112) and sacrificial layers (114) alternately stacked on the substrate; forming a trench (TR1) vertically penetrating the multilayer stack (110); removing portions of the sacrificial layers (114) exposed by the trench (TR1) to form recesses (R), each of the recesses being formed between two adjacent insulating layers (112); forming ferroelectric layers (120) in the recesses (R) to cover the side surfaces of the remaining portions of the sacrificial layers (114) exposed by the recesses; forming channel layers (122) in the recesses (R) to be in contact with the ferroelectric layers (120); Filling the trench (TR1) with a dielectric material to form a dielectric wall (124); forming conductive pillars (126) vertically penetrating the dielectric wall (124); and replacing the remaining portions of the sacrificial layers (114) with gate layers (118).The method of claim 17, wherein the insulating layers (112) and the sacrificial layers (114) include materials having mutually different etch selectivities.The method of claim 17 or 18, further comprising: forming insulators (300) vertically penetrating the dielectric wall (124) and the channel layers (122).The method of claim 17, 18 or 19, wherein replacing the remaining portions of the sacrificial layers (114) with the gate layers (118) comprises: forming trenches (TR2) vertically penetrating the multilayer stack (110); removing the remaining portions of the sacrificial layers (114) over the trenches (TR2) to form gaps (G), each of the gaps being formed between two adjacent insulating layers (112); and forming the gate layers (118) in the gaps (G).

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