Mesa contact for MOS-controlled power semiconductor device and method for manufacturing a power semiconductor device

Abstract

Power semiconductor device (1), comprising: - a semiconductor body (10) comprising a first surface (110) and a mesa portion (17), wherein the mesa portion (17) comprises a surface portion (175) of the first surface (110) and a body region (102); - at least two trenches (14) extending from the first surface (110) along a vertical direction (Z) into the semiconductor body (10), wherein each of the two trenches (14) comprises a trench electrode (141) and a trench insulator (142) insulating the trench electrode (141) from the semiconductor body (10), and wherein the mesa section (17) is laterally delimited by the two trenches (14) in a first vertical cross-section along a first lateral direction (X); - a contact plug (111) in contact with the body region (102), wherein the contact plug (111) laterally overlaps the entire trench electrode (141) of a first trench (14) of the two trenches (14) in the first vertical cross-section, and wherein the contact plug (111) only partially overlaps the mesa section (17) in the first vertical cross-section; and - a protective structure (145), wherein the protective structure - has a section arranged in the first trench (14); - is arranged between the contact plug (111) and the trench electrode (141) of the first trench (14); - extends along the vertical direction (Z) deeper than both the surface part (175) of the mesa section (17) and a trench cover (1423) of a second trench (14) of the two trenches (14); and - is an electrically insulating structure or a protective device structure.

Description

TECHNICAL FIELDThe present specification relates to embodiments of a power semiconductor device and to embodiments of a method of manufacturing a power semiconductor device. In particular, this document relates to embodiments in which a contact plug contacts a narrow mesa of the power semiconductor device.BACKGROUNDMany functions of modern devices in automotive, consumer and industrial applications, such as conversion of electrical energy and driving an electric motor or machine rely on power semiconductor switches. For example, insulated gate bipolar transistors (IGBTs), metal oxide semiconductor field effect transistors (MOSFETs), and diodes, to name a few, have been used for various applications including switches in power supplies and power converters.A power semiconductor device typically comprises a semiconductor body configured to conduct a forward load current along a load current path between two load terminals of the device.Further, in the case of a controllable power semiconductor device, for example a transistor, the load current path may be controlled by means of an insulated electrode commonly referred to as gate electrode. For example, upon receiving a corresponding control signal, for example from a driver unit, the control electrode may put the power semiconductor device in a forward conducting state or a blocking state.Often, the gate electrode may be included within a trench of the power semiconductor switch, wherein the trench may have a stripe configuration.Two adjacent trenches laterally delimit a portion of the semiconductor body, which is generally referred to as a mesa or mesa portion. Such a mesa is typically configured to provide a path of the forward load current by including, for example, a source region and a body region.In order to provide a path of the forward load current, the mesa must be electrically contacted with one of the load terminals of the power semiconductor device. Such a contact may be made, for example, by means of a contact plug structure according to which an electrically conductive material of a contact plug extends into a groove-like recess in a central portion of the mesa, in order to contact there both the source region and the body region. Alternatively, the contact plug is arranged over and in contact with a surface of the mesa in order to contact both the source region and the body region there.For various reasons, it may be desirable to keep the width of such a mesa, i.e. the distance between mutually opposite trench sidewalls of the adjacent trenches laterally delimiting the mesa, small.However, as the width of the mesa becomes smaller, it also becomes more difficult to reliably contact it based on a contact plug structure.US 2020 / 006687 A1 describes a power semiconductor having electrodes embedded in trenches, wherein a contact plug is used to contact both a semiconductor mesa section between two adjacent trenches and a subsection of one of the two trenches.SUMMARYAccording to an embodiment, a power semiconductor device comprises: a semiconductor body comprising a first surface and a mesa portion, wherein the mesa portion comprises a surface part of the first surface and a body region; at least two trenches extending from the first surface along a vertical direction into the semiconductor body, wherein each of the two trenches comprises a trench electrode and a trench insulator insulating the trench electrode from the semiconductor body, and wherein the mesa portion is laterally bounded by the two trenches in a first vertical cross section along a first lateral direction, a contact plug in contact with the body region, wherein the contact plug laterally overlaps the entire trench electrode of a first trench of the two trenches in the first vertical cross section, and wherein the contact plug only partially overlaps with the mesa portion in the first vertical cross section; and a protection structure. The protection structure includes a portion disposed in the first trench. The protection structure is arranged between the contact plug and the trench electrode of the first trench. The protection structure may be an electrically insulating structure or a protection device structure. For example, the protection structure extends along the vertical direction deeper than both the surface part of the mesa portion and a trench cover of a second trench of the two trenches. In another embodiment, the protection structure is arranged at or above the surface part of the mesa portion and / or at or above the trench cover of the second trench.According to another embodiment, a method of manufacturing a power semiconductor device comprises forming: a semiconductor body comprising a first surface and a mesa portion, wherein the mesa portion comprises a surface part of the first surface and a body region; at least two trenches extending from the first surface along a vertical direction into the semiconductor body, wherein each of the two trenches comprises a trench electrode and a trench insulator insulating the trench electrode from the semiconductor body; and wherein the mesa portion is laterally bounded by the two trenches in a first vertical cross section along a first lateral direction; a contact plug in contact with the body region, wherein the contact plug laterally overlaps the entire trench electrode of a first trench of the two trenches in the first vertical cross section, and wherein the contact plug only partially overlaps the mesa portion in the first vertical cross section; and a protection structure. The protection structure includes a portion disposed in the first trench. The protection structure is arranged between the contact plug and the trench electrode of the first trench. The protection structure may be an electrically insulating structure or a protection device structure. For example, the protection structure extends along the vertical direction deeper than both the surface part of the mesa portion and a trench cover of a second trench of the two trenches. In another embodiment, the protection structure is arranged at or above the surface part of the mesa portion and / or at or above the trench cover of the second trench.In the following, reference is made to both the method and the semiconductor device, unless otherwise stated.According to embodiments presented herein, the protection structure enables the use of a shared trench contact adjacent to a mesa for a device such as an IGBT, wherein a contact scheme is employed according to which the electrode of the trench adjacent to the mesa portion may not be connected to the emitter potential of the device, but to another potential such as a gate potential. In other words, a mesa contact window (e.g. an IGBT mesa or a diode mesa) has an overlap with the adjacent trench having a trench electrode that is not at the emitter / source potential at least in some locations. For example, the mesa connection electrode, i.e. the contact plug, is electrically insulated from the trench electrode adjacent to the mesa, e.g. at least at the locations where the mesa contacts overlap with the adjacent trench, wherein the electrical insulation may be established at least based on the protection structure. Furthermore, since lateral overlap with the contact plug and the trench electrode is possible, the width of the mesa portion may be comparatively small. Moreover, a low-cost metallization material such as a mixture of aluminum, silicon and copper (AlSiCu) may be used to form the contact plug.Some exemplary embodiments are described below. The features of these embodiments may be combined to form yet another embodiment unless expressly stated otherwise.In an embodiment, the power semiconductor device comprises a first load terminal on the first side and a second load terminal, wherein the semiconductor body is configured to conduct a load current between the first load terminal and the second load terminal, and wherein the trenches and the contact plug are arranged near or on the first side. One or both of the two trenches may be control trenches and its trench electrode(s) may be a control electrode insulated from the first load terminal and configured to control the load current in the mesa portion. For example, the power semiconductor device is an IGBT (or an RC-IGBT) or a MOSFET. The first load terminal can thus be an emitter terminal (also referred to as source terminal) and the second load terminal can be a collector terminal (also referred to as drain terminal). Another terminal such as a control / gate terminal may be disposed on the first side. The gate terminal may be electrically connected to the control trench electrode(s). The second load terminal may be disposed on a second side, which may be a back side.In an embodiment of the power semiconductor device, the first trench and the second trench may be configured similarly or even identically. For example, both the first trench and the second trench have the same trench depth (along the vertical direction) and / or the same trench width (along the first lateral direction). Further, the second trench may accommodate a trench electrode. The trench electrode of the first and second trench may have the same electrical potential or have different electrical potentials from one another.In an embodiment of the power semiconductor device, the first trench is a control trench and its trench electrode is a control electrode isolated from the first load terminal (e.g. an emitter terminal) of the device and configured to control the load current in the mesa portion. The second trench may also be a control trench. Or, the second trench is a source trench and its trench electrode is a source electrode electrically connected to the first load terminal.Since the trench electrode of the first trench may be electrically insulated from the contact plug, the trench electrode may be connected to any other potential or electrically floating. For example, the trench electrode may be connected to one of a gate potential of a gate terminal, to another gate potential, or to a measurement potential. For example, the trench electrode may also function as a gate resistor or a temperature resistorFurther, it should be appreciated that the power semiconductor device may comprise more than only two trenches and accordingly more than only one mesa portion. For example, the power semiconductor device includes an active region in which a plurality of (e.g., more than 100 or more than 1000) unit power cells are formed based on a plurality of trenches and mesa portions arranged side by side along the first lateral direction, for example. The trenches and the mesa may be arranged according to a pattern according to which, for example, each power unit cell includes one or more control trenches, zero or more source trenches, zero or more second control trenches, zero or more floating trenches, one or more IGBT mesa portions, zero or more diode mesa portions, zero or more dummy mesa portions arranged in a specific order along the first lateral direction. The terms used in this section are further described below. In one, in some or in each of the power unit cells, the exemplary provisions described here regarding the protective structure for at least one mesa section and at least one first trench of the respective power unit cell can be made, furthermore, a further protective structure can be provided for the second trench.Furthermore, a further protective structure may be provided for the second trench. Thus, everything described with respect to the protection structure and the first trench can equally also apply to an optional further protection structure and the second trench.In an embodiment of the power semiconductor device, the protection structure extends along the vertical direction deeper than a trench cover of the first trench. For example, the protection structure may thus be arranged below, e.g. completely below, the trench cover of the first trench. For example, both the trench cover of the first trench and the trench cover of the second trench are arranged between the trench electrode of the respective trench and the first load terminal (e.g. an emitter terminal) of the device.In an embodiment of the power semiconductor device, the contact plug protrudes into the first trench. Thereby, the lateral overlap with the trench electrode of the first trench may be formed.In an embodiment of the power semiconductor device, the trench electrode of the first trench may have a width in the first lateral direction that varies along the vertical direction. For example, in a portion of the first trench into which the protection structure and / or the contact plug extends / extend, the width of the trench electrode may be smaller compared to another portion of the first trench. For example, the portion of the first trench into which the protection structure and / or the contact plug extends / extend and where the trench electrode width may be reduced is an upper portion of the first trench.In an embodiment of the power semiconductor device, the width of the mesa portion in the first lateral direction is at most 1.5 μm or at most 600 nm or at most 200 nm.In an embodiment of the power semiconductor device, the trench insulator forms trench side walls (e.g. extending at least partially perpendicular to both the vertical cross section and the first lateral direction) and a trench bottom (e.g. extending at least partially perpendicular to the vertical cross section and parallel to the first lateral direction). The trench cover may also be formed by the same material as the trench insulator and / or by a different insulation structure and / or a different material.In an embodiment of the power semiconductor device, the contact plug is arranged entirely over the trench electrode of the first trench.In an embodiment of the power semiconductor device, the mesa portion includes a source region and the contact plug is also in contact with the source region. The source region may be insulated from a drift region by the body region. For example, the trench electrode of the first trench is configured to generate an inversion channel in the body region upon receipt of a corresponding control signal, e.g. from a driver unit. The source region and the drift region may both be regions of the first conductivity type, while the body region may be a region of the second conductivity type complementary to the first conductivity type.In an embodiment of the power semiconductor device, the contact plug extends further along the vertical direction than the source region. It should be noted here that the contact plug may either be configured as a flat contact which substantially terminates at the surface part of the mesa portion, or the contact plug may extend under the surface part of the mesa portion.In an embodiment of the power semiconductor device, the protection structure comprises a dielectric layer or is a dielectric layer. For example, such a dielectric layer may be configured such that the electrical potential of the trench electrode may be different from the electrical potential of the contact plug. For example, the contact plug may be electrically insulated from the trench electrode based at least on the protective structure (e.g. in the form of the dielectric layer).In an embodiment of the power semiconductor device, the protection structure is a protection device structure and forms part of an npn structure, a pnp structure, anti-parallel connected zener diodes, a Schottky diode structure or a punch-through structure. For example, based on the protection device structure, it may be ensured that a voltage between the contact plug and the trench electrode is limited to a maximum voltage at least partially defined by the protection device structure. The exemplary structures (npn structure, pnp structure, antiparallel-connected zener diodes, Schottky diode structure, punchthrough structure) can furthermore be formed by the contact plug and / or the trench electrode itself. For example, when the trench electrode of the first trench is formed by a p-type polycrystalline semiconductor material, a pnp structure may be used for forming anti-parallel connected zener diodes or a punch-through structure. Materials used to form the protection device structure may include one or more of a polycrystalline semiconductor material and a thin dielectric material.In an embodiment of the power semiconductor device, the contact plug comprises a first side surface, a second side surface and a bottom surface, wherein the first side surface abuts the first trench, the bottom surface abuts the body region and the second side surface abuts the source region. The two side surfaces may be arranged in a plane substantially parallel to both the vertical direction and the second lateral direction (which may be perpendicular to the first lateral direction). The bottom surface may be disposed in a plane substantially parallel to both the second lateral direction and the first lateral direction. For example, the contact plug thus makes contact with each of the body region, the source region, and the inner portion of the first trench, but without being in contact with the trench electrode of the first trench.According to the invention, the contact plug laterally overlaps with the entire trench electrode of the first trench in the first vertical cross section, wherein the contact plug in the first vertical cross section only partially laterally overlaps with the mesa section. In such an embodiment, the contact plug may further make contact with a body region of another mesa portion adjacent to the first trench, for example.In an embodiment, the power semiconductor device comprises at least two first trenches, wherein the contact plug laterally overlaps with the at least two first trenches in the vertical cross section. For example, no further trench may be arranged between the two first trenches (e.g. only a part of the semiconductor body, for example a mesa portion, may be laterally arranged between the two first trenches). Alternatively, at least one further trench (e.g. a second trench) can be arranged between the two first trenches.In some embodiments, the power semiconductor device may include a plurality of mesa sections, a plurality of first trenches and a plurality of second trenches, wherein each of the mesa sections is laterally bounded in the first vertical cross section by two of the trenches (e.g. by two first trenches or by one first trench and one second trench), wherein the contact plug laterally completely overlaps with the first trenches in the first vertical cross section.In an embodiment of the power semiconductor device, the contact plug is laterally spaced apart from the second trench along the first lateral direction in the first vertical cross section. The contact plug does not laterally overlap, for example, with the other of the two trenches laterally delimiting the mesa portion.In an embodiment of the power semiconductor device, the contact plug adjoins a portion of a trench sidewall of the first trench. For example, the contact plug may extend from the mesa portion into the first trench by crossing a lower part of the trench sidewall.In an embodiment of the power semiconductor device, a portion of the trench insulator of the first trench is located between the contact plug and the trench electrode of the first trench. For example, the contact plug may thus be insulated from the trench electrode based on at least one of the trench insulator and the protection structure.In an embodiment of the power semiconductor device, a lateral distance in the first lateral direction between the contact plug and the trench insulator of the other trench is at most 1 μm and / or at least 150 nm. In some examples, the lateral distance is at most 250 nm, e.g., at most 200 nm. As described above, the configuration of the contact plug and the trenches proposed here allows the mesa portion to be designed with a comparatively small mesa width while at the same time allowing the mesa portion based on the contact plug to be reliably contacted.In an embodiment of the power semiconductor device, the body region comprises a contact portion having a locally enhanced dopant concentration, wherein the contact plug abuts the contact portion of the body region. Furthermore, the contact portion can adjoin a portion of the trench insulator, wherein the portion of the trench insulator can also be contacted by the contact plug. Further, the contact portion may be arranged in the first lateral direction at a distance from the trench insulator of the second trench that is at least 20% of the width of the mesa portion in the first lateral direction. Thus, even if the source region is present in the mesa portion, it can be ensured that the source region adjoins a portion of the body region that is different from its contact portion, i.e. a portion that does not have the locally enhanced dopant concentration but has the lower regular dopant concentration of the body region, so that it is possible to generate an inversion channel in the body region for load current conduction.In an embodiment of the power semiconductor device, the first trench is a multi-trench electrode trench. Based on the protection structure and / or an additional isolation structure in the first trench, the first trench may be provided with more than one trench electrode, e.g. two or more trench electrodes, wherein the two or more trench electrodes may be spatially separated from each other along at least one of the first lateral direction, the second lateral direction and the vertical direction. Further, the two or more trench electrodes may have the same electric potential or electric potentials different from each other, e.g., two different gate potentials or a gate potential and a floating potential or a gate potential and a source potential, just to name a few examples.In an embodiment, the power semiconductor device further comprises a trench contact plug arranged in electrical contact with the trench electrode of the first trench, wherein the first trench is laterally structured along the second lateral direction such that both the protection structure and the contact plug are laterally spaced apart from the trench contact plug along the second lateral direction. The trench contact plug establishes an electrical connection between the trench electrode of the first trench and a gate runner structure or a gate finger structure of the device, for example, wherein the gate runner structure or a gate finger structure is electrically connected to the gate / control terminal of the device and extends into the edge termination region and / or the active region of the device. For example, the trench electrode of the first trench may be a control trench electrode electrically connected to a gate potential based on, e.g., the trench contact plug and / or the gate runner / finger structure.Those skilled in the art will recognize additional features and advantages upon reading the following detailed description and upon review of the accompanying drawings.BRIEF DESCRIPTION OF THE DRAWINGSThe parts in the figures are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the invention. Moreover, in the figures, like reference numerals designate corresponding parts. In the drawings, there are shown: FIGS. 1A-B both schematically and exemplarily show a portion of a vertical cross section of a power semiconductor device; FIGS. 2A-B both schematically and exemplarily show a portion of a horizontal projection of a power semiconductor device according to some embodiments; FIGS. 3 and 4 each schematically and exemplarily show a portion of a vertical cross section of a power semiconductor device according to some examples; FIG. 5 schematically and exemplarily shows a portion of a vertical cross section of a power semiconductor device according to one or more embodiments; FIGS. 6-7 both schematically and exemplarily show a portion of a horizontal projection of a power semiconductor device according to some examples; and FIG. 8 schematically and exemplarily illustrates, based on regions of a vertical cross section, a method of manufacturing a power semiconductor device according to some examples.DETAILED DESCRIPTIONIn the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced.In this regard, directional terminology, such as "top," "bottom," "below," "front," "behind," "back," "leading," "trailing," "above," etc., may be used with reference to the orientation of the figures being described. Since portions of embodiments may be positioned in a number of different orientations, directional terminology is used for purposes of illustration and is in no way limiting. It is understood that other embodiments may be utilized and structural or logical changes may be made.Reference will now be made in detail to various embodiments, one or more examples of which are illustrated in the figures. Each example is provided by way of explanation and is not intended to limit the invention. Features illustrated or described as part of one embodiment may be used, for example, in or in combination with other embodiments to obtain yet another embodiment. The present invention is intended to include such modifications and variations. The drawings are not to scale and are for illustrative purposes only. For clarity, the same elements or manufacturing steps have been denoted by the same reference numerals throughout the several drawings, unless otherwise indicated.The term "horizontal" as used herein is intended to describe an orientation substantially parallel to a horizontal surface of a semiconductor substrate or structure. This may be, for example, the surface of a semiconductor wafer or a die or a chip. For example, both the first lateral direction X and the second lateral direction Y mentioned below may be horizontal directions, wherein the first lateral direction X and the second lateral direction Y may be perpendicular to each other.The term "vertical" as used herein is intended to describe an orientation that is substantially perpendicular to the horizontal surface, i.e., parallel to the normal direction of the surface of the semiconductor wafer / die / die. For example, the extension direction Z mentioned below may be an extension direction perpendicular to both the first lateral direction X and the second lateral direction Y. The extension direction Z is also referred to herein as "vertical direction Z".In this specification, n-doped is referred to as "first conductivity type", while p-doped is referred to as "second conductivity type". Alternatively, opposite doping relationships may be used such that the first conductivity type may be p-doped and the second conductivity type may be n-doped.As used herein, the terms "in ohmic contact", "in electrical contact", "in ohmic connection" and "electrically connected" are intended to describe that there is a low ohmic electrical connection or current path between two regions, regions, zones, portions or parts of a semiconductor device or between different terminals of one or more devices or between a terminal or metallization or an electrode and a region or part of a semiconductor device, wherein "low ohmic" may mean that the properties of the respective contact are substantially not affected by the ohmic resistance. Further, as used herein, the term "in contact" is intended to describe that there is a direct physical connection between two elements of the respective semiconductor device; for example, a transition between two elements in contact with each other may not include a further interposer or the like.Moreover, the term "electrical insulation" is used within the scope of its generally valid understanding, unless otherwise stated, and is thus intended to describe that two or more components are arranged separately from one another and that there is no ohmic connection connecting these components. However, components electrically insulated from one another may nevertheless be coupled to one another, for example mechanically coupled and / or capacitively coupled and / or inductively coupled. To name an example, two electrodes of a capacitor may be electrically insulated from each other and simultaneously mechanically and capacitively coupled to each other, for example by means of an insulation, for example a dielectric.Specific embodiments described herein relate to a power semiconductor device, e.g., a power semiconductor device, that may be used in a power converter or power supply. Thus, in one embodiment, such a device may be configured to carry a load current to be supplied to a load or to be respectively provided by a power source. For example, the power semiconductor device may comprise one or more active power semiconductor unit cells, such as a monolithically integrated diode cell, a derivative of a monolithically integrated diode cell (e.g. a monolithically integrated cell of two anti-series connected diodes), a monolithically integrated transistor cell, e.g. a monolithically integrated MOSFET or IGBT cell, and / or derivatives thereof. Such diode / transistor cells may be integrated in a power semiconductor module. A plurality of such cells may form a cell array disposed with an active region of the power semiconductor device.The term "power semiconductor device" as used herein is intended to describe a semiconductor device on a single chip with high voltage blocking and / or high current carrying capabilities. In other words, depending on the respective application, such a power semiconductor device is typically designed for a high current in the Ampere range, e.g. up to several tens or hundreds of Ampere, and / or high voltages, typically above 15 V, more typically 100 V and above, e.g. up to at least 400 V or even more, e.g. up to at least 3 kV or even up to 10 kV or more.For example, the term "power semiconductor device" as used herein is not directed to logic semiconductor devices used for storing data, computing data, and / or other types of semiconductor-based data processing, for example.The present document relates in particular to power semiconductor devices configured as respective MOSFETs or IGBTs, i.e. unipolar or bipolar power semiconductor transistors controlled by insulated electrodes (gates), or a derivative thereof.The power semiconductor device described below may be a single semiconductor chip having a strip cell configuration (rather than a cellular configuration / needle cell configuration) and may be configured to be employed as a power component in a low, medium and / or high voltage application. The technical teaching proposed here can also be applied to a power semiconductor device having a cellular configuration / needle cell configuration.FIGS. 1A-B schematically and exemplarily illustrate a range of a vertical cross section of a power semiconductor device 1. The power semiconductor device 1 may be based on a single chip.Referring to FIG. 2A, the power semiconductor device 1 may include an active region 1- 2 having a number of power unit cells 1- 1 arranged according to a stripe cell configuration as schematically illustrated in FIG. 2B. Accordingly, an extension in the second lateral direction Y of each power unit cell 1- 1 may amount to a multiple of the extension in the first lateral direction X. However, as stated above, the technical teaching proposed herein may also be applied to a power semiconductor device having a cellular cell configuration (also referred to as cellular cell configuration or pillar-shaped cell configuration) in which the extension in the second lateral direction Y of each power unit cell would be in a similar range as the extension in the first lateral direction X.An edge termination region 1- 3 of the power semiconductor device 1 may surround the active region 1- 2. Thus, the edge termination region 1- 3 may be arranged outside the active region 1- 2 and / or may adjoin the active region 1- 2. The edge termination region 1- 3 is laterally terminated by an edge 1- 4. The edge 1- 4 may form the chip edge of the power semiconductor device 1.As used herein, the terms "edge termination region" and "active region" are assigned the respective technical meaning typically ascribed to them to those skilled in the art in connection with power semiconductor devices. That is, the active region 1- 2 is configured primarily for load current conduction and (if applicable) for switching purposes, while the edge termination region 1- 3 serves primarily functions with respect to reliable blocking capabilities, suitable electric field guidance, sometimes also carrier dissipation functions and / or further functions with respect to protection and suitable termination of the active region 1- 2.Referring again to FIG. 1A, the power semiconductor device 1 includes a semiconductor body 10 having a first side 110, which may be a front side and is formed by, e.g., a semiconductor body surface (and is thus also referred to herein as first surface 110), and a second side 120, which may be a back side. The front side 110 and the back side 120 may vertically terminate the semiconductor body 10. That is, the semiconductor body 10 may have a total thickness d along the vertical direction Z between the front side 110 and the back side 120. In the lateral directions, the semiconductor body 10 may be terminated by the edge 1- 4 (not shown in FIG. 1A ). Furthermore, both the front side 110 and the rear side 120 may extend laterally along both the first lateral direction X and the second lateral direction Y. For example, both the front side 110 and the back side 120 may form a respective horizontal surface of the semiconductor body 10. The thickness d of the semiconductor body 10 may be the distance between the front side 110 and the back side 120 along the vertical direction Z in the active region 1- 2, for example measured at the center of the active region 1- 2.The semiconductor body 10 forms a part of both the active region 1- 2 and the edge termination region 1- 3. For example, the possible configurations of the power unit cell(s) 1- 1 described below are primarily implemented in the semiconductor body 10. The semiconductor body 10 is configured in the active region 1- 2 to conduct a forward load current between a first load terminal 11 and a second load terminal 12.For example, a first load terminal 11 is arranged on the semiconductor body front side 110 and a second load terminal 12 is arranged on the semiconductor body rear side 120. For example, the first load terminal 11 comprises a front side metallization and / or the second load terminal 12 comprises a rear side metallization. For example, the first load terminal 11 is an emitter terminal and the second load terminal 12 is a collector terminal. At the front side 110, the semiconductor body 10 may adjoin the front side metallization. At the rear side 120, the semiconductor body 10 may adjoin the rear side metallization.In an embodiment, the first load terminal 11 (e.g. the front side metallization) laterally, i.e. along the first lateral direction X and / or the second lateral direction Y and / or combinations thereof, overlaps with the active region 1- 2. It should be noted that the first load terminal 11 may be laterally structured, for example, to produce local contacts with the semiconductor body 10 at the front side 110. As exemplarily illustrated in FIG. 1A, the local contacts may be formed by means of a contact plug 111' penetrating a first insulating layer 13, e.g. according to which an electrically conductive material extends into a groove-like recess in a middle portion of a mesa portion 17' to contact there both a source region 101' and a body region 102'.Analogously, in an embodiment, the second load terminal 12 (e.g. the back side metallization) laterally overlaps with the active region 1- 2, i.e. along the first lateral direction X and / or the second lateral direction Y and / or combinations thereof. It should be noted that the second load terminal 12 is generally not structured, but rather is formed homogeneously and monolithically on the semiconductor body rear side 120, in order to produce a laterally homogeneous contact with the semiconductor body 10, for example, on the rear side 120. Such a homogeneous structure may also be implemented in regions in which the second load terminal 12 laterally overlaps with the edge termination region 1- 3.For example, the lateral boundary of the active region 1- 2 is defined by the lateral boundary of the outermost power unit cell(s) 1- 1. Thus, the lateral boundary of the active region 1- 2 may be defined at the front side 110. This lateral boundary may be defined by one or more outermost source region(s) 101' (see the more detailed explanation below). For example, all functional elements for enabling the conduction of the load current are present in a vertical projection of the active region 1- 2 of the power semiconductor device 1, including, for example, at least the first load terminal 11 (e.g. a front side metal contact thereof, e.g. one or more of the contact plugs 111'), the source region(s) 101', the body region 102', a drift region 100, a back side emitter 103 and the second load terminal 12 (e.g. a back side metallization thereof).In an embodiment, the edge termination region 1- 3 and the active region 1- 2 may be arranged symmetrically to each other with respect to a central vertical axis of the power semiconductor device 1, for example, as exemplarily illustrated in FIG. 2A.Furthermore, according to an embodiment, the lateral transition between the active region 1- 2 and the edge termination region 1- 3 may extend exclusively along the vertical direction Z. As explained above, the lateral boundary of the active region 1- 2 may be defined at the front side 110, and a vertical projection along the vertical direction Z of such a defined lateral boundary may thus be observed at the back side 120.Referring back to FIG. 1A, an exemplary configuration of one of the power unit cells 1- 1 will be described. Each power unit cell 1- 1 of the power semiconductor device 1 may be configured the same. For example, each power unit cell 1- 1 comprises at least one trench 14 and at least one mesa portion 17'. In other embodiments, each power unit cell 1- 1 may include more than one trench 14 and more than one mesa portion 17', wherein the trenches 14 may be identically or differently configured and wherein the mesa portions 17' may be identically or differently configured.The second conductivity type body region 102' is included in the semiconductor body 10. The body region 102' may be arranged in electrical contact with the first load terminal 11 by means of the contact plug 111', for example. In each power unit cell 1- 1, at least one source region 101' of the first conductivity type is further provided, which is also arranged in electrical contact with the first load terminal 11, for example, by means of the contact plug 111'.A main part of the semiconductor body 10 is formed as the drift region 100 of the first conductivity type, which partially adjoins the body region 102' and forms a pn-junction 1021 therewith.The body region 102' may be arranged between the source regions 101' and / or the first surface 110 and the drift region 100, and may isolate the source regions 101' from the drift region 100.Each power unit cell 1- 1 is further assigned a trench electrode 141. The trench electrodes 141 may be arranged in a respective trench 14 and may be insulated from the semiconductor body 10 by means of a respective trench insulator 142. Upon receiving a corresponding control signal provided, e.g., by a gate driver unit not illustrated, each trench electrode 141 may generate an inversion channel in a portion of the body region 102' adjacent to the respective trench electrode 141. Thus, each of the plurality of power unit cells 1- 1 is configured to control at least a part of the load current between the first load terminal 11 and the second load terminal 12.In the basic configuration of the power unit cells 1- 1 of a power semiconductor device (e.g., a MOSFET, an IGBT, or RC-IGBT) described above, the terminology used (e.g., the term "power unit cells") is within the scope of technical meaning that the skilled person typically associates therewith.Furthermore, in addition to the configuration as control electrodes, other trench electrodes 141 that perform another function, such as dummy trench electrodes, source trench electrodes, floating trench electrodes, and the like, may be provided in some or each of the power unit cells 1- 1.As illustrated in FIG. 1A, the body region 102' extends from the front side 110 along the vertical direction Z until it abuts the drift region 100. The drift region 100, which may laterally overlap with the entire lateral area occupied by the number of power unit cells 1- 1, extends over a longer range along the vertical direction Z until it abuts a field stop layer 108 (also known as buffer layer), wherein the field stop layer 108 is also of the first conductivity type but has a higher dopant dose compared to the drift region 100. The field stop layer 108 typically has a substantially smaller thickness than the drift region 100. Furthermore, it extends along the vertical direction Z until it adjoins the rear side emitter 103. The back side emitter region 103 is arranged in electrical contact with the second load terminal 12, as is illustrated in FIG. 1A.In an IGBT, the back side emitter region 103 functions as a second conductivity type emitter. When the power semiconductor device 1 is implemented as an RC-IGBT, the back side emitter region 103 may further comprise some regions of the first conductivity type that exhibit a rather high dopant concentration (e.g. higher compared to the dopant concentration of the drift region 100), e.g. in the range of 10 16 cm -3 to 10 20 cm -3. In a MOSFET, the back side emitter region 103 acts as an emitter of the first conductivity type.With respect to the lateral extension of the backside emitter 103, the emitter region 103 may in an embodiment laterally overlap with at least 80% or at least 90% of a lateral area occupied by the number of power unit cells 1- 1 in the active region 1- 2. In an embodiment, the emitter region 103 may laterally overlap with the total (100% of the) lateral area occupied by the number of power unit cells 1- 1 in the active region 1- 2, like the drift region 100. In other embodiments, as illustrated in FIG. 2A, the emitter region 103 laterally overlaps with less than 100% of the lateral area occupied by the number of power unit cells 1- 1 in the active region 1- 2, for example, with about 80% to 90%.A most outer portion of the active region 1- 2 at the back side 120, which in such a case is laterally arranged "between" (cf. following explanation) the edge termination region 1- 3 and the back side emitter region 103 (also referred to herein as "emitter region 103" or "back side emitter 103"), may be occupied by a termination frame region 105 formed in the semiconductor body 10 at the back side 120.The termination frame region 105 may be of the second conductivity type (e.g. p-type) and may be arranged in electrical contact with the second load terminal 12. The termination frame region 105 is not illustrated in FIG. 1A, but may have a thickness along the vertical direction Z that is approximately as large as the thickness of the back side emitter 103. The termination frame region 105 may extend not only into the active region 1- 2 but also into the edge termination region 1- 3. The edge termination region 1- 3 may extend to the chip edge 1- 4. As explained above, depending on the lateral extension of the backside emitter 103 at the backside 120, the termination frame region 105 may extend either into the active region 1- 2 or the edge termination region 1- 3 or into both the active region 1- 2 and the edge termination region 1- 3. In an embodiment, the percentage of the lateral area of the active region 1- 2 at the back side 120 occupied by the termination frame region 105 amounts to at most 20% or at most 10%, however, in an embodiment, according to an embodiment.Furthermore, the termination frame region 105 may have a VLD profile (VLD, variation of the lateral doping) with decreasing dopant concentration in the direction towards the edge termination region 1- 3 and / or a VLD profile with increasing dopant concentration in the direction towards the emitter region 103.The termination frame region 105 is sometimes also referred to as a high dynamic robustness (HDR) region and may be constructed as an interface region between the back side emitter 103 and the semiconductor body part in the edge termination region 1- 3 to be able to contribute to the appropriate electric field strengths in the semiconductor body 10, which are favorable in terms of the robustness of the power semiconductor device 1, for example.It should be emphasized that the power semiconductor device 1 can also be configured as a MOSFET, with the corresponding consequences with respect to the configuration of the semiconductor regions 103 and 108, or as a device deviating from a MOSFET configuration or an IGBT configuration.The aspects of the power semiconductor device 1 described above relate to an exemplary basic configuration of the power semiconductor device 1. embodiments described herein relate to a new design relating to the contact between the first load terminal 11 and the mesa portions 17', and optionally also to the mesa configuration with respect to the source region 101' and the body region 102'. In particular, since these aspects may be modified according to the embodiments disclosed herein, in the following description, reference is made to the body region with reference numeral 102, to the source region with reference numeral 101, to the mesa portion with reference numeral 17, and to the contact plug with reference numeral 111, while the other reference numerals introduced above do not denote components that are forcibly different from those introduced with reference to FIGS. 1A-2B, and are used in the same manner below accordingly. As will be apparent from the following description, the configuration of the trenches 14 may also change compared to the configuration illustrated in FIGS. 1A-B.For various reasons, it may be desirable to keep the width WMof the mesa portion, i.e. the distance between mutually opposite trench sidewalls of the adjacent trenches 14 laterally delimiting the mesa portion, small. However, as the mesa width WMbecomes smaller, it also becomes more difficult to reliably contact the mesa portion 17 (e.g., the source region 101 and / or the body region 102) with a contact plug 111' in a manner illustrated in FIGS. 1A-B. Referring to FIG. 1B, the contact plug 111' extends through an isolation structure 13, 18, for example, into a central region of the mesa portion 17' to contact both the source region 101' and a contact part 1022' of the body region 102' in the mesa portion 17'. In a portion of the body region 102' adjoining the trench insulators 142 under the source region 101, an inversion channel is generated. For this reason, it is generally desirable that the contact portion 1022' of the body region 102' is laterally offset from the trench insulator 142 of the trench 14 having the trench electrode 141 generating the inversion channel. As the mesa width WM becomes smaller, the design target may become difficult to achieve.Each of Examples (a)-(f) of FIG. 3 schematically and exemplarily illustrates a range of a vertical cross section of the power semiconductor device 1.For example, the power semiconductor device 1: includes the semiconductor body 10 including the first surface 110 and the mesa portion 17. The mesa portion 17 includes a surface part 175 of the first surface 110 and the body region 102. At least two trenches 14 extend from the first surface 110 along the vertical direction Z into the semiconductor body 10, wherein each of the two trenches 14 comprises the trench electrode 141 and the trench insulator 142 insulating the trench electrode 141 from the semiconductor body 10. The mesa section 17 is laterally bounded by the two trenches 14 in a first vertical cross section along the first lateral direction X. A contact plug 111 is in contact with the body region 102. The contact plug 111 and the trench electrode 141 of a first trench ( 14) of the two trenches 14 (here the first trench 14 may be the trench 14 on the right side of the mesa section 17 illustrated in FIG. 3 ) overlap laterally at least partially in the first vertical cross section. The power semiconductor device 1 includes a protection structure 145. The protection structure has a portion disposed in the first trench 14. The protection structure 145 is disposed between the contact plug 111 and the trench electrode 141 of the first trench 14. The protection structure 145 is an electrically insulating structure or a protection device structure (examples of which will be described below). For example, the protection structure 145 extends along the vertical direction Z deeper than both the surface part 175 of the mesa portion 17 and a trench cover 1423 of a second trench ( 14) of the two trenches (here, the second trench 14 may be the trench 14 on the left side of the mesa portion 17 illustrated in FIG. 3 ).Reference is made to each of Examples (a) to (f) of Fig. 3. According to each example (a) to (f) of FIG. 3, the body region 102 forms a pn junction 1021 with a first conductivity type region (e.g. a region of the drift region 100) in the mesa portion 17.Further, both trenches 14 laterally delimiting the mesa portion 17 may be control trenches 14, wherein the trench electrodes 141 are electrically connected to a gate / control terminal (not shown) of the device 1; i.e. the trench electrodes 141 of the two trenches 14 may be electrically insulated from the first load terminal 11.With regard to both trenches 14, the trench insulator may furthermore at least partially form trench side walls 1421 and / or a trench bottom 1422 of the respective trench 14. A trench cover 1423 of the respective trench 14 may be formed by the same material as the trench insulator and / or by a different insulation structure and / or may comprise a different material than the trench insulator.Further, the mesa portion 17 may include the source region 101, and the contact plug 111 may also be in contact with the source region 101. The source region 101 may be insulated from the drift region 100 by the body region 102. For example, the trench electrode 141 of the first trench 14 is configured to generate an inversion channel in the body region 102 upon receipt of a corresponding control signal, e.g. from the driver unit.Further, the body region 102 may include a contact portion 1022 having a locally enhanced dopant concentration, wherein the contact plug 111 abuts the contact portion 1022. Furthermore, the contact portion 1022 may adjoin a portion of the trench insulator 142, wherein the portion of the trench insulator 142 may also be contacted by the contact plug 111. Further, the contact portion 1022 may be arranged in the first lateral direction at a distance b from the trench insulator 142 of the second trench 142, which is at least 20% of the width of the mesa portion 17 in the first lateral direction X. Thus, even though the source region 101 is also present in the mesa portion 17, it may be ensured that the source region 101 is adjacent to a portion of the body region 102 different from its contact portion 1022, i.e. a portion having not the locally enhanced dopant concentration but the lower regular dopant concentration of the body region 102, such that it is possible to generate an inversion channel in the body region 102 for load current conduction.Likewise, the contact plug 111 may be laterally offset from the second trench 14 in the vertical cross section along the first lateral direction X. Thus, in an embodiment, the contact plug 111 laterally overlaps with only one of the two trenches 14 laterally delimiting the mesa portion 17.In an embodiment, the contact plug 111 further includes a first side surface 1011, a second side surface 1012, and a bottom surface 1013. The first side surface 1011 may adjoin the first trench 14 (cf. examples (a)-(c)), the bottom surface 1113 may adjoin the body region 102 (e.g. its contact portion 1022), and the second side surface 1112 may adjoin the source region 101 (cf. examples (a)-(c)). The two side surfaces 1111, 1112 may be arranged in a plane substantially parallel to both the vertical direction Z and the second lateral direction Y. The bottom surface 1113 may be disposed in a plane substantially parallel to both the second lateral direction Y and the first lateral direction X. For example, the contact plug 111 may thus make contact with (i.e., adjoin) each of the body region 102 (e.g., its contact portion 1022), the source region 101, and optionally an inner portion of the first trench 14, but without being in contact with the trench electrode 141 of the first trench 14.As shown above, the contact plug 111 may further be laterally spaced apart from the second trench 14 in the vertical cross section along the first lateral direction X. For example, a lateral boundary of the contact plug 111 may be defined by the first insulation layer 13 arranged over the trench cover 1423 of the second trench 14.Further, a portion of the trench insulator 142 of the first trench 14 may be located between the contact plug 111 and the trench electrode 141 of the first trench 14. Thus, the trench insulator may help electrically isolate the contact plug 111 from the trench electrode 141 of the first trench 14.Now considering examples (a)-(c) of FIG. 3, the contact plug may extend along the vertical direction Z deeper than both the surface part 175 of the mesa portion 17 and the trench cover 1423 of the second trench 14 of the two trenches 14. The contact plug 111 may even extend further than the source region 101 along the vertical direction Z.Further considering examples (a)-(c) of FIG. 3, the contact plug 111 may be adjacent to a portion of the trench sidewall 1421 of the first trench 14. A portion of the trench insulator 142, namely a portion of the trench sidewall 1421 of the first trench 14, may thus be located between the contact plug 111 and the trench electrode 141 of the first trench 14. For example, a portion of the trench sidewall 1421 may thus laterally overlap with a portion of the contact plug 111. Both the portion of the trench sidewall 1421 and the portion of the contact plug 111 (which laterally overlap) may be disposed under the surface part 175 (cf. examples (a)-(c)). Or considering examples (d)-(f), the contact plug 111 may be arranged completely over the surface part 175, such that also the portion of the portion contact plug 111 forming the lateral overlap with the portion of the trench sidewall 1421 is arranged over the surface part 175.Considering examples (d)-(f), the contact plug 111 may be configured as a flat contact plug terminating at the surface portion 175. The surface portion may be formed by at least the source region 101 and the contact portion 1022 of the body region 102 in these examples.The protective structure 145 may have one of several possible configurations. Generally, the protection structure 145 may be configured to contribute to electrically insulating the contact plug 111 from the trench electrode 141 of the first trench 14, wherein the trench electrode 141 may be the control electrode (gate electrode). Thus, the electric potential of the contact plug 111 and the electric potential of the trench electrode 141 may be different from each other. To this end, the protection structure 145 is an electrically insulating structure or a protection device structure. The protection device structure may form part of an npn structure, a pnp structure, anti-parallel connected zener diodes, a Schottky diode structure or a punch-through structure, for example. The exemplary structures (npn structure, pnp structure, antiparallel-connected zener diodes, Schottky diode structure, punchthrough structure) can furthermore be formed by the contact plug 111 and / or the trench electrode 141 itself. For example, when the trench electrode 141 of the first trench 14 is formed by a p-type polycrystalline semiconductor material, the pnp structure may be used for forming anti-parallel connected zener diodes or a punch-through structure. Materials used to form the protection device structure may include one or more of a polycrystalline semiconductor material and a thin dielectric material.In the latter case (protection device structure), based on the protection structure 145, for example, it may be ensured that a voltage between the electrical potential of the contact plug 111 and the electrical potential of the trench electrode 141 remains below a height at least partially defined by the protection device structure.In the first case (according to which the protection structure is an insulation structure), the protection structure 145 may comprise a dielectric layer or may be a dielectric layer.The protective structure 145 may further have one of a plurality of possible positions and one of a plurality of possible spatial shapes. Referring to FIG. 3, example (a) and example (d), the protection structure 145 may isolate an upper portion 143 of the first trench 14 from the trench electrode 141. The upper portion 143 may be configured in various ways. For example, the upper portion 143 is an insulating material or an electrically conductive material. The upper portion 143 may be disposed in contact with the contact plug 111. The contact plug 111 may thus be adjacent to the upper portion 143 of the first trench 14. Depending on the design / position of the protection structure 145, the upper trench portion 143 may extend along the entire width of the first trench 14 (cf. examples (b) and (e)) or partially (cf. examples (a) and (d) in FIG. 3 ). Or the protection structure 145 itself forms the upper portion 143 of the first trench 14, either only partially along the trench width, as illustrated (cf. examples (c) and (f) in FIG. 3 ) or along the entire trench width.As explained above, if the protection structure 145 is implemented as the protection device structure, an npn structure, a pnp structure, anti-parallel connected zener diodes, a Schottky diode structure or a punch-through structure may be formed based on the protection device structure, and moreover, the contact plug 111 and / or the trench electrode 141 itself may contribute to forming such a structure. Moreover, the upper portion 143 of the first trench 14 may also contribute to forming such an npn structure, pnp structure, anti-parallel connected zener diodes, a Schottky diode structure, or a punch-through structure.Depending on the position / spatial configuration of the protection structure 145, the trench electrode 141 of the first trench 14 may thus have a width in the first lateral direction X that varies along the vertical direction Z (cf. examples (a), (c), (d) and (f) in FIG. 3 ). For example, in a portion of the first trench 14 into which the protection structure 145 and / or the contact plug 111 extends / extend, the width of the trench electrode 141 may be smaller compared to another (e.g. lower) portion of the first trench 14. For example, the portion of the first trench into which the protection structure 145 and / or the contact plug 111 extends / extend and where the trench electrode width may be reduced is an upper portion of the first trench 14.Further, considering examples (a)-(f) of FIG. 3, a lateral distance in the first lateral direction X between the contact plug 111 and the trench insulator 142 of the second trench 14 may be in a certain range, for example, by being at most 1 μm and / or at least 150 nm. In some examples, the lateral distance is at most 250 nm, e.g., at most 200 nm. For example, the contact plug 111 neither adjoins the second trench 14 nor overlaps laterally with the second trench 14, but is laterally offset therefrom.Further examples are explained with reference to FIG. 4. According to example (a), the first trench 14, configured with respect to its upper part as in example (a) of FIG. 3, may further comprise a further isolation structure 147, such that an additional trench electrode 149 may be formed in the first trench 14. The first trench 14 may thus be a multi-trench electrode trench. For example, the further isolation structure 147 electrically isolates the trench electrode 141 from the additional trench electrode 149. The same applies to the second trench 14. the additional trench electrode 149, which is arranged, for example, in a lower portion of the first trench 14, may be connected to the same electrical potential as the trench electrode 141 (which may be the gate / control potential), electrically floating or connected to a different electrical potential, such as the electrical potential of the first load terminal 11.According to examples (b) to (e) of FIG. 4, the contact plug 111 (not shown) may be configured as a flat contact disposed entirely over and in contact with the surface part 175. For example, the contact plug 111 may laterally overlap with both the first trench 14 and the second trench 14 and may even form the trench covers of both the first trench 14 and the second trench 14. In order to ensure the electrical insulation between the trench electrodes 141 of the first and second trench 14, the protection structure 145 is provided in both the first trench 14 and the second trench 14. The explanations regarding possible positions and spatial configurations of the protective structure and the possibility of a further insulation structure 147, as provided with respect to FIGS. 3 and 4, variant (a), also apply to the examples (b)-(e) of FIG. 4.FIG. 5 schematically and exemplarily illustrates a range of a vertical cross section of the power semiconductor device 1 according to the invention. According to this embodiment, the protection structure 145 completely covers the trench electrode 141 included in the first trench 14 and thereby forms the trench cover. The contact plug 111 completely overlaps with the first trench 14 along the first lateral direction X and adjoins the mesa sections 17 adjacent to the first trench 14 in order to contact the source regions 101 and the body contact regions 1022 there. The contact plug 111 laterally overlaps in the first vertical cross section with the entire trench electrode 141 of the first trench 14, but only partially with one or both of the mesa sections 17 which are laterally next to it. The contact plug 111 may extend under the surface portions 175 formed by the mesa portions 17.Further, the power unit cell 1- 1 according to the embodiment illustrated in FIG. 5 may include a further trench 16, which may be, for example, a source trench whose trench electrode 161 is electrically connected to the first load terminal 11 or a dummy trench in which the trench electrode 161 would be electrically floating. Besides the different electrical potential of the trench electrode 161, the further trench 16 may be configured as the first trenches 14 (which may be control trenches) next to the first trench 14 covered by the contact plug 111, e.g. by receiving a corresponding trench insulator 162 and by covering by the trench cover 1623. Further, the power unit cell 1- 1 according to the embodiment illustrated in FIG. 5 may include a further mesa portion 15, which may be a dummy mesa portion that is not electrically connected to the first load terminal 11 (e.g., by a plug or the like), but where a junction between the first load terminal 11 and the dummy mesa portion 15 along the vertical direction Z is electrically insulating. Or the further mesa section 15 may be a diode mesa section, the body region 102 (but not source region) of which is electrically connected to the first load terminal 11.FIGS. 6 and 7 both schematically and exemplarily illustrate a range of a horizontal projection of the power semiconductor device 1 according to one or more examples. According to the illustrated examples, in each power unit cell 1- 1, three first / second trenches 14 in the form of control trenches are arranged laterally next to one another and laterally delimit two or three mesa sections 17.According to the examples illustrated in FIGS. 6-7, the trench electrodes 161 of the source trenches 16 are electrically connected to the first load terminal 11 based on source contact plugs 116. These source contact plugs 116 may be disposed in the active region 1- 2. Alternatively, as illustrated in FIG. 6( b), the trench electrode 161 of the source trench 16 may be contacted by the contact plug 111 that also contacts the adjacent mesa 17; in such a case, the provision of the protection structure 145 in the trench 16 may be omitted, since both the mesa 17 and the trench electrode 161 of the source trench 16 may have the same electrical potential.According to the examples illustrated in FIGS. 6-7, the power semiconductor device 1 further includes a trench contact plug 113 disposed in electrical contact with the trench electrode 141 of the first trench 14. Further, the first trench 14 may be laterally structured along a second lateral direction Y such that both the protection structure 145 and the contact plug 111 (used for contacting the mesa portions 17) are laterally spaced apart from the trench contact plug 113 along the second lateral direction Y. As illustrated, the trench contact plug / plugs 113 may / may be arranged in the edge termination region 1- 3 to adjoin there both the trench electrodes 141 and a gate runner structure, for example.According to the examples shown in FIGS. 6-7, the contact plugs 111 for contacting the mesa portions 17 are provided in recessed areas 112. For example, the configuration of the contact plugs 111 corresponds to the configuration shown in FIG. 3, examples (a) and (c).According to the examples illustrated in FIGS. 6-7, the source regions 101 in the mesa sections 17 are laterally structured along the second lateral direction Y, as is exemplarily illustrated in FIG. 6, example (a). Accordingly, in each of the mesa portions 17, the source region 101 is provided only locally along the length of the mesa portion 17 in the second lateral direction Y. The contact plug 111 may extend continuously along the second lateral direction Y.In another example, as best shown in FIG. 7( b), the contact plug 111 and / or the protection structure 145 and / or the trench electrode 141 may also be structured along the second lateral direction Y (cf. interruptions of the recessed portion 112 in FIG. 7( b)). For example, along the second lateral direction Y, there may be portions where the protection structure is not provided and where a portion of the contact plug 111 may thus adjoin a portion of the trench electrode 141; then both the portion of the contact plug 111 and the portion of the trench electrode 141 may have the same electrical potential. Thus, according to an embodiment, the trench mesa pattern may vary along the second lateral direction Y. For example, based on the protection structure 145, the portion of the trench electrode 141 contacted by the contact plug 111 is / are insulated from the portion(s) of the trench electrode 141 that is / are separated from the contact plug 111.The configuration of the power unit cell 1- 1 with respect to the trench mesa pattern may vary. For example, by comparing examples (a) and (b) of FIG. 6, it is possible to provide the power unit cell 1- 1 with two mesa portions 17 and two other mesa portions 15 (e.g., dummy mesa portions), or with three mesa portions 17 and one other mesa portion 15. Each of the three mesa sections 17 is contacted by a respective contact plug 111. As illustrated for example (b) of FIG. 6, one of the mesa portions 17 may be laterally bounded by one of the source trenches 16 and one of the control trenches 14.Referring to FIG. 7, in both examples (a) and (b), the trench mesa pattern may be identical to example (a) illustrated in FIG. 6. With regard to contacting the mesa sections 17 and the further mesa sections 15 and the trench electrodes 141 of the control trenches 14 and the trench electrodes 161 of the source trenches 16, the above description applies analogously. Example (a) in FIG. 7 illustrates a portion of both the edge termination region 1- 3 and the active region 1- 2, while example (b) relates only to the active region 1- 2.FIG. 7 illustrates one of the above-mentioned possible configurations of the protection structure 145 structured along the second lateral direction Y, such that, based on the protection structure 145, portions of the trench electrode 141 may be contacted by the contact plug 111 and other portions may be separated from the contact plug 111. In order to ensure that the different portions of the trench electrode 141 may have different electrical potentials, respectively, the trench electrode 141 may be formed by portions 1452 of a p-type polycrystalline material arranged alternately (with respect to the second lateral direction Y) and portions 1451 of an n-type polycrystalline material, for example, such that, based on one of the portions 1452 of the p-type polycrystalline material being arranged between the two portions 1451, two portions 1451 of the n-type polycrystalline material are separated from each other, respectively.Furthermore, a method for manufacturing a power semiconductor device is also presented here. According to an embodiment, the method comprises forming a semiconductor body comprising a first surface and a mesa portion, wherein the mesa portion comprises a surface part of the first surface and a body region; at least two trenches extending from the first surface along a vertical direction into the semiconductor body, wherein each of the two trenches comprises a trench electrode and a trench insulator insulating the trench electrode from the semiconductor body; and wherein the mesa portion is laterally bounded by the two trenches in a first vertical cross section along a first lateral direction; a contact plug in contact with the body region, wherein the contact plug laterally overlaps the entire trench electrode of a first trench of the two trenches in the first vertical cross section, and wherein the contact plug only partially overlaps with the mesa portion in the first vertical cross section; and a protection structure. The protection structure includes a portion disposed in the first trench. The protection structure is arranged between the contact plug and the trench electrode of the first trench. The protection structure is an electrically insulating structure or a protection device structure. For example, the protection structure extends along the vertical direction deeper than both the surface part of the mesa portion and a trench cover of a second trench of the two trenches. In another embodiment, the protection structure is arranged at or above the surface part of the mesa portion and / or at or above the trench cover of the second trench.Embodiments of the method for manufacturing a power semiconductor device correspond to the above-described embodiments of the power semiconductor device 1.FIG. 8 illustrates an example of the method for manufacturing a power semiconductor device (reference numeral 200) according to two variations, variation (a) including steps 201 to 205, and variation (b) including steps 201, 202, and 206 to 208.According to both variants (a) and (b), in step 201, the trench electrodes 141 are formed in the first trench 14 and in the second trench 14, e.g. by depositing an electrically conductive material such as polysilicon.Still referring to the two variants, in step 202, recesses 1415 are formed, e.g. based on an etch processing step, in the electrically conductive material at locations where the protection structure 145 is to be subsequently implemented.According to variant (a), step 203 includes forming both the protection structure 145, e.g. as a dielectric layer or a protection device structure, and over the protection structure 145 of the upper trench portion 143, which may comprise an insulating material or an electrically conductive material. Based on step 203, structures as exemplarily shown in FIG. 3, examples (a), (b), (d) and (e) may be formed, for example. According to variant (b), step 206 only includes forming the protection structure 145. There, the protection structure 145 is an electrically insulating structure or a protection device structure and simultaneously forms an upper trench portion. Based on step 206, structures as exemplarily shown in FIG. 3, examples (c) and (f) may be formed, for example.With regard to optional aspects of the protection structure 145 implemented as the protection device structure and / or optional aspects of the trench electrode 141, reference is made to the above description, which analogously also applies to the method. In a protection device structure implemented as a Zener diode structure, for example, a highly doped npn structure may be deposited forming two anti-parallel connected Zener diodes. Each zener diode may have a junction region at the pn junction with a lower effective doping with respect to n- and p-regions.According to both variants (a) and (b), step 204 and step 207 respectively comprises a planarization processing step and / or a trench cover forming step such as an oxidation processing step, so that based at least on trench covers 1423, a substantially planar surface is achieved over the surface part 175 of the mesa portion 17. In the planarization processing step, a protruding part of the trench electrode 141, a protruding part of the trench insulator 142, and a protruding part of the protection pattern 145 may be removed. The protruding part may be the part of the trench electrode 141, the trench insulator 142 and the protection structure 145 protruding above the surface part 175 of the mesa portion 17 against the vertical direction Z, respectively.According to both variants (a) and (b), step 205 and step 208, respectively, includes multiple processing steps, such as one or more implantation processing steps and one or more diffusion processing steps, which are carried out to form the body region 102, the contact portion 1022 of the body region 102, and the source region 101, respectively.Further, a deposition processing step for forming the first insulating layer 13 may be included. Further, an etching processing step of forming the recessed portion 112 (e.g., contact groove 112) in which an electrically conductive material including, for example, a metal may be deposited to form the contact plug 111 may be performed.Above, embodiments related to power semiconductor devices such as MOSFETs, IGBTs, RC-IGBTs and derivatives thereof and respective processing methods have been explained. These power semiconductor devices are based on silicon (Si), for example. Accordingly, an (e) monocrystalline (s) semiconductor region or layer, e.g. the semiconductor body 10 and its regions / zones, e.g. regions etc., may be a (e) monocrystalline (s) Si region or Si layer. In other embodiments, polycrystalline or amorphous silicon may be used.It should be appreciated, however, that the semiconductor body 10 and its regions / zones may be made of any semiconductor material suitable for manufacturing a semiconductor device. Examples of such materials include elementary semiconductor materials such as silicon (Si) or germanium (Ge), group IV compound semiconductor materials such as silicon carbide (SiC) or silicon germanium (SiGe), binary, ternary or quaternary III-V semiconductor materials such as gallium nitride (GaN), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium gallium phosphide (InGaPa), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), Aluminum gallium indium nitride (AlGaInN) or Indiumgalliumarsenidphosphid (InGaAsP), and binary or ternary II-VI semiconductor materials such as cadmium telluride (CdTe) and mercury cadmium telluride (HgCdTe) to name few. The above-mentioned semiconductor materials are also referred to as "homojunction semiconductor materials". When combining two different semiconductor materials, a heterojunction semiconductor material is formed. Examples of heterojunction semiconductor materials include aluminum gallium nitride (AlGaN)-aluminum gallium indium nitride (AlGaInN), indium gallium nitride (InGaN)-aluminum gallium indium nitride (AlGaInN), indium gallium nitride (InGaN)-gallium nitride (GaN), aluminum gallium nitride (AlGaN)-gallium nitride (GaN), indium gallium nitride (InGaN)-aluminum gallium nitride (AlGaN), silicon silicon carbide (SixC1-x), and silicon-SiGe heterojunction semiconductor materials. For applications with power semiconductor switches, Si, SiC, GaAs and GaN materials are mainly used at present.Spatial terms such as "below," "below," "lower," "over," "upper," and the like are used to describe the positioning of an element relative to a second element for convenience of description. These terms are intended to include different orientations of the respective device in addition to different orientations than those depicted in the figures. Further, terms such as "first", "second", and the like are also used to describe various elements, regions, sections, etc., and are also not intended to be limiting. Like terms refer to like elements throughout the specification.As used herein, the terms "have," "include," "include," "comprise," "have," and the like are open ended terms and indicate the presence of the stated elements or features, but do not exclude additional elements or features.

Claims

A power semiconductor device (1) comprising: - a semiconductor body (10) comprising a first surface (110) and a mesa portion (17), wherein the mesa portion (17) comprises a surface part (175) of the first surface (110) and a body region (102); - at least two trenches (14) extending from the first surface (110) along a vertical direction (Z) into the semiconductor body (10), wherein each of the two trenches (14) comprises a trench electrode (141) and a trench insulator (142) insulating the trench electrode (141) from the semiconductor body (10), and wherein the mesa portion (17) is laterally bounded by the two trenches (14) in a first vertical cross-section along a first lateral direction (X); a contact plug (111) in contact with the body region (102), wherein the contact plug (111) laterally overlaps with the entire trench electrode (141) of a first trench (14) of the two trenches (14) in the first vertical cross section, and wherein the contact plug (111) only partially overlaps with the mesa section (17) in the first vertical cross section; and a protective structure (145), wherein the protective structure - has a section arranged in the first trench (14); - is arranged between the contact plug (111) and the trench electrode (141) of the first trench (14); - extends along the vertical direction (Z) deeper than both the surface part (175) of the mesa section (17) and a trench cover (1423) of a second trench (14) of the two trenches (14); and an electrically insulating structure or a protection device structure.The power semiconductor device (1) according to claim 1, wherein the mesa portion (17) comprises a source region (101), and wherein the contact plug (111) is also in contact with the source region (101).The power semiconductor device (1) according to claim 2, wherein the contact plug (111) extends further than the source region (101) along the vertical direction (Z).The power semiconductor device (1) according to any of the preceding claims, wherein the protection structure (145) comprises a dielectric layer or is a dielectric layer.The power semiconductor device (1) according to any one of the preceding claims, wherein the protection structure (145) is the protection device structure and forms a part of - an npn structure; - a pnp structure; - anti-parallel connected zener diodes; - a Schottky diode structure; or - a punch-through structure.The power semiconductor device (1) according to claim 2 and optionally any additional one of the preceding claims, wherein the contact plug (111) comprises a first side surface (1111), a second side surface (1112) and a bottom surface (1113), wherein the first side surface (1111) abuts the first trench (14), the bottom surface (1113) abuts the body region (102) and the second side surface (1112) abuts the source region (101).Power semiconductor device (1) according to the preceding claim, comprising at least two first trenches (14), wherein the contact plug (111) laterally overlaps with the at least two first trenches (14) in vertical cross section.The power semiconductor device (1) according to any one of the preceding claims, wherein the contact plug (111) is laterally spaced apart from the second trench (14) in the vertical cross section along the first lateral direction (X).The power semiconductor device (1) according to any one of the preceding claims, wherein the contact plug (111) abuts a part of the trench sidewall (1421) of the first trench (14).The power semiconductor device (1) according to any one of the preceding claims, wherein a part (1421) of the trench insulator (142) of the first trench (14) is located between the contact plug (111) and the trench electrode (141) of the first trench (14).The power semiconductor device (1) according to any one of the preceding claims, wherein a lateral distance in the first lateral direction (X) between the contact plug (111) and the trench insulator (142) of the second trench (14) is at most 1 μm and / or at least 150 nm.The power semiconductor device (1) according to any of the preceding claims, wherein the body region (102) comprises a contact portion (1022) having a locally increased dopant concentration, wherein the contact plug (111) abuts the contact portion (1022).The power semiconductor device (1) according to any one of the preceding claims, wherein the first trench (14) is a multi-trench electrode trench (141, 143, 149).The power semiconductor device (1) according to any one of the preceding claims, further comprising a trench contact plug (113) arranged in electrical contact with the trench electrode (141) of the first trench (14), wherein the first trench (14) is laterally structured along a second lateral direction (Y) such that along the second lateral direction (Y) both the protection structure (145) and the contact plug (111) are laterally spaced from the trench contact plug (113).The power semiconductor device (1) according to any one of the preceding claims, wherein the contact plug (111) is electrically insulated from the trench electrode (141) of the first trench (14) at least based on the protection structure (145).A method (200) for manufacturing a power semiconductor device (1), comprising: - forming at least two trenches (14) in a semiconductor body (10) having a first surface (110), such that - the two trenches (14) extend from the first surface (110) along a vertical direction (Z) into the semiconductor body (10), - the two trenches (14) laterally delimit a mesa portion (17) of the semiconductor body (10) in a first vertical cross-section along a first lateral direction (X), wherein the mesa portion (17) comprises a surface part (175) of the first surface (110) and a body region (102), and - forming in the at least two trenches (14) a trench electrode (141) and a trench insulator (142) insulating the trench electrode (141) from the semiconductor body (10); forming a protective structure (145), the protective structure - having a part arranged in the first trench (14); - extending along the vertical direction (Z) deeper than both the surface part (175) of the mesa portion (17) and a trench cover (1423) of a second trench (14) of the two trenches (14); and - being an electrically insulating structure or a protection device structure; - forming a contact plug (111) in contact with the body region (102), - wherein the contact plug (111) and laterally overlaps with the entire trench electrode (141) of a first trench (14) of the two trenches (14) in the first vertical cross section, and wherein the contact plug (111) only partially overlaps with the mesa portion (17) in the first vertical cross section; and wherein the contact plug (111) and the protection structure (145) are formed such that the protection structure (145) is arranged between the contact plug (111) and the trench electrode of the first trench (14).The method of claim 16, wherein forming the protective structure (145) comprises: - removing at least a part of the trench electrode (141) of the first trench (14) to form a recess (1415) in the first trench (14), and - forming at least a portion of the protective structure (145) in the recess (1415).The method of claim 16 or 17, wherein forming the contact plug (111) comprises: - removing at least a part of the mesa portion (17) and the protection structure (145) to form a recessed area (112), and - depositing an electrically conductive material in the recessed area (112).The method according to any one of the preceding claims 16 to 18, comprising, after forming the protective structure (145) and before forming the contact plug (111), a planarization processing step and / or a trench capping forming step such that, based at least on the trench capping (1423) of the trenches (14), a substantially planar surface is formed over the surface part (175) of the mesa portion (17).

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