POLARIZATORS BASED ON LOOP-SHAPED SHAFT CONDUCTOR INTERSECTIONS

A compact polarizer structure with a waveguide junction and loop connection efficiently eliminates TM modes on photonic chips, addressing space consumption and noise issues.

DE102021104613B4Active Publication Date: 2025-12-31GLOBALFOUNDRIES US INC +1
View PDF 4 Cites 0 Cited by

Patent Information

Application Number
DE102021104613
Authority / Receiving Office
DE · DE
Patent Type
Patents
Current Assignee / Owner
Priority Date
2020-03-31
Filing Date
2021-02-26
Publication Date
2025-12-31
Estimated Expiration
2041-02-26

AI Technical Summary

Technical Problem

Polarizers on photonic chips that allow only TE modes to pass through have large footprints, consuming significant layout space.

Method used

A polarizer structure comprising a waveguide junction with arms and a loop-shaped waveguide connection that directly connects these arms, allowing TE modes to propagate while eliminating TM modes, using silicon-on-insulator wafer processing and etching techniques to form compact polarizers.

Benefits of technology

The solution provides a compact polarizer that effectively eliminates TM modes, optimizing layout space and reducing noise sources on photonic chips, particularly in the O-band.

✦ Generated by Eureka AI based on patent content.

Smart Images

  • Figure 00000000_0000_ABST
    Figure 00000000_0000_ABST
Patent Text Reader

Abstract

Structure (10) for a polarizer, wherein the structure (10) comprises: a first waveguide crossing (12) comprising a first arm (24), a second arm (26) and a transition (30) connecting the first arm (24) to the second arm (26); and a first waveguide loop (16) having an input port coupled to the first arm (24) of the first waveguide crossing (12) and an output port coupled to the second arm (26) of the first waveguide crossing (12), wherein the first waveguide loop (16) directly connects the first arm (24) to the second arm (26) of the first waveguide crossing (12).
Need to check novelty before this filing date? Find Prior Art

Description

BACKGROUND

[0001] The present invention relates to photonic chips and in particular structures for a polarizer and methods for manufacturing a structure for a polarizer.

[0002] Photonic chips are used in many applications and systems, including but not limited to data communication and computing systems. A photonic chip integrates optical components, such as waveguides, optical switches, and directional couplers, and electronic components, such as field-effect transistors, into a single platform. Integrating both types of components onto the same chip can reduce layout space, costs, and operational overhead, among other factors.

[0003] DE 19 39 447 A discloses, for example, a bandstop filter for optical waves, which has a circular cavity and a loop-shaped transmission line coupled to the cavity. Furthermore, CN 1 09 709 644 A discloses an optical switch, which has three intersecting straight waveguides and one ring-shaped waveguide. DE 10 2015 208 983 A1 also discloses an optoelectronic component, which has a coupling element for coupling optical radiation into a waveguide. The radiation losses generated during coupling are detected and evaluated via a detector and auxiliary coupling paths connected to the coupling element.

[0004] Polarizers are a type of optical component commonly found in photonic chips. A polarizer is configured to receive light containing multiple modes (e.g., transverse electric (TE) and transverse magnetic (TM) modes) and allow only one of these modes to propagate, while the other is eliminated or dropped. Polarizers that only allow TE modes to pass through have relatively large footprints, consuming significant layout space on the photonic chip.

[0005] Improved structures for a polarizer and methods for manufacturing a structure for a polarizer are needed. BRIEF SUMMARY

[0006] In one embodiment of the invention, a structure for a polarizer comprises a first waveguide junction comprising a first arm, a second arm and a transition connecting the first arm to the second arm, and a first waveguide loop comprising an input port coupled to the first arm of the first waveguide junction and an output port coupled to the second arm of the first waveguide junction, wherein the first waveguide loop directly connects the first arm to the second arm of the first waveguide junction.

[0007] In one embodiment of the invention, a method comprises forming a first waveguide crossing comprising a first arm, a second arm and a transition connecting the first arm to the second arm, and forming a first waveguide loop having an input port coupled to the first arm of the first waveguide crossing and an output port coupled to the second arm of the first waveguide crossing, wherein the first waveguide loop directly connects the first arm to the second arm of the first waveguide crossing. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The accompanying drawings, which are incorporated into and form part of this specification, illustrate various embodiments of the invention and, together with the general description of the invention given above and the detailed description of the embodiments given below, serve to explain these embodiments. The same reference numerals are used in the drawings to indicate the same features in the different views. Fig. Figure 1 is a diagrammatic top view of a structure in an initial manufacturing stage of a processing method according to embodiments of the invention. Fig. 2 is a cross-sectional view along a line 2-2 in the Fig. 1. Fig. Figure 3 is a cross-sectional view along a line 3-3 in the Fig. 1. Fig. 4 and Fig. Figure 5 shows cross-sectional views of the structure at each stage of the processing procedure following the manufacturing stage of the Fig. 2 and Fig. 3. Fig. 6 and Fig. Figure 7 shows cross-sectional views of a structure according to alternative embodiments of the invention. Fig. 8 and Fig. Figure 9 shows cross-sectional views of a structure according to alternative embodiments of the invention. Fig. 10 and Fig. Figure 11 are cross-sectional views of a structure according to alternative embodiments of the invention. Fig. Figure 12 is a top view of a structure according to alternative embodiments of the invention. DETAILED DESCRIPTION

[0009] With reference to the Fig. 1, Fig. 2, Fig. 3 and according to embodiments of the invention, a structure 10 comprises a waveguide junction 12 having arms 22, 24, 26, 28, a waveguide core 14 coupled to arm 22 of the waveguide junction 12 to provide an input port, a waveguide core 20 coupled to arm 28 of the waveguide junction 12, and a waveguide loop 16 having an input port coupled to arm 24 of the waveguide junction 12 and an output port coupled to arm 26 of the waveguide junction 12. The arms 22, 24 of the waveguide junction 12 are aligned along a longitudinal axis 15, and the arms 26, 28 of the waveguide junction 12 are aligned along a longitudinal axis 19, which may be transverse or orthogonal to the longitudinal axis 15.The waveguide junction 12 comprises a central section 30, which provides a transition between arms 22 and 24 of the waveguide junction 12, and also between arms 26 and 28 of the waveguide junction 12. Each of the arms 22, 24, 26, and 28 is coupled at one end to a different section of the central section 30. The waveguide junction 12, the waveguide cores 14 and 20, and the waveguide loop 16 can be planar structures with coplanar upper surfaces and coplanar lower surfaces.

[0010] The waveguide junction 12, the waveguide cores 14, 20, and the waveguide loop 16 can be composed of a single-crystal semiconductor material (e.g., single-crystal silicon). The waveguide junction 12, the waveguide cores 14, 20, and the waveguide loop 16 can be formed simultaneously by structuring a fixture layer of a silicon-on-insulator (SOI) wafer using lithography and etching processes. These processes create an etch mask over the fixture layer, and the masked fixture layer is then etched using an etching process such as reactive ion etching (RIE). The waveguide junction 12, the waveguide cores 14, 20, and the waveguide loop 16 can be arranged on a buried insulator layer 32 of the SOI wafer.The buried insulator layer 32 can be composed of a dielectric material, such as silicon dioxide, and is arranged over a substrate 34, which may contain a single-crystal semiconductor material (e.g., single-crystal silicon). The waveguide junction 12, the waveguide cores 14, 20, and the waveguide loop 16 may exhibit a burr buildup because the device layer is completely etched during the structuring process. The buried insulator layer 32 can act as a bottom sheath, providing confinement for the waveguide junction 12, the waveguide cores 14, 20, and the waveguide loop 16 of the structure 10.

[0011] Each of the arms 22, 24, 26, 28 can have shapes with curvatures that are identical or substantially identical with respect to the central section 30, except for their orientation along the respective longitudinal axis 15, 19. Each of the arms 22, 24, 26, 28 includes an interface 38 at one end coupled to the central section 30 and an interface 36 located at one end opposite the interface 38. Each of the arms 22, 24, 26, 28 can be shaped with side surfaces 23 having a curvature defined by a nonlinear function. For example, each of the arms 22, 24, 26, 28 can have a shape described by a cosine function where the width at the interfaces 38 is greater than the width at the interfaces 36.However, arms 22, 24, 26, 28 can also have other shapes, such as a conical shape or a combination of two or more cascading conical shapes.

[0012] The arm 24 of the waveguide junction 12 is coupled to the arm 26 of the waveguide junction 12 by the waveguide loop 16. The waveguide loop 16 comprises waveguide bends 40, 42, 44 and waveguide sections 46, 48, 50, 52, which are arranged and connected to each other such that they provide a direct connection between the arm 24 and the arm 26 of the waveguide junction 12. The waveguide section 46 can be directly connected to the arm 24 at any of the interfaces 36, and the waveguide bend 40 can be connected to the arm 24 through the waveguide section 46. The waveguide section 46 can be aligned parallel to the longitudinal axis 15. The waveguide section 48 can be directly connected at opposite ends to the two waveguide bends 40, 42 such that the waveguide bend 40 is connected to the waveguide bend 42 by the waveguide section 48.Waveguide section 48 can be aligned parallel to the longitudinal axis 19. Waveguide section 50 can be directly connected at opposite ends to waveguide bends 42 and 44 such that waveguide bend 42 is connected to waveguide bend 44 by waveguide section 50. Waveguide section 50 can be aligned parallel to the longitudinal axis 15. Waveguide section 52 can be directly connected to arm 26 at one of the interfaces 36, and waveguide bend 44 can be connected to arm 26 by waveguide section 52. Waveguide section 52 can be aligned parallel to the longitudinal axis 19.

[0013] The waveguide bends 40, 42, and 44 can each provide a 90° change in direction for the waveguide loop 16, defining right-angled intersections between the various waveguide sections 46, 48, 50, and 52. Together, the waveguide bends 40, 42, and 44 can provide a 270° change in direction connecting arm 24 of waveguide intersection 12 with arm 26 of waveguide intersection 12. The waveguide sections 46, 48, 50, and 52 can be straight sections without any curvature. Waveguide section 46 can have a width equal to the width of arm 24 at the associated interface 36, and waveguide section 52 can have a width equal to the width of arm 26 at the associated interface 36.

[0014] In operation, light can be received at arm 22 of the waveguide junction 12. The received light can contain both polarization components (e.g., a transverse electric (TE) component and a transverse magnetic (TM) component). The light propagates through the central section 30 to arm 24 of the waveguide junction 12 and from arm 24 to the waveguide loop 16. The light propagates through the waveguide loop 16 to arm 26 of the waveguide junction 12, and during propagation between arm 24 and arm 26, one of the mode components (e.g., the TM mode component) can be eliminated. The other mode component (e.g., the TE mode component) of the light is allowed to pass through the waveguide loop 16 to arm 26. The light spreads through arm 26 and central section 30 to arm 28 of waveguide crossing 12 and from arm 28 to waveguide core 20.

[0015] In alternative embodiments, the waveguide junction 12, the waveguide cores 14, 20, and the waveguide loop 16 can be composed of a different material. In one embodiment, the waveguide junction 12 can be composed of a dielectric material, such as silicon nitride. The waveguide junction 12, the waveguide cores 14, 20, and the waveguide loop 16 can be formed by depositing a layer of the existing material and structuring the deposited layer using lithography and etching processes. These processes create an etching mask over the deposited layer, and the masked deposited layer is then etched using an etching process such as reactive ion etching (RIE).

[0016] With reference to the Fig. 4, Fig. 5, in which identical reference signs refer to identical features in the Fig. 2, Fig. 3, and in a subsequent manufacturing stage, dielectric layers 60, 62, 64, 66, which are composed of respective dielectric materials, are successively formed in a layer stack over the waveguide junction 12, the waveguide cores 14, 20 and the waveguide loop 16. In the layer stack, dielectric layer 60 is arranged over the buried insulator layer 32, the waveguide junction 12, the waveguide cores 14, 20 and the waveguide loop 16, dielectric layer 62 is arranged over dielectric layer 60, dielectric layer 64 is arranged over dielectric layer 62 and dielectric layer 66 is arranged over dielectric layer 64. The waveguide crossing 12, the waveguide cores 14, 20 and the waveguide loop 16 are embedded or buried in the dielectric material of the dielectric layers 60, 62, which act as a sheath.

[0017] The dielectric layer 60 can be composed of a dielectric material, such as silicon dioxide, deposited by chemical vapor deposition and planarized, for example, by chemical-mechanical polishing to remove topography. The dielectric layer 62 can be composed of a dielectric material, such as silicon dioxide, deposited over dielectric layer 60 by chemical vapor deposition or atomic layer deposition. The dielectric layer 64 can be composed of a dielectric material, such as silicon nitride, deposited over dielectric layer 62 by chemical vapor deposition or atomic layer deposition. The dielectric layer 66 can be composed of a dielectric material, such as silicon dioxide, deposited over dielectric layer 64 by chemical vapor deposition or atomic layer deposition.The dielectric layers 62, 64, 66 can be planar layers arranged in the layer stack above the planarized top surface of the dielectric layer 60.

[0018] A dielectric layer 68 of a contact plane is formed by middle-of-line processing above the dielectric layer 66. The dielectric layer 68 can be composed of dielectric material, such as silicon dioxide, deposited by chemical vapor deposition using ozone and tetraethyl orthosilicate (TEOS) as reactants.

[0019] A back-end-of-line stack, collectively designated by reference numeral 58, is formed by back-end-of-line processing over the dielectric layer 68 and the structure 10. The back-end-of-line stack 58 can comprise one or more dielectric interlayer layers composed of one or more dielectric materials, such as a carbon-doped silicon oxide, and a metallization consisting, for example, of copper, tungsten, and / or cobalt, arranged within one or more of the dielectric interlayer layers.

[0020] The structure 10, in any of its embodiments described herein, can be integrated into a photonic chip, which may include electronic components 72 and additional optical components 74. The electronic components 72 may, for example, include field-effect transistors fabricated by CMOS front-end-of-line (FEOL) processing using the device layer of the SOI wafer.

[0021] Structure 10 provides a compact polarizer capable of eliminating one of the polarizations of light propagating on a photonic chip. Various optical components 74 can have a defined optical power for a specific polarization, so that eliminating the other polarization effectively eliminates a noise source. Structure 10 can be optimized for the O-band (1260 nm to 1360 nm) and can be optimized for transmitting light with transverse electric (TE) polarization and eliminating light with transverse magnetic (TM) polarization.

[0022] With reference to the Fig. 6, Fig. 7, in which the same reference signs refer to the same features in the Fig. 2, Fig. 3, and according to alternative embodiments of the invention, the device layer can be partially etched during the structuring of the waveguide junction 12, the waveguide cores 14, 20, and the waveguide loop 16 to define a plate layer 54. The plate layer 54, which is in direct contact with the buried insulator layer 32, is coupled to the waveguide junction 12, the waveguide cores 14, 20, and the waveguide loop 16. The plate layer 54 is thinner than the waveguide junction 12, the waveguide cores 14, 20, and the waveguide loop 16, which are masked during structuring. The waveguide junction 12, the waveguide cores 14, 20, and the waveguide loop 16 can have a ribbed structure by the addition of the plate layer 54.

[0023] With reference to the Fig. 8, Fig. 9, in which the same reference signs refer to the same features in the Fig. 6, Fig. 7, and according to alternative embodiments of the invention, the device layer can be partially etched during the structuring of only the waveguide loop 16 in order to define the disk layer 54. The waveguide junction 12 and the waveguide cores 14, 20 can be fully etched during their structuring, so that the disk layer 54 is not present. The waveguide junction 12 and the waveguide cores 14, 20 can have a burr structure, and the waveguide loop 16 can have a rib structure due to the addition of the disk layer 54.

[0024] With reference to the Fig. 10, Fig. 11, in which the same reference signs refer to the same features in the Fig. 6, Fig. 7, and according to alternative embodiments of the invention, the device layer can be partially etched during the structuring of the waveguide junction 12 and the waveguide cores 14, 20 to define the plate layer 54. The waveguide loop 16 can be completely etched during its structuring, so that the plate layer 54 is not present. The waveguide loop 16 can have a burr structure, and the waveguide junction 12 and the waveguide cores 14, 20 can have a rib structure due to the addition of the plate layer 54.

[0025] With reference to the Fig.12 and according to alternative embodiments of the invention, the waveguide crossing 12 and the waveguide loop 16 can be duplicated to form a waveguide crossing 12a and a waveguide loop 16a. The arm 28 of the waveguide crossing 12 is coupled to the arm 26 of the waveguide crossing 12a. The arm 28 of the waveguide crossing 12a is coupled to the arm 22 of the waveguide crossing 12a by the waveguide loop 16a of the waveguide crossing 12a. The arm 24 of the waveguide crossing 12a is coupled to the waveguide core 20. The waveguide crossing 12a and the waveguide loop 16a can be formed by structuring simultaneously with the formation of the waveguide crossing 12 and the waveguide loop 16a.

[0026] The processes described above are used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in raw wafer form (e.g., as a single wafer containing multiple unpackaged chips), as a bare die, or in a packaged form. The chip can be integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of either an intermediate or a final product. The final product can be any product that incorporates integrated circuit chips, such as computer products with a central processing unit or smartphones.

[0027] References herein to expressions modified by approximation language, such as "about," "approximately," and "essentially," are not to be limited to the specified precise value. The approximation language may correspond to the precision of an instrument used to measure the value and, unless otherwise dependent on the precision of the instrument, may be + / - 10% of the specified value(s).

[0028] References herein to terms such as "vertical," "horizontal," etc., are made for illustrative purposes only and not to limit or establish a frame of reference. The term "horizontal," as used herein, is defined as a plane parallel to a conventional plane of a semiconductor substrate, regardless of its actual three-dimensional spatial orientation. The terms "vertical" and "normal" refer to a direction perpendicular to the horizontal, as just defined. The term "lateral" refers to a direction within the horizontal plane.

[0029] A feature "connected" or "coupled" to another feature can be directly connected or coupled to the other feature, or one or more intervening features can be present. A feature can be "directly connected" or "directly coupled" to another feature if no intervening features are present. A feature can be "indirectly connected" or "indirectly coupled" to another feature if at least one intervening feature is present. A feature "at" or "contacting" another feature can be directly at or in direct contact with the other feature, or one or more intervening features can be present. A feature can be "directly at" or in "direct contact" with another feature if no intervening features are present.A feature can be “indirectly related” or “indirect contact” with another feature if at least one intervening feature is present.

[0030] The descriptions of the various embodiments of the present invention are presented for illustrative purposes only and are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations are obvious to those skilled in the art without altering the scope and concept of the described embodiments. The terminology used herein has been chosen to best explain the principles of the embodiments, their practical application, or technical improvements over commercially available technologies, or to enable other persons skilled in the art to understand the embodiments disclosed herein.

Claims

[1] Structure (10) for a polarizer, wherein the structure (10) comprises: a first waveguide crossing (12) comprising a first arm (24), a second arm (26) and a transition (30) connecting the first arm (24) to the second arm (26); and a first waveguide loop (16) having an input port coupled to the first arm (24) of the first waveguide crossing (12) and an output port coupled to the second arm (26) of the first waveguide crossing (12), wherein the first waveguide loop (16) directly connects the first arm (24) to the second arm (26) of the first waveguide crossing (12). [2] Structure (10) according to claim 1, wherein the first waveguide crossing (12) comprises a third arm (22) and a fourth arm (28), and further comprising: a first waveguide core (14) coupled to the third arm (22) of the first waveguide junction (12); and a second waveguide core (20) which is coupled to the fourth arm (28) of the first waveguide crossing (12). [3] Structure (10) according to claim 2, wherein the first arm (24) and the third arm (22) of the first waveguide crossing (12) are aligned along a first longitudinal axis (15), and the second arm (26) and the fourth arm (28) of the first waveguide crossing (12) are aligned along a second longitudinal axis (19). [4] Structure (10) according to claim 3, wherein the first longitudinal axis (15) is orthogonal to the second longitudinal axis (19). [5] Structure (10) according to claim 1, wherein the first waveguide loop (16) comprises a plurality of waveguide bends (40, 42, 44). [6] Structure (10) according to claim 5, wherein each of the plurality of waveguide bends (40, 42, 44) provides a change of direction of 90°. [7] Structure (10) according to claim 6, wherein the plurality of waveguide bends (40, 42, 44) together provide a change of direction of 270°. [8] Structure (10) according to claim 1, wherein the first waveguide loop (16) comprises a first waveguide bend (40), a second waveguide bend (42), and a third waveguide bend (44), wherein the first waveguide bend (40) provides a change of direction of 90°, the second waveguide bend (42) provides a change of direction of 90°, and the third waveguide bend (44) provides a change of direction of 90°. [9] Structure (10) according to claim 8, wherein the first waveguide loop (16) comprises a first section (46) coupling the first waveguide bend (40) to the first arm (24) of the waveguide crossing (12), a second section (48) coupling the second waveguide bend (42) to the first waveguide bend (40), a third section (50) coupling the second waveguide bend (42) to the third waveguide bend (44), and a fourth section (52) coupling the third waveguide bend (44) to the second arm (26). [10] Structure (10) according to claim 9, wherein the first section (46), the second section (48), the third section (50) and the fourth section (52) are each even sections. [11] Structure (10) according to claim 10, wherein the first section (46) is aligned parallel to the third section (50), and the second section (48) is aligned parallel to the fourth section (52). [12] Structure (10) according to claim 1, wherein the first arm (24) and the second arm (26) each have a side surface with a curvature defined by a cosine function. [13] Structure (10) according to claim 1, wherein the first waveguide crossing (12) comprises a third arm, and further comprising: a second waveguide junction (12a) comprising a first arm, a second arm and a third arm coupled to the third arm of the first waveguide junction (12); and a second waveguide loop (16a) having an input port coupled to the first arm of the second waveguide crossing (12a) and an output port coupled to the second arm of the second waveguide crossing (12a), wherein the second waveguide loop (16a) connects the first arm directly to the second arm of the second waveguide crossing (12a). [14] Structure (10) according to claim 13, wherein the first waveguide loop (16) comprises a first plurality of waveguide bends (40, 42, 44), and the second waveguide loop (16a) comprises a second plurality of waveguide bends (40, 42, 44). [15] Structure (10) according to claim 14, wherein each of the first plurality of waveguide bends (40, 42, 44) provides a change of direction of 90°, and each of the second plurality of waveguide bends (40, 42, 44) provides a change of direction of 90°. [16] Structure (10) according to claim 15, wherein the first plurality of waveguide bends (40, 42, 44) together provide a change of direction of 270°, and the second plurality of waveguide bends (40, 42, 44) together provide a change of direction of 270°. [17] Procedure encompassing: Forming a first waveguide crossing (12) comprising a first arm (24), a second arm (26) and a transition (30) connecting the first arm (24) to the second arm (26); and Forming a first waveguide loop (16) having an input port coupled to the first arm (24) of the first waveguide crossing (12) and an output port coupled to the second arm (26) of the first waveguide crossing (12), wherein the first waveguide loop (16) directly connects the first arm (24) to the second arm (26) of the first waveguide crossing (12). [18] Method according to claim 17, wherein the first waveguide crossing (12) comprises a third arm, and further comprising: Forming a second waveguide junction (12a) comprising a first arm, a second arm, and a third arm coupled to the third arm of the first waveguide junction (12); and Forming a second waveguide loop (16a) that couples the first arm of the second waveguide crossing (12a) with the second arm of the second waveguide crossing (12a). [19] Method according to claim 17, wherein the first waveguide loop (16) comprises a plurality of waveguide bends (40, 42, 44). [20] Method according to claim 19, wherein each of the plurality of waveguide bends (40, 42, 44) provides a change of direction of 90°, and the plurality of waveguide bends (40, 42, 44) together provide a change of direction of 270°.

Citation Information

Patent Citations

  • Track type micro-ring 2*4 thermo-optic switch prepared based on SOI material

    CN109709644A

  • optoelectronic component

    DE102015208983A1

  • reactive termination for a dielectric optical waveguide

    DE1939447A1

  • CN000109709644A