Threshold stress-modulated storage element with variable capacity and manufacturing process for it

Abstract

Storage device comprising a field-effect transistor and a variable-capacitance capacitor, wherein the field-effect transistor comprises: a source region (32), a drain region (38) and a channel region (35) located within a semiconductor material layer (10); and a gate structure located above the channel region (35) and comprising a gate dielectric (50) and an intermediate electrode (52), and where the variable-capacitance capacitor has the following characteristics: a lower capacitor plate having the intermediate electrode (52); an upper capacitor plate that is vertically spaced from the lower capacitor plate, the upper capacitor plate having a control gate electrode (58); a node dielectric (54) with variable capacitance located between the lower capacitor plate and the upper capacitor plate, comprising an electric field-programmable dielectric material providing a variable effective dielectric constant, wherein a data bit is stored in the storage device as a dielectric state of the node dielectric (54) with variable capacitance; and a trench isolation structure (12) that laterally surrounds the source area (32), the drain area (38) and the channel area (35), wherein the intermediate electrode (52) bridges the channel area (35) and a section of the trench isolation structure (12) and the control gate electrode (58) lies within an area of ​​the section of the trench isolation structure (12) and does not extend over the channel area (35).

Description

BACKGROUND

[0001] The threshold voltage of a field-effect transistor is influenced by the capacitance of the gate electrode. If the gate voltage is higher than the threshold voltage, the field-effect transistor is turned on. If the gate voltage is lower than the threshold voltage, the field-effect transistor is turned off. Conventional charge-trap memory devices often have high programming / erase power (greater than 5 volts) to achieve MOSFET threshold voltage modulation.

[0002] US 2019 / 0 130 957 A1 discloses a device comprising a memory cell and a FET transistor that do not have a common electrode layer. US 2006 / 0 223 251 A1 discloses a memory device according to the preamble of claim 8. SUMMARY OF THE INVENTION

[0003] The present invention relates to a memory device according to claim 1, a memory device according to claim 8 and a method for operating a memory device according to claim 13. Preferred embodiments of the invention are specified in the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Aspects of the present disclosure can best be understood by reference to the following detailed description when taken in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various elements are not drawn to scale. Indeed, the dimensions of various elements may be arbitrarily exaggerated or reduced for the purpose of clarity of explanation. Fig. 1A is a top view of a first exemplary structure after forming a trench isolation structure, a gate dielectric material layer, an interelectrode material layer, a variable capacitance node dielectric material layer, and a control gate electrode material layer according to an embodiment of the present disclosure. Fig. Figure 1B is a vertical cross-sectional view of an exemplary structure taken along the vertical plane B - B' of Fig. 1A. Fig. Figure 1C is a vertical cross-sectional view of the first exemplary structure taken along the vertical plane C - C' of Fig. 1A. Fig. 2A is a top view of the first exemplary structure after forming a control gate electrode and a variable capacitance node dielectric according to an embodiment of the present disclosure. Fig. Figure 2B is a vertical cross-sectional view of the first exemplary structure along the vertical plane B - B' of Fig. 2A. Fig. Figure 2C is a vertical cross-sectional view of the first exemplary structure taken along the vertical plane C - C' of Fig. 2A. Fig. 3A is a top view of the first exemplary structure after formation of an intermediate electrode and a gate dielectric according to an embodiment of the present disclosure. Fig. Figure 3B is a vertical cross-sectional view of the first exemplary structure taken along the vertical plane B - B' of Fig. 3A. Fig. Figure 3C is a vertical cross-sectional view of the first exemplary structure along the vertical plane C - C' of Fig. 3A. Fig. 4A is a top view of the first exemplary structure after forming source / drain extension regions and a dielectric gate spacer according to an embodiment of the present disclosure. Fig. Figure 4B is a vertical cross-sectional view of the first exemplary structure taken along the vertical plane B - B' of Fig. 4A. Fig. Figure 4C is a vertical cross-sectional view of the first exemplary structure along the vertical plane C - C' of Fig. 4A. Fig. 5A is a top view of the first exemplary structure after forming source / drain regions according to an embodiment of the present disclosure. Fig. Figure 5B is a vertical cross-sectional view of the first exemplary structure taken along the vertical plane B - B' of Fig. 5A. Fig. Figure 5C is a vertical cross-sectional view of the first exemplary structure taken along the vertical plane C - C' of Fig. 5A. Fig. 6A is a top view of the first exemplary structure after formation of a contact level dielectric layer, via cavities, and metal-semiconductor alloy regions according to an embodiment of the present disclosure. Fig. Figure 6B is a vertical cross-sectional view of the first exemplary structure taken along the vertical plane B - B' of Fig. 6A. Fig. Figure 6C is a vertical cross-sectional view of the first exemplary structure taken along the vertical plane C - C' of Fig. 6A. Fig. 7A is a top view of the first exemplary structure after formation of via structures according to an embodiment of the present disclosure. Fig. Figure 7B is a vertical cross-sectional view of the first exemplary structure taken along the vertical plane B - B' of Fig. 7A. Fig. Figure 7C is a vertical cross-sectional view of the first exemplary structure taken along the vertical plane C - C' of Fig. 7A. Fig. 8A is a top view of a second exemplary structure after forming a trench isolation structure, a sacrificial dielectric layer, a dummy gate structure, and a source extension region and a drain extension region according to an embodiment of the present disclosure. Fig. Figure 8B is a vertical cross-sectional view of the second exemplary structure taken along the vertical plane B-B' of Fig. 8A. Fig. Figure 8C is a vertical cross-sectional view of the second exemplary structure taken along the vertical plane C-C' of Fig. 8A. Fig. 9A is a top view of the second exemplary structure after forming a dummy spacer, a deep source region, and a deep drain region according to an embodiment of the present disclosure. Fig. 9B is a vertical cross-sectional view of the second exemplary structure taken along the vertical plane B - B' of Fig. 9A. Fig. Figure 9C is a vertical cross-sectional view of the second exemplary structure taken along the vertical plane C-C' of Fig. 9A. Fig. 10A is a top view of the second exemplary structure after removing dummy structures according to an embodiment of the present disclosure. Fig. 10B is a vertical cross-sectional view of the second exemplary structure taken along the vertical plane B - B' of Fig. 10A. Fig. Figure 10C is a vertical cross-sectional view of the second exemplary structure taken along the vertical plane C-C' of Fig. 10A. Fig. 11A is a top view of the second exemplary structure after formation of a gate dielectric and an intermediate electrode according to an embodiment of the present disclosure. Fig. 11B is a vertical cross-sectional view of the second exemplary structure taken along the vertical plane B - B' of Fig. 11A. Fig. Figure 11C is a vertical cross-sectional view of the second exemplary structure taken along the vertical plane C-C' of Fig. 11A. Fig. 12A is a top view of the second exemplary structure after formation of a variable capacitance node dielectric and a control gate electrode according to an embodiment of the present disclosure. Fig. 12B is a vertical cross-sectional view of the second exemplary structure taken along the vertical plane B - B' of Fig. 12A. Fig. 12C is a vertical cross-sectional view of the second exemplary structure taken along the vertical plane C - C' of Fig. 12A. Fig. 13A is a top view of the second example structure after formation of a contact level dielectric layer, metal-semiconductor alloy regions, and via structures according to an embodiment of the present disclosure. Fig. 13B is a vertical cross-sectional view of the second exemplary structure taken along the vertical plane B - B' of Fig. 13A. Fig. Figure 13C is a vertical cross-sectional view of the second exemplary structure taken along the vertical plane C-C' of Fig. 13A. Fig. 14A is a top view of a third exemplary structure after formation of a semiconductor fin according to an embodiment of the present disclosure. Fig. 14B is a vertical cross-sectional view of the third exemplary structure taken along the vertical plane B - B' of Fig. 14A. Fig. Figure 14C is a vertical cross-sectional view of the third exemplary structure taken along the vertical plane C-C' of Fig. 14A. Fig. 15A is a top view of the third exemplary structure after forming a gate dielectric, an intergate electrode, a source extension region, and a drain extension region according to an embodiment of the present disclosure. Fig. 15B is a vertical cross-sectional view of the third exemplary structure taken along the vertical plane B - B' of Fig. 15A. Fig. Figure 15C is a vertical cross-sectional view of the third exemplary structure taken along the vertical plane C-C' of Fig. 15A. Fig. 16A is a top view of the third exemplary structure after formation of a variable capacitance node dielectric and a control gate electrode according to an embodiment of the present disclosure. Fig. 16B is a vertical cross-sectional view of the third exemplary structure taken along the vertical plane B - B' of Fig. 16A. Fig. Figure 16C is a vertical cross-sectional view of the third exemplary structure taken along the vertical plane C-C' of Fig. 16A. Fig. 17 is a top view of the third exemplary structure after formation of a dielectric gate spacer and deep source / drain regions according to an embodiment of the present disclosure. Fig. 17B is a vertical cross-sectional view of the third exemplary structure taken along the vertical plane B - B' of Fig. 17A. Fig. Figure 17C is a vertical cross-sectional view of the third exemplary structure taken along the vertical plane C-C' of Fig. 17A. Fig. 18A is a top view of the third exemplary structure after formation of a contact level dielectric layer, metal-semiconductor alloy regions, and via structures according to an embodiment of the present disclosure. Fig. Figure 18B is a vertical cross-sectional view of the third exemplary structure taken along the vertical plane B-B' of Fig. 18A. Fig. Figure 18C is a vertical cross-sectional view of the third exemplary structure taken along the vertical plane C-C' of Fig. 18A. Fig. 19 is a circuit diagram of a combination of a memory device and a control circuit according to an embodiment of the present disclosure. Fig. 20 is a circuit diagram of an active portion of the combination of the memory device and the control circuit of Fig. 19 during a programming operation according to an embodiment of the present disclosure. Fig. 21 is a circuit diagram of an active portion of the combination of the memory device and the circuit diagram of Fig. 19 during an extinguishing operation according to an embodiment of the present disclosure. Fig. Figure 22 is a circuit diagram of an active portion of the combination of the memory device and the control circuit of Fig. 19 during a detection operation according to an embodiment of the present disclosure. Fig. 23 is a flow diagram illustrating steps for operating a memory device of the present disclosure according to an embodiment of the present disclosure. Fig. 24 is a flow diagram illustrating steps for fabricating a memory device of the present disclosure according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0005] The following disclosure provides many different embodiments, or examples, for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples. For example, the formation of a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are formed in direct contact, and may also include embodiments in which additional elements may be formed between the first and second elements such that the first and second elements may not be in direct contact. Additionally, the present disclosure may repeat reference numbers and / or letters in the various examples.This repetition is for the purpose of simplification and clarity and does not in itself imply any relationship between the different embodiments and / or configurations discussed.

[0006] Furthermore, spatially relative terms such as "underlying," "beneath," "under," "overlying," "upper," and the like may be used herein for ease of description to describe the relationship of one element or feature to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass various orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be oriented differently (rotated 90 degrees or at other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly. Unless expressly stated otherwise, any element having the same reference number is assumed to have the same material composition and a thickness within the same thickness range.

[0007] The present disclosure relates generally to semiconductor devices, and more particularly to a threshold voltage modulated memory device employing variable capacitance and methods of forming the same, various aspects of which are described in detail herein. Conventional charge-trap memories utilize high program / erase power (greater than 5 volts) to achieve MOSFET threshold voltage modulation. By stacking resistive switching oxide layers and covering a gate on a MOSFET, a variable capacitance can modulate the threshold voltage by changing its resistance. By employing an RRAM / PCRAM / MRAM as a variable capacitor on the MOSFET, the threshold voltage can be modulated by changing its resistance. In such embodiments, the power consumption of a program / erase operation can be reduced to less than 5 volts compared to other charge-trap memory devices requiring up to 10 volts.

[0008] Fig. 1A is a top view of a first exemplary structure after forming a trench isolation structure, a gate dielectric material layer, an interelectrode material layer, a variable capacitance node dielectric material layer, and a control gate electrode material layer according to an embodiment of the present disclosure. Fig. Figure 1B is a vertical cross-sectional view of the first exemplary structure taken along the vertical plane B - B' of Fig. 1A. Fig. Figure 1C is a vertical cross-sectional view of the first exemplary structure taken along the vertical plane C - C' of Fig. 1A. With regard to Fig. 1A-1C illustrates a first exemplary structure according to an embodiment of the present disclosure, including a substrate 8 having a semiconductor material layer 10. The substrate 8 may be a bulk semiconductor substrate in which the semiconductor material layer 10 may extend from a front surface to a back surface, or may be a semiconductor-on-insulator (SOI) substrate having a buried insulator layer (not shown) underlying the semiconductor material layer 10 and a handle substrate (not shown) underlying the buried insulator layer. For example, the substrate 8 may be a commercially available single crystalline bulk semiconductor substrate or a commercially available semiconductor-on-insulator substrate.

[0009] The semiconductor material layer 10 may contain a single-crystalline semiconductor material or a polycrystalline semiconductor material. In one embodiment, the entirety of the semiconductor material layer 10 may contain a single-crystalline semiconductor material, such as single-crystalline silicon. The semiconductor material of the semiconductor material layer 10 may have a doping of a first conductivity, which may be p or n. The atomic concentration of dopants of the first conductivity in the semiconductor material layer 10 may be in a range of 1.0 × 10 14 / cm 3 up to 3.0 ×10 17 / cm 3 , although lower and higher atomic concentrations may also be used. In one embodiment, the semiconductor material layer 10 may consist essentially of silicon and dopants of the first conductivity.

[0010] Trench isolation structure 12 may be formed in an upper portion of semiconductor material layer 10. For example, trenches having a depth in a range of 50 nm to 500 nm may be formed through the top surface of semiconductor material layer 10 by applying a photoresist over the top surface of semiconductor material layer 10 and transferring the structure in the photoresist layer into the upper portion of semiconductor material layer 10 using an anisotropic etching process. The photoresist layer may be substantially removed, e.g., by ashing. A dielectric material may be deposited in the trenches, and excess portions of the dielectric may be removed from above the horizontal plane comprising the top surface of semiconductor material layer 10 using a planarization process, such as a chemical mechanical polishing (CMP) process.The remaining portions of the dielectric material filling the trenches comprise the trench isolation structure 12. The trench isolation structure 12 may laterally surround device regions, one of which is shown in . Fig. 1A-1C. For example, a device region may have a perimeter P that is laterally surrounded by the trench isolation structure 12. In one embodiment, each device region may be laterally surrounded by a trench isolation structure 12. While embodiments of the present disclosure are described using a single device region, it should be understood that multiple device regions, laterally surrounded by a respective trench isolation structure 12, may be formed in the first example structure.

[0011] A gate dielectric material layer 50L may be formed over the top surface of the semiconductor material layer 10. The gate dielectric material layer 50L may include a semiconductor oxide material formed by oxidizing a surface portion of the semiconductor material layer 10. For example, the semiconductor material layer 10 may include silicon, and a thermal oxidation process or a plasma oxidation process may be performed to convert the surface portion of the semiconductor material layer 10 into a silicon oxide layer. Alternatively or additionally, a gate dielectric material may be deposited over the top surface of the substrate 8. The gate dielectric material may include silicon oxide and / or a dielectric metal oxide material, such as aluminum oxide, hafnium oxide, yttrium oxide, lanthanum oxide, tantalum oxide, titanium oxide, zirconium oxide, hafnium aluminum oxide, hafnium zirconium oxide, hafnium tantalum oxide, etc.Other suitable gate dielectric materials may be within the contemplated scope of the disclosure. The gate dielectric material may be deposited by a conformal deposition process, such as a chemical vapor deposition process or an atomic layer deposition process. The thickness of the gate dielectric material layer 50L may be in a range from 1 nm to 10 nm, such as from 2 nm to 6 nm, although lesser or greater thicknesses may also be used.

[0012] An interelectrode material layer 52L may be deposited over the gate dielectric material layer 50L. The interelectrode material layer 52L includes a conductive material that can subsequently be used to form a gate electrode. In particular, the interelectrode material layer 52L includes a material that can provide a suitable threshold voltage to the field-effect transistor that is subsequently formed. In one illustrative example, the interelectrode material layer 52L may include at least one conductive material, such as doped polysilicon, a metal silicide, platinum, ruthenium, iridium, aluminum, molybdenum, palladium, tantalum, zirconium, osmium, titanium, rhodium, rhenium, alloys thereof, or combinations thereof. Other suitable interelectrode materials may be within the contemplated scope of the disclosure.The interelectrode material layer 52L may be deposited by a conformal deposition process, such as a chemical vapor deposition process, and / or by a non-conformal deposition process, such as a physical vapor deposition process. The thickness of the interelectrode material layer 52L may be in a range from 5 nm to 100 nm, such as from 10 nm to 40 nm, although lower and higher thicknesses may also be used.

[0013] A variable-capacitance dielectric material layer 54L may subsequently be deposited over the interelectrode material layer 52L. The variable-capacitance dielectric material layer 54L includes a dielectric material capable of providing a variable effective dielectric constant depending on the hysteresis effect of an external vertical electric field applied thereover. The variable-capacitance dielectric material layer 54L is subsequently used as a node oxide of a capacitor structure subsequently formed. The effective dielectric constant of the variable-capacitance node dielectric layer 54L may change by at least 5%, and preferably by at least 10%, and may change by a percentage in a range of 10% to 100% relative to a minimum value, although larger percentage changes may also be used.

[0014] In one embodiment, the variable-capacitance node dielectric material layer 54L may include, or consist essentially of, a metal oxide material that provides reversible electric field-dependent resistance magnitude modulation. The reversible electric field-dependent resistance magnitude modulation within the material of the variable-capacitance node dielectric material layer 54L may provide two dielectric states provided using the hysteresis effect of a vertical electric field to be subsequently applied thereover. The two dielectric states may include a first dielectric state having a first electrical resistance and a first effective dielectric constant, and a second dielectric state having a second electrical resistance and a second effective dielectric constant.The range of the first electrical resistance value and the second electrical resistance value may be less than 1.0 × 10. -2 S / m and can generally be in a range of 1.0 × 10 -15 S / m to 1.0 × 10 -3 S / m. In general, the first dielectric state and the second dielectric state may provide different electrical resistance values ​​for the metal oxide material of the variable capacitance node dielectric layer 54L.

[0015] In one embodiment, the variable-capacitance node dielectric material layer 54L may include an oxygen-vacancy-modulated metal oxide material or a filament-forming metal oxide. An oxygen-vacancy-modulated metal oxide material contains oxygen vacancies that shift along the direction of an externally applied electric field. A filament-forming metal oxide material creates conductive filaments that increase the electrical conductivity of the filament-forming metal oxide material upon application of an electric field having a field strength exceeding a critical field strength. Resistivity modulation in a thin metal oxide material may result in a change in the effective electrical resistance of the metal oxide material and a change in the effective dielectric constant of the metal oxide material.Examples of metal oxide materials exhibiting resistance modulation include hafnium oxide, zirconium oxide, alumina, tantalum oxide, hafnium aluminum oxide, hafnium zirconium oxide, and hafnium tantalum oxide. The metal oxide material providing reverse electric field-dependent resistance modulation can be deposited by chemical vapor deposition or physical vapor deposition.

[0016] In another embodiment, the variable-capacitance node dielectric material layer 54L includes a metal oxide material capable of providing reverse electric field-dependent motion of metal atoms therein. Generally, dielectric-metal oxides and dielectric-semiconductor compounds that can be used in a conductive bridge structure fall into this category. For example, the variable-capacitance node dielectric material layer 54L may include a metal oxide material such as hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide, hafnium aluminum oxide, hafnium zirconium oxide, and hafnium tantalum oxide. Alternatively, the variable-capacitance node dielectric material layer 54L may include a dielectric-semiconductor compound material such as silicon oxide, silicon oxynitride, or silicon nitride.In general, reversible electric field-dependent movement of metal atoms through the variable-capacitance node dielectric material layer 54L enables formation of a reversibly conductive bridge within the variable-capacitance node dielectric material layer 54L. Other suitable variable-capacitance node dielectric materials may be within the contemplated scope of the disclosure.

[0017] Generally, the variable-capacitance node dielectric material layer 54L can be deposited by chemical vapor deposition, atomic layer deposition, and / or physical vapor deposition. The thickness of the variable-capacitance node dielectric material layer 54L can be in a range from 2 nm to 20 nm, such as from 4 nm to 10 nm, although lesser or greater thicknesses can also be used. The variable-capacitance node dielectric material layer 54L can be thick enough to prevent dielectric breakdown during operation of a field-effect transistor and can be thin enough to apply a sufficiently strong electric field across it to cause a transition from the first dielectric state to the second dielectric state and vice versa.In general, the variable capacitance node dielectric material layer 54L has a variable effective dielectric constant that depends on the hysteresis effect of an electric field thereover.

[0018] A control gate electrode material layer 58L may be deposited over the variable-capacitance node dielectric material layer 54L. The control gate electrode material layer 58L includes a conductive material conducive to creating two dielectric states in conjunction with the variable-capacitance node dielectric material layer 54L and the inter-electrode material layer 52L. In one embodiment, the control gate electrode material layer 58L includes a metallic material that differs from the conductive material of the inter-electrode material layer 52L, thus providing asymmetry in material composition between the control gate electrode material layer 58L and the inter-electrode material layer 52L with respect to the variable-capacitance node dielectric material layer 54L.

[0019] In one embodiment, the variable-capacitance node dielectric material layer 54L includes an oxygen-gap modulated metal oxide material or a filament-forming metal oxide, and the control gate electrode material layer 58L includes a metallic material that is not susceptible to bulk or surface diffusion of materials under device operating conditions. In one embodiment, the control gate electrode material layer 58L includes a transition metal having a melting point higher than 1000 degrees Celsius or a conductive metallic nitride material. For example, the control gate electrode material layer 58L may include a metal such as hafnium, zirconium, tungsten, tantalum, titanium, molybdenum, niobium, rhenium, osmium, iridium, or combinations thereof. In another embodiment, the control gate electrode material layer 58L may include a conductive metallic nitride material such as TiN, TaN, or WN.Other suitable control gate electrode materials may be within the contemplated scope of the disclosure.

[0020] In another embodiment, the variable-capacitance node dielectric material layer 54L includes a metal oxide material capable of providing reversible, electric-field-dependent movement of metal atoms therein, and the control gate electrode material layer 58L includes a metallic material conducive to metal diffusion within the variable-capacitance node dielectric material layer 54L. In one embodiment, the control gate electrode material layer 58L essentially includes and / or consists of a conductive metallic bridge material selected from copper, a copper-containing compound or intermetallic alloy, silver, a silver-containing compound or intermetallic alloy, tellurium, a tellurium-containing compound or intermetallic alloy, aluminum, aluminum, and an aluminum-containing compound or intermetallic alloy.

[0021] The control gate electrode material layer 58L may be deposited by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. The thickness of the control gate electrode material layer 58L may range from 5 nm to 100 nm, such as from 10 nm to 40 nm, although lower or higher thicknesses may also be used.

[0022] Fig. 2A is a top view of the first exemplary structure after forming a control gate electrode and a variable capacitance node dielectric according to an embodiment of the present disclosure. Fig. Figure 2B is a vertical cross-sectional view of the first exemplary structure taken along the vertical plane B - B' of Fig. 2A. Fig. Figure 2C is a vertical cross-sectional view of the first exemplary structure taken along the vertical plane C - C' of Fig. 2A. With regard to Fig. 2A-2C, a first photoresist layer may be applied over the control gate electrode material layer 58L and may be lithographically patterned to form a first photoresist material portion 59. In one embodiment, the first photoresist material portion 59 covers a region of the trench isolation structure 12 and does not cover the portion of the device region. In one embodiment, the first photoresist material portion 59 borders the portion of a channel region that is subsequently formed within the device region.

[0023] A first anisotropic etch process may be performed to remove unmasked portions of the control gate electrode material layer 58L and the variable-capacity node dielectric material layer 54L. The first photoresist material portion 59 is used as an etch mask during the first anisotropic etch process. The first anisotropic etch process may include a sequence of anisotropic etch steps that etch the materials of the control gate electrode material layer 58L and the variable-capacity node dielectric material layer 54L. A patterned portion of the control gate electrode material layer 58L includes a control gate electrode 58. A patterned portion of the variable-capacity node dielectric material layer 54L includes a variable-capacity node dielectric 54. The first photoresist material portion 59 may subsequently be removed, for example, by ashing.

[0024] Fig. 3A is a top view of the first exemplary structure after formation of an intermediate electrode and a gate dielectric according to an embodiment of the present disclosure. Fig. Figure 3B is a vertical cross-sectional view of the first exemplary structure taken along the vertical plane B - B' of Fig. 3A. Fig. Figure 3C is a vertical cross-sectional view of the first exemplary structure along the vertical plane C - C' of Fig. 3A. Fig. 13 is a flow diagram illustrating manufacturing steps of a memory device of the present disclosure according to an embodiment of the present disclosure. With reference to Fig. 3A-3C, a second photoresist layer may be applied over the control gate electrode 58 and the inter-electrode material layer 52L and may be lithographically patterned to form a second photoresist material portion 69. The second photoresist material portion 69 may cover the entire area of ​​the control gate electrode 58 and may have a stripe portion covering an additional area extending over a central portion of the device region adjacent to the control gate electrode 58. In one embodiment, the area of ​​the stripe portion of the second photoresist material portion 69 corresponds to the area of ​​a channel region that will be subsequently formed.

[0025] A second anisotropic etch process may be performed to remove unmasked portions of the interelectrode material layer 52L and the gate dielectric material layer 50L. The second photoresist material portion 69 is used as an etch mask during the second anisotropic etch process. The second anisotropic etch process may include a sequence of anisotropic etch steps that etch the materials of the interelectrode material layer 52L and the gate dielectric material layer 50L. A patterned portion of the interelectrode material layer 52L includes an intermediate electrode 52. A patterned portion of the gate dielectric material layer 50L includes a gate dielectric 50.

[0026] Fig. 4A is a top view of the first exemplary structure after forming source / drain extension regions and a dielectric gate spacer according to an embodiment of the present disclosure. Fig. Figure 4B is a vertical cross-sectional view of the first exemplary structure taken along the vertical plane B - B' of Fig. 4A. Fig. Figure 4C is a vertical cross-sectional view of the first exemplary structure along the vertical plane C - C' of Fig. 4A. With regard to Fig. 4A-4C, electrical dopants may be implanted into unmasked portions of the semiconductor material layer 10 to form source / drain extension regions (32E, 38E). For example, if the semiconductor material layer 10 contains dopants of a first conductivity, dopants of a second conductivity may be implanted into surface portions of the semiconductor material layer 10 to form the source / drain extension regions (32E, 38E). If the first conductivity is p, the second conductivity is n, and vice versa. The source / drain extension regions (32E, 38E) may include a source extension region 32E and a drain extension region 38E. The atomic concentration of dopants of the second conductivity in the source / drain extension regions (32E, 38E) may be in a range of 1.0 × 10 16 / cm 3 up to 5.0 × 10 19 / cm 3, although lower and higher atomic concentrations may also be used. The depth of the source / drain extension regions (32E, 38E) may be in a range of 5 nm to 50 nm, although lower and higher depths may also be used. The portion of the semiconductor material layer 10 lying between the source extension region 32E and the drain extension region 38E includes a channel region 35. The channel region 35 underlies the gate dielectric 50. In one embodiment, the control gate electrode 58 lies within a portion of the portion of the trench isolation structure 12 and does not extend beyond the channel region 35. The second photoresist material portion 69 may subsequently be substantially removed by, for example, ashing.

[0027] The combination of the control gate electrode 58, the variable-capacitance node dielectric 54, and the intermediate electrode 52 constitutes a variable-capacitance capacitor, or varactor. The control gate electrode 58 acts as an upper capacitor plate, the variable-capacitance node dielectric 54 acts as a node dielectric capable of providing a variable dielectric constant, and the intermediate electrode 52 acts as a lower capacitor plate. Therefore, the intermediate electrode 52 spans the channel region 35 and a portion of the trench isolation structure 12. The upper capacitor plate, which includes the control gate electrode 58, is vertically spaced from the lower capacitor plate, which includes an intermediate electrode 52.The variable-capacitance node dielectric 54 is located between the lower capacitor plate and the upper capacitor plate and includes an electric field-programmable metal oxide material that provides a variable effective dielectric constant. The electric field-programmable metal oxide material may include two dielectric states that provide two different effective dielectric constants. A data bit may be stored as a dielectric state of the variable-capacitance node dielectric in the memory device.

[0028] At least one dielectric material, such as silicon oxide and / or silicon nitride, may be conformally deposited over the control gate electrode 58 and the intermediate electrode 52 and may be anisotropically etched to form a dielectric gate spacer 56. In particular, the at least one dielectric material may be deposited by a conformal deposition process, such as a chemical vapor deposition process or an atomic layer deposition process. Horizontal portions of at least one dielectric material may be removed by performing an anisotropic etching process. Remaining vertical portions of the at least one dielectric material constitute a dielectric gate spacer 56. The lateral thickness of the dielectric gate spacer 56 may be in a range from 5 nm to 100 nm, such as from 10 nm to 50 nm, although lower and higher lateral thicknesses may also be used.A lower portion of the dielectric-gate spacer 56 laterally surrounds a stack of the gate dielectric 50 and the intermediate electrode 52, and an upper portion of the dielectric-gate spacer 56 laterally surrounds a stack of the control gate electrode 58 and the variable-capacitance node dielectric 54. In one embodiment, the dielectric-gate spacer 56 may have a first opening in which the stack of the control gate electrode 58 and the variable-capacitance node dielectric 54 lies, and a second opening surrounding the portion of the channel region 35.

[0029] Fig. 5A is a top view of the first exemplary structure after forming source / drain regions according to an embodiment of the present disclosure. Fig. Figure 5B is a vertical cross-sectional view of the first exemplary structure taken along the vertical plane B - B' of Fig. 5A. Fig. Figure 5C is a vertical cross-sectional view of the first exemplary structure taken along the vertical plane C - C' of Fig. 5A. With regard to Fig. 5A-5C, electrical dopants of the second conductivity may be implanted into unmasked portions of the semiconductor material layer 10 and the source / drain extension regions (32E, 38E) to form deep source / drain regions (32D, 38D). The deep source / drain regions (32D, 38D) may include a deep source region 32D and a deep drain region 38D. The atomic concentration of dopants of the second conductivity in the deep source / drain regions (32D, 38D) may be in a range of 5.0 × 10 19 / cm 3 up to 2.0 × 10 21 / cm 3, although lower and higher atom concentrations can also be used. The depth of the deep source / drain regions (32D, 38D) can be in a range from 20 nm to 200 nm, such as from 40 nm to 100 nm, although shallower and deeper depths can also be used. The combination of the source extension region 32E and the deep source region 32D forms a source region 32, and the combination of the drain extension region 38E and the deep drain region 38D forms a drain region 38.

[0030] The trench isolation structure 12 laterally surrounds the device region, which includes the source region 32, the drain region 38, and the channel region 35. In one embodiment, the entire upper capacitor plate, which includes the control gate electrode 58, lies within the region of the trench isolation structure 12 and outside the device region, i.e., outside the regions of the source region 32, the drain region 38, and the channel region 35. The lower capacitor plate, which includes the intermediate electrode 52, further includes a first portion located above the channel region 35 and a second portion located below the upper capacitor plate. The entire region of the upper capacitor plate may lie within the region of the lower capacitor plate.

[0031] A combination of a field-effect transistor and a variable-capacitance capacitor is provided. The variable-capacitance capacitor (52, 54, 58) acts as a composite gate structure for the field-effect transistor. The threshold voltage Vt of the field-effect transistor is given by: V t = V FB + 2Φ F + (4εqN a Φ F ) 1 / 2 / C total , where V FB is the flat band voltage of the semiconductor material of the channel region 35, Φ F is the Fermi potential of the semiconductor material of the channel region 35, ε is the permittivity of the semiconductor material of the channel region 35, q is the electric charge of each charge carrier in the semiconductor material of the channel region 35, N a is the density of donor atoms or recipient atoms in the semiconductor material of the channel region 35, and C totalis the total capacitance between the channel region 35 and an electrode to which a gate voltage is applied. According to one embodiment of the present disclosure, the gate voltage is applied to the control gate electrode. In this embodiment, the total capacitance C total between the channel region 35 and the control gate electrode 58, the series capacitance of two capacitor structures comprising the channel region 35, the gate dielectric 50, the intermediate electrode 52, the variable-capacitance node dielectric 54, and the control gate electrode. Therefore, a change in the effective dielectric constant of the variable-capacitance node dielectric 54 results in a change in the total capacitance C total between the channel region 35 and the control gate electrode 58 and therefore results in a change in the threshold voltage V t of the field effect transistor.

[0032] Fig. 6A is a top view of the first exemplary structure after formation of a contact level dielectric layer, via cavities, and metal-semiconductor alloy regions according to an embodiment of the present disclosure. Fig. Figure 6B is a vertical cross-sectional view of the first exemplary structure taken along the vertical plane B - B' of Fig. 6A. Fig. Figure 6C is a vertical cross-sectional view of the first exemplary structure taken along the vertical plane C - C' of Fig. 6A. With regard to Fig. 6A-6C, a dielectric material may be deposited over the field effect transistor incorporating the variable capacitance capacitor (52, 54, 58) and the trench isolation structure 12. The dielectric material may include a planarizable dielectric material, such as undoped silicate glass or a doped silicate glass, or a self-planarizing dielectric material, such as flowable oxide (FOX). The dielectric material may be deposited by a chemical vapor deposition process (such as a plasma-enhanced chemical vapor deposition process) or by spin coating. The top surface of the dielectric material may be planarized during or after the deposition process. A dielectric material layer having a planar (i.e., horizontal) top surface is formed, through which via structures are substantially formed.Therefore, the dielectric material is referred to herein as a contact level dielectric layer 70. The top surface of the contact level dielectric layer 70 may be planar and may overlie the top surface of the control gate electrode 58. The vertical distance between the top surface of the contact level dielectric layer 70 and the top surfaces of the control gate electrode 58 may be in a range of 30 nm to 400 nm, although thinner and thicker thicknesses may also be used.

[0033] A photoresist layer (not shown) may be applied over the contact level dielectric layer 70 and may be lithographically patterned to form discrete openings therethrough. The openings in the photoresist layer may be formed over the source region 32, the drain region 38, the control gate electrode 58, and a portion of the intermediate electrode 52 not underlying the control gate electrode 58. An anisotropic etch process may be performed to form via cavities 71 through the contact level dielectric layer 70.The via cavities 71 include a source via cavity extending from the top surface of the contact level dielectric layer 70 to a top surface of the source region 32, a drain via cavity extending from the top surface of the contact level dielectric layer 70 to a top surface of the drain region 38, an intergate via cavity extending from the top surface of the contact level dielectric layer 70 to a top surface of the intermediate electrode 52, and a control gate via cavity extending from the top surface of the contact level dielectric layer 70 to a top surface of the control gate electrode 58.

[0034] Optionally, a metal capable of forming a metal-semiconductor alloy may be deposited into the via cavities 71 by a conformal or non-conformal deposition process. If the semiconductor material layer 10 contains and / or consists essentially of doped silicon, the metal may be a material capable of forming a metal silicide. For example, the metal may include nickel, titanium, tungsten, molybdenum, platinum, or another metal capable of forming a metal silicide. Other suitable metal materials are within the contemplated scope of the disclosure. An annealing process may be performed at an elevated temperature to induce formation of a metal silicide material. The elevated temperature may be in a range of 500 degrees Celsius to 750 degrees Celsius. Unreacted portions of the metal may be removed by a wet etching process that selectively etches the metal onto the metal silicide material.Remaining portions of the metal silicide material may include source-side metal-semiconductor alloy regions 62 contacting the source region 32 and drain-side metal-semiconductor alloy regions 68 contacting the drain region 38. In embodiments where the intermediate electrode 52 includes a semiconductor material, a gate-side metal-semiconductor alloy region may be formed.

[0035] Fig. 7A is a top view of the first exemplary structure after formation of via structures according to an embodiment of the present disclosure. Fig. Figure 7B is a vertical cross-sectional view of the first exemplary structure taken along the vertical plane B - B' of Fig. 7A. Fig. Figure 7V is a vertical cross-sectional view of the first exemplary structure along the vertical plane C - C' of Fig. 7A. With regard to Fig. 7A-7C, a metallic liner 72A containing diffusion barrier material may be deposited at peripheral portions of the remaining volumes of the via cavities 71. The metallic liner 72A includes a conducive metallic nitride material (such as TiN, TaN, or WN) and / or a metallic carbide material (such as TiC, TaC, or WC). Other suitable metallic liner and metallic carbide materials are within the contemplated scope of the disclosure. The thickness of the metallic liner 72A may be in a range of 3 nm to 15 nm, although lesser or greater thicknesses may also be used.

[0036] A metallic fill material 72B, such as Cu, W, Mo, Co, Ru, and / or another elemental metal or intermetallic alloy, may be deposited in remaining volumes of the via cavities 71. Other suitable metallic fill materials are within the contemplated scope of the disclosure. Portions of the metallic fill material 72B and the metallic liner 72A that lie above the horizontal plane comprising the top surface of the contact level dielectric layer 70 may be removed by a planarization process. Each combination of a remaining portion of the metallic fill material 72B and the metallic liner 72A that fills a respective one of the via cavities 71 constitutes a via structure (82, 88, 85, 86).The via structures (82, 88, 85, 86) include a source via structure 82 contacting the source-side metal-semiconductor alloy region 62, drain via structures 88 contacting the drain-side metal-semiconductor alloy region 68, intergate via structures 85 contacting the intermediate electrode 52 (or a gate-side metal-semiconductor alloy region, if present), and a control gate via structure 86 contacting the control gate electrode 58. Each of the via structures (82, 88, 85, 86) includes a respective metallic liner 72A and a respective portion of metallic fill material 72B, and may include a top surface within the horizontal plane that includes the top surface of the contact level dielectric layer 70.

[0037] The combination of the field effect transistor and the variable capacitance capacitor (52, 54, 58) acts as a memory device capable of storing a bit as the dielectric state of the variable capacitance node dielectric 54.

[0038] In relation to Fig. 8A-8C illustrate a second exemplary structure according to an embodiment of the present disclosure, comprising a trench isolation structure formed in a semiconductor material layer 10 of a substrate 8. The semiconductor material layer 10 and the trench isolation structure 12 may be the same as in the first exemplary structure, as shown in Fig. 1A-7C previously illustrated.

[0039] A sacrificial dielectric layer, such as a silicon oxide layer, and a sacrificial gate material layer may be formed over the top surface of the substrate 8. The sacrificial dielectric layer and sacrificial gate material layer may be patterned into a gate structure to form a stack of a sacrificial gate dielectric 450 and a dummy gate structure 452. The sacrificial gate dielectric 450 may include a sacrificial dielectric material, such as silicon oxide, having a thickness ranging from 1 nm to 30 nm, although thicker or thinner layers may be used. The dummy gate structure 452 includes any sacrificial material that can be selectively removed from the materials of the semiconductor material layer 10 and the trench isolation structure 12. For example, the dummy gate structure 452 may include a silicon-germanium alloy, amorphous carbon, diamond-like carbon, borosilicate glass, a silicon-based polymer, etc.

[0040] Semiconductor material layer 10 may be doped with a first conductivity. Dopants with a second conductivity may be implanted using dummy gate structure 452 as an implantation mask to form a source extension region 32E and a drain extension region 38E, which may have the same depth and the same dopant concentration range as in the first exemplary structure.

[0041] In relation to Fig. 9A-9C, a dummy spacer 456 may be formed around the dummy gate structure 452 by conformally depositing a sacrificial material layer and anisotropic etching of the sacrificial material layer. The dummy spacer 456 may include any material that may be used for the dummy gate structure 452. The material of the dummy spacer 456 may be the same as or different from the material of the dummy gate structure 452. The thickness of the dummy spacer 456 may be in the same range as the dielectric gate spacer 56 of the first example structure.

[0042] Additional dopants of the second conductivity may be implanted into unmasked portions of the semiconductor material layer 10 and the source / drain extension regions (32E, 38E) to form a deep source region 32D and a deep drain region 38E. The combination of the dummy spacer 456 and the dummy gate structure 452 may be used as an implantation mask. The deep source regions 32D and the deep drain regions 38D may have the same range of dopant concentrations and the same range of depths as in the first example structure. Each combination of a source extension region 32E and a deep source region 32D constitutes a source region 32, and each combination of a drain extension region 38E and a deep drain region 38D constitutes a drain region 38.

[0043] In relation to Fig. 10A-10C, the dummy spacer 456, the dummy gate structure 452, and the sacrificial gate dielectric 450 may be selectively removed from the materials of the semiconductor material layer 10 and the trench isolation structure 12 by performing at least one etching process (such as at least one wet etching process) and / or an ashing process. A suitable cleaning process may be performed subsequently.

[0044] In relation to Fig. 11A-11C, a gate dielectric material layer and an interelectrode material layer may be deposited. The gate dielectric material layer and the interelectrode material layer may be patterned into a gate electrode structure to form a gate dielectric 50 and an interelectrode 52. A patterned photoresist layer may be formed over the interelectrode material layer. An anisotropic etch process may be used to transfer the pattern in the photoresist layer through the interelectrode material layer and the gate dielectric material layer. The structure of the patterned photoresist layer may be the same as the structure of the interelectrode 52 in the first example structure, as previously described with respect to Fig. 1A-7C. The gate dielectric 50 may include the same material and have the same thickness range as in the first example structure. The intermediate electrode 52 may include the same material and have the same thickness range as in the first example structure.

[0045] In relation to Fig. 12A-12C, a variable-capacity node dielectric material layer and a control gate electrode material layer may be deposited. The variable-capacity node dielectric material layer and the control gate electrode material layer may be patterned into a variable-capacity node dielectric 54 and a control gate electrode 58. A patterned photoresist layer may be formed over the control gate electrode material layer. An anisotropic etch process may be used to transfer the pattern in the photoresist layer through the control gate electrode material layer and the variable-capacity node dielectric material layer. The structure of the patterned photoresist layer may be the same as the structure of control gate electrode 58 in the first example structure (see, for example, Fig. 2A-2C). The variable capacitance node dielectric 54 may include the same material and may have the same thickness range as in the first example structure. The control gate electrode 58 may include the same material and may have the same thickness range as in the first example structure.

[0046] In relation to Fig. 13A-13C, a dielectric gate spacer 56 may optionally be formed by conformal deposition and anisotropic etching of a dielectric gate spacer material layer. The dielectric gate spacer 56 may have the same material and lateral thickness as in the first exemplary structure. Following are the processing steps of Fig. 6A - 7C to form a contact level dielectric layer 70, metal-semiconductor alloy regions (62, 68) and via structures (82, 85, 88, 86).

[0047] Generally speaking, various other types of field-effect transistors may be employed to provide the semiconductor device of the present disclosure, which may be a fin field-effect transistor, a gate-all-around field-effect transistor, a nanowire field-effect transistor, a vertical field-effect transistor, or any other type of field-effect transistor. In each embodiment, a gate dielectric 50 and an intergate electrode 52 may be formed over the entire channel surface overlying a channel region 35, and a stack of a variable-capacitance node dielectric 54 and a control gate electrode 58 may be formed on a portion of the intergate electrode 52. Another portion of the intergate electrode 52 may be contacted by intergate via structures 85.

[0048] Fig. 14A-18C illustrate a third exemplary structure in which a fin field effect transistor may be formed instead of a planar field effect transistor.

[0049] In relation to Fig. 14-14C, a semiconductor fin 720 may be provided over a substrate 8 having an insulating substrate layer 710. In one embodiment, the semiconductor fin 720 may be a patterned portion of a top-side semiconductor layer of a semiconductor-on-insulator (SOI) substrate. The insulating substrate layer 720 may be a buried oxide layer of the SOI substrate. Alternatively, the semiconductor fin 720 may be a portion of a semiconductor material layer bonded to the insulating substrate layer 710 and subsequently patterned. For example, a single-crystal silicon substrate having a hydrogen implantation layer therein may be bonded to the insulating substrate layer 710 and subsequently cleaved to remove a bulk portion of the single-crystal silicon substrate.The remaining thin surface portion of the single-crystalline silicon substrate may be patterned to form the semiconductor fin 720. While the present disclosure is described using an embodiment in which the semiconductor fin 720 is provided on an insulating substrate layer 710, embodiments are expressly contemplated herein in which the semiconductor fin 720 may be formed on a top surface of a semiconductor material layer, and an underlying portion of the semiconductor material layer is suitably electrically isolated from a combination of trench isolation structures and a plurality of reverse-biased doped wells thereunder. The semiconductor fin 720 may be single-crystalline or polycrystalline. The height of the semiconductor fin 720 may be in a range of 50 nm to 500 nm, although lower or higher heights may also be used.The semiconductor fin 720 may be doped with a first conductivity. The atomic concentration of dopants in the semiconductor fin 720 may be in a range of 1.0 × 10 14 / cm 3 up to 3.0 × 10 17 / cm 3 , although lower and higher atom concentrations can also be used. The width of the semiconductor fin 720 can be in a range of 10 nm to 80 nm, although lower and higher widths can also be used.

[0050] In relation to Fig. 15A - 15C, the processing steps of Fig. 1A-1C, discussed previously, may be performed to sequentially deposit a gate dielectric material layer 50L, an interelectrode material layer 52L, a variable-capacitance node dielectric material layer, and a control gate electrode material layer. The material composition and thickness of each layer may be the same as in the first example structure.

[0051] A photoresist layer (not shown) may be applied over the control gate electrode material layer. The photoresist layer may be lithographically patterned to form a gate structure covering a portion of the control gate electrode material layer that is laterally displaced from a central portion of the semiconductor fin 720. An anisotropic etch process may be performed to etch unmasked portions of the control gate electrode material layer and the variable-capacity node dielectric material layer. A patterned portion of the control gate electrode material layer includes a control gate electrode 58. A patterned portion of the variable-capacity node dielectric material layer includes a variable-capacity node dielectric 54. The control gate electrode 58 and the variable-capacity node dielectric 54 may have vertically coincident sidewalls, i.e.,Sidewalls that lie within a common vertical plane. The photoresist layer can subsequently be removed, for example, by ashing.

[0052] In relation to Fig. 16A - 16C, the processing steps of Fig. 3A-3C, previously described, may be performed to pattern the gate dielectric material layer 50L and the interelectrode material layer 52L. A patterned photoresist layer may be used as an etch mask layer during an anisotropic etch process that patterns the gate dielectric material layer 50L and the interelectrode material layer 52L into a gate dielectric 50 and an interelectrode 52. The gate dielectric 50 and the interelectrode 52 bridge a central portion of the semiconductor fin 720 and underlie the stack of the control gate electrode 58 and the variable-capacitance node dielectric 54. The dimension of the interelectrode 52 along the longitudinal direction of the semiconductor fin 720 is the gate length of the fin field-effect transistor.

[0053] An ion implantation process may be performed using the intermediate electrode 52 as an implantation mask structure to implant dopants of a second conductivity into unmasked portions of the semiconductor fin 720. The second conductivity is opposite to the first conductivity. A source extension region 32E and a drain extension region 38E may be formed in the implanted portions of the semiconductor fin 720. The unimplanted portion of the semiconductor fin 720 underlying the intermediate electrode 52 establishes a channel region 35. The atomic concentration of dopants of the second conductivity in the source extension region 32E and the drain extension region 38E may be the same as in the first exemplary structure.

[0054] In relation to Fig. 17A - 17C, the processing steps of Fig. 5A-5C, previously described, may be performed to form a dielectric gate spacer 56, a deep source region 32D, and a deep drain region 38D. The dielectric gate spacer 56 may include the same material and may have the same thickness range as in the first example structure. The deep source region 32D and the deep drain region 38D may be formed by implanting dopants of the second conductivity using the combination of the intermediate electrode 52 and the dielectric gate spacer 56 as an implantation mask. The deep source region 32D and the deep drain region 38D may have the same atomic concentration range of dopants of the second conductivity as in the first example structure.Each combination of a source extension region 32E and a deep source region 32D establishes a source region 32, and each combination of a drain extension region 38E and a deep drain region 38D establishes a drain region 38.

[0055] In relation to Fig. 18A - 18C, the processing steps of Fig. 6A - 7C to form a contact level dielectric layer 70, metal-semiconductor alloy regions (62, 68) and via structures (82, 85, 88, 86).

[0056] Fig. 19 illustrates a circuit diagram for a combination of the memory device 100 (comprising the combination of the field-effect transistor and the variable-capacitance capacitor (52, 54, 58)) and a control circuit according to an embodiment of the present disclosure. The memory device 100 includes the field-effect transistor and the variable-capacitance capacitor (52, 54, 58). The field-effect transistor has a gate structure (50, 52) including a gate dielectric 50 and an intermediate electrode 52, and the variable-capacitance capacitor (52, 54, 58) includes a lower capacitor including the intermediate electrode 52, an upper capacitor plate including a control gate electrode 58, and a variable-capacitance node dielectric 54 disposed between the lower capacitor plate and the upper capacitor plate.The threshold voltage of the field-effect transistor while the intermediate electrode 52 is floating depends on the dielectric state of the variable-capacitance node dielectric 54. The threshold voltage of the field-effect transistor while the intermediate electrode 52 is floating is the minimum voltage that must be applied to the control gate electrode 58 while the intermediate electrode 52 is floating to turn on the field-effect transistor.

[0057] The dielectric state of the variable-capacitance node dielectric 54 can be programmed to a state selected from a first dielectric state (e.g., a program state) providing a first capacitance across the variable-capacitance capacitor (52, 54, 58) and a second dielectric state (e.g., an erase state) providing a second capacitance across the variable-capacitance capacitor (52, 54, 58). For example, the dielectric state of the variable-capacitance node dielectric 54 can be programmed to the first dielectric state by applying a first voltage having a first polarity to the control gate electrode 58 relative to the intermediate electrode 52, or can be programmed to the second dielectric state by applying a second voltage having a second polarity to the control gate electrode 58 relative to the intermediate electrode 52.The second polarity can be opposite to the first polarity.

[0058] Application of the first voltage or the second voltage can be effected by a programming circuit (120, 110) or by an erase circuit (130, 110). The programming circuit (120, 110) is configured to apply a programming voltage having the first polarity to the control gate electrode 58 relative to the intermediate electrode 52. The erase circuit (130, 110) can be configured to apply an erase voltage having the second polarity to the control gate electrode 58 relative to the intermediate electrode 52. The second polarity is opposite to the first polarity. For example, if the first polarity is positive, the second polarity is negative and vice versa.

[0059] In an illustrative example, the programming circuit (120, 110) may include a programming voltage connection switch 120, which may include a field-effect transistor. One of the source / drain regions of the field-effect transistor of the programming voltage connection switch 120 may be electrically connected to the control gate electrode 58, and another of the source / drain regions of the field-effect transistor of the programming voltage connection switch 120 may be electrically connected to a voltage source that provides a programming voltage +Vp, which may be the first voltage. The programming circuit (120, 110) may include a ground switch 110 connected to the intermediate electrode 52 and configured to provide the intermediate electrode 52 with a state consisting of a first state in which the intermediate electrode 52 is floating (i.e.a floating state), and a second state in which the intermediate electrode is electrically grounded (i.e., a grounded state). In one embodiment, the programming circuit +Vp may have a magnitude in a range of 2 V to 10 V, such as from 3 V to 10 V, although lower or higher magnitudes may also be used.

[0060] The erase circuit (130, 110) may include an erase voltage connection switch 130, which may include a field-effect transistor. One of the source / drain regions of the field-effect transistor of the erase voltage connection switch 130 may be electrically connected to the control gate electrode 58, and another of the source / drain regions of the field-effect transistor of the erase voltage connection switch 130 may be electrically connected to a voltage source providing an erase voltage -Ve, which may be the second voltage. The erase circuit (130, 110) may include the ground switch 110. In one embodiment, the erase voltage -Ve may have a magnitude in a range of 2 V to 10 V, such as from 3 V to 10 V, although lower and higher magnitudes may also be used.

[0061] In general, the variable-capacitance node dielectric 54 of the variable-capacitance capacitor (52, 54, 58) may have a variable effective dielectric constant that depends on the hysteresis effect of the electric field across the upper capacitor plate (including the control gate electrode 58) and the lower capacitor plate (including the intermediate electrode 52). The variable-capacitance node dielectric 54 may be programmed to the first state or the second state by applying an electric field across the upper capacitor plate and the lower capacitor plate. To perform a program operation, the programming voltage connection switch 120 and the ground switch 110 are turned on. During the program operation, a programming voltage having the first polarity is applied to the control gate electrode 58 relative to the intermediate electrode 52.To perform an erase operation, the erase voltage connection switch 130 and the ground switch 110 are turned on. During the erase operation, an erase voltage having the second polarity may be applied to the control gate electrode 58 relative to the intermediate electrode 52.

[0062] In one embodiment, the variable-capacitance node dielectric 54 includes and / or consists essentially of a metal oxide material that provides reversible electric field-dependent resistance modulation, and the first dielectric state and the second dielectric state provide different electrical resistances for the metal oxide material of the variable-capacitance node dielectric 54. The ratio of the electrical resistance of the first electrical state to the electrical resistance of the second electrical state may be in a range of 1.0 × 10 -10to 1 / 3 or in a range of 3 to 1.0 × 10 10 , although different ratios may also be used. In one embodiment, the variable-capacitance node dielectric 54 includes and / or consists essentially of a resistance-modulated metal oxide material, and the control gate electrode 58 includes and / or consists essentially of a transition metal having a melting point higher than 1000 degrees Celsius or a conductive metallic nitride material. In one embodiment, the oxygen vacancy distribution within the variable-capacitance node dielectric 54 can be altered during programming of the dielectric state of the variable-capacitance node dielectric 54.

[0063] In one embodiment, the variable-capacitance node dielectric 54 includes and / or consists essentially of a metal oxide material that provides reversible electric field-dependent movement of metal atoms therein. In this embodiment, the control gate electrode 58 may include and / or consist essentially of a conductive metallic bridge material selected from copper, a copper-containing compound or intermetallic alloy, tellurium, a tellurium-containing compound or intermetallic alloy, aluminum, and an aluminum-containing compound or intermetallic alloy. Other suitable metallic materials are within the contemplated scope of the disclosure. The electrical resistance within the variable-capacitance node dielectric 58 may be changed during programming of the dielectric state of the variable-capacitance node dielectric 54.

[0064] The memory device may include a sense circuit (150, 110, 160, 180, 190). The sense circuit (150, 110, 160, 180, 190) may be configured to apply a bias voltage across the drain region 38 and the source region 32 and to apply a sense gate voltage Vs to the control gate electrode 58 during the sense step. The field-effect transistor may have a first threshold voltage while the variable-capacitance node dielectric 58 is under the first dielectric state and may have a second threshold voltage while the variable-capacitance node dielectric 58 is under the second dielectric state. The sense gate voltage Vs may be between the first threshold voltage and the second threshold voltage.

[0065] In one embodiment, the sensing circuit (150, 110, 160, 180, 190) may include a sense gate voltage switch 150 configured to apply the sense gate voltage Vs to the control gate electrode 58 during the sensing operation, a source grounding switch 160 configured to electrically ground the source region 32 during the sensing operation, a drain bias switch 180 configured to apply a drain bias voltage Vd to the drain region 38 during the sensing operation, and a current sensing circuit 190 configured to measure the current flowing between the source region 32 and the drain region 38 during the sensing operation. The detection circuit (150, 110, 160, 180, 190) comprises the grounding switch 110, which is configured to detect the first state (iethe potential-free state) to the intermediate electrode 52 during the detection operation and to provide the second state (ie, the electrically grounded state) to the intermediate electrode 52 during the programming operation or during the erasing operation.

[0066] In relation to Fig. 20 is an equivalent circuit diagram for the circuit diagram of Fig. 8 during programming operation. The programming voltage +Vp is applied to the control gate electrode 58, and the intermediate electrode 52 may be electrically grounded to program the intermediate electrode 52 to the first dielectric state. The field-effect transistor is turned off because the intermediate electrode is electrically grounded.

[0067] In relation to Fig. 21 is an equivalent circuit diagram for the circuit diagram of Fig. 19 during the erase operation. The erase voltage -Ve is applied to the control gate electrode 58, and the intermediate electrode 52 may be electrically grounded to program the intermediate electrode 52 to the first dielectric state. The field-effect transistor is turned off because the intermediate electrode is electrically grounded.

[0068] In relation to Fig. 22 is an equivalent circuit diagram for the circuit diagram of Fig. 19 during the sensing operation. The sense gate voltage Vs is applied to the control gate electrode 58, and the intermediate electrode 52 may be floating. The drain bias switch 180 is turned on and applies the drain bias voltage Vd to the drain region 38, and the source ground switch 160 is turned on and electrically grounds the source region 32. The current sensing circuit 190 measures the current flowing between the source region 32 and the drain region 38 during the sensing operation. In one embodiment, the magnitudes of the first threshold voltage, the second threshold voltage, and the sense gate voltage may be no greater than 5 V and / or may be in a range of 2 V to 5 V.

[0069] In embodiments where the first threshold voltage is lower than the second threshold voltage, the sense gate voltage Vs is higher than the first threshold voltage and lower than the second threshold voltage. In this embodiment, if the current sense circuit 190 detects electrical current flow during the sense operation, the variable capacitance node dielectric 54 is in the first dielectric state, and if the current sense circuit 190 does not detect electrical current flow during the sense operation, the variable capacitance node dielectric 54 is in the second dielectric state.

[0070] In contrast, in embodiments where the first threshold voltage is higher than the second threshold voltage, the sense gate voltage Vs is lower than the first threshold voltage and higher than the second threshold voltage. In this embodiment, if the current sense circuit 190 detects electric current flow during the sense operation, the variable capacitance node dielectric 54 is in the second dielectric state, and if the current sense circuit 190 does not detect electric current flow during the sense operation, the variable capacitance node dielectric 54 is in the first dielectric state.

[0071] In relation to Fig. 23 illustrates a flowchart of operational steps for operating a memory device of the present disclosure according to an embodiment of the present disclosure. With reference to step 2310 and Fig. 1A-18C, a memory device is provided that includes a field-effect transistor and a variable-capacitance capacitor (52, 54, 58). The field-effect transistor has a gate structure (50, 52) including a gate dielectric 50 and an intermediate electrode 52, and the variable-capacitance capacitor (52, 54, 58) includes a lower capacitor plate including the intermediate electrode 52, an upper capacitor plate including a control gate electrode 58, and a variable-capacitance node dielectric 54 located between the lower capacitor plate and the upper capacitor plate. A threshold voltage (for the control gate electrode 58) of the field-effect transistor, while the intermediate electrode 52 is floating, depends on a dielectric state of the variable-capacitance node dielectric 54.

[0072] With respect to step 2320 and Fig. 19, Fig. 20 and Fig. 21, the dielectric state of the variable capacitance node dielectric 54 may be programmed to a state selected from a first dielectric state providing a first capacitance across the variable capacitance capacitor (52, 54, 58) and a second dielectric state providing a second capacitance across the variable capacitance capacitor (52, 54, 58). Referring to step 2330 and Fig. 19 and Fig. 22, the dielectric state of the variable capacitance node dielectric 54 can be sensed by applying a sense gate voltage Vs between the first threshold voltage and the second threshold voltage to the control gate electrode 58.

[0073] In relation to Fig. 24 illustrates a flowchart of processing steps for fabricating a memory device of the present disclosure according to an embodiment of the present disclosure. With reference to step 2410 and Fig. 1A -1C, Fig. 11A - 12C and Fig. 15A-15C, a gate dielectric material layer 50L, an interelectrode material layer 52L, a variable capacitance node dielectric material layer 54L, and a control gate electrode material layer 58L may be deposited over a device region and a trench isolation structure 12. With respect to step 2420 and Fig. 2A-2C, 12A-12C, and 15A-15C, a variable capacitance node dielectric 54 and a control gate electrode 58 may be formed by patterning the variable capacitance node dielectric material layer 54L and the control gate electrode material layer 58L, respectively. With respect to step 2430 and Fig. 3A-3C, 11A-11C, and 16A-16C, a gate dielectric 50 and an intermediate electrode 52 may be formed by patterning the gate dielectric material layer 50L and the intermediate electrode material layer 52L. With respect to step 2440 and Fig. 4A - 7C, 8A - 9C, 13A - 13C and 16A - 18C, source / drain regions (32, 38) and metal interconnect structures (such as the via structures (82, 88, 85, 86)) may be formed to provide electrical connection to the various nodes of the field effect transistor and the capacitor (52, 54, 58) of the variable capacitor.

[0074] With reference to all the drawings and according to various embodiments of the present disclosure, a memory device is provided comprising a field-effect transistor and a capacitor (52, 54, 58) with variable capacitance. The field-effect transistor comprises: a source region 32, a drain region 38, and a channel region 35 located within a semiconductor material layer 10; and a gate structure (50, 52) located over the channel region 35 and comprising a gate dielectric 50 and an intermediate electrode 52.The variable capacitance capacitor (52, 54, 58) comprises: a lower capacitor plate having the intermediate electrode 52; an upper capacitor plate vertically spaced from the lower capacitor plate and having a control gate electrode 58; and a variable capacitance node dielectric 54 disposed between the lower capacitor plate and the upper capacitor plate and including an electric field programmable metal oxide material providing a variable effective dielectric constant. A bit of data is stored as a dielectric state of the variable capacitance node dielectric 54 in the memory device. The area of ​​the upper capacitor plate may be smaller than the area of ​​the lower capacitor plate and may lie entirely within the area of ​​the lower capacitor plate.

[0075] According to another embodiment of the present disclosure, a memory device comprising a field-effect transistor and a capacitor (52, 54, 58) with variable capacitance is provided. The field-effect transistor comprises: a source region 32, a drain region 38, and a channel region 35 located within a semiconductor material layer 10; and a gate structure (50, 52) located over the channel region 35 and including a gate dielectric 50 and an intermediate electrode 52.The variable capacitance capacitor (52, 54, 58) comprises: a lower capacitor plate having the intermediate electrode 52; an upper capacitor plate vertically spaced from the lower capacitor plate and having a control gate electrode 58; and a variable capacitance node dielectric 54 disposed between the lower capacitor plate and the upper capacitor plate, and a metal oxide material providing reversible electric field dependent resistance magnitude modulation.

[0076] The various embodiments of the present disclosure can be used to provide a memory device in which the dielectric state of a variable-capacitance node dielectric 54 disposed between the lower capacitor plate and the upper capacitor plate is used to store a bit of data. The lower capacitor plate has an intermediate electrode that directly contacts a gate dielectric 50 and is floating during sensing. The upper capacitor plate has a control gate electrode used to apply a gate control voltage during programming, erasing, and sensing. The various embodiments of the present disclosure can be used to provide a compact non-volatile memory device.The gate dielectric 50 may be non-tunneling and thus the durability and reliability of the memory device are not affected by any tunnel damage or tunnel degradation.

Claims

[1] A memory device comprising a field-effect transistor and a variable-capacitance capacitor, the field-effect transistor comprising: a source region (32), a drain region (38) and a channel region (35) located within a semiconductor material layer (10); and a gate structure lying over the channel region (35) and having a gate dielectric (50) and an intermediate electrode (52), and wherein the variable capacitance capacitor has: a lower capacitor plate having the intermediate electrode (52); an upper capacitor plate vertically spaced from the lower capacitor plate, the upper capacitor plate having a control gate electrode (58); a variable-capacitance node dielectric (54) disposed between the lower capacitor plate and the upper capacitor plate and containing an electric field-programmable dielectric material providing a variable effective dielectric constant, wherein a data bit is stored as a dielectric state of the variable-capacitance node dielectric (54) in the memory device; and a trench isolation structure (12) laterally surrounding the source region (32), the drain region (38) and the channel region (35), wherein the intermediate electrode (52) bridges the channel region (35) and a portion of the trench isolation structure (12) and the control gate electrode (58) lies within a region of the section of the trench isolation structure (12) and does not extend over the channel region (35). [2] The memory device of claim 1, further comprising a detection circuit (150, 100, 160, 180, 190) configured to: Applying a bias voltage across the drain region (38) and the source region (32) during a detection step; and Applying a sense gate voltage to the control gate electrode (58) during the sense step. [3] The memory device of claim 2, wherein the field effect transistor has two stable configurations comprising: a first configuration in which the variable capacitance node dielectric (54) has a first effective dielectric constant and the field effect transistor has a first threshold voltage; and a second configuration in which the variable capacitance node dielectric (54) has a second effective dielectric constant and the field effect transistor has a second threshold voltage, wherein the sense gate voltage is greater than the first threshold voltage and less than the second threshold voltage. [4] A storage device according to any one of the preceding claims, further comprising: an intergate via structure (85) contacting a top surface of the intermediate electrode (52); and a control electrode via structure (86) contacting a top surface of the control gate electrode (58). [5] The storage device according to claim 4, further comprising: a programming circuit (120) configured to apply a programming voltage having a first polarity to the control gate electrode (58) relative to the intermediate electrode (52); and an erase circuit (130) configured to apply an erase voltage having a second polarity to the control gate electrode (58) relative to the intermediate electrode (52), the second polarity being opposite to the first polarity. [6] The memory device of claim 4 or 5, further comprising a grounding switch (110) connected to the intermediate electrode (52) and configured to provide a condition selected from: a first state in which the intermediate electrode (52) is potential-free; and a second state in which the intermediate electrode (52) is electrically grounded. [7] The storage device of claim 6, wherein the grounding switch (110) is configured to: Providing the first state at the intermediate electrode (52) during a sensing operation; and Providing the second state at the intermediate electrode (52) during a programming operation. [8] A memory device comprising a transistor and a capacitor of variable capacitance, the transistor comprising: a source region (32), a drain region (38) and a channel region (35) located within a semiconductor material layer (10); and a gate structure lying over the channel region (35) and having a gate dielectric (50) and an intermediate electrode (52), and wherein the variable capacitance capacitor has: a lower capacitor plate having the intermediate electrode (52); an upper capacitor plate vertically spaced from the lower capacitor plate, the upper capacitor plate having a control gate electrode (58); and a variable capacitance node dielectric (54) disposed between the lower capacitor plate and the upper capacitor plate and containing a metal oxide material providing reversible electric field dependent resistance magnitude modulation; characterized by that the memory device further comprises a trench isolation structure (12) laterally surrounding the source region (32), the drain region (38) and the channel region (35), wherein: an entirety of the upper capacitor plate lies within a region of the trench isolation structure (12) and outside regions of the source region (32), the drain region (38) and the channel region (35); the lower capacitor plate has a first portion lying above the channel region (35) and a second portion lying below the upper capacitor plate. [9] The memory device of claim 8, wherein the metal oxide material of the variable capacitance node dielectric (54) has two dielectric states determined by a hysteresis effect of a vertical electric field across the lower capacitor plate and the upper capacitor plate. [10] The memory device of claim 9, wherein the two dielectric states of the variable capacitance node dielectric (54) comprise: a first dielectric state having a first effective dielectric constant and has a first electrical resistance value; and a second dielectric state having a second effective dielectric constant different from the first effective dielectric constant and a second electrical resistance different from the first electrical resistance. [11] A storage device according to any one of claims 8 to 10, wherein: the variable capacitance node dielectric (54) contains an oxygen gap modulated metal oxide material or a filament-forming metal oxide; and the control gate electrode (58) contains a transition metal having a melting point higher than 1000 degrees Celsius or a conductive metallic nitride material. [12] A storage device according to any one of claims 8 to 10, wherein: the variable capacitance node dielectric (54) comprises a metal oxide material providing reversible electric field dependent movement of metal atoms therein; and the control gate electrode (58) contains a conductive metallic bridge material selected from copper, a copper-containing compound or intermetallic alloy, tellurium, a tellurium-containing compound or intermetallic alloy, aluminum, and an aluminum-containing compound or intermetallic alloy. [13] A method of operating a memory device, comprising: Providing a memory device according to any one of the preceding claims, wherein a threshold voltage of the field effect transistor is dependent on a dielectric state of the variable capacitance node dielectric (54) while the intermediate electrode (52) is floating; Programming the dielectric state of the variable capacitance node dielectric (54) of the memory device to a state consisting of a first dielectric state providing a first capacitance across the variable capacitance capacitor, and a second dielectric state providing a second capacitance across the variable capacitance capacitor, wherein the field effect transistor has a first threshold voltage while the variable capacitance node dielectric (54) is under the first dielectric state and has a second threshold voltage while the variable capacitance node dielectric (54) is under the second dielectric state; and Sensing the dielectric state of the variable capacitance node dielectric (54) of the memory device by applying a sense gate voltage between the first threshold voltage and the second threshold voltage to the control gate electrode (58) of the memory device. [14] The method of claim 13, wherein the variable capacitance node dielectric (54) has a variable effective dielectric constant that depends on a hysteresis effect of an electric field across the upper capacitor plate and the lower capacitor plate, and the method comprises programming the variable capacitance node dielectric (54) to the first state or the second state by applying an electric field across the upper capacitor plate and the lower capacitor plate. [15] The method of claim 13 or 14, wherein programming the dielectric state of the variable capacitance node dielectric (54) comprises: Applying a programming voltage having a first polarity to the control gate electrode (58) of the memory device relative to the intermediate electrode (52); or Applying an erase voltage having a second polarity to the control gate electrode (58) of the memory device relative to the intermediate electrode (52) of the memory device, the second polarity being opposite to the first polarity. [16] A method according to any one of claims 13 to 15, wherein: the variable capacitance node dielectric (54) of the memory device comprises a metal oxide material providing at least one of reversible electric field dependent resistance magnitude modulation and reversible electric field dependent movement of metal atoms therein; and the first dielectric state and the second dielectric state provide different electrical resistances to the metal oxide material of the variable capacitance node dielectric (54) of the memory device. [17] A method according to any one of claims 13 to 15, wherein: the variable capacitance node dielectric (54) of the memory device contains an oxygen gap modulated metal oxide material or a filament-forming metal oxide; the control gate electrode (58) of the memory device contains a transition metal having a melting point higher than 1000 degrees Celsius or a conductive metallic nitride material; and the method further comprises changing an oxygen vacancy distribution within the variable capacitance node dielectric (54) of the memory device during programming the dielectric state of the variable capacitance node dielectric (54) of the memory device. [18] The method of claim 13, wherein: the variable capacitance node dielectric (54) of the memory device includes a metal oxide material providing reversible electric field dependent movement of metal atoms therein; the control gate electrode (58) of the memory device contains a conductive metallic bridge material selected from copper, a copper-containing compound or intermetallic alloy, tellurium, a tellurium-containing compound or intermetallic alloy, aluminum, and an aluminum-containing compound or intermetallic alloy; and the method further comprises changing an electrical resistance within the variable capacitance node dielectric (54) of the memory device during programming the dielectric state of the variable capacitance node dielectric (54) of the memory device.

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