Curved membrane structure for MEMS building element and method for its manufacture

Abstract

Procedure (200), comprising: Bonding (212) of a support substrate (50) to a semiconductor substrate (24) of a wafer (20), wherein a bonding layer (44, 48) lies between the support substrate (50) and the semiconductor substrate (24) and is bonded to both of them; Performing (218) a first etching process to etch the support substrate (50) and to form an opening (60), wherein the opening (60) penetrates the support substrate (50) and terminates at the bond layer (44, 48), and wherein the opening (60) has substantially straight edges; Etching (220) of the bond layer (44, 48); and Performing (222) a second etching process to widen the opening (60) downwards into the semiconductor substrate (24), wherein a lower section of the opening is curved, further comprising: Etching of the wafer (20) to form a plurality of openings (86) prior to bonding the support substrate (50) to the semiconductor substrate (24), wherein the plurality of openings (86) penetrate a plurality of dielectric layers (38) and extend into the semiconductor substrate (24), and wherein the plurality of openings (86) are connected to the opening (60) after the opening (60) has been extended into the semiconductor substrate (24), wherein the bonding of the support substrate (50) to the semiconductor substrate (24) takes place on the side of the semiconductor substrate (24) that does not have the dielectric layers (38).

Description

BACKGROUND

[0001] MEMS (Micro Electro Mechanical System) devices often have membranes, which are flexible structures subject to movement. The membranes are thin enough to allow them to vibrate. It is desirable to have thin membranes so that the membranes are sensitive while also being structurally sound and able to withstand stress.

[0002] Document DE 10 2018 219 380 A1 describes a MEMS reflector with a center mount. EP 3 518 631 A1 proposes an anisotropic etching process. Document EP 0 969 505 A2 describes a manufacturing method for an SOI substrate. DE 10 2014 103 341 A1 discusses various semiconductor devices and methods for their formation.

[0003] The invention is defined in the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Aspects of the present disclosure can best be understood by reference to the following detailed description when taken in conjunction with the accompanying figures. It should be noted that, in accordance with industry practice, various structural elements are not drawn to scale. Indeed, the dimensions of the various structural elements may be arbitrarily exaggerated or reduced for clarity of illustration. Fig. 1 to 13 illustrate cross-sectional views of intermediate stages in the formation of a micro electro mechanical system (MEMS) device having a domed opening according to some embodiments. Fig. 14 to 23 illustrate cross-sectional views of intermediate formation stages of a process for forming a MEMS device with a domed opening and vias according to some embodiments. Fig. 24 illustrates a process flow for forming a MEMS device according to some embodiments. DETAILED DESCRIPTION

[0005] The following disclosure provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below. For example, the formation of a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are formed in direct contact, as well as embodiments in which additional elements may be formed between the first and second elements such that the first and second elements may not be in direct contact. Furthermore, the present invention may repeat reference numerals and / or letters in the various examples.This repetition is for the purpose of simplicity and clarity and does not, in itself, prescribe any relationship between the various embodiments and / or configurations discussed.

[0006] Furthermore, spatial terms such as "underlying," "beneath," "lower," "overlying," "upper," and the like may be used herein for ease of description to describe a relationship of one element or feature to one or more other elements or features, as illustrated in the figures. The spatial terms are intended to encompass various orientations of the device in use or operation in addition to the orientation illustrated in the figures. The device may be oriented differently (rotated 90 degrees or in other orientations), and the spatial designators used herein may also be interpreted accordingly.

[0007] A micro electromechanical system (MEMS) device with a domed opening and the method for forming it are provided. According to some embodiments of the present disclosure, the domed opening is formed by two or more etching processes, including a first etching process for etching a support substrate and exposing a membrane layer (e.g., a silicon layer), and a second etching process for forming a dome. With the domed opening, the membrane is mechanically strong and can withstand higher stresses. The deformation of the respective die is also reduced. The embodiments discussed herein provide examples for enabling the implementation or use of the subject matter of this disclosure, and modifications that may be made while remaining within the intended scope of various embodiments will be readily apparent to those of ordinary skill in the art.Throughout the views and illustrative embodiments, like reference numerals are used to refer to like elements. Although embodiments of methods may be discussed as being performed in a specific order, other embodiments of methods may be performed in any logical order.

[0008] Fig. 1 to 13 illustrate cross-sectional views of intermediate stages in the formation of a MEMS device with a domed opening according to some embodiments of the present disclosure. The corresponding processes are also schematically depicted in the process flow shown in Fig. 24 is shown.

[0009] Fig. 1 illustrates a cross-sectional view of a device 20. According to some embodiments of the present disclosure, the device is or includes a device wafer that includes active devices and possibly passive devices, illustrated as IC devices 26. The device 20 may have a plurality of chips 22 therein, with one of the chips 22 being illustrated. According to alternative embodiments of the present disclosure, the device 20 is devoid of active devices and may or may not include passive devices. In the discussion below, a device wafer is used as an example of the device 20, so the device 20 is accordingly referred to as a wafer 20. However, embodiments of the present disclosure may also be applied to other types of package components, for example, interposer wafers.

[0010] According to some embodiments of the present disclosure, wafer 20 includes a semiconductor substrate 24 and the elements formed on a top surface of semiconductor substrate 24. Semiconductor substrate 24 may include or be formed from crystalline silicon, crystalline germanium, silicon-germanium, carbon-doped silicon, or a III-V compound semiconductor such as GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or the like. Semiconductor substrate 24 may also be a bulk semiconductor substrate or a semiconductor-on-insulator (SOI) substrate. Shallow trench isolation (STI) regions (not shown) may be formed in semiconductor substrate 24 to separate the active regions in semiconductor substrate 24.

[0011] According to some embodiments of the present disclosure, wafer 20 includes IC devices 26 formed on the top surface of semiconductor substrate 24. IC devices 26 may, according to some embodiments, include complementary metal-oxide-semiconductor (CMOS) transistors, resistors, capacitors, diodes, and the like. The details of IC devices 26 are not illustrated herein. According to alternative embodiments, the wafer is used to form interposers (which are free of active devices), and substrate 24 may be a semiconductor substrate or a dielectric substrate. According to some embodiments, as shown in Fig. 13, a portion of the substrate 24 may have an opening 60 ( Fig. 13) formed in subsequent processes, and the IC components 26 may or may not be formed directly over the opening 60. Accordingly, the IC components 26 directly over the opening 60 are shown in dashed lines to indicate that these portions of the IC components may or may not be formed.

[0012] An inter-layer dielectric (ILD) 28 is formed over the semiconductor substrate 24 and fills the spaces between the gate stacks of transistors (not shown) in the IC devices 26. According to some embodiments, the ILD 28 is formed from phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), fluorine-doped silicate glass (FSG), silicon oxide, silicon nitride, silicon oxynitride (SiO x N y), low-k dielectric materials, or the like. The ILD 28 may be formed using spin coating, flowable chemical vapor deposition (FCVD), or the like. According to some embodiments of the present disclosure, the ILD 28 is formed using a deposition process such as plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), or the like.

[0013] Contact plugs 30 are formed in the ILD 28 and used to electrically connect IC devices 26 to overlying metal lines and vias. According to some embodiments of the present disclosure, the contact plugs 30 comprise or are formed from a conductive material selected from tungsten, aluminum, copper, titanium, tantalum, titanium nitride, tantalum nitride, alloys thereof, and / or multilayers thereof. Formation of contact plugs 30 may include forming contact openings in the ILD 28, filling a conductive material(s) into the contact openings, and performing a planarization process (e.g., a chemical mechanical polishing (CMP) process or a mechanical grinding process) to level the top surfaces of the contact plugs 30 with the top surface of the ILD 28.

[0014] An interconnect structure 32 is formed over the ILD 28 and the contact plugs 30. The interconnect structure 32 includes metal lines 34 and vias 36 formed in dielectric layers (also referred to as inter-metal dielectrics (IMD). The metal lines on a same level are collectively referred to herein as a metal layer. The metal lines 34 in different metal layers are connected to each other by continuous vias 36. The metal lines 34 and the vias 36 may be formed from copper or copper alloys, and may also be formed from other metals. According to some embodiments of the present disclosure, the dielectric layers 38 are formed from dielectric materials with low k values.The dielectric constants (k values) of the low-k dielectric materials may, for example, be lower than about 3.0. The dielectric layers 38 may comprise a low-k carbonaceous material, hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), or the like. According to some embodiments of the present disclosure, forming the dielectric layers 38 includes depositing a porogen-containing dielectric material into the dielectric layers 38 and then performing a curing process to expel the porogen. The remaining dielectric layers 38 are therefore porous.

[0015] The formation of the metal lines 34 and the vias 36 may include single damascene processes and / or double damascene processes. In a single damascene process for forming a metal line or via, a trench or via opening is first formed in one of the dielectric layers 38, followed by filling the trench or via opening with a conductive material. A planarization process, such as a CMP process, is then performed to remove the excess portions of the conductive material that are higher than the top surface of the dielectric layer, leaving a metal line or via in the corresponding trench or via.In a double damascene process, both a trench and a via opening are formed in a dielectric layer, with the via opening underlying and connected to the trench. Conductive materials are then filled into the trench and the via opening to form a metal line and a via, respectively. The conductive materials may include a diffusion barrier layer and a copper-containing metal material over the diffusion barrier layer. The diffusion barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, or the like.

[0016] The metal lines 34 include upper conductive (metal) elements, such as metal lines, metal pads (denoted by 34A), in an upper dielectric layer (denoted as dielectric layer 38A), which is the uppermost layer of the dielectric layers 38. The vias immediately below the upper metal lines 34A are referred to as vias 36A. According to some embodiments, the dielectric layer 38A is formed from a low-k dielectric material similar to the materials of the lower one of the dielectric layers 38. According to other embodiments, the dielectric layer 38A is formed from a dielectric material that does not have a low-k value and may include silicon nitride, undoped silicate glass (USG), silicon oxide, or the like.Dielectric layer 38A, if formed from a dielectric layer with a non-low k value, may directly overlie and contact an underlying dielectric layer 38 with a low k value. Top metal features 34A may also be formed from copper or a copper alloy, and may have a double damascene structure or a single damascene structure. Dielectric layer 38A is sometimes referred to as the topmost dielectric layer.

[0017] A passivation layer 40 is formed over the interconnect structure 32. The respective process is in the process flow 200, which is shown in Fig. 24, as process 202. According to some embodiments, the passivation layer 40 is formed from a non-low-k dielectric material having a dielectric constant equal to or greater than the dielectric constant of silicon oxide. The passivation layer 40 may be formed from an inorganic material, which may include, but is not limited to, a material selected from silicon nitride (SiN x ), silicon oxide (SiO2), silicon carbide (SiC), silicon oxynitride (SiON x ), silicon oxycarbide (SiOC x) or the like, combinations thereof, and / or multilayers thereof. The value "x" represents the relative atomic ratio. The formation process may include low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), plasma enhanced atomic layer deposition (PEALD), or the like. According to some embodiments, the upper surfaces of the upper dielectric layer 38A and the metal lines / pads 34A are coplanar. Accordingly, the passivation layer 40 may be a planar layer. According to alternative embodiments, the upper conductive features protrude above the upper surface of the upper dielectric layer 38A, and the passivation layer 40 is non-planar.

[0018] The passivation layer 40 is patterned in an etching process to form openings. The etching process may include a dry etching process, which includes forming a patterned etch mask (not shown), such as a patterned photoresist, and subsequently etching the passivation layer 40. The patterned etch mask is then removed. The metal lines and pads 34A are exposed through the openings.

[0019] A barrier layer 42 is formed, according to some embodiments, to extend into the passivation layer 40. The respective process is shown in process flow 200, which is shown in Fig. 24, as process 204. The barrier layer 42 may extend into the openings in the passivation layer 40 to contact the metal lines / pads 34A, such that the barrier layer 42 is electrically connected to the IC devices 26. The barrier layer 42 may be used to prevent charge accumulation in dielectric layers and IC devices 26. According to some embodiments, the barrier layer 42 includes a titanium layer and a copper layer over the titanium layer. The deposition process may be performed using PVD to deposit a titanium layer and a copper seed layer. Then, copper is deposited over the copper seed layer. The barrier layer 42 may be an unpatterned layer that is not patterned.Alternatively, the barrier layer 42 may be structured by an etching process to form a plurality of discrete sections, each of which connects to the respective underlying IC components 26 through a via in the passivation layer 40.

[0020] In a subsequent process, as in Fig. 2, a bonding layer 44 is deposited on the barrier layer 42. The respective process is shown in process flow 200, which is shown in Fig. 24, as process 206. According to some embodiments, the bonding layer 44 comprises or is formed from a silicon-containing material, which may include SiO2, SiN, SiC, SiON, SiOCN, or the like. The formation process may include LPCVD, PECVD, PVD, ALD, PEALD, or the like. After deposition, a planarization process, such as a chemical mechanical polishing (CMP) process or a mechanical grinding process, may be performed to make the top surface of the bonding layer 44 planar.

[0021] Further with reference to Fig. 2, a hard mask plate 46 is bonded to the bonding layer 44. The respective process is in process flow 200, which is shown in Fig. 24, as process 208. According to some embodiments, the hard mask plate 46 may include a silicon-containing material, such as silicon. The hard mask plate 46 may be, for example, a silicon substrate. According to alternative embodiments, the hard mask plate 46 is formed from a different material (e.g., silicon carbide) than the material of the bond layer 44. The hard mask plate 46 is thick enough to be used as a support during the subsequent thinning of the substrate 24. According to some embodiments, the thickness T1 of the hard mask plate 46 is in the range of about 500 μm to about 1,000 μm. Bonding the hard mask plate 46 to the bond layer 44 may be performed by fusion bonding, for example, with Si-O-Si bonds formed to connect the hard mask plate 46 to the bond layer 44.

[0022] The structure, as in Fig. 2, is then reversed as shown in Fig. 3. The semiconductor substrate 24 is then thinned. The respective process is shown in process flow 200, which is shown in Fig. 24, as process 210. The thickness T2 of the thinned semiconductor substrate 24 is related to the type of device to be formed. According to some embodiments, the thickness T2 of the thinned semiconductor substrate 24 is in the range of about 50 µm to about 100 µm.

[0023] With reference to Fig. 4, the carrier substrate 50 is bonded to the semiconductor substrate 24. The respective process is in the process flow 200, which is shown in Fig. 24, is illustrated as process 212. The carrier substrate 50 may be bonded to the semiconductor substrate by a bonding layer 48. According to some embodiments, the bonding layer 48 is deposited onto the semiconductor substrate 24, and the carrier substrate 50 is bonded to the bonding layer 48. According to alternative embodiments, the bonding layer 48 is pre-formed on the carrier substrate 50, for example, by thermal oxidation or deposition, and the structure comprising the bonding layer 48 and the carrier substrate 50 is bonded to the semiconductor substrate 24. The bonding layer 48 may be a silicon-containing dielectric layer comprising or formed from SiO2, SiN, SiC, SiON, or the like. The deposition process may include LPCVD, PECVD, PVD, ALD, PEALD, or the like. Bonding the bonding layer 48 to the carrier substrate 50 and the semiconductor substrate 24 may comprise melt bonding.According to some embodiments, the thickness T3 of the bonding layer 48 is in the range of about 1 µm to about 5 µm. The thickness T4 of the carrier substrate 50 may be in the range of about 500 µm to about 775 µm.

[0024] With reference to Fig. 5, the hard mask plate 46 is thinned, for example, by a CMP process or a mechanical grinding process. The respective process is shown in process flow 200, which is shown in Fig. 24, as process 214. The thickness T5 of the resulting hard mask plate 46 may range from about 30 µm to about 100 µm. According to alternative embodiments, thinning of the hard mask plate 46 may be skipped.

[0025] In a subsequent process, as also in Fig. 5, a carrier 52 is attached to the hard mask plate 46 by a release film 51. The carrier 52 may be formed from a light-transmitting material, which may be a glass carrier, a ceramic carrier, or the like. The respective process is shown in process flow 200, which is shown in Fig. 24, as process 216. The release film 51 may be formed from a light-to-heat conversion (LTHC) coating material applied by coating onto the carrier 52. According to some embodiments of the present disclosure, the LTHC coating material may decompose under the heat of light / radiation (e.g., a laser beam) and, as a result, separate the hard mask plate 46 from the carrier 52 in subsequent processes.

[0026] Fig. 6 to 12 illustrate the processes for the formation of an opening 60 ( Fig. 12) that penetrates the carrier substrate 50 and the bond layer 48 and extends into the semiconductor substrate 24. The etching processes may include reactive ion etching (RIE) processes in which plasma is generated and ions are produced from the etching gases. Fig. 6 to 10 illustrate the formation of the opening 60 in the carrier substrate 50 so that the bonding layer 48 is exposed. The respective process is shown in process flow 200, which is shown in Fig. 24, as process 218. With reference to Fig. 6, an etch mask 58 is formed. The etch mask 58 may comprise a hard mask formed from TiN, TaN, BN, SiN, SiON, SiCN, SiOCN, or the like. The formation process may include ALD, PECVD, or the like. The etch mask 58 may be patterned using a patterned photoresist, which is removed after patterning the etch mask 58. Next, the support substrate 50 is etched. According to some embodiments in which the support substrate 50 is a silicon substrate, the etching is performed using process gases selected from, but not limited to, SF6, CF4, C4F8, O2, Ar, and / or the like, and combinations thereof. The etch time may range from about 0.15 seconds to about 3 seconds. The etching of the carrier substrate 50 can be performed at a pressure in the range of approximately 15 mTorr to approximately 50 mTorr. Here and below, 1 Torr corresponds to approximately 133.322 Pascals.The flow rate of the process gases may range from about 150 sccm to about 500 sccm. An RF source power may be applied, and the RF source power may range from about 1,200 watts to about 5,000 watts. A bias power may also be applied in the range from about 50 watts to about 300 watts. The etching may be isotropic. Accordingly, the opening 60 is controlled to be shallow so that the opening 60 does not extend directly below the etch mask 58.

[0027] In subsequent processes, as shown in Figures 7 to 10, a plurality of etch cycles are performed to extend the opening 60 downward so that it penetrates the carrier substrate 50. The respective etch process is also referred to as a Bosch etch process, which is designed to form deep trenches with straight sidewalls. Fig. Figures 7 to 9 illustrate a deposition-etch cycle.

[0028] With reference to Fig. 7, a deposition process for depositing a polymer layer 62 is performed. The deposition is performed using process gases selected from, but not limited to, CF4, C4F8, and / or the like, and combinations thereof. The deposition time may range from about 0.15 seconds to about 2 seconds. The deposition of the polymer layer 50 may be performed at a pressure in the range of about 15 mTorr to about 50 mTorr. The flow rate of the process gases may range from about 150 sccm to about 500 sccm. An RF source power is applied, and the RF source power may range from about 1,200 watts to about 5,000 watts. No bias power may be applied, or a low bias power may be applied. The polymer layer 62 may comprise carbon, hydrogen, oxygen, and the like. Accordingly, the polymer layer 62 may be a conformal layer.

[0029] Fig. Figure 8 illustrates the self-aligned patterning of the polymer layer 62 achieved by an anisotropic etching process. According to some embodiments, the etching is performed using process gases selected from, but not limited to, SF6, CF4, C4F8, O2, Ar, and / or the like, and combinations thereof. The etching time may range from about 0.15 seconds to about 3 seconds. The etching process may be performed at a pressure in the range of about 15 mTorr to about 50 mTorr. The flow rate of the process gases may range from about 150 sccm to about 500 sccm. An RF source power is applied, and the RF source power may range from about 1,200 watts to about 5,000 watts. A bias power in the range of about 400 watts to about 700 watts may also be applied.

[0030] As a result of the self-aligned patterning process, the polymer layer 62 includes sidewall portions on the sidewalls of the carrier substrate 50 to protect the sidewalls so that the upper portions of the opening 60 are not laterally expanded when the opening 60 is downwardly expanded in a subsequent etching process.

[0031] With reference to Fig. 9, an etching process is performed to expand the opening 60 deeper into the support substrate 50. The etching may be performed using process gases selected from, but not limited to, SF6, CF4, C4F8, O2, Ar, and / or the like, and combinations thereof. The etching time may range from about 0.15 seconds to about 3 seconds. The etching process may be performed at a pressure in the range of about 15 mTorr to about 50 mTorr. The flow rate of the process gases may range from about 150 sccm to about 500 sccm. An RF source power is applied, and the RF source power may range from about 1,200 watts to about 5,000 watts. A bias power in the range of about 50 watts to about 300 watts may also be applied.Etching is stopped when opening 60 extends slightly downward, and is terminated before the trench extends directly below etch mask 58 so that opening 60 has straight edges. The bottom end of opening 60 is also planar. Because the bias power is low, there is essentially no shadow effect, as discussed in more detail in subsequent paragraphs.

[0032] According to some embodiments, etching the carrier substrate 50 comprises a plurality of deposition-etch cycles, each comprising a polymer deposition process (as in Fig. 7), a self-adjusting structuring process (as shown in Fig. 8) and an etching process for extending the opening 60 downwards (as shown in Fig. 9). The polymer layer 62 formed in the previous cycle may be removed or left for the next cycle. Figure 10 illustrates that an additional cycle or cycles may be performed to form the polymer layer 62 to extend further downward. Each of the deposition-etch cycles results in the opening 60 extending further downward until the carrier substrate 50 is etched through, and the opening 60 extends into the bond layer 48, which serves as an etch stop layer. After the last etch process, no more polymer layer is deposited, and as a result, Fig. 10 the lower ends of the polymer layer 62 higher than the lower end of the opening 60. The polymer layer 62 may be removed at this time or alternatively at a time after completion of the formation of the opening, as in Fig. 12 shown.

[0033] With reference to Fig. 11, the bond layer 48 is etched. The respective process is in process flow 200, which is shown in Fig. 24, as process 220. The etching may be anisotropic or isotropic, and it may be performed by a wet etching process or a dry etching process.

[0034] Next, as in Fig. 12, an etching process 63 is performed to etch the semiconductor substrate 24 so that the opening 24 extends further into the semiconductor substrate 24, wherein a lower part of the opening 60 is curved. The respective process is in the process flow 200, which is shown in Fig. 24, as process 222. According to some embodiments, the etching is performed by RIE. The etching may be performed using process gases selected from, but not limited to, SF6, CF4, C4F8, O2, Ar, and / or the like, and combinations thereof. The etching time may range from about 0.15 seconds to about 3 seconds. The etching process may be performed at a pressure in the range of about 15 mTorr to about 50 mTorr. The flow rate of the process gases may range from about 150 sccm to about 500 sccm. An RF source power is applied, and the RF source power may range from about 1,200 watts to about 5,000 watts.

[0035] In the etching process, a bias power may be used that is higher than the bias power used in etching the carrier substrate 50. For example, the bias power in the etching process 63 may be in the range of about 500 watts to about 1,200 watts. The etching may be anisotropic. The etching may be performed by a continuous etching process without interruption in between and without the formation of polymer and the Fig. 7 to 9 are performed. Because the opening 60 may be a high aspect ratio opening (although the figures are not drawn to scale) and anisotropic etching is applied, a loading effect and a shielding effect may occur. The regions within the opening 60 and closer to the sidewalls of the support substrate 50 and the semiconductor substrate 24 are shielded more than the regions closer to the center between opposing sidewalls of the support substrate 50 and the semiconductor substrate 24. Accordingly, the central regions are etched faster than the regions closer to the sidewalls. The central regions of the opening 60 therefore have greater depths than the respective side portions of the opening 60. The resulting opening is therefore trough-shaped, with the central regions being increasingly deeper than the respective side portions. The lower end of the opening 60 is also continuously curved.On the other hand, the sidewalls of the support substrate 50 facing the opening 60 are straight and may be inclined or vertical. In contrast, when etching the support substrate 50, since a Bosch (and isotropic) etching process is used, there is essentially no shielding effect, and as a result, the lower end of the corresponding opening 60 is planar, and the edges are straight.

[0036] In a subsequent process, the carrier 52 is separated from the overlying wafer 20. The respective process is in the process flow 200, which is shown in Fig. 24, as process 224. This separation process may include projecting a light beam, such as a laser beam, onto the separation film 51 so that the separation film 51 decomposes and separates the wafer 20 from the carrier 52. In a subsequent process, the hard mask plate 46, the bonding layer 44, and the barrier layer 42 may be removed, for example, by a grinding process or a laser lift-off process followed by an etching process.

[0037] Fig. 13 illustrates a process for forming a capacitor on wafer 20 according to some embodiments. The respective process is shown in process flow 200 shown in Fig. 24, as process 226. First, conductive pads 64A and 64B may be formed. According to some embodiments, conductive pads 64A and 64B are formed from aluminum, copper, copper, tungsten, or the like. The formation process may include PVD, plating, and / or the like. Conductive pads 64A and 64B may be electrically connected to IC devices 26. Metal pads 66A and 66B may be formed on conductive pads 64A and 64B, respectively, and may be formed from conductive materials such as copper, nickel, palladium, or the like. A backplate 70 is formed on or bonded to conductive pads 64B. According to some embodiments, backplate 70 is formed from a conductive material, which may be a metallic material or polysilicon.The backplate 70 is electrically separated from the conductive pad 64A by a dielectric layer 74, which may be formed of silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or the like. Vias 76 are formed in the backplate 70 and connected to an air gap 78 that separates the backplate 70 from the conductive pad 64A. Accordingly, a capacitor 80 is formed, comprising the conductive pad 64A and the backplate 70 as capacitor plates and the air gap 78 as a capacitor insulator. Forming the air gap 78 may include forming a sacrificial material onto which the backplate 70 is deposited. The backplate 79 is patterned to form openings 76, and the sacrificial material is removed through the vias 76 to form the air gap 78.Metal pads 66A and 66B can be used to connect to external components, for example, by solder bonding to an external component (not shown), with solder regions connecting metal pads 66A and 66B and the metal pads of the external component. Alternatively, wire bonds, which may include bond studs and bond wires, are connected to metal pads 66A and 66B.

[0038] According to some embodiments, the Fig. 13 is separated by scribe lines 82 to form a plurality of dies 84. The plurality of dies 84 may be identical, each including one or more capacitors 80. In the resulting capacitor 80, the portions of the substrate 24 and the overlying structures that are between the opening 60 and the air gap 78 form a membrane that can vibrate under mechanical force or the voltages applied to the metal pads 66A and 66B.

[0039] As in Fig. 13, the opening 60 has a portion in the semiconductor substrate 24, which portion is domed. The height HA1 of the dome, which height is equal to the difference between the edge thickness ET1 and the center thickness CT1 of the wafer 20, may range from about 15 µm to about 50 µm. The thickness ratio CT1 / ET1 may range from 0.7 to about 0.95. The total thickness H2 of the structure may range from about 720 µm to about 780 µm. The thickness H2 includes the center height CT1 of the membrane and the height of the opening 60. The width of the bottom end BW1 (which may be a diameter) of the opening 60 may range from about 17.8 mm to about 25 mm. The thickness T3 of the bonding layer 48 may range from about 1 µm to about 5 µm. The thickness of the lower end BW2 (which may be a diameter) of the curved portion of the opening 60 in the semiconductor substrate 24 may range from about 15 mm to about 25 mm. The ratio HA1 / BW2 may range from about 0.0001 to about 0.003. The opening 60 may have the shape of a circle, a rectangle, a hexagon, or the like when viewed from above or below.

[0040] According to some embodiments, by forming the domed opening 60, the edge portions of the membrane become increasingly thicker, and as a result, the membrane is stronger and does not suffer from collapse problems. Furthermore, the overall deformation of the die 84 and the wafer as a whole is reduced because thicker edge portions of the membrane provide a better ability to withstand die deformation and stress.

[0041] Fig. Figures 14 to 23 illustrate cross-sectional views of intermediate stages in the formation of a device according to alternative embodiments of the present disclosure. Unless otherwise indicated, the materials and formation processes of the components in these embodiments are substantially the same as the same components used in the preceding embodiments described in Fig. 1 to 13 are designated by the same reference numerals. The details regarding the formation process and materials of the Fig. The components illustrated in Figures 14 to 23 can therefore be found in the discussion of the preceding embodiments.

[0042] With reference to Fig. 14, a wafer 20 is formed. The initial structure and formation processes of the wafer 20 according to these embodiments are similar to the embodiments shown in Fig. 1, except that a plurality of openings 86 are formed penetrating the dielectric layers above the semiconductor substrate 24. The openings 86 also extend into the semiconductor substrate 24. According to some embodiments, a barrier layer is formed after the formation of the openings 86, and the barrier layer 42 extends into the openings 86. A dielectric layer (not shown) may be formed prior to the formation of the barrier layer 42 and extends into the openings 86 to electrically isolate the barrier layer 42 from the substrate 24. When viewed from above the wafer 20 and the device dies 22, the openings 86 may have a repeated structure, such as a row, a beehive (hexagonal) structure, or the like. IC devices 26 may be formed in the spaces between the openings 86 and in the regions surrounding the openings 86.

[0043] With reference to Fig. 15, a bonding layer 44 is deposited, which may comprise a silicon-containing material (which may be a dielectric material), such as SiO2, SiN, SiC, SiON, SiOCN, or the like. A planarization process is then performed to level the top surface of the bonding layer 44. A hard mask plate 46, which may comprise or be formed from a silicon substrate, is fusion bonded to the bonding layer 44.

[0044] Fig. 16 illustrates the reversal of the Fig. 15, followed by thinning the semiconductor substrate 24 to a desired thickness suitable for forming a dome having a desired height.

[0045] As in Fig. 17, a carrier substrate 50 is next bonded to the semiconductor substrate 24 through the bonding layer 48, which also serves as an etch stop layer in subsequent etching processes. The carrier substrate 50 is then etched to form an opening 60, as shown in Fig. 18. The etching process may include a Bosch etching process, which includes a plurality of etching processes, as discussed in previous embodiments. A polymer layer 62 is formed to assist the etching and help form vertical sidewalls for the opening 60. The details of the processes are substantially the same as those discussed with reference to Fig. 7 to 10 and are not repeated here. Bond layer 48, which is an etch stop layer for stopping the etching of the carrier substrate 50, is exposed.

[0046] With reference to Fig. 19, the bonding layer 48 is etched through either by a dry etching process or a wet etching process. Next, a continuous etching process is performed to etch the semiconductor substrate, during which a load effect and a shadow effect occur, so that the lower end of the opening 60 is curved (bulged when viewed upside down). The etching process may be similar to that described with reference to Fig. 12, so the details of the etching process will not be repeated. According to some embodiments, in addition to the etching gas for etching the semiconductor substrate 24, the etching gas may include an etching gas configured to etch the barrier layer 42 so that, as the etching of the semiconductor substrate progresses, the exposed portions of the barrier layer 42 are also etched. For example, a small amount of chlorine-containing gas, such as TiClx, TaClx, WClx, or the like, may be added to the etching gas for etching the barrier layer 42. According to alternative embodiments, the argon in the etching gas may remove the exposed barrier layer 42 by sputtering, since the barrier layer 42 is thin. After the etching process, the polymer layer 62, if present, is removed. Due to the curved shape of the opening 60, the membrane, which is the part of the substrate directly below the opening 60, is stronger and can withstand high stress without collapsing.In addition, the resulting component 94 (. Fig. 23) shows less deformation.

[0047] Fig. 21 illustrates the formation of a patterned conductive layer 88, which may cover a portion of the exposed surfaces of the support substrate 50, the bond layer 48, and the semiconductor substrate 24. The conductive layer 88 may be formed, for example, from tungsten, aluminum, aluminum-copper, or the like, and may be formed, for example, by PVD. A dielectric layer (not shown) may be formed prior to the formation of the conductive layer 88 to electrically separate the conductive layer 88 from the substrate 24. After deposition, the conductive layer 88 is patterned. The remaining portions of the conductive layer 88 may comprise a plurality of separate portions, each adjoining or connected to the portion of the barrier layer 42 in an opening 86.Throughout this description, the portions of barrier layer 42 and their connecting portions to conductive layer 88 are collectively referred to as conductive tubes 90. The portions of conductive layer 88 in different conductive tubes 90 are physically and electrically separated from each other so that a voltage can be applied to each conductive tube 90 individually.

[0048] The Fig. The structure shown in Figure 21 is turned over, and the support 52 is separated from its overlying structure. The resulting structure is shown in Fig. 22. Then, the hard mask plate 46 and the bonding layer 44 are removed. The resulting structure is shown in Fig. 22. Next, the structure is placed over a saw band 92, which is fixed to a frame 93. Bond pads 66 can be formed to electrically connect the IC components 26. Next, a dicing process can be used to saw the Fig. 22. In this way, component(s) 94 are formed. According to alternative embodiments, no singulation of the structure is performed. According to further alternative embodiments, the structure is trimmed to remove edge portions that have neither IC components 26 nor an opening 86, while leaving the portion with IC components 26 and opening 86.

[0049] Fig.23 illustrates a resulting device 94. Solder bonding or wire bonding may be performed to electrically connect an external device to the device 94, where the external device may include, for example, a voltage regulator. According to some embodiments, the electrical tubes 90 are electrically connected to the IC devices 26 and configured to apply desired voltages. Accordingly, a voltage may be individually applied (through the voltage regulator) to each of the conductive tubes 90. The device 94 may be used to form lithography masks. For example, an unpatterned lithography mask (not shown) may be disposed beneath the device 94. An eBeam source may be disposed above the device 94 and projects an eBeam. Voltages may be applied to the IC devices 26 through the bond pads 66.The voltages are applied to the conductive tubes 90 so that a voltage can be applied to each of the conductive tubes 90. By controlling the voltages applied to the conductive tubes 90, each of the conductive tubes (90) can be used as a switch that allows the eBeam to pass through or prevents the eBeam from passing through. The underlying unpatterned lithography mask is thus patterned by the eBeam to have a desired pattern. In this way, a patterned lithography mask is formed.

[0050] Embodiments of the present disclosure have several advantageous features. By adapting etching processes during the formation of an opening in device 94, the opening is curved under the formed membrane. The membrane thus has a thinner, sensitive central portion and thicker edge portions. The mechanical strength of the membrane is improved, and the corresponding membrane is more resistant to the collapse problem. According to some embodiments, the deformation of the corresponding device is also reduced.

Claims

[1] Method (200) comprising: Bonding (212) a carrier substrate (50) to a semiconductor substrate (24) of a wafer (20), wherein a bonding layer (44, 48) is located between the carrier substrate (50) and the semiconductor substrate (24) and is bonded to both of them; Performing (218) a first etching process for etching the carrier substrate (50) and for forming an opening (60), wherein the opening (60) penetrates the carrier substrate (50) and ends at the bonding layer (44, 48), and wherein the opening (60) has substantially straight edges; etching (220) through the bonding layer (44, 48); and Performing (222) a second etching process to widen the opening (60) downward into the semiconductor substrate (24), wherein a lower portion of the opening is curved, further comprising: Etching the wafer (20) to form a plurality of openings (86) prior to bonding the carrier substrate (50) to the semiconductor substrate (24), wherein the plurality of openings (86) penetrate a plurality of dielectric layers (38) and extend into the semiconductor substrate (24), and wherein the plurality of openings (86) are connected to the opening (60) after expanding the opening (60) into the semiconductor substrate (24), wherein the bonding of the carrier substrate (50) to the semiconductor substrate (24) occurs on the side of the semiconductor substrate (24) that does not have the dielectric layers (38). [2] The method (200) of claim 1, further comprising: Forming a conductive layer (64A) overlapping the opening (60), wherein a portion of the semiconductor substrate (24) is between the opening (60) and the conductive layer (64A); and Forming a conductive backplate (70) overlapping the conductive layer (64A) and the opening (60), wherein the conductive backplate (70) and the conductive layer (64A) are separated from each other by an air gap (78), and the conductive layer (64A), the air gap (78), and the conductive backplate (70) together form a capacitor (80). [3] The method (200) of claim 1 or 2, wherein the first etching process comprises a first plurality of etching cycles, and each of the plurality of etching cycles comprises: Forming a polymer layer (62) extending into the opening (60); Removing horizontal sections of the polymer layer (62), wherein vertical sections of the polymer layer (62) are in the opening (60) and cover side walls of the carrier substrate (50); and Etching the carrier substrate (50) using the vertical sections of the polymer layer (62) as an etching mask. [4] The method (200) of claim 3, wherein the etching of the carrier substrate (50) is isotropic. [5] The method (200) of claim 3 or 4, wherein the opening (60) has a planar bottom end surface after each of the plurality of etch cycles. [6] The method (200) of any preceding claim, wherein the first etching process comprises isotropic etching processes. [7] The method (200) of any preceding claim, wherein the first etching process is performed using a first bias power in the range of about 50 watts to about 300 watts, and the second etching process is performed using a second bias power greater than the first bias power. [8] The method (200) of any one of claims 1 to 7, further comprising forming a plurality of conductive tubes (90) each extending into each of the plurality of openings (86) after connecting the plurality of openings (86) to the opening (60). [9] The method (200) of any preceding claim, further comprising thinning the semiconductor substrate (24) from the backside, wherein the bonding layer (44, 48) contacts a backside of the thinned semiconductor substrate (24). [10] The method (200) according to any one of the preceding claims, wherein the second etching process is a continuous etching process without interruption. [11] Device comprising: a semiconductor substrate (24); a bonding layer (44, 48) underlying and contacting the semiconductor substrate (24); a carrier substrate (50) underlying and contacting the bonding layer (44, 48); an opening (60) extending upwardly from a lower surface of the carrier substrate (50) to penetrate the bonding layer (44, 48), the opening (60) further extending into the semiconductor substrate (24), the opening (60) being domed, and the upper end of the opening (60) being continuously curved; a plurality of dielectric layers (38) over the semiconductor substrate (24); and IC components (26) on a surface of the semiconductor substrate (24). [12] The apparatus of claim 11, further comprising: a conductive layer (64A) overlapping the opening (60), wherein a portion of the semiconductor substrate (24) is located between the opening (60) and the conductive layer (64A); and a conductive backplate (70) overlapping the conductive layer (64A) and the opening (60), the conductive backplate (70) and the conductive layer (64A) being separated from each other by an air gap (78), and the conductive layer (64A), the air gap (78) and the conductive backplate (70) together forming a capacitor (80). [13] Apparatus according to claim 11 or 12, further comprising: a plurality of openings (86) penetrating the semiconductor substrate (24), the plurality of openings (86) being connected to the opening (60). [14] A device according to any one of claims 11 to 13, wherein central portions of the lower surface are progressively higher than edge portions of the lower surface. [15] The device of any one of claims 11 to 14, wherein edges of a portion of the opening (60) in the carrier substrate (50) are substantially straight. [16] Device according to one of claims 11 to 15, wherein the carrier substrate (50) comprises a silicon substrate. [17] Device comprising: a device die comprising: a semiconductor substrate (24); and a plurality of dielectric layers (38) over the semiconductor substrate (24), wherein portions of the semiconductor substrate (24) and the plurality of dielectric layers (38) form a diaphragm configured to vibrate, and wherein edge portions of the diaphragm are progressively thicker than central portions of the diaphragm; a bonding layer (44, 48) underlying and contacting the semiconductor substrate (24); and a carrier substrate (50) lying beneath the bonding layer (44, 48) and connected to the bonding layer (44, 48), wherein an opening (60) lies directly beneath the membrane and extends into the semiconductor substrate (24) and penetrates the bonding layer (44, 48) and the carrier substrate (50), and wherein the opening (60) is domed and wherein the upper end of the opening (60) is continuously curved. [18] The device of claim 17, further comprising a plurality of openings (86) penetrating the semiconductor substrate (24) and the plurality of dielectric layers (38), the plurality of openings (86) being connected to the opening (60).

Images