Traveling wave oscillator systems and methods for traveling wave oscillation

Abstract

Traveling wave oscillator system (RTWO system) which features the following: a first RTWO ring designed to guide a traveling wave; several selectable capacitors distributed around the first RTWO ring, each of the several selectable capacitors being operable in a selected state and a non-selected state; and a decoder system configured to control the selection of several selectable capacitors based on a frequency tuning code having a fine tuning code and a coarse tuning code, wherein the decoder system is configured to operate a constant number of capacitors that switch the state for each value of the fine tuning code.

Description

Territory of Revelation

[0001] Embodiments of the invention relate to electronic systems and in particular to rotary traveling wave oscillators (RTWO). BACKGROUND

[0002] Traveling wave oscillators (RTWOs) can be used in many different applications, including telecommunications systems, optical networks, and / or chip-to-chip communication. For example, an RTWO can be included in a frequency synthesizer to generate an output clock signal that has a controlled phase and frequency relationship to a reference clock signal.

[0003] DE 11 2017 005 105 T5 discloses devices and methods for frequency tuning of rotating-wave oscillators (RTWOs). In certain configurations, distributed quantized tuning is used to tune the frequency of the RTWO. The RTWO has several segments distributed around the RTWO ring, and the segments contain tuning capacitors and other circuitry. The distributed quantized frequency tuning is used to control the tuning capacitors in the RTWO segments using separately controllable code values, thereby improving the step size or resolution of the RTWO frequency. Furthermore, in configurations with multiple RTWO rings coupled together to reduce phase noise, the distributed quantized frequency tuning can be used to adjust the tuning capacitors separately across multiple coupled RTWO rings. SUMMARY OF THE REVELATION

[0004] Traveling wave oscillator (RTWO) systems are disclosed herein. In particular embodiments, an RTWO system comprises an RTWO ring guiding a traveling wave, several selectable capacitors distributed around the RTWO ring, each of which can be operated in a selected state and an unselected state, and a decoder system that controls the selection of the several selectable capacitors based on a frequency tuning code. The frequency tuning code includes a fine-tuning code and a coarse-tuning code, and the decoder system is operable to operate a constant number of capacitors that switch their state for each value of the fine-tuning code. Implementing the RTWO system in this manner reduces or eliminates code-dependent frequency error.

[0005] In one aspect, an RTWO system comprises a first RTWO ring configured to guide a traveling wave, several selectable capacitors distributed around the first RTWO ring, each of which can be operated in a selected state and an unselected state, and a decoder system configured to control the selection of the several selectable capacitors based on a frequency tuning code that includes a fine-tuning code and a coarse-tuning code. The decoder system is configured to operate a constant number of capacitors that toggle their state for each value of the fine-tuning code.

[0006] In another aspect, a method for traveling-wave recirculation oscillation (RTWO) is provided. The method involves propagating a traveling wave around an RTWO ring, controlling a delay of the traveling wave around the RTWO ring using several selectable capacitors distributed around the first RTWO ring, each of which can be operated in a selected and an unselected state, controlling the selection of the several selectable capacitors based on a frequency tuning code that includes a fine-tuning code and a coarse-tuning code, using a decoder system, and operating a constant number of capacitors from the several selectable capacitors, which switch their state for each value of the fine-tuning code, using the decoder system.

[0007] In another aspect, an RTWO system comprises an RTWO ring configured to guide a traveling wave, several selectable capacitors distributed around the RTWO ring, each operable in a selected and an unselected state, and a decoder system configured to control the selection of the several selectable capacitors based on a frequency tuning code that includes a fine-tuning code and a coarse-tuning code. The decoder system includes means for operating a constant number of capacitors that toggle their state for each value of the fine-tuning code. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 is a schematic representation of an implementation of a fully digital phase-locked loop (ADPLL). Fig. Figure 2 is a schematic representation of an implementation of a traveling wave oscillator (RTWO). Fig. 3A is a schematic representation of another implementation of an RTWO. Fig. Figure 3B is a schematic representation of an implementation of an RTWO segment. Fig. Figure 4 represents an implementation of RTWO with segmented decoding. Fig. 5 represents an implementation of voting decoders for a multi-ring RTWO. The Fig. 6A and Fig. 6B represents an implementation of dynamic element matching for the segment selection of an RTWO. The Fig. 7A and Fig. 7B represents another implementation of dynamic element matching for segment selection of an RTWO. Fig. Figure 8A is a schematic representation of an embodiment of an RTWO system comprising four coupled RTWO rings. Fig. 8B is an example of a graph of transitions versus fine-tuning code for the RTWO system by Fig. 8A. Fig. Figure 8C is a graphic of an example of switching time mismatch for the RTWO system of Fig. 8A. Fig. 8D is a graphic of an example of gain error for the RTWO system of Fig. 8A. Fig. Figure 8E is a schematic representation of a varactor circuit arrangement for an RTWO segment according to one embodiment. Fig. Figure 9 is a graphic of an example of the transition for transition-controlled dynamic element matching (DEM). Fig. Figure 10 is an example of an operating diagram for spare banks for transition-controlled DEM. Fig. 11 is an example of the operation of a transition control bank. Fig. Figure 12A is a graphic of an example of switching time mismatch for an RTWO system with transition control. Fig. Figure 12B is a graph of an example of gain error for an RTWO system with transition control. Fig. Figure 13A is a graphic of another example of gain error for an RTWO system with transition control, which also models varactor gain mismatch. Fig. Figure 13B is a graphic of another example of gain mismatch with transition control. Fig. 14A is another example of an operating diagram for spare banks for transition-controlled DEM. Fig. Figure 14B is a graphic of an example of an open-loop amplification circuit with modeled switching time and gain mismatch. Fig. Figure 15A is a graphic of an example of simulated baseband diagrams. Fig. Figure 15B is a graphic of another example of simulated baseband diagrams. Fig. Figure 16 is a graph of measured baseband diagrams with and without transition control. DETAILED DESCRIPTION OF EXECUTION FORMS

[0008] The following detailed description of specific embodiments presents various descriptions of specific embodiments of the invention. However, the invention can be implemented in a multitude of different ways, as defined and covered by the claims. Reference is made in this description to the drawings, where the same reference numerals may denote identical or functionally similar elements. It should be understood that elements shown in the figures are not necessarily drawn to scale. Furthermore, it should be understood that specific embodiments may have more elements than shown in a drawing and / or may include a subset of the elements shown in a drawing. Finally, some embodiments may incorporate any suitable combination of features from two or more drawings.

[0009] As those familiar with the subject matter will recognize, a traveling wave oscillator (RTWO) may include a differential transmission line connected in a ring with an odd number of one or more crossings, and several regeneration circuits electrically connected along a path of the differential transmission line. Additionally, each of the crossings may reverse the polarity of a wave propagating along the differential transmission line, and the regeneration circuits may provide energy to the wave to compensate for losses in the differential transmission line. Further details for RTWO may be as described in U.S. Patent No. 6,556,089, issued on April 29, 2003, entitled "ELECTRONIC CIRCUITRY," which is hereby incorporated in its entirety by reference. Example of a fully digital phase-locked loop with a traveling-wave oscillator

[0010] In specific configurations, a fully digital phase-locked loop (ADPLL) incorporating a traveling-wave oscillator (RTWO) is provided. The ADPLL can be used in a wide variety of applications, including but not limited to radar (e.g., vehicle radar), telecommunications, chip-to-chip communication, and / or automated test systems. In one example, the ADPLL generates an output clock signal exhibiting a wide variety of frequency ramp profiles and / or rates.

[0011] In contrast, an analog PLL with charge pumps can suffer from supply voltage variation, a narrow tuning voltage range, and / or variation in loop dynamics. These disadvantages can be exacerbated in implementations using processes with relatively small geometries, such as fine-line CMOS processes. While an ADPLL architecture can provide a number of advantages, the lessons learned here are also applicable to RTWO used in other electronic systems, such as analog PLLs that employ RTWO.

[0012] In specific implementations, an ADPLL incorporates a RTWO that functions as both a digitally controlled oscillator (DCO) and a time-to-digital converter (TDC). Implementing the RTWO to provide a variety of functions improves the compactness of a design by utilizing the RTWO for multiple purposes.

[0013] Using a RTWO in the ADPLL allows for a low factor of merit (FOM). The superior FOM is partly achieved through the fine resolution of the RTWO's TDC.

[0014] Although the RTWOs described here can be used in ADPLLs, an RTWO implemented in accordance with the teachings presented here can be used in a wide range of electronic systems and applications.

[0015] Fig. Figure 1 is a schematic representation of an implementation of a fully digital phase-locked loop (ADPLL) 10. The ADPLL 10 comprises a fractional accumulator 1, a digital filter 2, a combined digital control oscillator (DCO) and time-to-digital converter (TDC) 4, a counter 5, counter latches 6, a multiplier 7, a subtraction block 11, and an addition block 12. The combined DCO and TDC 4 includes a real-time clock (RTWO) 15 and TDC latches 16.

[0016] As in Fig. As shown in Figure 1, ADPLL 10 has the fractional accumulator 1, which is a digital voting word or code N. freq with the rate of a reference clock signal CLK REF accumulated. The digital voting code N freq can be used to control an output frequency of the ADPLL 10. In the illustrated embodiment, the subtraction block 11 generates CLK for each cycle of the reference clock signal. REF A difference signal based on the difference between an output of fractional accumulator 1 and a number of DCO clock cycles NUM_DCO, partially generated by the RTWO 15. The number of DCO clock cycles NUM_DCO corresponds to a digital code represented in integer and fractional form.

[0017] As in Fig. As shown in Figure 1, the RTWO 15 and the TDC latches 16 work together to generate a fractional number of DCO clock cycles, FRAC_DCO, which the addition block 12 combines with an integer number of DCO clock cycles, INT_DCO, to generate the number of DCO clock cycles, NUM_DCO. Specifically, the RTWO 15 generates K clock phases, which are provided to the TDC latches 16. The TDC latches 16 process the K clock phases from the RTWO 15 based on the time of the reference clock signal, CLK. REF To determine the fractional number of DCO clock cycles, FRAC_DCO, the K clock phases all have the same oscillation frequency but different phases. In one embodiment, the RTWO outputs 64 or more phases to the TDC latches 16. However, other implementations are possible.

[0018] Although the TDC-Latches 16 are represented as a separate block from the RTWO 15, in special implementations the TDC-Latches 16 are integrated into a layout of the RTWO 15, such as the layout of the segments of the RTWO.

[0019] Furthermore with reference to Fig. 1 gives the RTWO 15 a DCO clock signal CLK DCO from which one of the K clock phases can correspond in specific implementations. In the illustrated embodiment, the DCO clock signal CLK serves this purpose. DCO as an input into the multiplier 7, which is the DCO clock signal CLK DCO multiplied by a multiplication factor M to obtain an output clock signal CLK OUT to generate. Including the multiplier 7 improves the flexibility of the ADPLL 10 by extending a range of frequencies for which the clock signal CLK is available. OUT can be controlled. For example, the multiplier 7 can be used to control the output clock signal CLK. OUTto control frequencies that are higher than a maximum oscillation frequency of the RTWO 15, and can therefore serve as a frequency multiplier.

[0020] In one example, an RTWO is multiplied by a multiplication factor M. In another example, the multiplier is omitted.

[0021] As in Fig. As shown in 1, the DCO clock signal CLK is DCO The integer counter 5 is provided, which works in combination with the counter latches 6 to generate the integer number of DCO cycles INT_DCO. In the illustrated embodiment, the integer counter 5 counts a number of cycles of the DCO clock signal CLK. DCO For example, the integer counter 5 can be loaded with an initial value of 1 and then for each cycle of the DCO clock signal CLK DCO increment by 1.

[0022] The difference signal generated by the subtraction block 11 is filtered by the digital filter 2. Additionally, the filtered difference signal is used to tune the RTWO 15 with both a digital integer tuning code INT and a digital fractional tuning code F in this embodiment.

[0023] The RTWO 15 from Fig. 1 is tuned using the digital integer tuning code INT and the digital fractional tuning code F to change the RTWO's fundamental oscillation frequency. In special implementations, the RTWO 15 can employ additional tuning, which includes, for example, coarse tuning and / or process, voltage, and temperature (PVT) tuning.

[0024] Accordingly, in specific implementations, the digital fraction reconciliation code F provides fractional fine reconciliation of RTWO 15, and the digital integer reconciliation code INT provides integer fine reconciliation.

[0025] The RTWO 15 can be implemented in such a way that it has one or more of the features disclosed here.

[0026] The ADPLL 10 represents an example of an electronic system that can incorporate an RTWO implemented in accordance with the teachings presented here. However, the RTWOs described here can be used in a wide variety of electronic systems, which, but are not limited to, include a wide variety of data converters and / or frequency synthesizers. Examples of traveling wave oscillators

[0027] Fig. Figure 2 is a schematic representation of an implementation of an RTWO 30. The RTWO 30 has a differential transmission line comprising a first conductor 31 and a second conductor 32. As shown in Fig. As shown in Figure 2, the differential transmission line 31, 32 is connected to a closed loop or ring, and the differential transmission line has a crossing 33 to provide an inversion for the traveling wave propagating around the ring. The RTWO 30 of Fig. 3 further has several segments 35, each of which has a regeneration circuit.

[0028] The RTWO 30 shown in this example has one crossover and thirty-two regeneration circuits, each implemented using back-to-back inverters. However, other configurations are possible, including configurations with a different number of crossovers, more or fewer segments, more or fewer regeneration circuits, and / or regeneration circuits implemented in other ways. Furthermore, the RTWO 30 may have a different circuit layout, which, but is not limited to, includes tuning capacitors, latches, buffers, and / or other circuitry in the segments.

[0029] As in Fig. As shown in Figure 2, the differential transmission line of the RTWO is connected in a closed loop and is folded at each of its four corners. However, the differential transmission line of the RTWO can be implemented in other ways, for example, with different implementations of folding and / or routing the conductors 31, 32. For instance, the gauges shown here are not only applicable to RTWOs implemented using rectangular or square rings, but also to RTWOs with transmission lines of other shapes. Thus, although the RTWO shown has four sides, the gauges shown here are applicable to RTWOs with more or fewer sides as well as to RTWOs with curved rings.

[0030] In the illustrated embodiment, the RTWO 30 comprises segments 35, each having a regeneration circuit distributed at substantially uniform intervals around the differential transmission line. The uniform distribution of the regeneration circuits contributes to maintaining a uniform characteristic impedance of the differential transmission line and a substantially constant wave velocity. Although each segment 35 has a pair of back-to-back inverters, the teachings presented here are applicable to segments having a different number of regeneration circuits and / or different implementations of regeneration circuits.

[0031] In the illustrated embodiment, the RTWO 30 is segmented into 8 segments per side. Since each of the conductors 31, 32 provides a clock signal phase, the 32 illustrated segments 35 operate with a total of 64 clock signal phases. However, other implementations are possible.

[0032] The oscillation frequency f OSC The RTWO 30 is based on the speed of a traveling wave propagating along the transmission line, divided by the total length or distance the wave travels in one cycle. In specific implementations, the oscillation frequency f OSC of RTWO 30 given by the following equation 1, where v p the wave phase velocity, I the length of the transmission line loop or ring, L TL the inductance of the transmission line is and C TL the capacity of the transmission line. fOSC=νp2l=12LTLCTL

[0033] In special configurations, the segments of an RTWO (for example, segments 35 of the RTWO 30) have one or more tuning capacitors that have a capacitance that is digitally controllable to set an oscillation frequency of the RTWO.

[0034] Meeting the RTWO specification regarding tuning range and frequency tuning step size can be challenging. Such problems can be exacerbated in configurations where the RTWO is required to operate at a relatively high oscillation frequency. For example, an RTWO with a relatively high oscillation frequency may have a relatively short transmission line loop and may therefore be limited by available layout resources such as available active transistor area and / or metal routing channels.

[0035] For example, the RTWO 30 can be found in the ADPLL 10 of Fig. 1. However, in specific applications it may be desirable for the ADPLL 10 to have a relatively high oscillation frequency f. OSC (for example, 10 GHz or more), with a relatively wide tuning range (for example, 625 MHz or more) and with a relatively fine tuning resolution (for example, 200 kHz or less).

[0036] The segments of an RTWO can incorporate a wide variety of circuit arrangements, including regeneration circuitry (such as assisting amplifiers), tuning capacitors, latches, buffers, and / or other circuitry. In one example, to achieve a sufficient tuning range, each RTWO segment might have multiple tuning capacitor banks, for example, three or more. In another example, the segments of an RTWO might have TDC latches to provide time-to-digital conversion. In a third example, each RTWO segment might have a tap buffer (such as a non-inverting or inverting buffer) used to obtain or extract a clock signal of a specific phase from the RTWO ring.

[0037] Although it is desirable for the segments of an RTWO to contain a large number of circuits and / or circuits of a relatively large size, the RTWO can be limited by the available layout resources, such as the available active area and / or routing traces. Furthermore, providing additional layout resources by increasing the length of the RTWO segments can undesirably increase the length of the RTWO ring, which in turn reduces the oscillation frequency of the RTWO.

[0038] In specific configurations, an RTWO features segments with metal spurs extending from the RTWO's differential transmission line. These metal spurs provide connectivity to additional layout equipment. For example, the segment layouts may be relatively wide (e.g., essentially perpendicular in a first dimension to a local portion or section of the RTWO's transmission line) and may include tuning capacitors and other circuitry connected to the metal spurs. However, the segment layouts are relatively short (e.g., essentially parallel in a second dimension to a local portion or section of the RTWO's transmission line), allowing the RTWO's transmission line loop to be relatively short in order to provide a high oscillation frequency, such as 10 GHz or higher.

[0039] Accordingly, the metal spur lines extend from the differential transmission line of the RTWO to provide a connection to tuning capacitors and / or other circuit arrangements that support the implementation of a wide tuning range, a fine frequency step size, a high oscillation frequency, and / or equip the RTWO with additional functionality such as time / digital conversion functionality and / or segment programmability.

[0040] Fig. Figure 3A is a schematic representation of another implementation of an RTWO 70. The RTWO 70 has a differential transmission line comprising a first conductor 31, a second conductor 32, and a crossing. The RTWO 70 also has several segments 75.

[0041] In the illustrated embodiment, the RTWO 70 has one crossing and thirty-two segments. However, other configurations are possible, including configurations that use a different number of crossings and / or more or fewer segments. Additionally, in the illustrated embodiment, the differential transmission line of the RTWO is connected in a closed loop and folded at each of its four corners. However, the differential transmission line of the RTWO can be implemented in other ways, including, for example, different implementations of the folding and / or routing of conductors 31 and 32. For instance, the teachings presented here are applicable not only to RTWOs implemented using rectangular or square loops, but also to RTWOs with transmission lines of other shapes.Thus, although the RTWO 70 shown has four pages, the lessons taught here are applicable to RTWOs that have more or fewer pages.

[0042] In the illustrated embodiment, the RTWO 70 has segments 75, each of which has a first metal spur 81 and a second metal spur 82 extending from the first conductor 31 and the second conductor 32, respectively. The first and second metal spurs 81 and 82 are used to provide local clock phase signals from the differential transmission line of the RTWO for the circuit arrangement of segments 75.

[0043] In the illustrated embodiment, each segment 75 has a TDC latch 91, tuning capacitors 92, and a regeneration circuit 93 that operates using both a clock signal phase from the first conductor 31 and a clock signal phase from the second conductor 32. However, other implementations are possible. Although shown connected between the first and second conductors 31, 32 of the RTWO ring, in another example the regeneration circuit 93 is connected between the first and second metal spur lines 81, 82. In the illustrated embodiment, each segment 75 has a first tap buffer 94 that taps the first conductor 31 to obtain a first clock signal phase and a second tap buffer 95 that taps the second conductor 32 to obtain a second clock signal phase.

[0044] Although a specific implementation of the segment circuit arrangement in Fig. As shown in Figure 3A, other implementations of the segment circuit arrangement are possible, featuring configurations with more or fewer circuits and / or different circuits. For example, in another embodiment, a first group and a second group of tuning capacitors are connected to the first and second conductors 31 and 32, respectively. In yet another embodiment, the segments feature a circuit arrangement that provides segment programmability.

[0045] By incorporating the first and second metal spur lines 81, 82, which extend from the differential transmission line 31, 32 of the RTWO, the segments 75 of the RTWO can be implemented with a wide layout, providing an active area and routing resources suitable for segment circuit arrangement. Additionally, the RTWO has a differential transmission line 31, 32 in a relatively short loop, and thus the RTWO 70 has a relatively high oscillation frequency.

[0046] In one embodiment, the RTWO has a total loop length of less than 7,500 µm, and the spur length of each of the first and second metal spurs 81, 82 is at least 25 µm. For example, with reference to the Fig. 3A rectangular loop shown in an embodiment of the RTWO of Fig. 3A a first length L RING-X smaller than approximately 1,875 µm and a second length L RING-Ysmaller than approximately 1,875 µm.

[0047] The stub line length can be expressed as a fraction of a wavelength of the traveling wave of the RTWO. In one embodiment, the first and second metal stub lines 81, 82 are each at least 0.05 λ long, where λ is the wavelength of the RTWO. As those skilled in the art will recognize, the wavelength of an RTWO can be expressed as a ratio of the wave phase velocity of the RTWO to the oscillation frequency of the RTWO, or v p / f osc , can be expressed.

[0048] In one embodiment, the segments 75 have a length of less than about 25 µm and a width of at least about 25 µm.

[0049] In one embodiment, an RTWO has at least 1 segment per 25 µm of the loop.

[0050] Fig. Figure 3B is a schematic representation of an implementation of an RTWO segment 100. The RTWO segment 100 is connected to a first transmission line conductor 101 and a second transmission line conductor 102 of a ring of an RTWO.

[0051] For the sake of clarity, only a section of the first transmission line conductor 101 and the second transmission line conductor 102 are shown in the figures. Fig. 3B shown. However, the first transmission line conductor 101 and the second transmission line conductor 102 operate as a section of the differential transmission line of an RTWO, which is connected in a ring.

[0052] The RTWO segment 100 of Fig. 3B features a PVT tuning capacitor bank 111, a coarse tuning capacitor bank 112, a fine tuning capacitor bank 113, a regeneration circuit 115, a TDC latch 117, a first tap buffer 118a, a second tap buffer 118b, a first metal spur 131 and a second metal spur 132.

[0053] The PVT tuning capacitor bank 111 features selectable capacitors used to compensate for process, temperature, and / or voltage variations. Additionally, the coarse tuning capacitor bank 112 features selectable capacitors used to provide coarse tuning of the RTWO's oscillation frequency. Furthermore, the fine tuning capacitor bank 113 features selectable capacitors used to provide fine tuning of the RTWO's oscillation frequency. The tuning capacitor banks can be implemented using any suitable tunable capacitor structure, which, but is not limited to, includes banks of parallel capacitor elements digitally selectable via switches.

[0054] Although an example of an RTWO segment featuring three tuning capacitor banks is in Fig. As shown in Figure 3B, the teachings here are applicable to RTWO, which are tuned using more or fewer capacitor banks.

[0055] In the illustrated embodiment, the PVT tuning capacitor bank 111 operates using a three-bit PVT tuning code, the coarse tuning capacitor bank 112 operates using a seven-bit coarse tuning code, and the fine tuning capacitor bank 113 operates using a thirty-one-bit fine integer tuning code. Although a specific example of bit widths is shown, the lessons taught here are applicable to tuning with a wide variety of bit widths. Accordingly, other implementations are possible. In specific implementations, the fine tuning capacitor bank 113 is controlled via a PLL feedback loop. For example, the fine integer tuning code can be controlled by a digital filter of a PLL.

[0056] The depicted RTWO segment 100 further includes the TDC latch 117, which is used to detect the passage of a traveling wave propagating along the first and second transmission line conductors 101 and 102. For example, the outputs of the TDC latches around the RTWO ring can be processed to generate a digital representation of the times at which the traveling wave passes through different positions around the loop. The output of the TDC latches can be used, for example, to determine a fraction of clock cycles that have elapsed.

[0057] As in Fig. As shown in Figure 3B, the TDC latch 117 receives a reference clock signal CLK. REF In specific implementations, the reference clock signal CLK REF provided for RTWO segment 100 via a takt distribution tree.

[0058] In the illustrated embodiment, the first tap buffer 118a and the second tap buffer 118b are implemented using inverters. The first tap buffer 118a and the second tap buffer 118b are used to generate clock signal phases that are separated by approximately 180°. By providing tap buffers along different positions along the RTWO ring, a group of clock signals with desired phases can be obtained. Fig. 7 represents a configuration in which inverters are used to provide the tapping; an RTWO can have a tapping buffer circuit arrangement implemented in a variety of ways.

[0059] In the illustrated embodiment, the regeneration circuit 115 comprises a first inverter 116a and a second inverter 116b. Additionally, an input of the first inverter 116a is electrically connected to an output of the second inverter 116b, and an output of the first inverter 116a is electrically connected to an input of the second inverter 116b. However, an RTWO segment may have regeneration circuits implemented in other ways.

[0060] The first and second metal spurs 131, 132 provide local clock phases from the RTWO loop for the circuit arrangement of the RTWO segment 100. Using the first and second metal spurs 131, 132, the length of the RTWO segment 100 can be relatively short, which in turn leads to a relatively short RTWO ring and a correspondingly high RTWO oscillation frequency.

[0061] In special configurations, an RTWO segment here contains a routing channel 133, which is used to provide a pass-through for routing conductor tracks through the RTWO segment.

[0062] As in Fig. As shown in Figure 3B, the first and second metal spur lines 131, 132 provide connections from the first transmission line conductor 101 and the second transmission line conductor 102, respectively, to the circuit arrangement of the RTWO segment 100. For example, the first and second metal spur lines 131, 132 connect the RTWO ring to tuning capacitors and other circuit arrangements of the RTWO segment 100.

[0063] The first and second metal branch lines 131, 132 provide a capacitive load which is part of the characteristic impedance Z othe transmission line. In specific implementations, the metal spurs may be implemented with approximately the same length and may be spaced at substantially equal intervals around the RTWO ring. Although the spurs are shown to be essentially the same for each segment, in other configurations the spurs for one or more of the segments may be implemented differently. In one example, design rules of the process restrict the transistor layout so that they are oriented in one direction, and the spurs along the top and bottom of an RTWO are implemented differently than spurs on the left and right sides of the RTWO.

[0064] As in Fig. As shown in Figure 3B, the first metal stub line 131 is connected to the first transmission line conductor 101 (for example, by means of a via) and extends from the first transmission line conductor 101 to provide connections to the circuit arrangement of the RTWO segment 100. In the illustrated embodiment, the first metal stub line 131 connects to a first terminal of the PVT tuning capacitor bank 111, to a first terminal of the coarse tuning capacitor bank 112, to a first terminal of the fine tuning capacitor bank 113, to an input of the first tap buffer 118a, and to a first input of the TDC latch 117. In the illustrated embodiment, an end section of the first metal stub line 131 bends before connecting to the first input of the TDC latch 117. However, other implementations are possible.

[0065] Furthermore with reference to Fig. 3B, the second metal spur 132 is connected to the second transmission line conductor 102 (for example, by means of a via). After an initial twist or bend, the second metal spur 132 extends from the second transmission line conductor 102 to provide connections to the circuit arrangement of the RTWO segment 100. In the illustrated embodiment, the second metal spur 132 connects to a second terminal of the PVT tuning capacitor bank 111, to a second terminal of the coarse tuning capacitor bank 112, to a second terminal of the fine tuning capacitor bank 113, to an input of the second tap buffer 118b, and to a second input of the TDC latch 117. However, other implementations are possible.

[0066] In one embodiment, the first metal spur line 131 and the second metal spur line 132 each have a length (including bends) of at least approximately 25 µm. In another example, the spur lines 131, 132 are approximately 95 µm long, which corresponds to approximately 6% of a wavelength (or 0.06 λ) of an RTWO operating at 10 GHz.

[0067] As in Fig. As shown in Figure 3B, the transmission line conductors 101 and 102 of the RTWO ring have a width W and are spaced apart from each other by a gap S. The width W and the gap S can be any suitable value, for example, W = 12 µm and S = 8 µm.

[0068] In specific implementations, the transmission line conductors 101, 102 are positioned on different metal layers relative to the metal spur lines 131, 132. In one example, the RTWO differential transmission line conductors 101, 102 are implemented on two or more adjacent upper metal layers (for example, a stack of metal-8 and metal-9), and the spur lines are implemented on a lower metal layer (for example, metal-7). As those familiar with electronics will recognize, a lower metal layer is closer to a semiconductor substrate relative to an upper metal layer.

[0069] As in Fig. Figure 3B shows a floor plan layout 120 of the RTWO segment 100. The floor plan layout 120 includes a PVT tuning capacitor bank layout 121, a coarse tuning capacitor bank layout 122, a fine tuning capacitor bank layout 123, a regeneration amplifier layout 125, a TDC latch layout 127, a tap buffer layout 128, and a decoupling capacitor layout 129.

[0070] The PVT tuning capacitor bank layout 121 corresponds to a boundary of the active area (e.g., transistor layouts and / or capacitor sizes) of the PVT tuning capacitor bank 111, the coarse tuning capacitor bank layout 122 corresponds to a boundary of the active area of ​​the coarse tuning capacitor bank 112, and the fine tuning capacitor bank layout 123 corresponds to a boundary of the active area of ​​the fine tuning capacitor bank 113. Furthermore, the tap buffer layout 128 corresponds to a boundary of the active area of ​​the tap buffers 118a, 118b, and the TDC latch layout 127 corresponds to a boundary of an active area of ​​the TDC latch 117. Additionally, the regeneration amplifier layout 125 corresponds to a boundary of an active area for the inverters 116a, 116b, and the decoupling capacitor layout 129 corresponds to a boundary of an active area of ​​a decoupling capacitor between power supply and ground for the regeneration circuit 115.

[0071] In one embodiment, segment 100 has a length S L of less than approximately 25 µm and a width S W of at least approximately 25 µm. In special implementations, the RTWO segment 100 has a width greater than its length, so that numerous segments can be distributed around the ring of the RTWO, while maintaining a relatively short RTWO conductor loop length and a correspondingly high oscillation frequency.

[0072] In one embodiment, an RTWO has at least 1 segment per 25 µm of the loop.

[0073] Although a specific implementation of the RTWO segment circuit arrangement and floor plan layout has been described above, the lessons taught here are applicable to a wide variety of RTWO segment implementations. Examples of segmented decoding for a traveling wave oscillator

[0074] In specific configurations, a segmented decoding scheme for RTWO frequency tuning codes is provided to reduce decoding complexity. This segmented scheme can operate using a combination of global and local decoding to process the frequency tuning codes. By using segmented decoding, the number of signal routes associated with the frequency tuning codes can be reduced.

[0075] An RTWO can operate with a large number of tuning capacitors, including tuning capacitors for PVT tuning, coarse tuning, and fine tuning (which may include both fine integer and fractional number tuning). The number of tuning capacitors can be further increased in implementations using multiple coupled rings to reduce phase noise. However, the large number of tuning capacitors can also lead to a large number of signal routes or wires.

[0076] In one example, a 4-ring RTWO has 32 segments per ring, where each segment contains a 2-bit PVT tuning capacitor bank, a 3-bit coarse tuning capacitor bank, and a 5-bit fine integer tuning capacitor bank. Additionally, each ring has an instantiation of a 5-bit fine fractional tuning capacitor bank. In this example without segmented decoding, the PVT tuning capacitor banks operate with 256 wires (2 bits * 32 segments * 4 rings), the coarse tuning capacitor banks with 384 wires (3 bits * 32 segments * 4 rings), the fine integer tuning capacitor banks with 640 wires (5 bits * 32 segments * 4 rings), and the fine fractional tuning capacitor banks with 20 wires (5 bits * 4 rings). Thus, the total number of wires in this example can be 256 + 384 + 640 + 20 = 1300 wires.

[0077] However, routing a large number of wires leads to routing density. Furthermore, the routes can result in an electrical environment that is susceptible to coupling of digitally improper components to the RTWO. For example, a large cluster of wires can act as a large antenna on a semiconductor chip. Additionally, the flexibility and / or scalability of the RTWO design can be limited. For instance, such routing density can restrict the maximum number of RTWO rings that can be coupled together to improve phase noise.

[0078] In specific configurations, the tuning capacitors are quantized across RTWO segments, allowing the tuning capacitors of each RTWO segment to be controlled separately from those of other segments. Additionally, a global decoder processes frequency tuning codes (such as a PVT tuning code, a coarse tuning code, and / or a fine integer tuning code) to generate input codes for local RTWO decoders. In specific implementations, unary decoding (thermometer decoding) is performed locally for each segment via the local decoders. In multi-ring implementations, the frequency tuning codes can be routed to global decoders assigned to each of the RTWO rings.

[0079] By using a segmented decoding scheme, the number of metal routes or wires can be reduced.

[0080] For example, in the specific example described above, 1300 wires were used for a 4-ring RTWO operating without segmented decoding. In contrast, segmented decoding can be used in this specific example to achieve 7-bit PVT tuning (for example, 3 unary bits per segment * 32 segments = 96 LSB < 2). 7 ), Coarse tuning with 8 bits (for example, 7 unary bits per segment * 32 segments = 224 LSB < 2 8 ) and fine integer tuning with 12 bits (for example, 31 unary bits per segment * 32 segments * 4 rings = 3968 LSB < 2 12). Thus, PVT tuning uses 28 wires (7 bits * 4 rings), coarse tuning uses 32 wires (8 bits * 4 rings), and fine integer tuning uses 48 wires (12 bits * 4 rings). Therefore, the total number of wires in this example can be 28 + 32 + 48 + 20 = 128 wires, which is approximately an order of magnitude smaller than in the implementation without segmented decoding.

[0081] Fig. Figure 4 represents an embodiment of an RTWO 400 with segmented decoding. In specific configurations, segmented decoding is provided to reduce the number of wires that need to be routed to an RTWO, such as the number of digital signal routes from an ADPLL core to an RTWO.

[0082] The RTWO 400 has a differential transmission line connected in a closed loop or ring. The differential transmission line has a first conductor 31, a second conductor 32, and a crossing 33. The RTWO 400 also has segments 100, which are described above with reference to Fig. 3B can be described. In the illustrated embodiment, thirty-two instantiations of segment 100 are positioned around the ring, with eight segments per side of the ring. As in Fig. As shown in Figure 10, the thirty-two segments are labelled with indices ranging from 0 to 31.

[0083] The RTWO 400 also features a global decoder system 401, a local decoder system 402, a digital routing bus 405, a serial interface 406 and a fine fraction tuning capacitor bank 410.

[0084] Although a specific RTWO implementation is shown, the lessons here are applicable to RTWO implemented in a wide variety of ways, including, but not limited to, RTWO with different ring implementations, different segment implementations and / or different decoder implementations.

[0085] The global decoder system 401 comprises a segment decoder system 403 and a voting decoder system 404. The global decoder system 401 can be implemented using a digital logic circuit arrangement, such as digital logic generated via digital synthesis. For example, the segment decoder system 403 and / or the voting decoder system 404 can be described using a hardware description language such as Verilog, which can be synthesized to generate a digital logic circuit arrangement. However, other implementations are possible. Although shown as distributed per segment, one or more decoders can be configured to provide decoding for multiple segments. For example, one decoder can be used per RTWO page.

[0086] The tuning decoder system 404 is used to decode frequency tuning codes (for example, PVT, coarse and / or fine integer tuning codes) in order to generate input codes for the local decoder system 402. The input codes are processed by the local decoder system 402 to activate the corresponding tuning capacitors of the RTWO segments.

[0087] In the illustrated embodiment, the tuning decoder system 404 has a tuning decoder (TD) for each segment 100. Additionally, the local decoder system 402 has a local decoder (LD) for each segment 100. In specific implementations, an LD is used to convert a binary input code from a corresponding TD into a unary-coded output code, which is used to select a number of active tuning capacitors of a specific RTWO segment 100.

[0088] As in Fig. As shown in Figure 4, the digital routing bus 405 surrounds a perimeter of the RTWO 400. The digital routing bus 405 can be used to route a large variety of input signals to the global decoder system 401.

[0089] For example, the global decoder system 401 of the RTWO 400 has been annotated to represent input signals 411-412 used for frequency tuning, which have a PVT tuning code (pvt_code<6:0>), a coarse tuning code (coarse_code<7:0>), a fine integer tuning code (fineint_code<7:0>), and a fine fractional tuning code (finefrac_code<2:0>). Although it is in Fig. 10. Not shown for clarity, the RTWO 400 can receive one or more clock signals which are used to indicate the timing of the voting codes.

[0090] In the illustrated embodiment, the digital routing bus 405 provides the PVT tuning code, the coarse tuning code, and the fine integer tuning code to the tuning decoder system 404, which processes the codes to generate input codes for controlling the local decoder system 402. The local decoder system 402 processes input codes for controlling PVT tuning banks, coarse tuning banks, and fine integer tuning banks of the RTWO segments 100.

[0091] As in Fig. As shown in Figure 4, an instantiation of the fine fraction tuning bank 410 is contained within the depicted RTWO 400, and the fine fraction tuning code (finefrac_code<2:0>) is provided for the fine fraction tuning bank 410 to control the fine fraction tuning. Thus, the fine fraction tuning code bypasses the tuning decoder system 404 in this example. In specific implementations, an LD is included to decode the fine fraction tuning code in order to generate unary bits for controlling the fine fraction tuning bank 410.

[0092] Although a specific implementation of frequency tuning codes and decoding is shown, the lessons taught here are applicable to a wide variety of implementations.

[0093] The Segment Decoder System 403 has one Segment Decoder (SD) for each segment 100. The Segment Decoder System 403 is used to decode data received via the Serial Interface 406 for the segments 100 of the RTWO.

[0094] As in Fig. As shown in Figure 4, the serial interface 406 receives the input signals 413, which include a segment data signal (rtwo_seg_data<7:0>), a segment address signal (rtwo_seg_addr<4:0>), a write enable signal (rtwo_wr_en), a serial interface clock signal (rtwo_sclk), and a data read signal (rtwo_rd_data<7:0>). In specific implementations, the serial interface 406 is implemented as a local serial peripheral interface (SPI).

[0095] In the illustrated embodiment, the digital routing bus 405 routes the input signals 413 to each SD of the segment decoding system 403 for decoding.

[0096] It may be desirable for the segments of an RTWO, such as RTWO segment 100, to be configurable. To provide configurability, RTWO segment 100 can be written to or read from via serial interface 406.

[0097] The RTWO 400 shown incorporates the segment decoder system 401, which reduces the number of routes allocated to communicating with the RTWO segments 100. In specific implementations, the segment decoder system 403 operates using a local tab. The local tab is used to provide bit addresses for each of the segments and is used to determine when the serial interface 406 communicates with a specific segment from the RTWO segments 100.

[0098] By including the segment decoder system 401, the number of data and address bus bits allocated to routing from the serial interface 406 to the RTWO segments 100 can be reduced.

[0099] For example, in one specific implementation, a 4-ring RTWO with 32 segments per ring has a data bus that uses 8 bits shared across all 4 rings, and an address bus that uses 5 bits shared across all 4 rings. In such an example, the 4-ring RTWO operates with 13 bits and wires.

[0100] In contrast, a similar 4-ring RTWO implemented with a segment decoder system can have 2048 bits and wires (16 bits per segment * 32 segments * 4 rings). Thus, a reduction of more than a hundredfold can be achieved by incorporating a segment decoder system in this specific example.

[0101] Fig. Figure 5 presents an implementation of voting decoders for a multi-ring RTWO 600. The multi-ring RTWO 600 features a southwest RTWO ring 601 (R0), a southeast RTWO ring 602 (R1), a northeast RTWO ring 603 (R2), and a northwest RTWO ring 604 (R3). Although a configuration using four rectangular RTWO rings is shown, the lessons learned here are applicable to implementations using more or fewer rings and / or rings implemented with other shapes.

[0102] Although terms relating to cardinal directions (north, south, east, west, northeast, northwest, southeast, southwest) are used to describe the RTWO with multiple rings, those familiar with the subject will recognize that these terms are used to understand relative orientations and do not refer to true directions. For example, the RTWO 600 with multiple rings is typically implemented, at least partially, on an integrated circuit (IC) or semiconductor device, and the orientation of the RTWO 600 with multiple rings changes when the IC changes its position or angle. Similarly, terms relating to up, down, left, and right are used to describe relative directions.

[0103] As in Fig. As shown in Figure 5, PVT tuning decoders, coarse tuning decoders and fine integer tuning decoders are provided around the sides of each of the RTWO rings 601-604.

[0104] With respect to the northwest RTWO ring 604, a northern PVT decoder 614a, a northern coarse decoder 624a, and a northern fine integer decoder 624a are positioned on the first or upper side. Additionally, a southern PVT decoder 614b, a southern coarse decoder 624b, and a southern fine integer decoder 634b are positioned on the second or lower side. Furthermore, a western PVT decoder 614c, a western coarse decoder 624c, and a western fine integer decoder 634c are positioned on the third or left side. Additionally, an eastern PVT decoder 614d, an eastern coarse decoder 624d, and an eastern fine integer decoder 634d are positioned on the fourth or right side.

[0105] Additionally, the orientations of the corresponding tuning decoders of the northeastern RTWO ring 603 are axially symmetrical with respect to the northwestern RTWO ring 604. For example, with respect to the northeastern RTWO ring 603, a northern PVT decoder 613a, a northern coarse decoder 623a, and a northern fine integer decoder 633a are positioned on the upper side. Additionally, a southern PVT decoder 613b, a southern coarse decoder 623b, and a southern fine integer decoder 633b are positioned on the lower side. Furthermore, a western PVT decoder 613c, a western coarse decoder 623c, and a western fine integer decoder 633c are positioned on the right side. Additionally, an eastern PVT decoder 613d, an eastern coarse decoder 623d and an eastern fine integer decoder 633d are positioned on a left side.

[0106] Furthermore, the orientations of the corresponding tuning decoders of the southwest RTWO ring 601 are axially symmetrical with respect to the northwest RTWO ring 604. For example, with respect to the southwest RTWO ring 601, a northern PVT decoder 611a, a northern coarse decoder 621a, and a northern fine integer decoder 631a are positioned on a lower side. Additionally, a southern PVT decoder 611b, a southern coarse decoder 621b, and a southern fine integer decoder 631b are positioned on an upper side. Furthermore, a western PVT decoder 611c, a western coarse decoder 621c, and a western fine integer decoder 631c are positioned on a left side. Additionally, an eastern PVT decoder 611d, an eastern coarse decoder 621d and an eastern fine integer decoder 631d are positioned on a right-hand side.

[0107] Additionally, the orientations of the corresponding tuning decoders of the southeastern RTWO ring 602 are axially symmetrical with respect to both the southwestern RTWO ring 601 and the northeastern RTWO ring 603. For example, with respect to the southeastern RTWO ring 602, a northern PVT decoder 612a, a northern coarse decoder 622a, and a northern fine integer decoder 632a are positioned on a lower side. Additionally, a southern PVT decoder 612b, a southern coarse decoder 622b, and a southern fine integer decoder 632b are positioned on an upper side. Furthermore, a western PVT decoder 612c, a western coarse decoder 622c, and a western fine integer decoder 632c are positioned on a right side. Additionally, an eastern PVT decoder 612d, an eastern coarse decoder 622d and an eastern fine integer decoder 632d are positioned on a left side.

[0108] Implementing tuning decoders of one RTWO ring with axial symmetry with respect to the tuning decoders of another RTWO ring provides a symmetry that reduces mismatch between the rings.

[0109] In the illustrated embodiment, tuning decoders are placed on each side of the RTWO ring. Additionally, the tuning decoders control tuning capacitors of adjacent RTWO segments, reducing the connections between the tuning decoder outputs and RTWO segments. For example, in an implementation with 32 segments per RTWO ring, the northern tuning decoders provide decoding for 8 corresponding segments of the RTWO ring. Consequently, the route lengths are reduced. Thus, the illustrated tuning decoders can represent a collection of TD blocks, as shown in Fig. Figure 4 is shown. However, other implementations are possible. For example, a separate TD block can be provided for each RTWO segment.

[0110] As in Fig. As shown in Figure 5, the PVT tuning decoders of RTWO rings 601-604 are labeled pvt_decoder_north, pvt_decoder_west, pvt_decoder_south, and pvt_decoder_east. Additionally, the coarse tuning decoders are labeled coarse_decoder_north, coarse_decoder_west, coarse_decoder_south, and coarse_decoder_east. In specific implementations, the PVT tuning decoders are essentially the same for each of the RTWO rings and segments, and the PVT tuning decoders operate with common PVT tuning codes.

[0111] As in Fig. Figure 5 shows the fine integer tuning decoders of the RTWO rings 601-604 with the labels fine integer_decoder_r0_north, fine integer_decoder_r0_west, fine integer_decoder_r0_south, fine integer_decoder_r0_east, fine integer_decoder_r1_north, fine integer_decoder_r1_west, fine integer_decoder_r1_south, fine integer_decoder_r1_east, fine integer_decoder_r2_north, fine integer_decoder_r2_west, fine integer_decoder_r2_south, fine integer_decoder_r2_east, fine integer_decoder_r3_north, fine integer_decoder_r3_west, marked feinganzzahl_decodierer_r3_süd and feinganzzahl_decodierer_r3_ost.

[0112] In specific implementations, the fine integer tuning decoders are implemented using essentially the same hardware (for example, essentially the same Verilog), but operate with different values ​​of rtwo_location<3:0> and thus exhibit different output values. Implementing the decoders in this way improves scalability and flexibility.

[0113] Although Fig. 5 represents an embodiment of voting decoders for a multi-ring RTWO; voting decoders can be implemented in a wide variety of ways. Examples of dynamic element matching for linearizing the fine-tuning of the gain of an RTWO

[0114] In specific configurations, a dynamic element matching (DEM) scheme is provided to linearize the fine-tuning characteristics of an RTWO. For example, dynamic element matching can be used to break the periodicity of a fixed sequence of segment selections used in the segmented decoding scheme for the RTWO. Reducing or eliminating the periodicity of the segment selection sequence attenuates unwanted false frequency components. Conversely, a fixed sequence for selecting RTWO segments can degrade spectral integrity by generating false frequency components.

[0115] For example, a wide frequency ramp can span a full range of fine-tuning codes. If a fixed sequence is used for segment selection, the incorrect component will appear at a frequency offset from the fundamental frequency. The frequency of the incorrect component is based on the period of the fixed sequence used for segment selection.

[0116] Table 1 below provides an example of a fixed-sequence selection for a multi-ring implementation of RTWO 600. Fig. Figure 5. In Table 1, W0, W1, W2, and W3 indicate the western voting decoders of the RTWO rings R0, R1, R2, and R3, respectively. Similarly, S0, S1, S2, and S3 indicate the southern voting decoders of the RTWO rings R0, R1, R2, and R3, respectively. Likewise, O0, O1, O2, and O3 indicate the eastern voting decoders of the RTWO rings R0, R1, R2, and R3, respectively. Additionally, N0, N1, N2, and N3 indicate the northern voting decoders of the RTWO rings R0, R1, R2, and R3, respectively.

[0117] As shown in the example in Table 1, the decoders activate or fire in a specific sequence when feinganzz_code increases. The periodicity of the segment selection can lead to a degradation of the spectral purity of the RTWO output clock phases.

[0118] In specific implementations, an RTWO decoding system with a dynamic element matching scheme is implemented to linearize the fixed sequence. Additionally, the dynamic element matching scheme can increase the period of the fixed sequence and / or remove the periodicity altogether.

[0119] The Fig. 6A and Fig. Section 6B presents an implementation of dynamic element matching for segment selection in an RTWO. The scheme for dynamic element matching of the Fig. 6A and Fig. 6B represents an embodiment for dynamic element matching for the RTWO 600 with multiple rings of Fig. 5. Thus, the illustrated embodiment of dynamic element matching is presented in the context of sixteen tuning decoders, which are accordingly labelled as decoder 0 to decoder 15.

[0120] However, dynamic element matching schemes can be used for a wide variety of RTWOs, including but not limited to RTWOs that have more or fewer rings, different implementations of rings, more or fewer segments, different implementations of segments, more or fewer voting decoders, and / or different implementations of voting decoders.

[0121] As in the Fig. 6A and Fig. Figure 6B shows a sequence of a 16-decoder cycle (in this example), with the sequence of selected decoders labeled accordingly as first to sixteenth decoder selection 1001-1016. The decoder cycle indicates the selection of decoders in response to an increase in the fine-integer code received by the RTWO. As discussed above, in specific applications, a broad frequency ramp can span the full range of fine-tuning codes.

[0122] A pointer 1000 is used to indicate the last voting decoder that was selected. Additionally, a pointer 1020 for the next cycle indicates a voting decoder that will be used at the beginning of the next decoder cycle (a 16-decoder cycle in this example). As shown by the first decoder selection 1001, the pointer 1020 for the next cycle is positioned at a different decoder location than the pointer 1000 located in the first decoder selection 1001. Implementing dynamic element matching in this way reduces the periodicity of decoder selection by preventing two consecutive 16-decoder cycles from starting at the same decoder location.

[0123] In the illustrated embodiment, the pointer 1000 starts at decoder 0 at the first decoder selection 1001. In special implementations, if the pointer 1000 has never been set, for example during the startup or reset of a chip, the pointer 1000 can be set to a special starting value (for example decoder 0) or to a random or pseudo-random decoder position.

[0124] As in the Fig. 6A and Fig. As shown in Figure 6B, the selected decoders change when transitioning from one decoder selection to the next. For example, in the illustrated embodiment, the selected decoders in the next decoder selection begin after the decoders of the current decoder selection have finished. Thus, in this embodiment, all previously selected decoders are switched off when transitioning to the next decoder selection.

[0125] For example, when transitioning from the first decoder selection 1001 to the second decoder selection 1002, decoder 0 is switched off, and decoders 1-2 are switched on. Additionally, when transitioning from the second decoder selection 1002 to the third decoder selection 1003, decoders 1-2 are switched off, and decoders 3-5 are switched on. Furthermore, when transitioning from the third decoder selection 1003 to the fourth decoder selection 1004, decoders 3-5 are switched off, and decoders 6-9 are switched on. Additionally, when transitioning from the fourth decoder selection 1004 to the fifth decoder selection 1005, decoders 6-9 are switched off, and decoders 10-14 are switched on.

[0126] In the illustrated embodiment, the selected decoders are labeled in a numerical sequence, starting with a start index 0 and ending with an end index 15. Additionally, the selected decoders wrap when the end index is exceeded during decoder selection to accommodate decoders starting at the start index. For example, when transitioning from the fifth decoder selection 1005 to the sixth decoder selection 1006, decoders 10-14 are switched off, and decoders 15 and 0-4 are switched on.

[0127] As shown in the sixth to sixteenth decoder selection 1006-1016, the algorithm is repeated up to the sixteenth decoder selection 1016, in which all sixteen decoders are selected.

[0128] The number of selected decoders can be chosen based on the fine integer code. For example, in this embodiment, in the case of distributed quantization over four rings, mod(fine_integer_code, 16) + 1 can be calculated. Additionally, in this example, fine_integer_code 0 selects no decoder. Accordingly, the result will be a value in the range of 1 to 16.

[0129] Depending on the current position of pointer 1000, the result will select a certain number of decoders starting from the current pointer position. In an example, pointer 1000 is at decoder 5, and feinganzz_code = 200 and mod(200, 16)+1 = 9, and the 9 selected decoders correspond to decoders 6 to 14. Afterward, pointer 1000 is at decoder 14.

[0130] The Fig. 7A and Fig. 7B represents another implementation of dynamic element matching for segment selection in an RTWO. The implementation of dynamic element matching of the Fig. 7A and Fig. 7B is similar to the implementation of dynamic element matching of the Fig. 6A and Fig. 6B, except that the dynamic element matching of the Fig. 7A and Fig. 7B is implemented to turn off only one decoder when transitioning from one decoder selection to the next.

[0131] For example, when transitioning from the first decoder selection 1101 to the second decoder selection 1102, decoder 0 is switched off, and decoders 1-2 are switched on. Additionally, when transitioning from the second decoder selection 1102 to the third decoder selection 1103, decoder 1 is switched off, decoder 2 remains switched on, and decoders 3-4 are switched on. Furthermore, when transitioning from the third decoder selection 1103 to the fourth decoder selection 1104, decoder 2 is switched off, decoders 3-4 remain switched on, and decoders 5-6 are switched on. Additionally, when transitioning from the fourth decoder selection 1104 to the fifth decoder selection 1105, decoder 3 is switched off, decoders 4-6 remain switched on, and decoders 7-8 are switched on.

[0132] As shown in the sixth to sixteenth decoder selection 1106-1116, the algorithm is repeated up to the sixteenth decoder selection 1116, in which all sixteen decoders are selected.

[0133] Additional details of the dynamic element matching of the Fig. 7A and Fig. 7B can be similar to those described earlier.

[0134] The scheme for dynamic element matching of the Fig. 6A and Fig. 6B and the scheme for dynamic element matching of the Fig. 7A and Fig. 7B are schemes for cyclic dynamic element matching. In the example with 16 decoder selections, there are 256 starting possibilities (16*16) for a cyclic cycle. Although schemes for cyclic dynamic element matching reduce periodicity by increasing the length of the period of the fixed sequence, a certain degree of periodicity can nevertheless be maintained.

[0135] In specific embodiments, a segment decoder system is implemented to work with random or pseudorandom dynamic element matching.

[0136] For example, in specific embodiments, a pseudorandom binary sequence (PRBS) is used to change the selection sequence of the decoders. The PRBS can be generated in any suitable way, such as using a digital logic circuit arrangement.

[0137] In one example, the PRBS changes the selection pointer at each specific number of codes, for example, every 16 fine integer codes, every 128 fine integer codes, etc. Thus, an even longer iterating sequence can be achieved to break the periodicity of the decoder selection.

[0138] In another example, dynamic element matching is used to randomize the sequence in which segments are selected by a specific tuning decoder. Thus, instead of activating tuning capacitors associated with a specific tuning decoder in a given sequence, the order in which the tuning capacitors controlled by a specific tuning decoder are selected is dynamically chosen. Accordingly, dynamic element matching can be used to break the periodicity in the selection of tuning decoders (a tuning decoder sequence) and / or to break the periodicity of tuning capacitors selected by the tuning decoders (a segment selection sequence). Examples of transition control schemes for RTWO

[0139] Facilities and procedures for handling the effects of mismatches in the ON-OFF switching times of controllable capacitors (also referred to here as varactors) of an RTWO are provided. Controlling the number of varactor transitions occurring on each code improves the performance of the RTWO by, for example, achieving constant transitions versus code when data-weighted DEM is applied to the RTWO decoders.

[0140] For example, in a vehicle radar application, frequency ramps are generated by a digital PLL with an RTWO (see, for example, Fig. 1) When DEM is enabled in the RTWO decoder, the number of varactor transitions is a function of the input code, and any mismatch in the on-to-off (ELN→OFF) and off-to-on (OFF→ELN) switching time of a varactor results in a frequency disturbance proportional to the number of switching varactors and thus the input code. This leads to a gain error, which is a function of the input code, and a corresponding excitation in the baseband spectrum in the target application.

[0141] In specific implementations, in addition to matching ON→OFF and OFF→ON switching times in the layout, a constant number of transitions versus code is ensured by generating dummy transitions using substitute banks. For example, the number of dummy transitions is the inverse of the number of transitions versus code, so that the total number of transitions remains constant.

[0142] Ensuring a constant number of transitions improves performance. For example, simulations showed a 100x reduction in gain variation with a 100p on / off mismatch, while measurements show a 20 dB reduction near the disturbance in the baseband spectrum for high-speed ramps.

[0143] Fig. Figure 8A is a schematic representation of an embodiment of an RTWO system 1150, which has four coupled RTWO rings. Fig. 8B is a graphic of transitions versus fine-tuning code for the RTWO system of Fig. 8A.

[0144] In this example, four rings are provided, with four sides for each ring, eight segments in each side, and 31 varactors in each segment. Specifically, the RTWO system 1150 has a northwest (NW) RTWO ring 1141, a northeast (NE) RTWO ring 1142, a southwest (SW) RTWO ring 1143, and a southeast (SE) RTWO ring 1144. In this example, each RTWO ring has four sides with eight segments per side. Thus, the RTWO system 1150 has 128 segments (4 x 4 x 8 = 128). Additionally, each segment has 128 varactors, with the varactors of one segment being reserved. Therefore, 3968 varactors (128 x 31 = 3968) are available for control. Furthermore, the 12-bit fine code is mapped to 3968 control lines. Additionally, DEM for segment selection is only applied to 7 LSBs.Although an RTWO is provided with a specific number of rings, segments, and varactors, the transition control schemes disclosed here can be applied to a wide variety of RTWOs.

[0145] As in Fig. As shown in Figure 8B, the number of transitions (0→1 and 1→0) is code-dependent if no transition control is provided.

[0146] Fig. Figure 8C is a graphic of an example of switching time mismatch for the RTWO system 1150 by Fig. 8A. The graph shows an upper diagram of the fine code value and a lower diagram of frequency versus time.

[0147] With reference to the simulation of Fig. In version 8C, a 100p mismatch is added to the varactor on / off switching times. This DEM leads to frequency distortions whose magnitude is a function of the number of transitions. This results in a code-dependent gain error.

[0148] Fig. 8D is a graphic of an example of gain error for the RTWO system of Fig. 8A. The graph shows an upper diagram of gain versus total code and a lower diagram of fine code versus total code for a frequency ramp.

[0149] With reference to Fig. Due to uneven transition density, 8D has one gain step every 64 codes. For the first 64 codes, the disturbance count increases as the code increases, and for the next 64 codes, the disturbance count decreases with the code. Varactor gain mismatches are disabled, and only switching time mismatches are modeled in this example.

[0150] To solve the problem from the Fig. To overcome 8A-8D, transition-driven DEM can be used to match the number of transitions per code in accordance with the teachings here.

[0151] For example, in the context of the RTWO system, Fig. 8A Two varactors from 31 (each labeled var0 to var30) are assigned to transition control in each segment. Thus, in this specific example, a total of 128 segments * 2 per segment = 256 varactors can be used for transition control. Var29 (reserve bank 0) and Var30 (reserve bank 1) in each segment are designated for transition control. Half of them are switched ON at the beginning. Depending on the code, varactors from the reserve banks are switched, providing a total of 64 0→1 and 64 1→0 transitions. The same logic can be used to control both reserve banks to save space.

[0152] Thus, in an example for code 2 (64-2), 62 additional transitions are obtained by switching 31 Var29 plus 31 Var30. Additionally, in an example for code 3 (64-3), 61 additional transitions are obtained by alternatively switching 30 Var29 plus 30 Var30 and 31 Var29 plus 31 Var30, resulting in an average of 61 transitions. Furthermore, in these examples, the spare banks always have exactly 64 Var29 and 64 Var30 switched ON.

[0153] Accordingly, a constant total number of switched-on varactors achieves a constant frequency offset for a first order.

[0154] Although an example with a specific number of varactors, surrogate varactors, and segments is provided, the lessons here are applicable to RTWO, which is implemented in a wide variety of ways.

[0155] Fig. Figure 8E is a schematic representation of a varactor circuit arrangement for an RTWO segment 1220 according to one embodiment. The RTWO segment 1220 comprises a segment decoder 1201, frequency control varactors 1202, and transition control varactors 1203. As shown in Fig. As shown in Figure 8E, the frequency control varactors 1202 and the transition control varactors 1203 are each connected between a differential transmission line 1204a / 1204b of an RTWO. Each of the varactors from the frequency control varactors 1202 and each of the varactors from the transition control varactors 1203 can be individually selected to control the capacitive charging of the differential transmission line 1204a / 1204b.

[0156] As in Fig. As shown in Figure 8E, the segment decoder 1201 receives a coarse frequency control signal (GROB) and a fine frequency control signal (FEIN). Additionally, the segment decoder 1201 includes a frequency control decoder 1207, which controls the frequency control varactors 1202 based on the coarse tuning code and the fine tuning code. Furthermore, the segment decoder 1202 includes a transition control decoder 1208, which controls the transition control varactors 1203 based on the fine tuning code to compensate the frequency control decoder 1207 for any difference in transition density relative to the fine tuning code.

[0157] For example, in specific embodiments, the transition control decoder 1208 selects a number of varactors from the transition control varactors 1203 whose state transitions, based on a value of the fine-tuning code. In particular, the transition control decoder 1208 selects a number of varactors from the transition control varactors 1203 to ensure that the sum of the number of transitions provided by the transition control decoder 1201 and the number of transitions provided by the frequency control decoder 1207 is constant for each value of the fine-tuning code.

[0158] In specific implementations, the segment decoder 1201 is controlled by a clock signal CLK, and the transition control decoder 1208 updates the number of transition control varactors 1203 selected in each cycle of the clock signal CLK. Additionally, if the frequency tuning code is fixed with a given value (the coarse tuning code and the fine tuning code are both constant), the total number of varactors in the selected state is constant, but a specific selection of the transition control varactors 1203 changes in each cycle of the clock signal CLK.

[0159] Thus, when dynamic element matching with a fixed frequency tuning code takes place, the transition control keeps the total number of varactors transitioning from 0→1 and from 1→0 constant from one clock cycle to the next. Accordingly, code-dependent frequency errors are attenuated.

[0160] Fig. Figure 9 is a graph of an example of the transition for transition-driven DEM. As in the diagram above. Fig. As shown in 9, DEM exhibits a triangular shape of transitions versus fine code, as above with reference to Fig. 8B is discussed. Additionally, as shown in the middle diagram of Fig. Figure 9 shows that the substitute banks are implemented with an inverted triangular form of transitions versus fine code to compensate for the transitions of the main banks used for DEM. Accordingly, as shown in the lower diagram of Fig. As shown in Figure 9, the total number of transitions versus fine code is essentially constant.

[0161] Fig. Figure 10 is an example of an operating diagram for replacement banks for transition-controlled DEMs. In this example, OFF-to-ON transitions are indicated with bold upward-pointing arrows, while ON-to-OFF transitions are indicated with bold downward-pointing arrows.

[0162] As in Fig. As shown in Figure 10, the number of varactors that have transitioned to the replacement banks is a function of the input code and is selected such that the total number of transitions for the RTWO system versus fine code is essentially constant.

[0163] Fig. 11 is an example of the operation of a transition control bank.

[0164] As in Fig. As shown in Figure 11, the varactors used to maintain the transition density are also switched using a DEM scheme. Thus, the switching varactors are changed in each clock cycle (shown in bold arrows in the figure). Furthermore, the backup bank in this example always has exactly 64 varactors switched ON. Additionally, the transitions complement those coming from the DEM on the main banks.

[0165] Fig. Figure 12A is a graph of an example of switching time mismatch for an RTWO system with transition control. The graph shows an upper plot of the fine-code value and a lower plot of frequency versus time.

[0166] In the example shown, a 100p mismatch is added to the on / off switching times of the varactors. DEM plus transition control results in constant transitions. This leads to a code-independent gain error.

[0167] Fig. Figure 12B is a graph of an example of gain error for an RTWO system with transition control.

[0168] As by comparing Fig. 12B and Fig. As shown in 8D, the amplification level has now disappeared in all 64 codes.

[0169] In particular, the transition density is constant, and the error due to interference frequency is the same for all codes.

[0170] In this example, varactor gain mismatches are disabled. Only switching time mismatches are modeled.

[0171] Fig. Figure 13A is a graph of another example of gain error for an RTWO system with transition control, which also models varactor gain mistuning. The graph shows a top graph of gain error versus total code, a middle graph of gain error versus total code in a magnified view, and a bottom graph of fine code versus total code for a frequency ramp.

[0172] Varactor gain mismatches are now modeled in this example. As in Fig. As shown in Figure 13A, there is a large disturbance on code 64. Additionally, there is a small difference in the gains for the lower and upper codes 64.

[0173] Fig. Figure 13B is a graphic of another example of gain mismatch with transition control.

[0174] When transition control is enabled, 128 varactors switched ON in the substitute bank cause a frequency offset. This offset changes in each clock cycle because a different group of varactors contributes to this offset with the DEM in transition control. Additionally, for code[6:0] = 64, there are no transitions in the substitute bank, and thus the offset is constant, leading to the gain disturbance at this code.

[0175] In specific embodiments, a modified transition control is provided here to address the problem that the Fig. 13A and Fig. 13B is assigned to overcome, taking into account the varactor gain mismatch.

[0176] In a first aspect of the modified transient control, the inventors recognized that the varactor gain varies significantly across segments compared to the variation within a segment. Accordingly, by inverting the two substitute banks relative to each other, the scatter of the frequency offset can be greatly reduced.

[0177] In a second aspect, non-zero substitute bank transitions on each code are ensured by increasing the total number of transitions, for example 66 instead of 64.

[0178] Fig. Figure 14A is another example of a substitute bank operating diagram for transition-controlled DEM. The diagram corresponds to an example of modified transition control with 66 transitions instead of 64 as discussed above.

[0179] Fig. Figure 14B is a graphic of an example of an open-loop gain with modeled switching time and gain mismatch.

[0180] In this example, the gain error is reduced from 3.2 kHz to -30 Hz every 64 codes.

[0181] Fig. Figure 15A is a graphic of an example of simulated baseband diagrams.

[0182] In Fig. At 15A, the transition control is deactivated. Gain mismatch and switching time mismatch are modeled.

[0183] Fig. Figure 15B is a graphic of another example of simulated baseband diagrams.

[0184] In Fig. 15B activates the transition control. Gain mismatch and switching time mismatch are modeled.

[0185] Fig. Figure 16 is a graph of measured baseband diagrams with and without transition control.

[0186] Switching time mismatches in the ON / OFF paths of the varactors lead to periodic gain errors and reduce the baseband power.

[0187] By making the switching density independent of the code, the side lobe level is reduced by -20 dB in measurements. Applications

[0188] Devices employing RTWO, which possess one or more of the features described above, can be implemented in various electronic devices. Examples of electronic devices may include, but are not limited to, consumer electronics, consumer electronics components, electronic testing machines, radar systems, etc. Examples of electronic devices may also include optical network and other communication network circuits. Consumer electronics may include, but are not limited to, a motor vehicle, camcorder, camera, digital camera, portable memory chip, washing machine, clothes dryer, washer / dryer combination, copier, fax machine, scanner, multifunctional peripheral device, etc.Furthermore, the electronic device may contain unfinished products, including those for industrial, medical, and automotive applications.

[0189] The foregoing description and the claims may refer to elements or features as being “connected” or “coupled” to one another. As used herein, “connected,” unless expressly stated otherwise, means that an element / feature is directly or indirectly connected to another element / feature, and not necessarily mechanically. Similarly, unless expressly stated otherwise, “coupled” means that an element / feature is directly or indirectly coupled to another element / feature, and not necessarily mechanically. Thus, although the various circuit diagrams shown in the figures represent exemplary arrangements of elements and components, additional intervening elements, devices, features, or components may be present in an actual embodiment (assuming that the functionality of the depicted circuits is not adversely affected).

[0190] Although this invention has been described with respect to specific embodiments, other embodiments, which are obvious to those skilled in the art and which include embodiments that do not provide all the features and advantages set forth herein, are also within the scope of protection of this invention. Furthermore, the various embodiments described above can be combined to provide further embodiments. Additionally, specific features shown in the context of one embodiment may also be incorporated into other embodiments. Accordingly, the scope of protection of the present invention is defined only by reference to the appended claims.

[0191] According to one aspect, the setup and method for traveling-wave oscillators (RTWOs) are disclosed. In particular embodiments, an RTWO system can include an RTWO ring that guides a traveling wave, several selectable capacitors distributed around the RTWO ring, each of which can be operated in a selected state and an unselected state, and a decoder system that controls the selection of the several selectable capacitors based on a frequency tuning code. The frequency tuning code can have a fine-tuning code and a coarse-tuning code, and the decoder system can be operated to control a constant number of capacitors that switch the state for each value of the fine-tuning code.

Claims

[1] Traveling wave oscillator system (RTWO system) comprising the following: a first RTWO ring designed to guide a traveling wave; several selectable capacitors distributed around the first RTWO ring, each of the several selectable capacitors being operable in a selected state and a non-selected state; and a decoder system configured to control the selection of several selectable capacitors based on a frequency tuning code having a fine tuning code and a coarse tuning code, wherein the decoder system is configured to operate a constant number of capacitors that switch the state for each value of the fine tuning code. [2] RTWO system according to claim 1, wherein the decoder system comprises a transition control decoder configured to control a first part of the multiple selectable capacitors, wherein the transition control decoder is configured to select a number of capacitors in the first part that transition in state based on a value of the fine-tuning code. [3] RTWO system according to claim 2, wherein the transition control decoder operates a constant number of capacitors in the selected state for each value of the fine-tuning code. [4] RTWO system according to claim 2 or 3, wherein the decoder system further comprises a frequency control decoder configured to control a second part of the multiple selectable capacitors based on the fine-tuning code, wherein the transition control decoder compensates the frequency control decoder for a difference in transition density versus the fine-tuning code. [5] RTWO system according to claim 4, wherein a sum of a first number of transitions provided by the transition control decoder and a second number of transitions provided by the frequency control decoder is constant for each value of the fine-tuning code. [6] RTWO system according to any one of claims 2 to 5, wherein the transition control decoder selects a group of capacitors for transition control for a given value of the fine-tuning code. [7] RTWO system according to claim 6, wherein the transition control decoder is controlled by a clock signal, wherein the selected group of capacitors for transition control changes in each cycle of the clock signal. [8] RTWO system according to claim 7, wherein the selected group of capacitors circulates for transition control. [9] RTWO system according to any one of claims 6 to 8, wherein the transition control decoder is implemented to provide at least one transition for each value of the fine-tuning code. [10] RTWO system according to one of the preceding claims, wherein the decoder system is controlled by a clock signal, wherein when the frequency tuning code is fixed at a given value, a total number of capacitors in the selected state is constant, but a specific selection of the several selectable capacitors changes in each cycle of the clock signal. [11] RTWO system according to one of the preceding claims, further comprising a second RTWO ring coupled to the first RTWO ring. [12] Method for traveling wave oscillation, wherein the method comprises: Propagation of a traveling wave around an RTWO ring; Controlling a delay of the traveling wave around the RTWO ring using multiple selectable capacitors distributed around the first RTWO ring, each of the multiple selectable capacitors being operable in a selected state and in a non-selected state; Controlling the selection of multiple selectable capacitors based on a frequency tuning code using a decoder system, wherein the frequency tuning code includes a fine tuning code and a coarse tuning code; and Operating a constant number of capacitors from the multiple selectable capacitors, switching the state for each value of the fine-tuning code using the decoder system. [13] Method according to claim 12, wherein the decoder system comprises a transition control decoder configured to control a first part of the multiple selectable capacitors, wherein the method further comprises selecting a number of capacitors in the first part that transition to the state based on a value of the fine-tuning code. [14] The method of claim 13, further comprising operating a constant number of capacitors in the selected state for each value of the fine-tuning code. [15] Method according to claim 13 or 14, wherein the decoder system further comprises a frequency control decoder configured to control a second part of the multiple selectable capacitors based on the fine-tuning code, wherein the method further comprises using the transition control decoder to compensate the frequency control decoder for a difference in transition density versus the fine-tuning code. [16] Method according to claim 15, wherein a sum of a first number of transitions provided by the transition control decoder and a second number of transitions provided by the frequency control decoder is constant for each value of the fine-tuning code. [17] Method according to any one of claims 13 to 16, further comprising the use of the transition control decoder to select a group of capacitors for transition control for a given value of the fine-tuning code. [18] Method according to claim 17, wherein the transition control decoder is controlled by a clock signal, the method further comprising changing the selected group of capacitors for transition control in each cycle of the clock signal. [19] The method of claim 18, further comprising the use of the transition control decoder to provide at least one transition for each value of the fine-tuning code.

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