AMPLIFIER CIRCUIT, METHOD FOR OPERATING AN AMPLIFIER CIRCUIT AND FOLDED CASCODE OPERATIONAL AMPLIFIER

Abstract

Amplifier circuit, comprising: a positive bias circuit (210) coupled to a power supply node (214) and comprising a driver PMOS, the driver PMOS configured to bias in a sub-threshold range; a negative bias circuit (230) coupled to a ground node (234) and comprising a driver NMOS, the driver NMOS being configured to bias in the sub-threshold range; and an amplification circuit (280) coupled to the positive bias circuit (210) and the negative bias circuit (230), the amplification circuit (280) comprising: a first stage (250) comprising PMOS transistors (422) and a first additional stage (252), one of the PMOS transistors (422) being coupled to the driver PMOS; a second stage (260) comprising NMOS transistors (426) and a second auxiliary stage (262), one of the NMOS transistors (426) being coupled to the driver NMOS; a resistive element (270) coupled between the first stage (250) and the second stage (260); and an output node (282) connected to the first stage (250) and the second stage (260), wherein: the resistance element (270) has: a PMOS transistor (422); a resistor (404); and an NMOS transistor (426); wherein the PMOS transistor (422) is connected in series with the resistor (404); and the resistor (404) is connected in series with the NMOS transistor (426).

Description

TECHNICAL FIELD

[0001] The disclosure relates to an amplifier circuit and an integrated circuit implementing the amplifier circuit. BACKGROUND

[0002] Operational amplifiers are high-gain electronic voltage amplifier circuits with a differential input and one or more outputs. The operational amplifiers generate an output potential that is typically thousands of times higher than the potential difference between their input terminals. Operational amplifiers can be used in various amplification modes, including, but not limited to, linear amplification, nonlinear amplification, and / or frequency-dependent amplification. Furthermore, operational amplifiers are used in both analog and digital circuits as an electronic building block for a wide variety of applications. And because operational amplifiers can be adapted to external components for specific operations, operational amplifiers are highly adaptable for individual operations.For example, the gain, input, output, impedance, and bandwidth of an operational amplifier can be adjusted to suit external components.

[0003] Operational amplifiers can be implemented in integrated circuits using specific configurations of active and / or passive electronic components. For example, operational amplifiers within integrated circuits can be fabricated using networks of transistors configured for high-gain conversion. Such operational amplifiers can be used for on-chip amplification of weak signals, noise reduction, and other signal processing operations. For example, operational amplifiers in integrated circuits can be used to filter and amplify signals input to processing circuits and / or logic circuits within the integrated circuit.Operational amplifiers in integrated circuits can use BJT technology and / or CMOS technology, and can use cascaded configurations to adjust gains, operating frequencies, and signal phases.

[0004] The disclosed systems, devices, and methods for operational amplifiers and integrated circuits are directed to addressing one or more problems or challenges of the prior art. US 2008 / 0 036 538 A1 discloses a rail-to-rail Class AB amplifier comprising an input circuit for converting a voltage difference between a first input signal and a second input signal into respective currents, a first current adder circuit for adding a drain current of a first input NMOS transistor and a drain current of a second input NMOS transistor, a second current adder circuit for adding a drain current of a first input PMOS transistor and a drain current of a second input PMOS transistor, a floating current source for controlling a bias current of the first current adder circuit and the second current adder circuit,a control circuit for controlling a voltage level of the drain terminal of a second cascode PMOS transistor and a second cascode NMOS transistor, and an output circuit coupled to the drain terminals of the second cascode PMOS transistor and the second cascode NMOS transistor. The invention is based on the object of simplifying the manufacture of integrated circuits. The invention is defined in the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Aspects of the present disclosure are best understood by reference to the following detailed description when taken in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features / elements are not drawn to scale. Indeed, the dimensions of the various features / elements may be arbitrarily exaggerated or reduced for clarity of illustration. Fig. 1 shows a circuit diagram of a duty cycle corrector (DCC) with synchronous input clock in accordance with some embodiments of the present disclosure. Fig. 2 shows a circuit diagram of an example operational amplifier consistent with some embodiments of the present disclosure. Fig. 3A shows a circuit diagram of an example configuration of driver transistors using a resistor, in accordance with some embodiments of the present disclosure. Fig. 3B shows a circuit diagram of an example configuration of driver transistors using a transistor, in accordance with some embodiments of the present disclosure. Fig. 3C shows a circuit diagram of an example configuration of driver transistors using a diode, in accordance with some embodiments of the present disclosure. Fig. 4A shows a circuit diagram of an example configuration of an operational amplifier using variable resistors, in accordance with some embodiments of the present disclosure. Fig. 4B shows a circuit diagram of an example configuration of an operational amplifier using triode transistors, in accordance with some embodiments of the present disclosure. Fig. 5A shows a circuit diagram of a first exemplary auxiliary stage consistent with some embodiments of the present disclosure. Fig. 5B shows a circuit diagram of a second exemplary auxiliary stage consistent with some embodiments of the present disclosure. Fig. 6A shows a circuit diagram of an exemplary boost stage using a resistive load, consistent with some embodiments of the present disclosure. Fig. 6B shows a circuit diagram of an exemplary boost stage utilizing an inductive load, consistent with some embodiments of the present disclosure. Fig. 6C shows a circuit diagram of an exemplary boost stage utilizing an active load, consistent with some embodiments of the present disclosure. Fig. 6D shows a circuit diagram of an exemplary boost stage using an active PMOS diode load, consistent with some embodiments of the present disclosure. Fig. 6E shows a circuit diagram of an exemplary boost stage using an active NMOS diode load, consistent with some embodiments of the present disclosure. Fig. 7 shows a circuit diagram of a first example amplifier with active loads and resistive coupling for sub-threshold bias in accordance with some embodiments of the present disclosure. Fig. 8 shows a circuit diagram of a second example sub-threshold bias amplifier using a coupling resistor, in accordance with some embodiments of the present disclosure. Fig. 9A shows an example schematic of a first layout plan for an integrated circuit in accordance with some embodiments of the present disclosure. Fig. 9B shows an example schematic of a second layout plan for an integrated circuit in accordance with some embodiments of the present disclosure. Fig. 10 shows a flow diagram of an example method for operating an amplifier circuit in accordance with some embodiments of the present disclosure. DETAILED DESCRIPTION

[0006] The following disclosure provides many different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, the formation of a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are formed in direct contact with each other, but may also include embodiments in which additional elements may be formed between the first element and the second element such that the first and second elements may not be in direct contact with each other. Furthermore, the present disclosure may repeat reference numbers and / or characters in the various examples.This repetition is for the purpose of simplicity and clarity, and does not in itself prescribe any relationship between the various embodiments and / or configurations discussed.

[0007] Furthermore, terms of spatial relationships, such as "beneath," "below," "low," "above," "upper," and the like, may be used herein for the purpose of more conveniently describing the relationship of one element or feature illustrated in the figures to another element or feature. The terms of spatial relationships are intended to encompass various orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be arranged in a different orientation (rotated 90 degrees or in other orientations), and the terms of spatial relationships used herein may thus be interpreted accordingly.

[0008] Furthermore, connection terms such as "connected," "coupled," "connected," "attached," and the like may be used herein for ease of description to describe elements having an electrical, electromagnetic, radio frequency, or ultrasonic connection. Furthermore, connection terms may refer to general electrical or magnetic communication between components. These connection terms may refer to a direct connection (i.e., two components connected without any intervening element) or an indirect connection (i.e., two components connected by one or more intervening elements).

[0009] Fig. 1 shows a circuit diagram of a synchronous input clock duty cycle corrector (DCC) 100 in accordance with some embodiments of the present disclosure. In some embodiments, the DCC 100 may be configured to adjust a clock duty cycle to a selected percentage. For example, the DCC 100 may be configured to adjust the clock duty cycle to modify clock signals for double data rate (DDR), half-clock data recovery (CDR), and / or a delay-locked loop (DLL). In some embodiments, the DCC 100 may be used in applications that utilize multi-phase clocks, MUX / DEMUX circuits, or other circuits with fixed rising edge requirements. The DCC 100 may be used for analog, half-digital, and / or digital applications.

[0010] The DCC 100 includes a clock input CLK_IN 114, which may be connected to an external input circuit that carries an input signal to be modified and / or corrected. The DCC 100 also includes differential inputs of a signal CKP 102 and a signal CKN 104. In some embodiments, as shown in Fig. 1, the signal CKP 102 and the signal CKN 104 are generated by operational amplifiers in the DCC 100. In such embodiments, as discussed in more detail below, CKP 102 is generated by an inverter 126, and CKN 104 is generated by an inverter 128. And CKP 102 and CKN 104 can be used as feedback signals. As shown in Fig. 1, the inputs CKP 102 and CKN 104 are thus connected to an amplifier 200, which is connected to a power supply node PWD_DCC 106. The amplifier 200 is used in conjunction with Fig. 2 is discussed in more detail.

[0011] As in Fig. 1, an output of amplifier 200 is coupled to a first control stage 108. The first control stage 108 includes first coupled CMOS transistors 108A, second coupled CMOS transistors 108C, and a first connection node 108B. The first coupled CMOS transistors 108A are connected to the first output of amplifier 200, the first connection node 108B is connected to a first reset control signal RSTB1 110, and the second coupled transistors 108C are connected to a first tie control signal tieo 112. While the output of amplifier 200 and an input of the signal tieo 112 are connected to the drain / source of the first coupled CMOS transistors 108A and the second coupled CMOS transistors 108C, as shown in Fig. 1, the RSTB1 signal 110 is coupled to the first connection node 108B. Further, the first coupled CMOS transistors 108A and the second coupled CMOS transistors 108C may be coupled to each other through their respective gates.

[0012] The DCC 100 includes a second control stage 122 having a configuration similar to that described above for the first control stage 108. In some embodiments, as in Fig. 1, the second control stage 122 includes third coupled CMOS transistors 122A, fourth coupled CMOS transistors 122C, and a second connection node 122B. The third coupled CMOS transistors 122A are coupled to a control node 116. Although not shown, the control node 116 may be coupled to an output of another amplifier similar to amplifier 200. However, in other embodiments, the control node 116 may be connected to another circuit and / or another electronic device. The second connection node 122B is coupled to a second reset control signal RSTB2 118, and the fourth coupled CMOS transistors 122C are coupled to receive a second tie control signal tie1 120.Similar to the connections in the first control stage 108, the control node 116 and an input for the signal tie1 120 are connected to drain / source nodes of the third coupled CMOS transistors 122A and the fourth coupled CMOS transistors 122C, while the signal RSTB2 118 is connected to the second connection node 122B.

[0013] The DCC 100 also includes a correction stage 124 coupled to the first control stage 108, the second control stage 122, and an input of the CLK_IN signal 114. The correction stage 124 includes a first PMOS transistor 124A, a second PMOS transistor 124B, a first NMOS transistor 124C, and a second NMOS transistor 124D. As shown in Fig. 1, transistors 124A - 124D are coupled in series. As also shown in Fig. 1, the first PMOS transistor 124A is coupled to a power supply node, which in some embodiments may be the same node as PWD_DCC 106. And the second NMOS transistor 124D is connected to a ground node. The gate of the first PMOS transistor 124A is coupled to drains / sources of the first coupled CMOS transistors 108A and the second coupled CMOS transistors 108C. The gate of the first NMOS transistor 124C is coupled to drains / sources of the third coupled CMOS transistors 122A and the fourth coupled CMOS transistors 122C. Furthermore, the gates of the second PMOS transistor 124B and the first NMOS transistor 124C are short-circuited, as shown in Fig. 1, and the shorted gates are coupled to receive the CLK_IN signal 114. As shown in Fig. 1, the second PMOS transistor 124B and the first NMOS transistor 124C provide an output of the correction stage 124. For example, drain / source nodes of the second PMOS transistor 124B and the first NMOS transistor 124C provide an output of the correction stage 124. This configuration of the correction stage 124 may serve as a buffer and / or a charge pump to modify the CLK_IN signal 114. The correction stage 124 may also be configured to be an integrator and / or a modifier of CLK_IN 114.

[0014] An output of the correction stage 124 is coupled to a series of inverters, which produce an output signal CLK_OUT 136. As in Fig. 1, the output of the correction stage 124 (drain / source node of transistors with shorted gates) is connected, for example, to a first inverter 126. The output of the first inverter 126 may provide a differential output. In some embodiments, the output of the first inverter 126 may be used as feedback by passing it to CKP 102. The first inverter 126 is connected in series to a second inverter 128. The output of the second inverter 128 may also be passed as feedback in series to CKN 104.

[0015] The DCC 100 also includes a third inverter 130, which is connected in series with the second inverter 128. However, unlike the first inverter 126 and the second inverter 128, the output of the third inverter 130 is the output of the DCC 100.

[0016] In some embodiments, the inverters 126, 128, and 130 may also be configured to provide amplification and / or attenuation. Furthermore, in some embodiments, the inverters 126, 128, and 130 may be equipped with amplifiers similar to amplifier 200, which is described below in connection with Fig. 2 is discussed.

[0017] Fig. 2 shows a circuit diagram of an example implementation of amplifier 200 in accordance with some embodiments of the present disclosure. As described in connection with Fig. 1, in some embodiments, amplifier 200 forms part of DCC 100. For example, amplifier 200 may be used to receive differential clock signals for duty cycle modifications and / or corrections. However, amplifier 200 may also be used in other applications unrelated to DCC 100. For example, amplifier 200 may be used as a differential amplifier, as an inverter amplifier (such as the first inverter 126 in Fig. 1) and used as a non-inverter amplifier. In some embodiments, as in Fig. As shown in Figure 2, amplifier 200 is configured as a folded cascode amplifier. However, in other embodiments, elements of amplifier 200 may be reconfigured to have unfolded cascode configurations.

[0018] Amplifier 200 includes a positive bias circuit 210 and a negative bias circuit 230. Amplifier 200 further includes a differential input circuit 220. Amplifier 200 further includes a first stage 250 and a second stage 260, which together form a gain circuit 280 that provides the differential gain in amplifier 200.

[0019] The positive bias circuit 210 may provide voltages and / or currents for operation of the amplifier 200. As shown in Fig. As shown in Figure 2, the positive bias circuit 210 includes a plurality of PMOS transistors. However, in other embodiments, the positive bias circuit 210 may include alternative transistors, such as BJT transistors and / or NMOS transistors.

[0020] The transistors in the positive bias circuit 210 include a first bias PMOS transistor 211, a second bias PMOS transistor 213, and a driver PMOS transistor 212. As described below in connection with the Fig. 3A, Fig. 3B and Fig. 7, the driver PMOS transistor 212 may be configured to be biased in a subthreshold range. A threshold voltage of the driver PMOS transistor 212 may be determined by MOSFET threshold voltage equations, such as V t = V FB +2ϕ f + √(2ε s qN a (2ϕ f +V SB )) / C ox , where V t the threshold voltage is V FB is the transistor band voltage, ϕ f is the surface potential, ε s is the relative dielectric constant, q is the elementary charge, N a is the doping concentration, VSB is the source-to-body substrate bias and C ox is the effective capacitance. The dimensions, doping characteristics, and processing of the driver PMOS transistor 212 can be chosen such that the driver PMOS transistor 212 operates in a sub-threshold region when the amplifier 200 is turned on. In some embodiments, for example, W / D, C ox , doping and V FB in PMOS transistor 212 for sub-threshold operation in amplifier 200.

[0021] As in Fig. 2, the gates of the first bias PMOS transistor 211, the second bias PMOS transistor 213, and the driver PMOS transistor 212 are directly connected to each other. Furthermore, the first bias PMOS transistor 211, the second bias PMOS transistor 213, and the driver PMOS transistor 212 in the positive bias circuit 210 are connected to a power supply node 214, which provides a voltage and / or current supply. In some embodiments, the power supply node 214 may, for example, be the same node as PWD_DCC 106 ( Fig. 1). The first bias PMOS transistor 211, the second bias PMOS transistor 213, and the driver PMOS transistor 212 in the positive bias circuit 210 are also connected to other stages or components in the amplifier 200. For example, the first bias PMOS transistor 211 and the driver PMOS transistor 212 may be connected to the differential input circuit 220 and the first stage 250.

[0022] Fig. Figure 2 shows one embodiment of a positive bias circuit 210 with three PMOS transistors. Other embodiments not shown may use alternative configurations of transistors in the positive bias circuit 210. For example, the positive bias circuit 210 may include four or more transistors, which may include both CMOS transistors and BJT transistors. Alternatively or additionally, the positive bias circuit 210 may include alternative three-terminal devices, such as vacuum tubes or other semiconductor devices.

[0023] Similar to the positive bias circuit 210, the negative bias circuit 230 includes transistors directly connected to the differential input circuit 220. However, instead of being connected to the first stage 250, transistors in the negative bias circuit 230 are also connected to the second stage 260. Further, transistors in the negative bias circuit 230 include a plurality of NMOS transistors. In other embodiments, however, the negative bias circuit 230 may include alternative transistors. For example, the negative bias circuit 230 may include four or more transistors, which may include both CMOS transistors and BJT transistors. Alternatively, or in addition, the negative bias circuit 230 may include alternative three-terminal devices, such as vacuum tubes or other semiconductor devices.

[0024] The transistors in the negative bias circuit 230 include a driver NMOS transistor 232, a first bias NMOS transistor 231, and a second bias NMOS transistor 233. Similar to the driver PMOS transistor 212, the driver NMOS transistor 232 can be configured to be biased in the subthreshold region. For example, the dimensions, oxide, doping, and bias circuit of the driver NMOS transistor 232 can be selected for a subthreshold bias when the amplifier 200 is turned on or operating. In some embodiments, for example, W / D, C ox , doping and VFB in NMOS transistor 232 are selected for sub-threshold operation in amplifier 200.

[0025] As in Fig. 2, the gates of the driver NMOS transistor 232, the first bias NMOS transistor 231, and the second bias NMOS transistor 233 have shorted gates. Furthermore, the transistors in the negative bias circuit 230 are connected to a ground node 234. In some embodiments, the ground node 234 may be the same node as the ground nodes in the DCC 100. The driver NMOS transistor 232, the first bias NMOS transistor 231, and the second bias NMOS transistor 233 are also connected to other stages or transistors in the amplifier 200. For example, some of the transistors of the negative bias circuit 230 may be connected to the differential input circuit 220 and the second stage 260.

[0026] The differential input circuit 220 includes a plurality of transistors connected to either the first amplifier input VIP 202 or the second amplifier input VIN 204. In some embodiments, VIP 202 and VIN 204 may be connected to external elements. For example, VIP 202 and VIN 204 may be coupled to capacitors and / or resistors and receive input signals. In some embodiments, as in Fig. 1, the inputs VIP 202 and VIN 204 of the amplifier 200 receive the signals CKP 102 and CKN 104, respectively.

[0027] As in Fig. 2, the transistors in differential input circuit 220 include both NMOS transistors and PMOS transistors. For example, differential input circuit 220 includes NMOS transistors 222A and 222B and PMOS transistors 224A and 224B. NMOS transistors 222A and 222B may be matching transistors. This means that NMOS transistors 222A and 222B may have the same dimensions, C ox , doping, and bias circuitry. Furthermore, NMOS transistors 222A and 222B may be configured to operate in the same bias range and under similar voltage and current conditions. However, in other embodiments, NMOS transistors 222A and 222B may be independent of each other and configured with different W / D or different bias circuit configurations.

[0028] Like the NMOS portion of the differential input circuit 220, the PMOS transistors 224A and 224B may be matching transistors. For example, the PMOS transistors 224A and 224B may have the same dimensions, C ox , doping, and bias circuitry. And the PMOS transistors 224A and 224B may be configured to operate in the same or similar bias ranges. However, in other embodiments, the PMOS transistors 224A and 224B may be independent of each other and configured with different W / D or different bias circuit configurations.

[0029] As in Fig. 2, the gate of both NMOS transistor 222A and PMOS transistor 224A is coupled to VIP 202. In contrast, the gate of both NMOS transistor 222B and PMOS transistor 224B is coupled to VIN 204. The resulting differential input configuration enables the reception of a differential signal to be amplified. In some embodiments, VIP 202 and VIN 204 may, for example, be CKP 102 and CKN 104, respectively, of DCC 100 ( Fig. 1). In such embodiments, the differential input circuit 220 may serve as an interface to the inputs and / or feedback in the DCC 100.

[0030] Furthermore, the drain / source of the transistors in differential input circuit 220 are directly connected to other elements of amplifier 200. For example, NMOS transistor 222A is directly connected to driver PMOS transistor 212 and NMOS transistor 222B. NMOS transistor 222B, in turn, is directly connected to a PMOS in positive bias circuit 210. PMOS transistors 224A and 224B are both directly connected to the first bias PMOS transistor 211 in positive bias circuit 210, while PMOS transistor 224A is directly connected to driver NMOS transistor 232 and first bias NMOS transistor 231 in negative bias circuit 230.

[0031] Fig. 2 shows a configuration of the differential input circuit 220 with two NMOS transistors and two PMOS transistors. However, other configurations are also possible for the differential input circuit 220. For example, the differential input circuit 220 can be implemented with BJT transistors. Alternatively or additionally, the differential input circuit 220 can be implemented with other three-terminal components. Furthermore, instead of four transistors, the differential input circuit 220 can have other arrangements including more transistors, unpaired transistors, and / or a mixture of transistor types. Furthermore, the differential input circuit 220 can connect to other elements in the amplifier 200 to enable the detection of a differential input to be amplified. As shown in Fig. 2, the differential input circuit 220 is coupled to the positive bias circuit 210 and the negative bias circuit 230, for example.

[0032] The first stage 250 is coupled to the positive bias circuit 210 and the second stage 260 through a resistive element 270. The first stage 250 includes PMOS transistors 254, which include a first PMOS transistor 254A and a second PMOS transistor 254B. In some embodiments, the first PMOS transistor 254A and the second PMOS transistor 254B are matching transistors with the same dimensions, C ox , doping, and bias circuitry. In other embodiments, the first PMOS transistor 254A and the second PMOS transistor 254B are independent transistors. The first stage 250 also includes a first auxiliary stage 252. As shown in Fig. As shown in Figure 2, the first auxiliary stage 252 is connected to the gates of PMOS transistors 254. Furthermore, the drain / source nodes of PMOS transistor 254A are connected in series with the driver PMOS transistor 212 and with the gate of the driver PMOS transistor 212. The PMOS transistor 254B is directly connected between a drain / source of NMOS transistor 222B, which is coupled to VIN 204, and an output node 282 of the amplifier 200.

[0033] In addition to its connection to the PMOS transistors 254, the first auxiliary stage 252 may also be directly connected to transistors in the positive bias circuit 210. For example, the first auxiliary stage 252 is also connected to a drain / source of the driver PMOS transistor 212 and a drain / source of a second bias PMOS transistor 213 in the positive bias circuit 210. Furthermore, the first auxiliary stage 252 may be directly connected to respective gates of the first PMOS transistor 254A and the second PMOS transistor 254B.

[0034] The second stage 260 has a configuration similar to that of the first stage 250. However, instead of being coupled to the positive bias circuit 210, the second stage 260 is coupled to the negative bias circuit 230. Furthermore, the second stage 260 includes NMOS transistors 264 instead of PMOS transistors 254. The second stage 260 includes NMOS transistors 264, which include a first NMOS transistor 264A and a second NMOS transistor 264B. The second stage 260 also includes a second auxiliary stage 262. Similar to the first auxiliary stage 252, the second amplification stage 262 may be connected to the gates of the NMOS transistors 264. Furthermore, the drain / source of the NMOS transistor 264A are connected in series with the driver NMOS transistor 232 and with the gate of the driver NMOS transistor 232.NMOS transistor 264B is directly connected to a drain / source of the second bias NMOS transistor 233 in the negative bias circuit 230, as well as to PMOS transistor 254B. The shared node between PMOS transistor 254B and NMOS transistor 264B forms output node 282.

[0035] In addition to its connection to the NMOS transistors 264, the second auxiliary stage 262 is also directly connected to transistors in the negative bias circuit 230. The second auxiliary stage 262 is also connected to a drain / source of the driver NMOS transistor 232 and a drain / source of a second bias NMOS transistor 233 in the negative bias circuit 230.

[0036] As in Fig. 2, the first stage 250 connects to the second stage 260 via the resistance element 270. In particular, a drain / source of the PMOS transistor 254A is directly connected to the resistance element 270, which is connected to a drain / source of the NMOS transistor 264A. Furthermore, the resistance element 270 is also connected to the gates of the driver PMOS transistor 212 and the driver NMOS transistor 232. As shown in Fig. 2, resistive element 270 connects to PMOS transistor 254A and the gate of driver PMOS transistor 212 at the same node. Thus, a gate of driver PMOS transistor 212 is directly connected to a first terminal of resistive element 270. More specifically, in some embodiments, a gate of driver NMOS transistor 232 is directly connected to a second terminal of resistive element 270. And resistive element 270 connects to NMOS transistor 264A and the gate of driver NMOS transistor 232 at the same node, which is different from the node connecting to PMOS transistor 212.

[0037] The resistance element 270 is in Fig. 2 as a two-terminal element, which may comprise a resistor, a capacitor, or an inductor (or any combination thereof). However, in some embodiments, the resistive element 270 may comprise a different type of device. For example, the resistive element 270 may comprise a three-terminal device, such as a transistor or a controlled diode. For example, the resistive element 270 may comprise a transistor biased in a triode mode. In such embodiments, the resistive element 270 may be coupled to receive a control signal that enables the selection of a particular resistance desired for operation of the amplifier 200. In certain embodiments, the resistive element 270 may be dynamically configured, for example, based on the operation of other elements in the amplifier 200.Furthermore, the resistance element 270, as described in connection with . Fig. 4B, in some embodiments, a PMOS transistor, a resistor, and an NMOS transistor, wherein the PMOS transistor is connected in series with the resistor, and the resistor is connected in series with the NMOS transistor.

[0038] The inclusion of the resistance element 270 as in Fig. 2, allows amplifier 200 to be configured for self-biased gain boost operation. For example, resistive element 270 can be selected to place both driver PMOS transistor 212 and driver NMOS transistor 232 into sub-threshold operation. Thus, in certain embodiments, a value of resistive element 270 can be selected to set a gate voltage of driver NMOS transistor 232 for sub-threshold operation and a gate voltage of driver PMOS transistor 212 for sub-threshold operation. By appropriately selecting the transistors in amplifier 200 and the value of resistive element 270, one or more of the transistors in amplifier 200 can operate in the sub-threshold region. This configuration results in several advantages for amplifier 200.For example, by operating in the subthreshold region, amplifier 200 requires a lower supply voltage (or Vdd) compared to other amplifiers. Furthermore, by operating in the subthreshold region, the amplifier achieves higher DC gain compared to other amplifiers. In particular, the use of gain-boosted stages in amplifier 200 enables higher DC gain than other amplifiers.

[0039] In addition to increased DC gain, the amplifier 200 (as shown in Fig. 2) provides further operational advantages. For example, compared to other folded cascode amplifiers, amplifier 200 reduces the number of external bias voltages. Folded cascode configurations require a large number of external bias voltages. This requirement introduces several limitations, particularly when the amplifier is fabricated in an integrated circuit. For example, having multiple bias voltages results in increased area and power requirements, as well as susceptibility to crosstalk between bias lines and / or noise. And given the relationship between amplifier gain and noise sensitivity, the gain of other folded cascode amplifiers is limited by practical signal-to-noise ratio (SNR) considerations.The configuration of amplifier 200 addresses these issues by providing a low-voltage, self-biased and gain-boosted amplifier (e.g., less than 2.5 V). The use of resistive element 270 between first stage 250 and second stage 260 (each with its corresponding boost stage) enables subthreshold transistor operation, improving gain and reducing the number of external bias lines, which in turn results in smaller footprint, less noise, and lower power consumption.

[0040] Furthermore, the detailed configuration of amplifier 200 can also modify the gain spectrum compared to other operational amplifiers. Because the resistive element 270 places the driver NMOS transistor 232 and the driver PMOS transistor 212 into the subthreshold range, it is possible to improve the dynamic range of amplifier 200, enabling strong gains at both low and high input or output voltages. For example, the configuration shown for amplifier 200 results in higher gains at low input voltages (e.g., input voltages of less than 100 mV), but also exhibits high gains for high input voltages (e.g., over 500 mV).

[0041] In addition to improvements in operating performance, the amplifier 200 configuration also improves manufacturing requirements. As further discussed in connection with the Fig. 9A and Fig. 9B, allows the configuration of the circuits and stages used in Fig. 2, the configuration of specific areas with a small footprint, simpler wiring, and lower power consumption. Furthermore, the amplifier design is adaptable and can be used in various technology nodes. For example, amplifier 200 can be implemented in a variety of manufacturing processes, such as 3 nm, 5 nm, 7 nm, 10 nm, 16 nm, and 20 nm.

[0042] The operational and manufacturing advantages provided by amplifier 200 make it a good candidate for an operational amplifier in digital and / or analog circuits. For example, amplifier 200 can improve or facilitate the operation and / or manufacturing of the DCC 100.

[0043] Fig. 3A shows a circuit diagram of an example configuration 300 of driver transistors implementing a resistor as resistive element 270, in accordance with some embodiments of the present disclosure. In configuration 300, resistive element 270 is implemented as a resistor 302. As shown in Fig. 3A, the insertion of resistor 302 as the resistive element creates a branch of amplifier circuit 280 ( Fig. 2), wherein the gate of driver PMOS transistor 212 is coupled to one end of resistor 302, while the gate of driver NMOS transistor 232 is coupled to the other end of resistor 302. Furthermore, resistor 302 is also connected to transistors of first stage 250 and second stage 260. Specifically, one end of resistor 302 is coupled to PMOS transistor 254A, and the other end of resistor 302 is coupled to NMOS transistor 264A.

[0044] By using resistor 302, configuration 300 effectively lowers the gate-to-source voltages of driver NMOS transistor 232 and driver PMOS transistor 212, allowing both to operate in the subthreshold region. Thus, incorporating resistor 302 into one branch of amplifier circuit 280 results in lower gate-to-source voltages in driver transistors, with such lower voltages facilitating subthreshold operation and enabling self-biasing. Thus, appropriately selecting the value of resistor 302 can lead to the benefits of amplifier 200 as described above.

[0045] Fig. 3B shows a circuit diagram of an example configuration 350 of driver transistors implementing a transistor as a resistive element 270, in accordance with some embodiments of the present disclosure. In configuration 350, the resistive element 270 is implemented as a transistor 304. As shown in Fig. 3B, in some embodiments, transistor 304 is a PMOS device. However, in other embodiments, transistor 304 may be an NMOS device or a BJT device. Transistor 304 may be used as a controlled variable resistor. For example, the Vb applied to the gate of transistor 304 may be selected to place transistor 304 in a resistive or triode mode of operation. The equivalent resistance may be selected to place driver PMOS transistor 212 and driver NMOS transistor 232 in the subthreshold region. Using transistor 304 as the resistive element creates one branch of amplifier circuit 280 ( Fig. 2), wherein the gate of driver PMOS transistor 212 is coupled to the source of transistor 304, while the gate of driver NMOS transistor 232 is coupled to the drain of transistor 304. Furthermore, transistor 304 is also connected to transistors of the first stage 250 and the second stage 260. In particular, the source of transistor 304 is coupled to PMOS transistor 254A, and the drain of transistor 304 is coupled to NMOS transistor 264A.

[0046] In configuration 350, the bias state of transistor 304 can be selected to reduce the gate-to-source voltages of driver NMOS transistor 232 and driver PMOS transistor 212, allowing both to operate in the subthreshold region. Thus, incorporating transistor 304 with the Vb applied for triode operation results in matched gate-to-source voltages in the driver transistors, facilitating subthreshold operation and enabling self-biasing. Thus, appropriately selecting the value and bias of transistor 304 results in the advantages of amplifier 200 described above.

[0047] Fig. 3C shows a circuit diagram of an example configuration 380 of driver transistors implementing a diode as a resistive element 270, consistent with some embodiments of the present disclosure. In configuration 380, resistive element 270 is implemented as a diode 306. Diode 306 may be a standard diode connected for forward biasing, and a selected diode voltage drop is required for resistive operation. However, in other embodiments, diode 306 may be configured for reverse biasing, and the breakdown voltage may be selected for an equivalent resistance. In some embodiments, diode 306 may be implemented with Zener diodes and / or Schottky diodes. The equivalent resistance of diode 306 may be selected to place driver PMOS transistor 212 and driver NMOS transistor 232 into the subthreshold region.Using diode 306 as the resistive element creates one branch of the amplification circuit 280 (. Fig. 2), in which the gate of driver PMOS transistor 212 is coupled to one end of diode 306, while the gate of driver NMOS transistor 232 is coupled to the other end of diode 306. Furthermore, diode 306 is also connected to transistors of first stage 250 and second stage 260. Specifically, one end of diode 306 is coupled to PMOS transistor 254A, and another end of diode 306 is coupled to NMOS transistor 264A.

[0048] In configuration 380, the bias state of diode 306 can be selected to reduce the gate-to-source voltages of driver NMOS transistor 232 and driver PMOS transistor 212, allowing both to operate in the subthreshold region. Thus, incorporating diode 306 with an appropriately selected equivalent resistance (either in forward or reverse mode) results in matched gate-to-source voltages in the driver transistors, facilitating subthreshold operation and enabling self-biasing. Thus, appropriately selecting the parameters of diode 306 can result in the benefits of amplifier 200 described above.

[0049] Fig. 4A shows a circuit diagram of an example configuration 400 of a portion of amplifier 200 using variable resistors, consistent with some embodiments of the present disclosure. In configuration 400, resistive element 270 is implemented as a series of variable and fixed resistors. Such a configuration may facilitate the selection of appropriate resistance values that result in a sub-threshold bias of driver PMOS transistor 212 and driver NMOS transistor 232.

[0050] In configuration 400, resistive element 270 is implemented as a first variable resistor 402, a fixed resistor 404, and a second variable resistor 406. This configuration allows for both increasing and decreasing the gate-to-source voltages (Vgs) of driver PMOS transistor 212 and driver NMOS transistor 232, resulting in more precise control of gain and power consumption by precisely selecting the operating modes of the driver transistors. Furthermore, the use of variable resistors as part of resistive element 270 allows for increasing the output of amplifier 200 and the common-mode range.

[0051] The ability to precisely control the gate-to-source voltage of the driver PMOS transistor 212 and the driver NMOS transistor 232 enables the selection of Vgs based on the output voltage (VO) at the output node 282. Placing the driver PMOS transistor 212 and the driver NMOS transistor 232 into the sub-threshold region allows the configuration 400 to adjust Vgs based on the VO. As discussed below in connection with Fig. For example, as further discussed in Figure 4B, a signal from the VO can be used as a feedback control to dynamically adjust the value of the first variable resistor 402 and the second variable resistor 406. In this way, when VO increases at the output node 282, the first variable resistor 402 and the second variable resistor 406 can be modified to increase Vgs, prevent saturation or triode operation, and maintain the transistor in the subthreshold region. Conversely, when VO decreases, the first variable resistor 402 and the second variable resistor 406 can be adjusted to decrease Vgs, prevent saturation or triode operation, and maintain the device in the subthreshold region.

[0052] In some embodiments, the first variable resistor 402 and the second variable resistor 406 may be implemented with transistors similar to the transistor 422 (as described below in connection with Fig. 4B). However, in other embodiments, the first variable resistor 402 and the second variable resistor 406 may be implemented with alternative devices that allow control of their resistance values.

[0053] Fig. 4B shows a circuit diagram of an example configuration 450 of an operational amplifier 200 that uses transistors as variable resistors, in accordance with some embodiments of the present disclosure. In configuration 450, the resistance element 270 is implemented with a PMOS transistor 422, a resistor 404, and an NMOS transistor 426. Configuration 450 shows an implementation of configuration 400 in which the variable resistors are implemented using transistors. Thus, in some embodiments, as in Fig. 4B, the first variable resistor 402 and the second variable resistor 406 ( Fig. 4A) is implemented by a PMOS transistor 422 and an NMOS transistor 426, respectively. Configuration 450 uses a combination of PMOS transistors and NMOS transistors to facilitate the fabrication of resistive element 270 and to provide self-biasing based on the VO at output node 282. However, other configurations are possible, using only NMOS or only PMOS transistors, as well as other device types (e.g., BJT).

[0054] In configuration 450, the gates of PMOS transistor 422 and NMOS transistor 426 are directly connected to output node 282. This configuration creates feedback through PMOS transistor 422 and NMOS transistor 426. With this configuration, when the output VO of amplifier 200 is low, the resistance of PMOS transistor 422 will decrease while the resistance of NMOS transistor 426 increases. And, as the resistance of NMOS transistor 426 increases, the Vgs at NMOS transistor 232 / NMOS transistor 233 will continue to decrease, and the overdrive voltage (Vov), defined as the gate-to-source voltage (Vgs) above the threshold voltage, of NMOS transistor 233 will also decrease. This type of feedback in resistive element 270 allows for precise gain control, as well as dynamic self-bias adjustments to maintain a target DC gain and dynamic range.

[0055] The PMOS transistor 422 and the NMOS transistor 426 in configuration 450 can be implemented with FinFETs. For example, the PMOS transistor 422 can be implemented with three FinFETs connected in parallel, each of the FinFETs having L=8n and M=24, where L defines the transistor length based on the selected process node, and M defines the transistor type. Likewise, the NMOS transistor 426 can be implemented with three FinFETs connected in parallel, each having L=8n and M=24. In such embodiments, the value of the resistor 404 can be in the kiloohm range. For example, the resistor 404 can have a value between 1 and 100 kΩ. For example, the resistor 404 can have a value of 1.8 kΩ.

[0056] Fig. 5A shows an example circuit diagram of a first auxiliary stage 252 in accordance with some embodiments of the present disclosure. The first auxiliary stage 252 provides additional gain to the amplifier 200. As discussed in connection with Fig. 2, the first additional stage 252 can be arranged within the first stage 250 ( Fig. 2).

[0057] The first auxiliary stage 252 includes a first input sub-stage 512. The first input sub-stage 512 includes input PMOS transistors 506A and 506B. One of the source / drain nodes of the PMOS transistors 506A and 506B is directly connected and coupled to the power supply node 214. The opposite source / drain nodes of the PMOS transistors 506A and 506B are connected to a first output VOPN 506 and a second output VOPP 508. The gates of the PMOS transistors 506A and 506B are connected to a first input VPP 502 and a second input VPN 504. In some embodiments, the input PMOS transistors within the first input sub-stage 512 may be identical, meaning they have the same dimensions, bias voltage, and operation. However, in other embodiments, the input PMOS transistors within the first input sub-stage 512 may be independent of each other.

[0058] The first auxiliary stage 252 also includes a first charge sub-stage 510. The first charge sub-stage 510 includes NMOS transistors 507A and 507B, which are connected to the PMOS transistors 506A and 506B in the first input sub-stage 512 and to the ground node 234. For example, the first input sub-stage 512 may include the PMOS transistors 506A and 506B coupled to the power supply node 214. Furthermore, the gates of the NMOS transistors 507A and 507B are shorted and may be connected to an input node VB1. Similar to the context of Fig. 3B, the input of node VB1 can be selected such that NMOS transistors 507A and 507B are arranged in a triode region to act as an active load. The effective impedance value of the charging substage 510 can be selected based on the desired gain, SNR, dynamic range, or a combination of these parameters. The first embodiment of the charging substage 510 of Fig. However, Figure 5A is only one option, and alternative embodiments are described below in connection with the Fig. 6A - 6E discussed.

[0059] Fig. 5B shows an example circuit diagram of a second auxiliary stage 262 in accordance with some embodiments of the present disclosure. The second auxiliary stage 262 provides additional gain to the amplifier 200. As discussed in connection with Fig. 2, the second additional stage 262 can be arranged within the first stage 260 ( Fig. 2).

[0060] The second auxiliary stage 262 has a second input sub-stage 532. The second input sub-stage 532 has input NMOS transistors 533A and 533B. One of the source / drain nodes of the input NMOS transistors 533A and 533B within the second input sub-stage 532 is directly connected to the ground node 234 ( Fig. 2) connected and coupled. For example, the second input substage 532 may be coupled to the drain / source node of each of the NMOS transistors 264, with the second charge substage coupled to a gate node of each of the NMOS transistors 533A and 533B. Additionally, the NMOS transistors 533A and 533B are coupled to the ground node 234.

[0061] The opposite source / drain nodes of the input NMOS transistors 533A and 533B are connected to a first output VOPN 526 and a second output VOPP 528. The gates of the NMOS transistors 533A and 533B are connected to a first input VNP 522 and a second input VNN 524. In some embodiments, the input NMOS transistors within the second input sub-stage 532 may be identical, meaning they have the same dimensions, bias voltage, and operation. However, in other embodiments, the input NMOS transistors within the second input sub-stage 532 may be independent of each other.

[0062] The second auxiliary stage 262 also includes a second charging sub-stage 530. The second charging sub-stage 530 includes PMOS transistors 531A and 531B, which are connected to the NMOS transistors 533A and 533B in the second input sub-stage 532 and to the power supply node 214. Furthermore, the gates of the PMOS transistors 531A and 531B in the second charging sub-stage 530 are short-circuited and may be connected to an input node VB2. As described in connection with Fig. As discussed in Figure 3B, the input of VB2 can be configured such that PMOS transistors 531A and 531B are arranged in a triode region to act as an active load. The effective impedance value of the second charging substage 530 can be selected based on the desired gain, SNR, dynamic range, or a combination of these parameters.

[0063] The Fig. Figures 6A - 6E show circuit diagrams of example boost stages using various charging devices. Depending on the application, integrated circuit area constraints, or specific power targets, a designer can choose different charging mechanisms or devices for boost stages.

[0064] Fig. 6A shows a circuit diagram of an exemplary auxiliary stage 252A that uses resistive charging, in accordance with some embodiments of the present disclosure. In the auxiliary stage 252A of Fig. 6A, the charging substage uses a passive charge with a charging resistor 642. Although the charging resistor 642 is shown as a single resistor, the charging resistor 642 may comprise a network of passive resistors.

[0065] Fig. 6B shows a circuit diagram of an exemplary auxiliary stage 252B that uses an inductive charge, in accordance with some embodiments of the present disclosure. In the auxiliary stage 252B of Fig. 6B, the charging sub-stage uses passive charging with a charging inductor 644. Although the charging inductor 644 is shown as a single inductor, the charging inductor 644 may comprise a network of inductors and / or capacitors with an equivalent impedance desired for the charging sub-stage. In certain embodiments, the auxiliary stages 252B may be embodiments of the Fig. 6A and Fig. 6B, which include resistor 642 or inductor 644 or combinations thereof.

[0066] Fig. 6C shows a circuit diagram of an exemplary auxiliary stage 252C using active charging, in accordance with some embodiments of the present disclosure. In the auxiliary stage 252C of Fig. 6C, the charging substage uses an active charge with a charging transistor 646. Although the charging transistor 646 is shown as a single component, the charging transistor 646 may comprise a network of transistors. One possible implementation of the additional stage 252C of Fig. For example, Figure 6C shows the first charging substage 510, which uses back-to-back transistors. Likewise, other embodiments may include networks of transistors connected in parallel, in series, or in a combination of parallel and series.

[0067] Fig. 6D shows a circuit diagram of an exemplary auxiliary stage 252D using an active PMOS diode load, in accordance with some embodiments of the present disclosure. In the auxiliary stage 252D of Fig. 6D, the charging substage uses an active charge with a PMOS diode 648. Although the PMOS diode 648 is shown as a single MOS device with a shorted gate, the PMOS diode 648 may comprise a network of transistors or standard (non-CMOS) diodes or Zener and / or Schottky diodes.

[0068] Fig. 6E shows a circuit diagram of an exemplary auxiliary stage 252E using an active NMOS diode load, in accordance with some embodiments of the present disclosure. In the auxiliary stage 252E of Fig. 6E, the charging substage uses an active charge with an NMOS diode 650. Although the NMOS diode 650 is shown as a single MOS device with a shorted gate, the NMOS diode 650 may comprise a network of transistors or standard (non-CMOS) diodes, such as (for example) Zener and / or Schottky diodes.

[0069] Fig. 7 shows a circuit diagram of a first example amplifier 700 with active loads and resistive coupling for sub-threshold biasing in accordance with some embodiments of the present disclosure. The amplifier 700 embodies one possible implementation of the amplifier 200. Like the amplifier 200, the amplifier 700 includes a differential input circuit 220, a positive bias circuit 210, a negative bias circuit 230, an amplification circuit 280 (which includes a first stage 250 and a second stage 260), and a resistive element 270 between the first stage 250 and the second stage 260. However, in the amplifier 700, the first auxiliary stage 252 (within the first stage 250) is provided by the Fig. 5A, the second additional stage 262 (within the second stage 260) is implemented by the Fig. 5B, and the resistance element 270 is replaced by the resistor 302 ( Fig. 3) implemented.

[0070] As in Fig. 7, the resulting circuit has a plurality of direct connections between the various transistors in amplifier 700. As shown in Fig. For example, as shown in Figure 7, one end of the resistive element 270 is directly connected to a transistor in the first stage 250 (e.g., PMOS transistor 254A), a gate of the driver PMOS transistor 212, and gates of the load transistors in the second auxiliary stage (e.g., transistors in the charge sub-stage 530). The opposite end of the resistive element 270 is directly connected to a transistor in the second stage 260 (e.g., NMOS transistor 264A), a gate of the driver NMOS transistor 232, and also to gates of the load transistors in the first auxiliary stage (e.g., transistors in the charge sub-stage 510). Furthermore, a gate of the PMOS transistor 254A is directly connected to drain / source nodes of transistors in the first auxiliary stage 252. In addition, a gate of the NMOS transistor 264A is directly connected to drain / source nodes of transistors in the second auxiliary stage 262.Thus, amplifier 700 may be configured such that a gate of driver PMOS transistor 212 is directly connected to a first terminal of resistive element 270, and a gate of driver NMOS transistor 232 is directly connected to a second terminal of resistive element 270. In such a configuration, the first terminal of resistive element 270 is directly connected to second charging sub-stage 530, and the second terminal of resistive element 270 is directly connected to first charging sub-stage 510.

[0071] Fig. 7 also shows connections between transistors in the first input sub-stage 512 and the second input sub-stage 532 as well as other elements of the amplifier 700. As in Fig. For example, as shown in Figure 7, gates of the first input sub-stage 512 are connected to drain / source nodes of the positive bias circuit 210. And gates of the second input sub-stage 532 are connected to drain / source nodes of the negative bias circuit 230. Furthermore, the gate of PMOS transistor 254B is directly connected to drain / source nodes of transistors in the first auxiliary stage 252. Furthermore, a gate of NMOS transistor 264B is directly connected to drain / source nodes of transistors in the second auxiliary stage 262.

[0072] Amplifier 700 illustrates an implementation of amplifier 200 in which the auxiliary substages utilize active loading, and resistive element 270 utilizes a passive load. This type of implementation can be used to improve control of the auxiliary stages while minimizing power and area consumption for coupling between the first stage 250 and the second stage 260.

[0073] Fig. 8 shows a circuit diagram of a second example subthreshold bias amplifier 800 using a coupling resistor, consistent with some embodiments of the present disclosure. Amplifier 800 embodies an alternative implementation of amplifier 200 that does not use additional stages and places the coupling resistor element between stages at a different node. Amplifier 800 still places driver NMOS transistor 232 into the subthreshold region by using a resistive element to couple stages of an amplification circuit. However, this is done between different elements of the stages to avoid using the additional stages and to minimize area and / or power consumption. However, this implementation may result in narrower dynamic ranges.

[0074] Like amplifier 200, amplifier 800 includes a positive bias circuit 210, a negative bias circuit 230, and a differential input circuit 220. However, instead of the first stage 250 and the second stage 260, amplifier 800 includes stages without gain. Amplifier 800 includes a first stage 810 including PMOS transistors 812 and a coupling NMOS transistor 814. PMOS transistors 812 include a PMOS transistor 812A (which may be similar to PMOS transistor 254A) and a PMOS transistor 812B (which may be similar to PMOS transistor 254B). However, instead of the first auxiliary stage 252, the first stage 810 includes the coupling NMOS transistor 814. The source / drain nodes of the coupling NMOS transistor 814 are connected to the power supply node 214 and a resistive element 830, respectively.Furthermore, the gate of the coupling NMOS transistor 814 is coupled to the driver PMOS transistor 212 and the PMOS transistor 812A.

[0075] The amplifier 800 also includes a second stage 820, which includes NMOS transistors 822 and a coupling PMOS transistor 824. The NMOS transistors 822 include an NMOS transistor 822A (which may be similar to NMOS transistor 264A) and an NMOS transistor 822B (which may be similar to NMOS transistor 264B). However, instead of the second auxiliary stage 262, the second stage 820 includes a coupling PMOS transistor 824. The source / drain nodes of the coupling PMOS transistor 824 are connected to the ground node 234 and the resistive element 830, respectively. Furthermore, the gate of the coupling PMOS transistor 824 is coupled to the driver NMOS transistor 232 and the NMOS transistor 822A.

[0076] In contrast to the first stage 250 and the second stage 260, which are coupled via the resistive element 270 and the output node 282, the first stage 810 and the second stage 820 are coupled via the resistive element 830, the output node 282, and other direct connections between elements of the stages. As shown in Fig. For example, as shown in Figure 8, NMOS transistor 822A and PMOS transistor 824A are directly connected to each other (without the resistor element 270 as in amplifier 200). The gates of PMOS transistors 812 are also directly connected to each other (without the auxiliary stage) and are connected to a drain / source node of NMOS transistor 822A. Furthermore, the gates of NMOS transistors 822 are directly connected to each other (without the auxiliary stage), and the gates are connected to a drain / source node of PMOS transistor 812A.

[0077] Furthermore, the first stage 810 and the second stage 820 are connected by the resistive element 830. The resistive element 830 connects the coupling NMOS transistor 814 and the coupling PMOS 824. The resistive element 830 is also directly connected to the gate of the driver NMOS transistor 232. Such a configuration results in a sub-threshold bias for the driver NMOS transistor 232. With an appropriately selected resistive element 830, the driver NMOS transistor 232 can be placed in the sub-threshold region. The resistive element 830 can be selected from the elements discussed above for the resistive element 270. This means that the resistive element 830 can be implemented with passive, active, or combined loads. For example, the resistive element 830 can be simply implemented with a resistor (see Fig. 3A) or an inductive element. However, the resistance element 830 can also be implemented with a transistor (see Fig. 3B). Furthermore, the resistance element 830 can also be implemented with a diode (see Fig. 3C) are implemented.

[0078] The bias configuration in amplifier 800 represents at least in part the above-mentioned Fig. 2, since amplifier 800 also operates driver transistors in the subthreshold range. For example, amplifier 800 also achieves greater DC gain than conventional amplifiers and has the potential to operate with a wider range of output voltages. Amplifier 800 can also be manufactured in a smaller area (since it has fewer transistors) and can be used for applications requiring lower power consumption. Based on gain, current, and area constraints and / or limitations of specific applications, circuit designers can combine embodiments of amplifiers 200, 700, and 800.

[0079] Fig. 9A shows an example schematic of a first layout plan 900 for an integrated circuit in accordance with some embodiments of the present disclosure. The first plan 900 may be used for amplifier 200, amplifier 700, and / or amplifier 800. The first plan 900 includes a positive bias region 902. In some embodiments, the positive bias region 902 may include elements of the positive bias circuit 210. Further, the positive bias region 902 may also include elements of the differential input circuit 220, such as PMOS transistors 224A and 224B. In such embodiments, the positive bias region 902 includes the driver PMOS transistor 212. The first plan 900 also includes a negative bias region 908. In some embodiments, the negative bias region 908 may include elements of the negative bias circuit 230.In such embodiments, the negative bias region 908 includes the driver NMOS transistor 232. Furthermore, the negative bias region 908 may also include elements of the differential input circuit 220, such as the NMOS transistors 222A and 222B.

[0080] The first floor plan 900 also includes an input region 905, which includes a p-type input region 904 and an n-type input region 906. The input region 905 may include elements of the differential input circuit 220. For example, the p-type input region 904 may include the PMOS transistors 224, and the n-type input region 906 may include the NMOS transistors 222.

[0081] The first floor plan 900 also includes a first additional region 810 and a second additional region 812. In some embodiments, the first additional region 910 may include elements of the first stage 250. In other embodiments, the first additional region 910 may include only elements of the first additional stage 252 (e.g., without the PMOS transistors 254). In some embodiments, the second additional region 912 may include elements of the second stage 260. In other embodiments, the second additional region 912 may include only elements of the second additional stage 262 (e.g., without the NMOS transistors 264).

[0082] The first footprint 900 also includes a resistance region 914, which may include two resistance elements 270. Alternatively or additionally, the resistance region 914 may include a resistance element 830. For example, the resistance region 914 may include the resistor 302, the transistor 304, or the diode 306 ( Fig. 3A-3C). Furthermore, the resistance region 914 can establish the connection between the first additional region 910 and the second additional region 912.

[0083] The first floor plan 900 shows a possible configuration of the different areas for the amplifiers 200, 700 or 800. As in Fig. As shown in Figure 9, the input region 905 is arranged between the positive bias region 902 and the negative bias region 908. In particular, the n-type input region 906 borders and contacts the negative bias region 908, while the p-type input region 904 borders and contacts the positive bias region 902. And the p-type input region 904 and the n-type input region 906 border each other, contact each other, and / or are arranged next to each other.

[0084] Furthermore, in a first floor plan 900, the first additional region 910 borders, contacts, or is arranged adjacent to both the positive bias region 902 and the p-type input region 904 on the same side of the first additional region 910. The second additional region 912 borders, contacts, and / or is arranged adjacent to both the negative bias region 908 and the n-type input region 906 on the same side of the second additional region 912. The first additional region 910 and the second additional region 912 also border each other, contact each other, and / or are arranged next to each other on a side that is different from the side that borders, contacts, or is arranged adjacent to other regions of the first floor plan 900.

[0085] In a first floor plan 900, the resistance region 914 borders both the first additional region 910 and the second additional region 912, contacts them, and / or is arranged adjacent to them on the same side of the resistance region 914. Furthermore, as shown in the first floor plan 900, the resistance region 914 may be arranged only adjacent to the first additional region 910 and the second additional region 912, but separated from the input region 905, the positive bias region 902, and the negative bias region 908.

[0086] As in Fig. Therefore, as shown in Figure 9A, an integrated circuit implementing the disclosed amplifiers may be arranged such that the positive bias region 902 borders the first auxiliary stage 910 and the p-type input region 904. Furthermore, the negative bias region 908 borders the second auxiliary stage 912 and the n-type input region 906. Additionally, or alternatively, the resistance region 914 borders the first auxiliary stage region 910 and the second auxiliary region 912.

[0087] Fig. 9B shows an example schematic of a second layout plan 920 for an integrated circuit in accordance with some embodiments of the present disclosure. The second plan 920 may be used for amplifiers 200, 700, and / or 800.

[0088] Similar to the first floor plan 900, the second floor plan 920 includes the positive bias region 902, the negative bias region 908, and the input region 905, which includes the p-type input region 904 and the n-type input region 906. However, unlike the first floor plan 900, the second floor plan 920 combines the additional regions into a single additional region 915. While the first floor plan 900 includes the first additional region 910 and the second additional region 912, the second floor plan 920 includes a single additional region 915, which may combine elements of the first stage 250 and the second stage 260. Alternatively, the additional region 915 may include only elements of the first additional stage 252 or the second additional stage 262.

[0089] Combining the additional elements in the additional region 915 creates a different arrangement for the second floor plan 920. In the second floor plan 920, the additional region 915 is surrounded by other regions. For example, the additional region 915 borders the input region 905 on one side. On an opposite side, the additional region 915 borders the resistance region 914. On a third side, the additional region borders, is arranged adjacent to, and / or contacts the positive bias region 902. And on a fourth side opposite the third side, the additional region 915 borders, is arranged adjacent to, and / or contacts the negative bias region 908. Furthermore, in the second floor plan layout 920, the resistance region 914 borders, contacts, and / or is arranged adjacent to the positive bias region 902 and the negative bias region 908 in addition to the input region 905.

[0090] Other elements in the second floor plan 920 have a similar arrangement as in the first floor plan 900. For example, the input region 905 is arranged between the positive bias region 902 and the negative bias region 908, with the p-input region 904 bordering, contacting, and / or being arranged next to the positive bias region, while the n-input region 906 bordering, contacting, and / or being arranged next to the negative bias region 908.

[0091] Fig. 10 shows a flowchart of an example method 1000 for operating an amplifier circuit in accordance with some embodiments of the present disclosure. In some embodiments, the disclosed amplifiers 200, 700, and / or 800 may operate based on method 1000. For example, transistors in amplifier 200 may be biased, connected, and / or operated based on method 1000 to provide gain at output node 282 when an input signal is input to first amplifier input VIP 202 and / or second amplifier input VIN 204.

[0092] The method 1000 may begin at step 1002. At step 1002, one or more PMOS transistors within a wide-swing p-cascode current mirror of an amplifier circuit are configured for operation in a saturation region. For example, at step 1002, the first PMOS transistor 254A may be biased in a saturation region. The PMOS transistors biased in the saturation region at step 1002 may be connected to driver transistors of the amplifier. For example, at step 1002, the PMOS transistor 254A may be biased for operation in the saturation region while directly connected to the driver PMOS transistor 212.

[0093] At step 1004, one or more NMOS transistors within a wide-swing n-cascode current mirror of an amplifier circuit are configured to operate in a saturation region. For example, at step 1004, the first NMOS transistor 264A may be biased to operate in a saturation region. The NMOS transistors biased in the saturation region at step 1004 may be connected to driver transistors of the amplifier. For example, at step 1004, the NMOS transistor 264A may be biased to operate in the saturation region while directly connected to the driver NMOS transistor 232.

[0094] At step 1006, the driver NMOS transistor 232 and the driver PMOS transistor 212 are configured for operation in a sub-threshold region. As described above in connection with Fig. As discussed in more detail in Figure 2, a resistive element can couple NMOS transistors to PMOS transistors in amplifier circuits. For example, in amplifier 200, resistive element 270 connects the first NMOS transistor 264A and the first PMOS transistor 254A together. This configuration enables the driver NMOS transistor 232 and the driver PMOS transistor 212 to operate in the subthreshold region. Without resistive element 270, the driver NMOS transistor 232 and the driver PMOS transistor 212 could not both operate in the subthreshold region because the gates of the driver NMOS transistor 232 and the driver PMOS transistor 212 would be connected together.However, the resistive element 270 can be used to decouple the gates of the driver NMOS transistor 232 and the driver PMOS transistor 212, thereby enabling a configuration in which both the driver NMOS transistor 232 and the driver PMOS transistor 212 operate in the sub-threshold region.

[0095] At step 1008, the amplifier circuit may be operated using a supply voltage. For example, amplifier 200 may be operated by applying the supply voltage to power supply node 214. The supply voltage may be selected based on the configuration of the transistors in the amplifier, the desired currents, and the biasing of the transistors in steps 1002 and 1004. For example, in some embodiments, the supply voltage applied to power supply nodes of the amplifiers may be proportional to a sum of a voltage drop in the driver transistors and the resistive element. The supply voltage used to power amplifier 200 may also (or alternatively) be proportional to a sum of the voltage drop across driver NMOS transistor 232, the voltage drop across resistive element 270, and the voltage drop across driver PMOS transistor 212.Furthermore, in some embodiments, the selected supply voltage (VDD) may be equal to the sum of the voltage drop across driver NMOS transistor 232 (Vgs_232), the voltage drop across resistive element 270 (Vr_270), and the voltage drop across driver PMOS transistor 212 (Vgs_212). Thus, in some embodiments, VDD = Vgs_232 + Vr_270 + Vgs_212. Furthermore, Vr_270 may be set based on a current through driver NMOS transistor 232, resistive element 270, and driver PMOS transistor 212, since Vr_270 = I * R, where I is the current and R is the equivalent resistance of resistive element 270.

[0096] Furthermore, the supply voltage (VDD) of step 1008 can also be selected based on the threshold voltage and overdrive conditions of the transistors in the amplifier circuit. In certain embodiments, the supply voltage (VDD) can be selected, for example, to be at least twice the sum of a threshold voltage of the transistors in the large-swing p-cascode current mirror and the large-swing n-cascode current mirror (Vt) and an overdrive voltage (ΔV) of the transistors biased in the saturation region. Thus, for such embodiments, at step 1006: VDD≥ 2*(Vt + ΔV).

[0097] Steps 1002-1008 of method 1000 enable the configuration of a self-biased amplifier without external bias voltages and without degrading its AC performance. The method enables the use of an amplifier circuit with improved gain that maintains a wide dynamic range.

[0098] At step 1010, a signal may be input to a differential input circuit of the amplifier circuit. For example, at step 1010, a signal may be input to the differential input circuit 220 of the amplifier circuit 200. As described in connection with Fig. 1, the differential input to amplifier 200 may be signal CKP 102 and signal CKN 104.

[0099] The input signal is amplified by the amplifier circuit. Based on the configuration established in steps 1002-1008, the amplifier circuit generates an amplified output. Thus, in step 1012, the amplifier circuit may generate an output at an output node based on the differential input signal. For example, in step 1012, amplifier 200 may generate an output at output node 282. As discussed in connection with Fig. 1, the output generated by amplifier 200 can be used as a control signal in a DCC.

[0100] The gain generated by the amplifier circuit at step 1012 is based on an auxiliary gain stage and an input gain stage. The input gain stage may be based on the configuration of the differential input circuit 220. For example, the input gain stage may be based on the transconductance of the transistors in the differential circuit 220. In some embodiments, the input gain stage in the amplifier 200 may be proportional to the transconductance of the NMOS transistors 222 and the PMOS transistors 224. The auxiliary gain stage may be based on the configuration of the amplifier circuits. For example, the auxiliary gain stage may be based on the transconductance and output resistance of the amplifier circuit 280. In some embodiments, the auxiliary gain stage in the amplifier circuit 280 may be based on the configuration of the first auxiliary stage 252 and the second auxiliary stage 262.The additional gain stage may be proportional to the transconductance of the first input substage 512, the first load substage 510, the second load substage 530, the second input substage 532, and the output resistance of the gain stages. In some embodiments, the overall gain of the gain circuit could be determined based on the gain of the first additional stage 252 (Avp, based on the transconductance of the first input substage 512) and the gain of the second additional stage (Avn, proportional to the transconductance of the second input substage 532). The gain in these stages then determines equivalent resistances of the first stage 250 (R250) and the second stage 260 (R260). In particular: R250=g_213−254B*r_254B(r_213 / r_222B)*Aυp, where (i) g_213-254B is the combined transconductance in the second bias PMOS transistor 213 and the second PMOS transistor 254B, (ii) r_254B is the output resistance for the second PMOS transistor 254B, (iii) r_213 is the output resistance of the second bias PMOS transistor 213, (iv) r_222B is the output resistance of the NMOS transistor 222B, and (v) Avp is the gain of the first auxiliary stage 252. Furthermore: R260=g233_264B*r_264B(r_233 / r_224B)*Aυn, where (i) g233-264B is the combined transconductance in the second bias NMOS transistor 223 and the second NMOS transistor 264B, (ii) r_264B is the output resistance for the second NMOS transistor 264B, (iii) r_233 is the output resistance of the second bias NMOS transistor 233, (iv) r_224B is the output resistance of the PMOS transistor 224B, and (v) Avn is the gain of the second boost stage 262.

[0101] The equivalent resistors R250 and R260 of the additional stages determine the overall gain of the amplifier circuit, defined as Aυ=(g_222+g_224)(R250 / R260), where (i) g_222 is the transconductance of NMOS transistors 222 and (ii) g_224 is the transconductance of PMOS transistors 224. Accordingly, at step 1012, the amplifier circuit may generate an output proportional to Av and the differential input signal. In some embodiments, the amplifier circuit generates an output that multiplies the input signal by Av to generate an output equal to Vout = Aυ*Vin.

[0102] In some embodiments, method 1000 may include a step of adjusting the operating mode. For example, at step 1014, dropout voltages in driver transistors may be reduced to adjust the power supply. At step 1008, the supply voltage is determined based on threshold voltages, overdrive voltages, and voltage drops. These voltages may be adjusted, for example, to reduce the supply voltage for low-current operations. Thus, at step 1014, the amplifier circuit may initiate a low-current application by reducing the supply voltage. For example, driver NMOS transistor 232 may be rebiased to have a lower voltage drop across driver NMOS transistor 232. Alternatively or additionally, step 1014 of method 1000 may include reducing the overdrive voltage to operate in a low-voltage application and increase an output swing.Accordingly, the method 1000 enables the adjustment of bias states and the selection of currents in the wide swing cascode current mirror to control and adjust the supply voltage for different operating modes.

[0103] The disclosed amplifiers, circuit configurations, and bias conditions improve amplifier operation and solve technical challenges in other designs. Furthermore, the disclosed configurations facilitate integrated circuit manufacturing by, for example, minimizing the required external bias voltages for the operational amplifiers.

[0104] For example, the disclosed amplifiers 200, 700, and / or 800 facilitate the operation and configuration of operational amplifiers by reducing the number of external bias voltages required to operate the circuit. The disclosed configuration of an amplifier with a positive bias circuit, a negative bias circuit, and an amplifier circuit (with multiple stages and a resistive element) overcomes drawbacks of conventional amplifiers. Conventional operational amplifiers (particularly folded cascode amplifiers) can use a large number of external bias voltages. Such a large number of external bias voltages presents performance and manufacturing challenges. For example, amplifiers with many external voltages require a larger manufacturing area and consume more power (which can lead to overheating problems).Furthermore, amplifiers with a large number of external voltages can suffer performance problems because they are more sensitive to noise and crosstalk, and exhibit high sensitivity to bias points and bias changes. The disclosed embodiments overcome this problem through a self-biasing configuration, where resistive elements self-bias transistors, resulting in fewer bias nodes than in alternative approaches. Furthermore, the disclosed embodiments enable self-biasing of transistors without degradation of AC performance or the need to increase the supply voltage.

[0105] In particular, the disclosed embodiments facilitate the self-biasing of transistors in the circuit using resistive elements that bias the auxiliary gain stages of the operational amplifiers. The disclosed embodiments utilize a resistive element (either active or passive) connected to auxiliary gain stages and driver transistors. This configuration facilitates the self-biasing of driver and auxiliary transistors. As discussed in connection with Fig.2, the resistive element (such as resistive element 270) can be selected and coupled between booster gain stages to place driver transistors in a subthreshold region. Operation in the subthreshold region of the driver transistors results in high DC gains without degrading AC performance and minimizes power consumption. The disclosed embodiments provide several advantages for both the operation and fabrication of operational amplifiers (and in particular, folded cascode amplifiers). For example, selecting a resistive element between booster stages allows certain transistors of amplifiers 200, 700, or 800 to be operated in the subthreshold region, thereby reducing power requirements.Furthermore, amplifiers of the disclosed embodiments achieve increased DC gain by operating in the sub-threshold region.

[0106] Furthermore, in addition to increased DC gain, the disclosed embodiments also provide other operational advantages. For example, the disclosed embodiments facilitate the fabrication of integrated circuits in smaller areas and with lower power consumption. Furthermore, the disclosed amplifier circuits also improve the stability of the amplifier as well as its noise sensitivity, since the disclosed self-biased configuration minimizes noise sources, whereas traditional folded cascode amplifiers have limited signal-to-noise ratios (SNR), partly due to the required bias conditions.

[0107] Thus, the disclosed embodiments and circuit configurations provide low-voltage, self-biased gain boost amplifiers. The use of resistive elements to self-bias transistors and operate them in the subthreshold region improves amplifier performance, reduces the number of external bias lines, minimizes potential noise, and improves power consumption characteristics.

[0108] Furthermore, the disclosed embodiments also have a wider operating range. By incorporating resistive elements for self-biasing and sub-threshold operation, the disclosed embodiments improve the dynamic range of the amplifier, allowing it to exhibit large gains at both low and high output voltages. Other amplifiers exhibit Gaussian gain, with peak gain at average output voltages, but little gain (or even attenuation) at low or high output voltages. Other amplifiers, for example, may exhibit peak gain at approximately VO = 350 mV, but low gain at low output voltages (e.g., VO = 100 mV) or high output voltages (e.g., VO = 650 mV).In contrast, the disclosed embodiments and amplifier configurations provide a better gain range with high gain at the extremes of the output voltage. For example, the disclosed embodiments achieve greater gains at low (e.g., VO = 100 mV) and high (e.g., VO = 650 mV) output voltages. Consistent with some of the disclosed configurations, the amplifiers achieve an additional gain of 20 dB - 30 dB at the edges of the output voltage range compared to other amplifiers.

[0109] Furthermore, the disclosed configurations can be adapted for different technologies. For example, disclosed embodiments of the amplifiers can be implemented in a wide variety of manufacturing processes, such as 3 nm, 5 nm, 7 nm, 10 nm, 16 nm, and 20 nm.

[0110] For at least these reasons, the advantages of the disclosed embodiments provide operational amplifiers with improved performance, simpler configuration, and / or easier manufacturing.

[0111] It should be understood that not all advantages have necessarily been discussed herein, that no particular advantage is required for all embodiments or examples, and that other embodiments or examples may provide different advantages.

Claims

[1] Amplifier circuit, comprising: a positive bias circuit (210) coupled to a power supply node (214) and comprising a driver PMOS, the driver PMOS configured to bias in a sub-threshold range; a negative bias circuit (230) coupled to a ground node (234) and comprising a driver NMOS, the driver NMOS being configured to bias in the sub-threshold range; and an amplification circuit (280) coupled to the positive bias circuit (210) and the negative bias circuit (230), the amplification circuit (280) comprising: a first stage (250) comprising PMOS transistors (422) and a first additional stage (252), one of the PMOS transistors (422) being coupled to the driver PMOS; a second stage (260) comprising NMOS transistors (426) and a second auxiliary stage (262), one of the NMOS transistors (426) being coupled to the driver NMOS; a resistive element (270) coupled between the first stage (250) and the second stage (260); and an output node (282) connected to the first stage (250) and the second stage (260), wherein: the resistance element (270) has: a PMOS transistor (422); a resistor (404); and an NMOS transistor (426); wherein the PMOS transistor (422) is connected in series with the resistor (404); and the resistor (404) is connected in series with the NMOS transistor (426). [2] The amplifier circuit of claim 1, wherein a gate of the driver PMOS is directly connected to a first terminal of the resistance element (270). [3] The amplifier circuit of claim 2, wherein a gate of the driver NMOS is directly connected to a second terminal of the resistive element (270), the second terminal being different from the first terminal. [4] Amplifier circuit according to one of the preceding claims, wherein the first additional stage (252) is directly connected to respective gates of the PMOS transistors (422). [5] An amplifier circuit according to any preceding claim, wherein the resistive element (270) comprises a triode mode transistor. [6] An amplifier circuit according to any preceding claim, wherein a value of the resistance element (270) is selected to set a gate voltage of the driver NMOS for operation in the sub-threshold region and to set a gate voltage of the driver PMOS for operation in the sub-threshold region. [7] The amplifier circuit of any preceding claim, further comprising a differential input circuit (220) coupled to the positive bias circuit (210) and the negative bias circuit (230), the differential input circuit (220) comprising two matching N-type input transistors and two matching P-type input transistors. [8] An amplifier circuit according to claim 7, arranged in an integrated circuit, wherein: the positive bias circuit (210) adjacent to the first additional stage (252) and the matching P-input transistors are arranged; the negative bias circuit (230) is arranged adjacent to the second auxiliary stage (262) and the matching N-input transistors; and the resistance element (270) is arranged next to the first additional stage (252) and the second additional stage (262). [9] Folded cascode operational amplifier, comprising: a positive bias circuit (210) coupled to a power supply node (214) and comprising a driver PMOS; a negative bias circuit (230) coupled to a ground node (234) and comprising a driver NMOS; a differential input circuit (220) coupled to the positive bias circuit (210) and the negative bias circuit (230); and an amplification circuit (280) coupled to the positive bias circuit (210) and the negative bias circuit (230), the amplification circuit (280) comprising: a first stage (250) coupled to the driver PMOS; a second stage (260) coupled to the driver NMOS; and a resistance element (270) coupled between the first stage (250) and the second stage (260), the resistance element (270) being directly connected to gates of the driver PMOS and the driver NMOS, wherein a value of the resistance element (270) is selected such that at least one of the MOS from the group comprising the driver PMOS and the driver NMOS is placed in a sub-threshold range, wherein the first stage (250) comprises a first input sub-stage (512), PMOS transistors (422), and a first charge sub-stage (510), the first input sub-stage (512) is connected to a drain / source node of each of the PMOS transistors (422), the first charge sub-stage (510) is connected to a gate node of each of the PMOS transistors (422), and the PMOS transistors (422) are connected to the driver PMOS. [10] A folded cascode operational amplifier according to claim 9, wherein the first charge sub-stage (510) comprises at least one element from the group comprising a resistor (404) and an inductor (644). [11] A folded cascode operational amplifier according to claim 9, wherein the first charge sub-stage (510) comprises at least one element selected from the group consisting of a MOS transistor and a MOS diode. [12] A folded cascode operational amplifier according to any one of claims 9 to 11, wherein the first input sub-stage (512) comprises two auxiliary transistors coupled to the power supply node (214). [13] A folded cascode operational amplifier according to any one of claims 9 to 12, wherein the second stage (260) comprises a second input sub-stage (532), NMOS transistors (426) and a second load sub-stage (530), the second input sub-stage (532) is connected to a drain / source node of each of the NMOS transistors (426), the second load sub-stage (530) is connected to a gate node of each of the NMOS transistors (426), and the NMOS transistors (426) are coupled to the driver NMOS. [14] A folded cascode operational amplifier according to claim 13, wherein: the second input sub-stage (532) comprises two auxiliary transistors coupled to the ground node (234); and the second charging sub-stage (530) comprises a PMOS transistor (422) coupled to the power supply node (214). [15] A folded cascode operational amplifier according to claim 13 or 14, wherein: a gate of the driver PMOS is directly connected to a first terminal of the resistance element (270); a gate of the driver NMOS is directly connected to a second terminal of the resistance element (270), the second terminal being different from the first terminal, where: the first terminal is directly connected to the second charging sub-stage (530); and the second terminal is directly connected to the first charging sub-stage (510). [16] A method of operating an amplifier circuit, comprising: Setting up a first transistor of the amplifier circuit for operation in a saturation region, the first transistor being directly connected to a driver PMOS transistor (212) connected to a power supply node (214); Setting up a second transistor of the amplifier circuit for operation in the saturation region, the second transistor being directly connected to a driver NMOS transistor (232) coupled to a ground node (234), wherein the PMOS transistor (422) is connected to the second transistor via a resistance element (270); Operating the amplifier circuit with a supply voltage proportional to a sum of a voltage drop of the driver PMOS transistor (212), a voltage drop across the resistance element (270), and a voltage drop across the driver NMOS, the supply voltage being at least twice the sum of a threshold voltage of the first transistor and an overdrive voltage of the first transistor; Inputting an input signal to a differential input circuit (220) of the amplifier circuit, wherein the differential input circuit comprises NMOS transistors and PMOS transistors (422); and Receiving an output signal at an output node (282) of the amplifier (200, 700), the output signal being the input signal multiplied by a gain of the amplifier circuit. [17] The method of claim 16, wherein: the operations further comprise initiating a low voltage application by decreasing the supply voltage to reduce the voltage drop of the driver NMOS, the low voltage application having an increased output swing; the supply voltage is equal to the sum of the voltage drop of the driver PMOS transistor (212), the voltage drop across the resistive element (270) and the voltage drop across the driver NMOS; the driver NMOS and the driver PMOS have the same current; and the first transistor is a PMOS transistor (422) and the second transistor is an NMOS transistor (426). [18] A method according to claim 16 or 17, wherein: the resistance element (270) comprises at least one of the elements from the group comprising a PMOS transistor (422), a resistor (404) and an NMOS transistor (426); the gain at the output of the amplifier circuit is proportional to a transconductance of the differential input stage and a transconductance of an amplification circuit (280) within the amplifier circuit.

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