Electronic system having an intermetallic interconnect structure with a central intermetallic network structure and network-free outer structures, and method for producing an electronic system

Abstract

An electronic system (100), the electronic system (100) comprising: • an at least partially electrically conductive carrier (102); • an electronic component (104); and • an intermetallic interconnect structure (106) connecting the carrier (102) and the component (104) and comprising: ◯ a soldering matrix (122); ◯ an intermetallic network structure (108) in a central portion of the intermetallic interconnection structure (106), which intermetallic network structure (108) forms a branched network of interconnected multi-metal particles of silver and copper, embedded in the solder matrix (122); and ◯ opposite outer structures (110, 112) without intermetallic network and each arranged between the intermetallic network structure (108) on the one hand and the carrier (102) or the component (104) on the other hand.

Description

BackgroundTechnical area

[0001] Various embodiments generally relate to an electronic system and a method of manufacturing an electronic system. Description of the state of the art

[0002] A conventional electronic system may include an electronic component soldered to a chip carrier, for example, a lead frame, and may optionally be encapsulated using a molding component, such as an encapsulant.

[0003] WO 2018 / 193760 A1 discloses a semiconductor device having an assembly structure in which a semiconductor element is mounted on a laminated substrate. A bonding layer connects the semiconductor element and an electrode pattern on the laminated substrate. The bonding layer comprises a solder material containing metal fibers, with the gaps between the metal fibers filled with solder material.

[0004] DE 10 2015 114 874 A1 discloses a solder preform structure for soldering a semiconductor chip assembly. The solder preform structure comprises a composite layer of carbon fibers and a solder layer formed over the composite layer of carbon fibers.

[0005] DE 11 2015 003 845 T5 discloses a bonding structure that connects a Cu wiring line and a component electrode. The bonding structure comprises an intermediate layer formed between a first intermetallic compound layer and a second intermetallic compound layer. The intermediate layer comprises a network-like intermetallic compound of copper and tin.

[0006] US 2006 / 0 061 974 A1 discloses a solder layer for attaching an electronic chip to a carrier. The solder layer can comprise a network of copper metal fibers, which are arranged between tin-coated copper beads and then pressed. Summary

[0007] There may be a need to connect an electronic component to a conductive carrier in an electronic system with high reliability.

[0008] According to an exemplary embodiment, an electronic system is provided which comprises an at least partially electrically conductive carrier, an electronic component, and an intermetallic interconnection structure which connects the carrier and the component and a solder matrix, an intermetallic network structure in a central portion of the intermetallic interconnection structure, which intermetallic network structure forms a branched network of connected multimetal particles of silver and copper, embedded in the solder matrix, and opposing outer structures without an intermetallic network and each arranged between the intermetallic network structure on the one hand and the carrier or the component on the other hand.

[0009] According to another exemplary embodiment, a method for producing an electronic system is provided, the method comprising connecting an at least partially electrically conductive carrier to an electronic component by means of an intermetallic interconnection structure, and forming the intermetallic interconnection structure with a solder matrix, an intermetallic network structure in a central portion of the intermetallic interconnection structure, which intermetallic network structure forms a branched network of connected multimetal particles of silver and copper, embedded in the solder matrix and opposite outer structures without an intermetallic network and each arranged between the intermetallic network structure on the one hand and the carrier or the component on the other hand.

[0010] According to an exemplary embodiment, an electrically conductive carrier (e.g., a lead frame) and an electronic component (e.g., a semiconductor die) in an electronic system (e.g., a package or a module) are connected to each other by means of an intermetallic interconnect structure (in particular, by soldering). Advantageously, the intermetallic interconnect structure may comprise a central intermetallic network structure—in which different metals form a continuous network—and may comprise peripheral or outer structures that do not have a continuous network in the form of an intermetallic network.Illustratively, the intermetallic network structure can form a mechanically strong, highly temperature-stable backbone that maintains the integrity of the solder-like intermetallic interconnect structure, thereby preventing delamination inside the electronic system. A first outer structure without an intermetallic network can be arranged between the intermetallic network structure and the carrier, whereas a second outer structure without an intermetallic network can be arranged between the intermetallic network structure and the component. Advantageously, the intermetallic network can form a highly reliable mechanical and / or electrical connection between the carrier and the component, capable of withstanding high thermal and mechanical stress without the risk of cracking or separation.Undesired remelting of the intermetallic compound structure in the event of a subsequent temperature increase can be reliably prevented. Advantageously, a top-to-bottom connection between the component and the carrier can be achieved, which significantly improves the reliability of the resulting electronic system compared to conventional connection structures. Illustratively, the external structures can be a fingerprint of the metallic structures on and between the carrier and the component prior to the connection and can advantageously smooth the transition between the carrier and the component. This can prevent an abrupt material interface between the intermetallic network on the one hand and the carrier and the component on the other. Description of further exemplary embodiments

[0011] Further exemplary embodiments of the method and the electronic system are explained below.

[0012] In the context of the present application, the term "electronic system" may, in particular, refer to an electronic device comprising one or more electronic components, optionally using an encapsulation. Furthermore, a carrier for the electronic component(s) may be implemented in an electronic system. For example, such an electronic system may be a module or a package.

[0013] In the context of the present application, the term "electronic component" may, in particular, encompass a semiconductor chip (in particular a power semiconductor chip), an active electronic device (for example, a transistor), a passive electronic device (for example, a capacitance, an inductance, or an ohmic resistance), a sensor (for example, a microphone, a light sensor, or a gas sensor), an actuator (for example, a loudspeaker), and a microelectromechanical system (MEMS). However, in other embodiments, the electronic component may also be of a different type, for example, a mechatronic element, in particular a mechanical switch, etc.

[0014] In the context of the present application, the term “intermetallic compound structure” may in particular refer to a medium which reliably connects the component and the carrier and has a plurality of different metallic components.

[0015] In the context of the present application, the term "intermetallic network" may specifically refer to a network of metallic structures made of different metallic materials in a metallic matrix, wherein the network forms a continuous connection between opposing metallic outer structures (the latter being provided without such a network). An intermetallic network may comprise fibers or filaments composed of interconnected metallic particles made of different metallic materials. For example, such fibers or filaments may be fused or bonded.

[0016] In the context of the present application, the term "external structures without an intermetallic network" can, in particular, refer to a metallic structure that connects an intermetallic network structure to an electronic component or to a conductive carrier and that is free of a continuous network of different metals. The external structures can be intermetallic structures, but no continuous network of different metallic components is formed in the external structures, creating a continuous vertical connection. The external structures can also comprise different metallic materials, which, however, do not create a continuous vertical connection in the form of a mesh or network.In contrast, the outer structures may comprise a matrix metal in which individual metallic islands and / or short intermetallic fragments may be embedded, which do not form a continuous vertical connection through the matrix metal. The outer structures without an intermetallic network may also provide a mechanical and / or electrically conductive connection without a continuous vertical intermetallic network and may be a fingerprint of a manufacturing process, for example, the manufacturing process according to . Fig. 1 to Fig. 8.

[0017] In one embodiment, the carrier has a leadframe structure (e.g., made of copper). Thus, the carrier can be embodied as a structured metal plate and thus in a simple and easily processable manner.

[0018] However, the carrier may alternatively be embodied in another way, for example, as a central electrically insulating and thermally conductive layer (e.g., made of ceramic) covered on one or both opposing major surfaces thereof with an electrically conductive layer (e.g., a copper or aluminum layer). For example, a carrier may be embodied as a DAB (Direct Aluminum Bonding), DCB (Direct Copper Bonding) substrate, etc. Furthermore, the carrier may also be configured as an Active Metal Brazing (AMB) substrate.

[0019] In one embodiment, the carrier comprises an electrically conductive main body (e.g., made of copper or aluminum) partially covered by a metallic diffusion barrier. For example, a surface of the main body or a portion thereof may be covered with a metallic diffusion layer of nickel. This may suppress excessive diffusion of material from the main body into the intermetallic compound structure.

[0020] In one embodiment, the component comprises a semiconductor body covered with a backside metallization, wherein the backside metallization is connected to the intermetallic interconnect structure. For example, the semiconductor body may be made of silicon. At least one monolithically integrated circuit element may be formed in the semiconductor body, for example, a transistor structure and / or a diode structure. For example, an active surface of the semiconductor body, in which at least one integrated circuit element is monolithically integrated, may be opposite another surface of the semiconductor body, on which a backside metallization is applied.

[0021] In one embodiment, the intermetallic interconnect structure comprises a solder matrix for creating a solder connection between the component and the carrier. For example, the solder matrix may be made of a solderable material (e.g., tin) that has a melting temperature below a melting temperature of any other metallic element of the intermetallic network structure. During a reflow process, only the solder matrix material may selectively melt or become liquid or flowable, whereas various metallic materials of the intermetallic network structure that may be formed during such a reflow process remain solid particles and may therefore dissolve in the flowable solder matrix.This provides an excellent basis for the formation of the intermetallic network structure - with a high melting point - in the solder matrix - with a lower melting point - resulting in an intermetallic compound structure that is reliably protected against unwanted remelting after its formation.

[0022] In one embodiment, the solder matrix comprises tin. Other solderable materials are also possible.

[0023] In one embodiment, the intermetallic compound structure comprises intermetallic phase promoter particles (which may be macroscopic or microscopic particles or even atomic-level particles) of at least one intermetallic phase promoter metal to promote the formation of an intermetallic phase in the intermetallic compound structure. Such intermetallic phase promoter particles may promote the formation of the intermetallic network structure and may be included in a solder paste applied between the carrier and the electronic component during fabrication of the electronic system. For example, the at least one intermetallic phase promoter metal comprises silver and / or copper.Such materials may have a higher melting point compared to a solder matrix (e.g., tin) of the intermetallic compound structure, and may be capable of forming an intermetallic phase with other metals in a flowable solder medium.

[0024] In one embodiment, the intermetallic interconnect structure comprises intermetallic phase accelerator particles made of at least one intermetallic phase accelerator metal for accelerating the formation of the intermetallic network structure. The intermetallic phase accelerator particles may be provided by means of a dedicated layer provided on top of the carrier and / or may be provided in the form of particles embedded in a solder matrix of a solder paste applied between the carrier and the component during the manufacture of the electronic system. Such an intermetallic phase accelerator material may drive, trigger, or even catalyze the formation of an intermetallic network structure in a temporarily flowable solder matrix and may contribute to the formation of an intermetallic layer that interconnects the chip and the carrier surface.For example, the at least one phase-accelerating intermetallic metal may comprise palladium, gold, platinum, and / or zinc. However, an intermetallic phase-accelerating metal may also be a metal from a wafer backside (i.e., a backside metallization of the electronic component), for example, vanadium.

[0025] In one embodiment, the intermetallic compound structure is free of lead (Pb). This can advantageously prevent biohazardous properties of the intermetallic compound structure. Consequently, an environmentally friendly electronic system can be formed by avoiding lead in the intermetallic compound structure.

[0026] In one embodiment, a vertical thickness of the intermetallic interconnect structure is in a range from 5 µm to 50 µm, in particular in a range from 10 µm to 30 µm, more particularly in a range from 10 µm to 20 µm. Advantageously, the described intermetallic interconnect structure or bond line can be provided with a very small thickness. This keeps the electronic system compact in a vertical direction and ensures high mechanical, thermal, and electrical reliability of the electronic system.

[0027] In one embodiment, the electronic system comprises an intermetallic phase-acceleration layer composed of at least one intermetallic phase-acceleration metal for accelerating the formation of the intermetallic network structure, which layer is arranged between the carrier and the intermetallic interconnect structure. During manufacturing, the intermetallic phase-acceleration layer can act as a reservoir for intermetallic phase-acceleration particles that dissolve in a temporarily flowable solder matrix. Together with the intermetallic phase-promoter particles in the solder matrix, the intermetallic phase-acceleration particles are components of the high-melting-point intermetallic network structure formed in the solder matrix with a lower melting point of the intermetallic interconnect structure.

[0028] In one embodiment, the intermetallic phase acceleration layer is a single layer (see, for example, Fig. 2) or a double layer (see for example Fig. 3). A single layer can be formed with little effort, whereas a double layer allows for fine-tuning of the properties of the intermetallic phase-accelerating layer.

[0029] In one embodiment, a partial vertical thickness of the intermetallic network structure relative to the total intermetallic phase structure is at least 80%, particularly at least 90%. Thus, the vast majority of the vertical thickness of the intermetallic phase structure can be contributed by the intermetallic network structure. Thus, the reinforcing and anti-reflow function of the intermetallic network or network can be provided over a significant portion of the total intermetallic compound structure.

[0030] In one embodiment, the intermetallic network structure forms a branched network of interconnected multimetal particles that extends continuously across a total vertical distance between the outer structures. Thus, the intermetallic network structure can be composed of a plurality of interconnected filaments or fibers, each formed from a sequence of directly interconnected metallic particles of at least two different metallic chemical elements, preferably of at least three different metallic chemical elements, for example, of three, four, or five different metallic chemical elements.The various intermetallic filaments or fibers of the intermetallic network structure may have one or more fusion and / or crossing points and may cover an entire vertical area between the two opposite outer structures of the intermetallic interconnection structure.

[0031] In one embodiment, a weight percent of the intermetallic network structure relative to the total intermetallic interconnect structure is in a range from 1 weight percent to 30 weight percent, in particular in a range from 3 weight percent to 8 weight percent, further in particular in a range from 4.5 weight percent to 6.5 weight percent. Preferably, a relatively small partial weight is contributed by the intermetallic network structure. This can ensure good flowability of the intermetallic interconnect structure during reflow soldering (due to the solder matrix), while simultaneously ensuring that no reflow can occur after completion of the soldering process. Relatively smooth properties of the solder matrix, which can have the highest material contribution in the intermetallic interconnect structure, can also act as a mechanical buffer in the electronic system.

[0032] In one embodiment, the method comprises forming the intermetallic compound structure by applying a solder paste to the carrier, wherein the solder paste comprises a solder matrix for creating a solder connection between the component and the carrier, and intermetallic phase promoter particles made of at least one intermetallic phase promoter metal for promoting the formation of an intermetallic phase in the intermetallic compound structure. Optionally, it may also be possible to add intermetallic phase accelerator particles to the solder matrix. Additionally or alternatively, an intermetallic phase accelerator material may be provided in the form of a plating layer on the carrier beneath the solder paste.Thus, the method may comprise covering the carrier with an intermetallic phase-accelerating layer to accelerate the formation of the intermetallic network structure, and disposing the intermetallic phase-accelerating layer between the carrier and the solder paste. Additionally or alternatively, the method may comprise providing the solder paste with intermetallic phase-accelerating particles to accelerate the formation of the intermetallic network structure.

[0033] In one embodiment, the method comprises providing the solder paste with intermetallic particles having a diameter in a range of 5 µm to 50 µm, particularly in a range of 10 µm to 20 µm. This minimizes the thickness of a bond line formed during the soldering process.

[0034] In one embodiment, the method comprises pressing the solder paste between the carrier and the component. Advantageously, such a pressing process can apply sufficient mechanical pressure to the solder paste to form a monolayer of intermetallic solder paste particles between the carrier and the component. In other words, after this pressing process, only individual solder paste particles connect the carrier and the component. This ensures a small bond line or thickness of the produced intermetallic interconnect structure.

[0035] In one embodiment, the method comprises forming the intermetallic compound structure by heating precursors of the intermetallic compound structure (in particular, a solder paste comprising a solder matrix and intermetallic phase promoter particles and optionally intermetallic phase accelerator particles, or one or more intermetallic phase accelerator layers beneath the solder paste) to a peak temperature above a melting temperature of a solder material precursor (i.e., the solder matrix) and below a melting temperature of the intermetallic network precursors (i.e., the intermetallic phase promoter and accelerator particles and / or layer(s)). This heating process renders the solder matrix flowable, whereas the intermetallic phase promoter and accelerator particles and / or layer(s) remain in a solid state and can be dissolved in the flowable solder matrix.The formation of this mixture, in combination with a suitable temperature profile, triggers the formation of the intermetallic network structure in a solder matrix. After the solder matrix has resolidified, the intermetallic compound structure as a whole is reliably protected from unwanted remelting, as this can be suppressed by the intermetallic network structure.

[0036] In one embodiment, the method comprises maintaining the peak temperature for a time interval of at least 1 minute, in particular for a time interval in a range of 1 minute to 4 minutes, more particularly for a time interval in a range of 1.5 minutes to 2 minutes. In a highly advantageous manner, the described mixture can be maintained in a partially flowable state for a relatively long time interval. This can give the mixture sufficient time to form an intermetallic network structure extending along the entire vertical distance between the two opposing outer structures without an intermetallic network.

[0037] In one embodiment, the peak temperature is in a range of 260°C to 350°C, particularly in a range of 280°C to 300°C. For comparison, the melting temperature of the brazing material precursor may be below 240°C. Furthermore, the melting temperature of the intermetallic network precursors may be at least 370°C. As a result of this processing, the brazing matrix selectively becomes flowable, whereas the metallic particles forming the intermetallic network structure are not melted during brazing.

[0038] In one embodiment, the method comprises forming the intermetallic interconnect structure by reflow soldering. Reflow soldering may refer to a process in which a solder paste (in particular, an adhesive mixture of solderable particles and flux, additionally enriched with precursors for forming the intermetallic network structure) is used to temporarily attach one or more electronic components to the carrier, after which the entire assembly is subjected to controlled heat. The solder paste, but not the precursors for forming the intermetallic network structure, melts back to a molten state, thereby creating permanent solder connections. The heating may be accomplished, for example, by passing the assembly through a reflow oven, for example, under an infrared lamp.

[0039] In one embodiment, the mesh structure and the outer structures comprise the same intermetallic materials. Although the concentrations of the various intermetallic materials in the mesh structure and in the two opposite outer structures may be different, the source of the various metals in the mesh structure and in the outer structures may be the same as a result of the described manufacturing process. For example, a lower outer structure may comprise one or more metallic materials of an intermetallic phase acceleration layer sandwiched between the carrier and the solder matrix, and particles of the solder matrix. For example, an upper outer structure may comprise a metallic material of a backside metallization layer sandwiched between the semiconductor body of the electronic component and the solder matrix, and particles of the solder matrix.The intermetallic network structure may comprise particles of the solder matrix, one or more metallic materials of an intermetallic phase accelerating layer sandwiched between the carrier and the solder matrix, one or more metallic materials of intermetallic phase promoter particles, and particles of a backside metallization layer sandwiched between the semiconductor body of the electronic component and the solder matrix.

[0040] In one embodiment, the electronic system comprises an encapsulation which at least partially encapsulates at least one of the at least one electronic component, the carrier, and the intermetallic compound structure. In the context of the present application, the term "encapsulation" can in particular refer to a substantially electrically insulating and preferably thermally conductive material which surrounds at least part of a component and at least part of a carrier, as well as part of the intermetallic compound structure. For example, the encapsulation can be a molding compound and can be produced, for example, by means of transfer molding. Alternatively, the encapsulation can be a potting compound which is formed by means of casting.

[0041] In one embodiment, at least one of the at least one electronic component is an unpackaged die. By embodying the at least one electronic component as an unencapsulated chip, i.e., a pure semiconductor chip without additional dielectric encapsulation, the compactness of the electronic system can be further increased.

[0042] In one embodiment, the electronic system comprises a plurality of (particularly electronic) components mounted on the carrier or on different carriers. Thus, the electronic system may comprise one or more electronic components (e.g., at least one passive component, e.g., a capacitor, and at least one active component, e.g., a semiconductor chip).

[0043] In one embodiment, the electronic device comprises a submount (e.g., a printed circuit board, PCB) on which the carrier-electronic component assembly is mounted, and which is electrically coupled to the electronic component and / or the carrier. Such a submount may be an electronic board that serves as a mechanical base for the electronic system, embodied, for example, as a package.

[0044] In one embodiment, the electronic system is configured as one of the group consisting of a leadframe-connected power module, a transistor outline (TO) electronic system, a quad flat no leads (QFN) electronic system, a small outline (SO) electronic system, a small outline transistor (SOT) electronic system, and a thin small outline (TSOP) electronic system. Electronic systems for sensors and / or mechatronic devices are also possible embodiments. Furthermore, example embodiments may also relate to electronic systems that act as nanobatteries or nanofuel cells or other devices with chemical, mechanical, optical, and / or magnetic actuators.Therefore, according to an exemplary embodiment, the electronic system is fully compatible with standard packaging concepts (in particular, fully compatible with standard TO packaging concepts).

[0045] In one embodiment, the electronic system is configured as a power module, for example, an overmolded power module. For example, an exemplary embodiment of the electronic system may be an intelligent power module (IPM). Another exemplary embodiment of the electronic system is a dual inline electronic system (DIP).

[0046] In one embodiment, the electronic component is configured as a power semiconductor chip. Thus, the electronic component (e.g., a semiconductor chip) can be used for power applications, for example, in the automotive field, and can, for example, have at least one integrated insulated gate bipolar transistor (IGBT) and / or at least one transistor of another type (e.g., a MOSFET, a JFET, etc.) and / or at least one integrated diode. Such integrated circuit elements can, for example, be manufactured using silicon technology or based on wide-gap semiconductors (e.g., silicon carbide). A semiconductor power chip can include one or more field-effect transistors, diodes, inverter circuits, half-bridges, full-bridges, drivers, logic circuits, other devices, etc.

[0047] A semiconductor substrate, in particular a silicon substrate, can be used as the substrate or wafer that forms the basis of the electronic components. Alternatively, a silicon oxide or other insulating substrate can be provided. It is also possible to implement a germanium substrate or a III-V semiconductor material. For example, exemplary embodiments can be implemented using GaN or SiC technology.

[0048] Furthermore, exemplary embodiments may use standard semiconductor processing technologies, for example, suitable etching technologies (including isotropic and anisotropic etching technologies, in particular plasma etching, dry etching, wet etching), patterning technologies (which may involve lithographic masks), deposition technologies (for example, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), sputtering, etc.).

[0049] The above and other objects, features and advantages will be apparent from the following description and the appended claims, taken in conjunction with the accompanying drawings in which like parts or elements are designated by like reference numerals. Short description of the drawings

[0050] The accompanying drawings, which are included to provide a further understanding of example embodiments and constitute a part of the specification, illustrate example embodiments.

[0051] In the drawings: Fig. 1 shows a schematic cross-sectional view of an electronic system according to an exemplary embodiment and a cross-sectional view of a manufactured electronic system according to an exemplary embodiment. Fig. 2 to Fig.8 are cross-sectional views of structures obtained during the manufacture of an electronic system such as that shown in Fig. 1, according to an exemplary embodiment. Fig. 9 shows a cross-sectional view of an electronic system according to another exemplary embodiment. Fig. 10 shows a cross-sectional view of an electronic system according to yet another exemplary embodiment. Fig. 11 to Fig. 13 are cross-sectional views of structures obtained during fabrication of an electronic system according to yet another exemplary embodiment. Fig. 14 is a phase diagram showing properties of various intermetallic phases produced by mixing silver, gold, and tin, and is used to explain a principle of an exemplary embodiment. Fig. 15 is a diagram illustrating a reflow soldering process performed during fabrication of an electronic system according to an exemplary embodiment. Fig. 16 and Fig. 17 show a method of manufacturing an electronic system according to an exemplary embodiment. Fig. 18 shows a cross-sectional view of an electronic system according to yet another exemplary embodiment. Detailed description

[0052] The representation in the drawing is schematic and not to scale.

[0053] Before exemplary embodiments are described in more detail with reference to the figures, some general considerations are summarized based on which exemplary embodiments were developed.

[0054] According to exemplary embodiments, an electronic system can be provided with an interconnect material in the form of an intermetallic interconnect structure between an electronic component (e.g., a die with a backside metallization) and a conductive carrier (e.g., a lead frame) with excellent interconnect properties. The intermetallic interconnect structure can be formed with an intermetallic mesh in the center (preferably embedded in a matrix of a solder material with a lower melting temperature than the intermetallic mesh) and layers without a mesh at the top and bottom boundaries (i.e., facing the component and the carrier, respectively). This can make it possible to obtain a non-reflowing reinforced solder structure that reliably connects the component and the carrier and is stable even up to high temperatures.Since the said intermetallic compound structure can be formed without lead (Pb) material, the compound can be achieved without biohazardous properties and without problems related to pollution.

[0055] Thus, an exemplary embodiment provides a non-reflow lead-free solder structure in the form of the intermetallic compound structure. Thus, an exemplary embodiment provides a method that enables the production of a simple lead-free solder material with a low melting point that advantageously has non-reflow properties due to the formation of an intermetallic network. More specifically, an exemplary embodiment provides a simple lead-free solder structure having a vertically connected intermetallic compound mesh that withstands even a high reflow temperature without reflow. It is believed that this property can be achieved and promoted in particular by means of the intermetallic network extending across a bond line.Advantageously, such a solder bond line can remain intact during reflow, even with partial or localized reflow. Such an intermetallic interconnect structure can be formed using dopants, which can be provided by coating on a carrier in a soldering system. Advantageously, small solder balls can be used to bring the bond line downward after die bonding, thereby enhancing the formation of a vertical intermetallic network. Thus, a lead-free solder replacement without undesirable reflow characteristics can be obtained.

[0056] A core idea of ​​an exemplary embodiment is thus to provide an interconnect system that enables a simple lead-free solder material with a low melting point that does not reflow after reflow due to the creation of an intermetallic interconnect network. Thus, an intermetallic interconnect network can be formed in an intermetallic interconnect structure above a bond line that can withstand a reflow temperature without reflow, thereby improving the reliability of the resulting electronic system. In particular, a corresponding intermetallic interconnect structure can be capable of keeping the solder bond line intact during reflow, even with partial or spatially limited reflow.

[0057] To create such an intermetallic interconnect structure, it may be possible to provide a thin solder paste for a low bond line prior to a reflow process. Therefore, such a low bond line can be created prior to a reflow process, with a bond line thickness of no more than 40 µm (for example, a Type 5 solder paste can be used for this purpose, where a nominal solder ball size can range from 20 µm to 25 µm).

[0058] Furthermore, one or more dopants may be provided in the form of one or more carrier plating layers: such a dopant system may comprise (i) one or more elements with a high solubility (in particular a high dispersion) in solder materials (for example, gold (Au), palladium (Pd), etc.), which contribute to forming a uniform intermetallic composite network across a bond line, and (ii) one or more elements which increase solder joint reliability (for example, zinc (Zn), nickel (Ni), etc.).

[0059] Regarding a reflow profile applied during the fabrication of an electronic system according to an exemplary embodiment, a maximum peak temperature may be in the range of a glass transition temperature (Tg, which may typically be in a range of 260°C to 350°C to manage warpage) of an organic carrier, and a liquidus duration (which may be in a range of 1 min to 2 min) is sufficient for formation of an intermetallic composite network. As a result, a vertically connected intermetallic composite network with a network of different metals may be formed, which may also be referred to as an intermetallic network structure in an intermetallic interconnect structure. At an upper and a lower periphery of the intermetallic interconnect structure, a respective outer structure without the intermetallic network may be formed.

[0060] More specifically, the intermetallic network structure (or network intermetallic composite) may have a complex mixture of different intermetallic composite species, for example: (i) Ag3Sn; (ii) Cu3Sn; and / or (iii) Pd and Au intermetallic network composite species in the low ppm range.

[0061] When such an intermetallic network is formed, the copper content in the bulk solder material may become very low. This may indicate the pulling of elements to form the intermetallic network.

[0062] In one embodiment, a bulk solder material—which may also form a matrix of the intermetallic compound structure—may be primarily tin (Sn). At the same time, the Sn content may be high in both the network intermetallic compound and the bulk solder material. This may indicate Sn capture for the formation of the intermetallic compound, leaving a lower content of free Sn, which may be a common cause of reflow in a general solder joint.

[0063] According to exemplary embodiments, additional metallic dopants (e.g., nickel and / or palladium) may assist with intermetallic network formation. Printing or dispensing a thin solder material may be sufficient to cover a die area.

[0064] Advantageously, a bond line thickness before a reflow process can be in a range of 25 µm to 50 µm, and after the reflow process in a range of 10 µm to 30 µm.

[0065] Fig. 1 shows a schematic cross-sectional view of an electronic system 100 according to an exemplary embodiment and a cross-sectional view of a manufactured electronic system 100 according to an exemplary embodiment. On the left side of Fig. 1 shows an experimentally fabricated electronic system 100, whereas the right side of Fig. 1 shows a schematic representation of such an electronic system 100. The electronic system 100 may be configured as a semiconductor package or module.

[0066] On its underside, the electronic system 100 may have an electrically conductive carrier 102, for example, a lead frame (for example, a structured copper plate). More specifically, the carrier 102 has an electrically conductive main body 114, which may be made of copper, for example, and which may be covered with a metallic diffusion barrier 116, for example, a layer of nickel. Clearly, the metallic diffusion barrier 116 inhibits or even prevents the diffusion of a metallic material of the main body 114 into an intermetallic phase acceleration layer 128 described below.

[0067] Furthermore, an electronic component 104, which may be embodied as a semiconductor die, may form an upper portion of the electronic system 100. In the illustrated embodiment, the component 104 comprises a semiconductor body 118 (which is made of silicon, for example, and has at least one monolithic integrated circuit element therein, not shown). The semiconductor body 118 is covered with a backside metallization 120, for example, a layer of copper, which is connected to an intermetallic interconnect structure 106.

[0068] As also in Fig.1, the electrically conductive solder-like intermetallic interconnect structure 106 is arranged vertically between the carrier 102 and the component 104 for mechanically and electrically connecting the carrier 102 and the component 104. The intermetallic interconnect structure 106 has an intermetallic network structure 108 in a central portion of the intermetallic interconnect structure 106. The intermetallic network structure 108 can be considered a network of various metallic particles that form continuous electrically conductive paths in the vertical direction and that are embedded in a metallic matrix of another metallic material. As also shown in Fig.1, a lower outer structure 110 is disposed vertically between the carrier 102 and the intermetallic network structure 108. Furthermore, an upper outer structure 112 is disposed vertically between the intermetallic network structure 108 and the component 104. More specifically, the upper outer structure 112 is disposed directly between the intermetallic network structure 108 at a bottom side and the pure backside metallization 120 (made of a homogeneous material) at a top side. As a result of the manufacturing process described below, the network structure 108 and the outer structures 110, 112 comprise the same intermetallic materials (tin, palladium, gold, silver, nickel, and copper in the embodiment shown), albeit at different concentrations along the vertical thickness of the intermetallic interconnect structure 106.

[0069] Advantageously, the intermetallic compound structure 106 comprises a solder matrix 122, which may be provided on a tin basis, for creating a solder connection between the component 104 and the carrier 102. The solder matrix 122 may have a relatively low melting temperature. In addition, the intermetallic compound structure 106 comprises intermetallic phase promoter particles 124 made of one or more intermetallic phase promoter metals, which are configured to promote the formation of an intermetallic phase in the intermetallic compound structure 106. For example, silver and / or copper may be used as the intermetallic phase promoter metal(s). Illustratively, the intermetallic phase promoter particles 124 may be incorporated into a solder paste (see reference numeral 130 in Fig.4) which is used as a base for fabricating the intermetallic interconnect structure 106, and may contribute to the formation of the intermetallic network, together with the particles of the intermetallic phase acceleration layer 128 thereunder.

[0070] As also in Fig.1, the intermetallic interconnect structure 106 may include intermetallic phase accelerator particles 126 made of one or more intermetallic phase accelerator metals for accelerating the formation of the intermetallic network structure 108. One or more such intermetallic phase accelerator metals may include palladium, gold, platinum, and / or zinc. As a source of the intermetallic phase accelerator particles 126, the electronic system 100 includes an intermetallic phase accelerator layer 128 (made of at least one of the aforementioned intermetallic phase accelerator metals) for accelerating the formation of the intermetallic network structure 108, disposed between the carrier 102 and the intermetallic interconnect structure 106.As shown, the intermetallic phase acceleration layer 128 may be a single layer of a homogeneous material disposed directly beneath the lower outer structure 110. The intermetallic phase acceleration layer 128, which may also be referred to as a dopant layer or protective layer, may comprise one or more materials (e.g., palladium, gold, zinc, etc.) that have a higher melting point than the material of the solder matrix 122 (particularly tin) and act as a seed or accelerator for the formation of the vertically connecting intermetallic network structure 108. The high melting point of the material of the intermetallic phase acceleration layer 128 advantageously suppresses reflow of the intermetallic network structure 108 after its formation, even at high reflow temperatures.

[0071] Advantageously, the intermetallic interconnect structure 106 may be lead-free. This makes the materials of the intermetallic interconnect structure 106 biocompatible and prevents any highly undesirable biohazardous properties of the electronic system 100.

[0072] Still referring to Fig. 1, a vertical thickness D of the intermetallic interconnect structure 106 may preferably be in a range from 10 µm to 20 µm, for example, may be 15 µm. Furthermore, a partial vertical thickness of the intermetallic network structure 108 divided by the vertical thickness D of the entire intermetallic interconnect structure 106 may be, for example, at least 80%, preferably at least 90%. For example, the partial vertical thickness may be in a range from 8 µm to 16 µm, for example, may be 12 µm.

[0073] As in Fig.1, the intermetallic network structure 108 forms a branched network of interconnected multi-metal particles that extend continuously between an entire vertical distance between the outer structures 110, 112. Although the intermetallic network structure 108 does not extend completely straight between the outer structures 110, 112, it provides an uninterrupted, continuous electrically conductive intermetallic connection between the outer structures 110, 112. The intermetallic network structure 108 is embedded in the solder matrix 122 and may be composed of a plurality of different metals, in particular of at least three different metals. The intermetallic network structure 108 may be formed from directly interconnected metallic particles of different chemical elements.In a highly advantageous manner, the presence of the intermetallic network structure 108 in the solder matrix 122 prevents undesired remelting of the intermetallic compound structure 106 as a whole, despite the relatively low melting temperature of the tin material of the solder matrix 122. Advantageously, this can already be achieved by means of a relatively low weight percentage of the partial weight of the intermetallic network structure 108 relative to the weight of the entire intermetallic compound structure 106. For example, the weight percentage can be in a range from 4.5 weight percent to 6.5 weight percent.

[0074] Advantageously, the described intermetallic interconnect structure can provide a reliable mechanical and electrical connection between the carrier 102 and the component 104, which is readily solderable due to the provision of the solder matrix 122, and which, at the same time, is reliably protected from reflow (particularly at typical reflow temperatures) due to the formation of the intermetallic network structure 108. In a synergistic manner, the opposing outer structures 110, 112 ensure a smooth material transition between the intermetallic network structure 108, which is embedded in the solder matrix 122, on the one hand, and the intermetallic phase acceleration layer 128 and the backside metallization 120, on the other. The intermetallic interconnect structure 106 exhibits high mechanical and thermal robustness and therefore leads to greater reliability of the manufactured electronic system 100.Its material composition poses no harm to the user, nor is there a risk of remelting during reflow. Consequently, the electronic system 100 provides high thermal, mechanical, and electrical performance.

[0075] Fig. 2 to Fig. 8 are cross-sectional views of structures obtained during the manufacture of an electronic system 100 such as that shown in Fig. 1, according to an exemplary embodiment.

[0076] Referring to Fig.2 shows a carrier 102 covered with an intermetallic phase acceleration layer 128 for later accelerating the formation of the intermetallic network structure 108. As described above, the carrier 102 may be formed from a base or main body 114 made of copper, which is covered with a metallic diffusion barrier 116 made of nickel. The metallic diffusion barrier 116 may prevent diffusion of material of the main body 114 in an upward direction. The intermetallic phase acceleration layer 128 may be a plated dopant layer, which may be made of palladium and gold. For example, a thickness b of the intermetallic phase acceleration layer 128 may be in a range from 0.05 µm to 1 µm, for example, 0.1 µm. Thus, the intermetallic phase acceleration layer 128 is according to Fig.2 a single layer. More generally, possible plating dopants for forming the intermetallic phase-accelerating layer 128 are palladium, gold, platinum, and zinc.

[0077] Referring to Fig. 3 shows a layer sequence which is an alternative to that of Fig. 2. According to Fig. 3, the carrier 102 is covered with an intermetallic phase acceleration layer 128 configured as a bilayer. In the illustrated embodiment, a lower layer 128A (also referred to as a dopant layer) formed on the carrier 102 comprises zinc, whereas an upper layer 128B (also referred to as a combined dopant and protection layer) formed on the lower layer 128A may comprise, for example, palladium and gold.

[0078] As already mentioned, Fig. 2 and Fig.3 shows two embodiments of a carrier 102 with a dopant plating in the form of the intermetallic phase acceleration layer 128, which can be formed as a single layer or a multilayer. The following process is explained on the basis of the structure shown in Fig. 2, wherein a corresponding process can be executed based on the structure shown in Fig. 3 is shown.

[0079] Referring to Fig.4, a solder paste 130 may be applied to the carrier 102 covered with the intermetallic phase acceleration layer 128. As shown, the solder paste 130 comprises intermetallic particles 132 comprising a solder matrix 122 (preferably made of tin) for creating a solder connection between the component 104 and the carrier 102. Furthermore, the intermetallic particles 132 comprise intermetallic phase promoter particles 124 in the solder matrix 122. The latter may be made of one or more intermetallic phase promoter metals for promoting the formation of an intermetallic phase in the intermetallic interconnect structure 106. In the embodiment shown, the intermetallic phase promoter particles 124 comprise a first type of particles and a second type of particles. For example, the first type of particles may be made of silver, whereas the second type of particles may be made of copper.

[0080] Thus, after plating the carrier 102 with the intermetallic phase acceleration layer 128 to accelerate the formation of the intermetallic network structure 108, the intermetallic phase acceleration layer 128 can be covered with the solder paste 130.

[0081] Although this is Fig. 2 to Fig. 8, it may be possible to provide intermetallic phase acceleration particles 126 in the solder paste 130 in addition to or as an alternative to providing a planar intermetallic phase acceleration layer 128 (see Fig. 1), to accelerate the formation of the intermetallic network structure 108. This can obviate the need to plate a dedicated intermetallic phase acceleration layer 128 onto the carrier 102.

[0082] It should be appreciated that the solder material printing process shown is not limited to a specific solder material type, but rather depends on the final solder connection requirement. Therefore, many different soldering systems can be implemented in various embodiments. For example, a suitable solder paste 130 may contain primarily Sn and one or more other metallic elements in smaller amounts. For example, 3 wt. % silver and 0.5 wt. % Cu may be added to the Sn matrix in a solder paste 130 used in an exemplary embodiment. Flux, additives, etc. may also be added to the solder paste 130.

[0083] Referring to Fig.5, an electronic component 104 comprising a semiconductor body 118 and a backside metallization 120 can be pressed from a top side onto the applied solder paste 130. Consequently, the solder paste 130 is pressed between the carrier 102 and the component 104, forming a layer with a substantially homogeneous thickness. Advantageously, the intermetallic particles 132 of the solder paste 130 can be planarized by means of the mechanical pressure exerted between the carrier 102 and the component 104, thereby forming a monolayer 134 of solderable intermetallic particles 132 (optionally in a matrix of solvent(s), which is not shown). The intermetallic particles 132 of the solder paste 130 can have a diameter d preferably in a range of 10 µm to 20 µm, for example, 15 µm.During die bonding, the solder layer can therefore be pressed down to the monolayer 134, allowing a controlled definition of the bond line thickness. The bond line thickness can describe the thickness of the solderable material between the carrier 102 and the component 104. During the described process, it is possible to provide additional dopants from the backside of the die, for example, Cu, Au, Pd, and / or V.

[0084] Referring to Fig.6, a process of connecting the electrically conductive carrier 102 to the electronic component 104 by means of an intermetallic interconnect structure 106 is initiated. More specifically, the formation of the intermetallic interconnect structure 106 is triggered by heating precursors of the intermetallic interconnect structure 106 to a peak temperature which is above a melting temperature of the solder matrix 122 as a solder material precursor and below a melting temperature of the intermetallic network precursors, which are embodied here as the intermetallic phase promoter particles 124, and the materials of the layer(s) 128 and / or 120. The structure is illustrated in Fig.5 is heated to melt the solder matrix 122 without melting the material according to reference numeral 120, 124, and / or 128. Advantageously, a maximum or peak temperature, which may preferably be in a range of 280°C to 300°C, may be maintained during this selective melting process for a time interval in a range of preferably 1.5 minutes to 2 minutes. For example, the melting temperature of the solder precursor in the form of the solder matrix 122 is below 240°C (for example, a melting point of tin may be approximately 230°C). In contrast, the melting temperature of the aforementioned intermetallic network precursors may be significantly above 300°C.

[0085] In particular, the described process can form the intermetallic interconnect structure 106 by reflow soldering. During reflow soldering, the material of the solder matrix 122 reaches and exceeds its melting point and becomes liquid, whereas the components of the intermetallic network structure 106 that is formed remain solid.

[0086] Referring to Fig. 7, the dopants become solutes when the material of the solder matrix 122 becomes liquid (illustratively, an element concentration difference drives the diffusion process) and dissolve in the liquid bulk solder material. In addition to the intermetallic phase promoter particles 124, the intermetallic phase acceleration particles 126 can be separated from the intermetallic phase acceleration layer 128. Furthermore, additional particles can be separated from the backside metallization 120 and can dissolve in the liquid solder matrix 122.

[0087] Referring to Fig. 8, the formation of the intermetallic compound structure 106 is continued by dissolving additional particles in the liquid solder matrix 122. As a result, an intermetallic compound structure 106 according to Fig.1. Such an intermetallic interconnect structure 106 may comprise an intermetallic network structure 108 in a central portion and opposing outer structures 110, 112 without the intermetallic network and each disposed between the intermetallic network structure 108 on the one hand and the carrier 102 or the component 104 on the other. As a result of the described manufacturing method, the network structure 108 and the outer structures 110, 112 comprise the same intermetallic materials, i.e., tin, copper, gold, silver, palladium, zinc, etc., particularly depending on the materials used for the solder paste 130, the intermetallic phase acceleration layer 128, and the backside metallization 120. A certain contribution of the material(s) of the carrier 102 may also be included in the intermetallic interconnect structure 106.

[0088] For the described manufacturing process, a doping system combining a paste and plating can be used. Since the solder paste 130 can be printed onto a plated surface and a reflow process can be performed, the plated element on the carrier 102 can be a dopant, for example, comprising Pd and Au. In addition to the freedom to choose different materials for the solder paste 130 (for example, SAC305, SAC405, or a Ni doping paste, etc.), other elements may be possible for different task profiles or reliability requirements, for example, Zn. Advantageously, the dopants from the carrier 102 do not affect the processability of the solder paste 130 (for example, with regard to flowability, wetting, melting point, etc.). The elements involved can continue to diffuse, thereby making the bulk solder material a more homogeneous solution.The dispersed dopants can act as a nucleus for the formation of the intermetallic composite network or the intermetallic network structure 108.

[0089] Referring again to the embodiments of Fig. 1 to Fig. 8, the dopant (particularly from the structures shown by reference numerals 124, 128) begins to form an intermetallic compound with Sn from the solder matrix 122 when the reaction energy is provided (during a reflow profile peak temperature and hold time), thereby creating the intermetallic network structure 108. A strong connection in the form of the external structures 110, 112 may also be created along the carrier 102 and the component 104 (particularly at a chip backside contact interface according to reference numeral 120).

[0090] Advantageously, the intermetallic network structure 108 or the intermetallic composite network does not remelt during a normal reflow profile (e.g., with a peak temperature of approximately 260°C). Illustratively, the intermetallic network structure 108 forms a backbone of a generated bond line from each move during a subsequent move. It may be possible that the intermetallic network structure 108 or the intermetallic composite network is generated at an atomic level from dopants that are more homogeneous and faster (due to a larger surface area or reaction sites) compared to using a metal powder. The material of the solder matrix 122 (in particular, Sn) is drawn in to form an intermetallic composite surrounding the dopants. This may leave pure Sn behind (e.g., unreacted Sn), with Sn enrichment generally observed in the bulk solder material.Traditionally, tin can be a major cause of unwanted remelting, as other elements melt at high or higher temperatures. Such unwanted remelting phenomena can be reliably suppressed, particularly by means of the intermetallic network structure 108.

[0091] As already mentioned above, a small bond line thickness can be achieved. Consequently, a short time may be sufficient to homogeneously dope the bulk solder material. This may be advantageous to enable the formation of the intermetallic composite network or intermetallic network structure 108, which connects an upper and a lower contact interface in the form of the opposing outer structures 110, 112 (i.e., at the chip backside and the carrier surface). Advantageously, a Sn bond may occur in the intermetallic composite (promoting the tendency of the intermetallic interconnect structure 106 to not reflow), which may also play a role in bonding the intermetallic composite network.

[0092] Fig. 9 shows a cross-sectional view of an electronic system 100 according to another exemplary embodiment. According to Fig.9, the vertical thickness of the intermetallic interconnect structure 106 is very small. In the embodiment of Fig. 9, the main body 114 is made of copper, the barrier layer 106 is made of nickel, and the intermetallic phase acceleration layer 128 has palladium and gold as dopants.

[0093] Table 1 shows a metallic content of various components of an intermetallic compound structure 106 according to Fig. 9. Table 2 summarizes the information from Table 1 and provides an indication of a ratio between a partial weight of the dopants and a total weight of the intermetallic compound structure 106 according to Table 1. Table 1 material Total mass Gold 1,158 × 10 -12 palladium 9,6 × 10 -13 Solder material (total) 1,01115 × 10 -10 Tin (96% of the solder paste) 9,70704 × 10 -11 Silver (3% of the solder paste) 3,03345 × 10 -12 Copper (0.5% of the solder paste) 5,05575 × 10 -13 Table 2 Total dopant mass (in[g]) 5,65703 × 10 -11 Total solder joint mass (in[g]) 1,03233 × 10 -10 Dopant mass / solder joint mass [%] 5,48

[0094] Thus, Table 1 and Table 2 indicate a dopant weight ratio in the solder joint of an intermetallic composite network. As shown, the dopant weight ratio across the entire solder joint when omitting the dopants from the chip backside is approximately 5.5% in the illustrated embodiment.

[0095] Increasing the dopant loading can accelerate the formation of the intermetallic network. However, if this rate is too fast, it can lead to flux discharge from the bond line (thus reducing the flowability of the solder material). This can create voids in the bond line. Optimization can be performed based on (i) the reflow profile and (ii) the dopant loading. Generally, the dopant loading can range from 1 wt% to 35 wt%, and in many scenarios, excellent results can be achieved in a range of 4.5 wt% to 6.5 wt%.

[0096] In one embodiment, a manufacturing method may include forming the intermetallic interconnect structure 106 having the intermetallic network structure 108 from a composition of tin (Sn) alloyed with copper (Cu) and silver (Ag), with copper in a range of 1 wt. % to 30 wt. %, silver in a range of 1 wt. % to 60 wt. %, and preferably the balance tin. Thus, the intermetallic network structure 108 may be formed from compositions of Sn alloyed with Cu and Ag, in the ranges of Cu from 1 wt. % to 30 wt. % and Ag from 1 wt. % to 60 wt. % (i.e., using an Ag-Cu-Sn brazing system).

[0097] Table 3 shows exemplary compositions of an intermetallic compound structure 106 having the intermetallic network structure 108 according to embodiments (along with a solidus temperature, T Solidus , and a liquidus temperature, T Liquidus): Table 3 Composition (at% / wt%) T Solidus [°C] T Liquidus [°C] 30.3Ag-24, 1Cu-45, 6Sn 216 448 32Ag-15Cu-53Sn 52.2Ag-19, 3Cu-28, 5Sn55Ag-12Cu-33Sn 214 477 30.5Ag-10, 4Cu-59, 1Sn30Ag-6Cu-64Sn 216 400 42.1Ag-23, 8Cu-34, 1Sn45Ag-15Cu-40Sn 216 506

[0098] Fig. 10 shows a cross-sectional view of an electronic system 100 according to yet another exemplary embodiment. In the embodiment according to Fig. 10 shows the formation of a metallic network structure 108 in a solder matrix 122, which extends almost over the entire extent between the carrier 102 and the component 104. Thus, the relative vertical extents of the outer structures 110, 112 (in Fig. 10 not shown) may be very low.

[0099] Fig. 11 to Fig. 13 are cross-sectional views of structures obtained during fabrication of an electronic system 100 according to yet another exemplary embodiment.

[0100] Referring to Fig.11, a solder paste 130 comprising intermetallic particles 132 is applied to an upper main surface of a leadframe-like carrier 102. Thus, the leadframe can be subjected to smart selective soldering. For example, a corresponding process can be performed with a defined pad line in laminates. Referring again to Fig. 11, it may be possible to dispense the solder paste 130 in a very small amount. For example, it may be possible to use a thin solder paste 130, for example, Type 5 solder paste.

[0101] Referring to Fig.12, the electronic component 104 is pressed from above onto the applied solder paste 130. Thus, a die bonding process can be performed, and the electronic component 104 can be pressed onto the solder paste 140, so that the thickness of the deformed solder paste 130 is reduced to preferably a solder ball size. In other words, a monolayer 134 of intermetallic particles 132 is formed between the carrier 102 and the component 104 by means of pressing.

[0102] Referring to Fig. 13 is the structure which in Fig. 12, is subjected to reflow soldering to thereby form an intermetallic bond structure 106 between the carrier 102 and the component 104, as described above. Thus, a reflow process is performed to enable a pronounced formation of an intermetallic bond (for example, a target may be 70%).

[0103] Fig.14 is a phase diagram 150 showing the properties of various intermetallic phases produced by mixing silver, gold, and tin, and is used to explain a principle of an exemplary embodiment.

[0104] A change in the molar fraction between silver (Ag) and tin (Sn) is shown by reference numeral 152. Correspondingly, a change in the molar fraction between silver (Ag) and gold (Au) is shown by reference numeral 154. Furthermore, a change in the molar fraction between tin (Sn) and gold (Au) is shown by reference numeral 157. The phase diagram 150 shows various phases of the gold-silver-tin system. For example, a liquid phase can be obtained in a region 159 with a high tin content. In a central region of the phase diagram 150, which corresponds to reference numeral 160, a strong mixing of several metallic elements can be achieved. This region can be used to form the intermetallic network structure 108 according to an exemplary embodiment.

[0105] More specifically, an exemplary embodiment may use multiple metallic elements to create a vertically connected intermetallic composite (or a plurality of intermetallic composites). This may make it possible to create an intermetallic composite network or an intermetallic network structure 108 after a reflow process. Advantageously, the intermetallic composite network does not melt during further reflows. Thus, it may be possible to maintain structural stability of the resulting bond line or intermetallic interconnect structure 106. Illustratively, the intermetallic interconnect structure 106 may hold electronic components 104 (in particular, silicon chips) to the carrier 102 during reflow. Advantageously, bulk solder material clusters may melt during reflow and cannot flow away due to their embedding in the intermetallic composite network.Advantageously, the bulk solder material (which may be soft and ductile) can compensate for stress in the bond line.

[0106] Fig.15 is a diagram 170 illustrating a reflow soldering process performed during the manufacture of an electronic system 100 according to an exemplary embodiment. Time in seconds is plotted along an abscissa 172. Temperature in °C is plotted along an ordinate 174. A curve 176 illustrates a high-temperature reflow profile. As indicated by reference numeral 178, the peak temperature (which may be selected in a range of 280°C to 300°C, for example, higher and below a carrier Tg) is maintained for a relatively long time during reflow soldering, preferably in the range of 1 minute to 2 minutes. With this control system, excellent properties can be achieved with respect to the formation of an intermetallic network structure 108 in the intermetallic interconnect structure 106.

[0107] Fig. 16 (first reflow) and Fig.17 (second reflow) show a method for manufacturing an electronic system 100 according to an exemplary embodiment. The described reflow profile can reliably prevent unwanted reflow of the solder material. During the described reflow soldering process, a preform of the electronic system 100 to be formed is passed through temperature zones I to VIII with different temperature values, as shown in Fig. 16. Referring to reference numeral 190, the preform may be passed through a soak zone in which a solder joint is not yet formed. As shown by reference numeral 192, the preform may then be subjected to an elevated peak time and temperature, which promotes growth of the intermetallic compound.

[0108] Subsequently, the processed preform of the electronic system 100 to be formed can be subjected to another reflow process. In this context, the preform can be passed through temperature zones 1 to 8 with different temperature values, as shown in Fig. 17. According to Fig. 17, another electronic component 104' is connected above the electronic component 104 by means of an additional solder paste 130'. Also in the process according to Fig. 17, no solder reflow occurs at the first component 104 in the temperature peak zone.

[0109] In a softening zone 194, no solder joint is yet formed. The solder material melts in a tip zone 196. The solder material solidifies in a cooling zone 198.

[0110] Fig.Figure 18 shows a cross-sectional view of an electronic system 100 embodied as a transistor outline (TO) package, according to an exemplary embodiment. The electronic system 100 is mounted on a mounting structure 182, embodied here as a printed circuit board, for fabricating an assembly 180.

[0111] The mounting structure 182 includes an electrical contact 184 embodied as a plating in a through-hole of the mounting structure 182. When the electronic system 100 is mounted on the mounting structure 182, an electronic component 104 of the electronic system 100 is electrically connected to the electrical contact 184 via an electrically conductive carrier 102 of the electronic system 100, which is embodied here as a copper lead frame.

[0112] The electronic system 100 thus comprises the electrically conductive carrier 102, the electronic component 104 (which is embodied here as a power semiconductor chip), which is mounted on the carrier 102 by means of the intermetallic interconnect structure 106, and an encapsulation 156, which encapsulates a part of the carrier 102 and the electronic component 104. As Fig. 18, a pad on an upper main surface of the electronic component 104 is electrically coupled to the carrier 102 via a bonding wire as an electrically conductive contact element 160.

[0113] During operation of the electronic power system or the electronic system 100, the power semiconductor chip in the form of the electronic component 104 generates a considerable amount of heat. At the same time, it is important to ensure that any unwanted current flow between a lower surface of the electronic system 100 and the surrounding environment is reliably prevented.

[0114] To ensure the electrical insulation of the electronic component 104 and the dissipation of heat from an interior of the electronic component 104 to an environment, an electrically insulating and thermally conductive interface structure 158 may be provided, covering an exposed surface portion of the carrier 102 and a connected surface portion of the encapsulation 156 at the bottom of the electronic system 100. The electrically insulating property of the interface structure 108 prevents unwanted current flow, even in the presence of high voltages between an interior and an exterior of the electronic system 100. The thermally conductive property of the interface structure 158 promotes the dissipation of heat from the electronic component 104 via the electrically conductive carrier 102 (made of highly thermally conductive copper) through the interface structure 108 and to a heat dissipation body 162.The heat dissipation body 162, which may be made of a highly thermally conductive material, for example, copper or aluminum, has a base body 164 directly connected to the interface structure 158 and has a plurality of cooling fins 166 extending from the base body 164 and parallel to each other to dissipate heat to the environment.

[0115] As also in Fig. 18, the intermetallic compound structure 106 is formed between the carrier 102 and the component 104, for example embodied as in Fig. 1 is shown.

[0116] It should be noted that the term "comprising" does not exclude other elements or features, and "a" or "an" does not exclude pluralities. Even elements described in connection with different embodiments may be combined. It should also be noted that reference numerals are not to be construed as limiting the scope of the claims. Furthermore, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods, and steps described in the specification. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.

Claims

[1] An electronic system (100), the electronic system (100) comprising: • an at least partially electrically conductive carrier (102); • an electronic component (104); and • an intermetallic interconnect structure (106) connecting the carrier (102) and the component (104) and comprising: ◯ a soldering matrix (122); ◯ an intermetallic network structure (108) in a central portion of the intermetallic interconnection structure (106), which intermetallic network structure (108) forms a branched network of interconnected multi-metal particles of silver and copper, embedded in the solder matrix (122); and ◯ opposite outer structures (110, 112) without intermetallic network and each arranged between the intermetallic network structure (108) on the one hand and the carrier (102) or the component (104) on the other hand. [2] The electronic system (100) according to claim 1, wherein the carrier (102) has a lead frame structure. [3] The electronic system (100) according to claim 1 or 2, wherein the carrier (102) comprises an electrically conductive main body (114) partially covered by a metallic diffusion barrier (116). [4] The electronic system (100) according to any one of claims 1 to 3, wherein the component (104) comprises a semiconductor body (118) covered with a backside metallization (120), the backside metallization (120) being connected to the intermetallic interconnect structure (106). [5] The electronic system (100) according to any one of claims 1 to 4, wherein the solder matrix (122) comprises tin. [6] The electronic system (100) according to any one of claims 1 to 5, wherein the intermetallic compound structure (106) comprises intermetallic phase promoter particles (124) of at least one intermetallic phase promoter metal. [7] The electronic system (100) of claim 6, wherein the at least one intermetallic phase promoter metal comprises at least one of a group consisting of silver and copper. [8] The electronic system (100) according to any one of claims 1 to 7, wherein the mesh structure (108) and the outer structures (110, 112) comprise the same intermetallic materials. [9] The electronic system (100) according to any one of claims 1 to 8, comprising at least one of the following features: • wherein the intermetallic compound structure (106) comprises intermetallic phase acceleration particles (126) made of at least one intermetallic phase acceleration metal, wherein in particular the at least one intermetallic phase acceleration metal comprises at least one of a group consisting of palladium, gold, platinum, vanadium and zinc; • wherein the intermetallic compound structure (106) is free of lead; • wherein a vertical thickness (D) of the intermetallic compound structure (106) is in a range from 5 µm to 50 µm, in particular in a range from 10 µm to 30 µm, further in particular in a range from 10 µm to 20 µm; • comprising an intermetallic phase acceleration layer (128) made of at least one intermetallic phase acceleration metal, arranged between the carrier (102) and the intermetallic connecting structure (106), wherein in particular the intermetallic phase acceleration layer (128) is a single layer or a double layer; • wherein a partial vertical thickness of the intermetallic network structure (108) is at least 80% relative to a total vertical thickness (D) of the entire intermetallic interconnect structure (106); • wherein the intermetallic network structure (108) forms a branched network of interconnected multi-metal particles which extends continuously between an entire vertical distance between the outer structures (110, 112); • wherein a weight percent of the intermetallic network structure (108) in relation to the entire intermetallic compound structure (106) is in a range from 1 weight percent to 30 weight percent, in particular in a range from 3 weight percent to 8 weight percent, further in particular in a range from 4.5 weight percent to 6.5 weight percent; • wherein the intermetallic compound structure (106) with the intermetallic network structure (108) has a composition of tin alloyed with copper and silver, with copper in a range of 1 weight percent to 30 weight percent, silver in a range of 1 weight percent to 60 weight percent, and preferably the remainder tin. [10] A method of manufacturing an electronic system (100), the method comprising: • Connecting an at least partially electrically conductive carrier (102) to an electronic component (104) by means of an intermetallic connecting structure (106); and • Forming the intermetallic compound structure (106) with: ◯ a soldering matrix (122); ◯ an intermetallic network structure (108) in a central portion of the intermetallic interconnection structure (106), which intermetallic network structure (108) forms a branched network of interconnected multi-metal particles of silver and copper, embedded in the solder matrix (122); and ◯ opposite outer structures (110, 112) without intermetallic network and each arranged between the intermetallic network structure (108) on the one hand and the carrier (102) or the component (104) on the other hand. [11] The method according to claim 10, wherein the method comprises forming the intermetallic compound structure (106) by applying a solder paste (130) to the carrier (102), the solder paste (130) comprising a solder matrix (122) for creating a solder connection between the component (104) and the carrier (102), and intermetallic phase promoter particles (124) of at least one intermetallic phase promoter metal for promoting the formation of an intermetallic phase in the intermetallic compound structure (106). [12] The method according to claim 11, wherein the method comprises providing the solder paste (130) with the intermetallic particles (132) having a diameter (d) in a range of 5 µm to 50 µm, in particular in a range of 10 µm to 20 µm. [13] The method of claim 11 or 12, wherein the method comprises pressing the solder paste (130) between the carrier (102) and the component (104). [14] The method according to any one of claims 11 to 13, comprising at least one of the following features: • wherein the method comprises covering the carrier (102) with an intermetallic phase acceleration layer (128) for accelerating the formation of the intermetallic network structure (108) and disposing the intermetallic phase acceleration layer (128) between the carrier (102) and the solder paste (130); • Providing the solder paste (130) with intermetallic phase accelerating particles (126) to accelerate the formation of the intermetallic network structure (108); • wherein the method comprises producing the intermetallic compound structure (106) with the intermetallic network structure (108) from a composition of tin alloyed with copper and silver, with copper in a range of 1 weight percent to 30 weight percent, silver in a range of 1 weight percent to 60 weight percent, and preferably the remainder tin. [15] The method of any one of claims 10 to 14, wherein the method comprises forming the intermetallic compound structure (106) by heating precursors of the intermetallic compound structure (106) to a peak temperature above a melting temperature of a braze material precursor and below a melting temperature of intermetallic network precursors. [16] The method according to claim 15, wherein the method comprises maintaining the peak temperature for a time interval of at least 1 minute, in particular for a time interval in a range of 1 minute to 4 minutes, further in particular for a time interval in a range of 1.5 minutes to 2 minutes. [17] The method according to claim 15 or 16, comprising at least one of the following features: • wherein the peak temperature is in a range of 260 °C to 350 °C, in particular in a range of 280 °C to 300 °C; • where the melting temperature of the solder precursor is below 240 °C; • where the melting temperature of the intermetallic network precursors is at least 370 °C. [18] The method according to any one of claims 10 to 17, wherein the method comprises forming the intermetallic compound structure (106) by reflow soldering.

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