DISPLAY DEVICE AND CONTROL METHOD FOR IT

Abstract

A display device (100), comprising: a display panel (110) which is divided into a plurality of active areas (AA); a data driver (130) configured to supply data voltages to a plurality of pixels (PX) arranged in each of the plurality of active areas (AA); and a timing control device (140) configured to output a power control signal (PWRC) for controlling a driver current for the data driver (130), wherein the plurality of active areas (AA) is divided into central active areas (CA), in which a plurality of pixel columns are arranged on a central section of a plurality of pixel columns that are arranged in each of the plurality of active areas (AA), and into active periphery areas (EA), in which a plurality of pixel columns are arranged on an outer section of a plurality of pixel columns that are arranged in each of the plurality of active areas (AA), the data driver (130) contains a plurality of integrated source driver circuits (SDICs), each of which is configured to supply at least one of the data voltages to one of the plurality of active areas (AA), and the timing control device (140) is configured to generate the power control signal (PWRC) as a function of a difference value (DV) between comparison data (CD), which is a maximum data transition value between adjacent pixel rows arranged in each of the multiple active areas (AA), and edge comparison data (ECD), which is the maximum data transition value between adjacent pixel rows arranged in the multiple active edge areas (EA), wherein the time control device (140) has: a data release signal generator (141) configured to generate a sub-data release signal (SDE) configured to determine an output timing of a data voltage supplied to each of the multiple active areas (AA), and a boundary data release signal (EDE) configured to determine an output timing of a data voltage supplied to each of the multiple active boundary areas (EA); a data delay unit (142) configured to delay video data (data) by one horizontal period and output the delayed video data (D_data); a data comparison unit (143) configured to compare the video data (data) and the delayed video data (D_data) and to generate the comparison data (CD) and the edge comparison data (ECD); and a power control signal generator (144) which is configured to generate the power control signal (PWRC) using the reference data (CD) and the boundary reference data (ECD). wherein the power control signal generator (144) is configured to set a first reference value (SV1) by applying the comparison data (CD) to a first lookup table, set a second reference value (SV2) by applying the boundary comparison data (ECD) to a second lookup table, set a compensation value (CV) by applying a difference value (DV) between a first reference value (SV1) corresponding to an active area (AA) and a second reference value (SV2) corresponding to an active boundary area (EA) adjacent to the active area (AA) to a third lookup table, and add the compensation value (CV) to the first reference value (SV1) corresponding to the active area (AA) and output a result as the power control signal (PWRC).

Description

BACKGROUND area

[0001] The present disclosure relates to a display device and a control method therefor, and in particular to a display device that can control a control current. Description of the related prior art

[0002] Display devices used by the screen of a computer, television, mobile phone or similar device include organic light-emitting diode (OLED) displays, which emit light on their own, and liquid crystal displays (LCDs), which require a separate light source.

[0003] Among these various display devices, the OLED features a display panel with a plurality of subpixels and drivers for controlling the display panel. The drivers include a gate driver, configured to supply gate voltages to the display panel, and a data driver, configured to supply data voltages. When a signal, such as a gate voltage and a data voltage, is applied to a subpixel of the OLED, the selected subpixel emits light to display an image.

[0004] The data driver has a plurality of integrated source driver circuits (SDICs), and each of the SDICs supplies a data voltage to each of a plurality of active areas.

[0005] Furthermore, a defect, such as block darkening, can occur at the boundary between an active area controlled by an SDIC where frequent data transitions take place and an active area controlled by an SDIC where no data transitions occur. This can be caused by a difference in driver current between the SDICs, even if data voltages are used to represent the same grayscale.

[0006] The following publications are cited as state of the art: US 2012 / 0133635 A1, US 2017 / 0004776 A1. OVERVIEW

[0007] One objective to be achieved by the present disclosure is to provide a display device capable of reducing block darkening between a plurality of active areas, and a control method for this.

[0008] Another objective to be achieved by the present disclosure is to provide a display device capable of reducing power consumption by adjusting a driver current, and a control method for this.

[0009] The objectives of this disclosure are not limited to those mentioned above, and other objectives not mentioned above can be clearly understood by those skilled in the art from the following descriptions.

[0010] The objectives can be achieved by a display device and a control method for a display device according to the independent claims. Preferred embodiments are described in the dependent claims. According to one aspect of the present disclosure, a display device comprises a display panel divided into a plurality of active areas. Furthermore, the display device includes a data driver configured to supply data voltages to a plurality of pixels arranged in each of the plurality of active areas. The display device also includes a timing device configured to output a power control signal to the data driver for controlling a driver current.Each of the active regions is subdivided into a central active region, in which a plurality of pixel columns are arranged in a central section of the plurality of pixel columns arranged in the active regions, and into one or more active perimeter regions, in which a plurality of pixel columns are arranged in an outer section of the plurality of pixel columns arranged in the active region. The data driver comprises a plurality of integrated source driver circuits (SDICs), each of which is configured to supply at least one of the data voltages to one of the plurality of active regions. For example, each integrated source driver circuit (SDIC) can supply one or more of the data voltages to a corresponding one of the plurality of active regions.The timing control unit generates the power control signal based on a difference between reference data, which represents the maximum data transition value between adjacent pixel rows in each of the multiple active areas, and edge reference data, which represents the maximum data transition value between adjacent pixel rows in the multiple active edge areas. This makes it possible to improve image quality at the boundary between the active areas.

[0011] According to another aspect of the present disclosure, a control method for a display device includes a data delay process for delaying video data by one horizontal period and outputting the delayed video data. Furthermore, the control method includes a data comparison process for generating comparison data and boundary comparison data by comparing the video data and the delayed video data. Additionally, the control method includes a first reference value setting process for setting a first reference value by applying the comparison data to a first lookup table. Moreover, the control method includes a second reference value setting process for setting a second reference value by applying the boundary comparison data to a second lookup table.Furthermore, the control method includes a compensation value calculation process for setting a compensation value by applying a difference value between a first reference value corresponding to an active area and a second reference value corresponding to an active boundary area adjacent to the active area to a third lookup table. The control method also includes a power control signal output process for adding the compensation value to the first reference value corresponding to the active area and outputting the result as the power control signal.

[0012] Further details regarding the exemplary embodiments are included in the detailed description and drawings.

[0013] According to the present disclosure, it is possible to suppress block darkening at a boundary between several active areas if data voltages are applied to the several active areas to represent the same grayscale.

[0014] According to the present disclosure, it is possible to determine an optimal drive power for each active area and thus optimize the power consumption of a display device.

[0015] The effects according to the present disclosure are not limited to the contents listed above as examples, and further various effects are included in the present specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The above and other aspects, features and other advantages of the present disclosure will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which: Fig. 1 is a schematic diagram showing a display device according to an embodiment of the present disclosure; Fig. 2 a diagram illustrating a plurality of active areas of the display device according to an embodiment of the present disclosure; Fig. 3 a diagram to illustrate a time control device of the display device according to an embodiment of the present disclosure; Fig. 4 is a waveform diagram showing a sub-data release signal and a boundary data release signal of the display device according to an embodiment of the present disclosure; Fig. 5 shows a lookup table (LUT) of a power control signal generator of the display device according to an embodiment of the present disclosure; Fig. 6 a diagram illustrating an integrated source driver circuit (SDIC) of the display device according to an embodiment of the present disclosure; Fig. 7 a circuit diagram illustrating a power control circuit and a buffer of the display device according to an embodiment of the present disclosure; and Fig. 8 is a flowchart to illustrate a control method for a display device according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE EXECUTION FORM

[0017] The advantages and features of the present disclosure, as well as the methods for its implementation, will be better understood with reference to the exemplary embodiments described below and the accompanying drawings. However, the present disclosure is not limited to the following exemplary embodiments, but can be implemented in various other forms. The exemplary embodiments are provided only to supplement the disclosure of the present disclosure and to fully familiarize a person with ordinary knowledge in the field to which the present disclosure relates with the category of the present disclosure, and the present disclosure is defined by the accompanying claims.

[0018] The shapes, dimensions, ratios, angles, numbers, and the like shown in the accompanying drawings to describe exemplary embodiments of the present disclosure are merely examples, and the present disclosure is not limited to them. The same reference numerals generally denote the same elements throughout the entire description. Furthermore, in order to avoid unnecessarily obscuring the subject matter of the present disclosure, a detailed explanation of known related technologies may be omitted in the following description of the present disclosure. The terms used herein, such as "have," "contain," and "consist of," are generally intended to permit the addition of other components, unless the terms are used with the term "only." All references to the singular include the plural unless expressly stated otherwise.

[0019] Components are interpreted as having a normal error margin, even if this is not explicitly stated.

[0020] When the positional relationship between two parts is described using terms such as "on", "above", "below" and "next to", one or more parts may be located between the two parts unless the terms are used together with the term "immediately" or "directly".

[0021] When an element or layer is described as lying “on” another element or layer, it may lie directly on top of the other element or layer, or there may be elements or layers in between.

[0022] Although the terms "first," "second," and the like are used to describe different components, these components are not limited by these terms. These terms are used merely to distinguish one component from the others. Therefore, a first component mentioned below may be a second component in a technical concept of the present disclosure.

[0023] Throughout the entire specification, the same reference numbers refer to the same elements.

[0024] Since the dimensions and thicknesses of the individual components shown in the drawings are presented for the sake of simplicity, the present disclosure is not necessarily limited to the dimensions and thicknesses of the individual components shown.

[0025] The features of the various embodiments of the present disclosure can be partially or completely coupled or combined with one another and can be technically interlocked and operated in various ways, and the embodiments can be implemented independently of one another or in combination with one another.

[0026] Various exemplary embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0027] Fig. Figure 1 is a schematic diagram showing a display device according to one embodiment of the present disclosure. Referring to Fig. 1 includes a display device 100, a display panel 110, a gate driver 120, a data driver 130 and a timing device 140.

[0028] The display panel 110 is a panel for displaying images. The display panel 110 can contain various circuits, lines, and light-emitting elements arranged on a substrate. The display panel 110 is divided by a plurality of intersecting data lines DL and a plurality of gate lines GL, and can contain a plurality of pixels PX connected to the plurality of data lines DL and the plurality of gate lines GL.

[0029] The display panel 110 can have a plurality of active areas AA, defined by the plurality of pixels PX, and a non-active area NA, in which various signal lines, pads, etc. are formed. The multiple active areas AA can be subdivided into a first active area AA1 to an m-th active area AA(m).

[0030] Each of the multiple pixels PX can contain multiple subpixels. These multiple subpixels can emit different colors. For example, each of the multiple subpixels can be a red subpixel, a green subpixel, and a blue subpixel, but this is not limited to them. Multiple subpixels can form a pixel PX. That is, a red subpixel, a green subpixel, and a blue subpixel can form a pixel PX, and the display panel 110 can contain multiple pixels PX.

[0031] The display panel 110 can be used as a display panel in various display devices such as liquid crystal display devices, organic light-emitting display devices and electrophoretic display devices.

[0032] The timing unit 140 receives timing signals such as a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a data release signal (DE), and a data clock signal (DCLK) via a receiving circuit such as LVDS and TMDS interfaces connected to a host system. The timing unit 140 generates control signals DCS and GCS to control the data driver 130 and the gate driver 120 based on the received timing signals.

[0033] For example, the timing device outputs 140 different gate control signals GCS, including a gate start pulse, a gate shift clock, and a gate output enable signal to control the gate driver 120.

[0034] In some embodiments, the gate start pulse controls the start-up time of the gate driver 120. The gate shift clock is a clock signal that is typically input into one or more gate circuits and controls the shift time of a gate voltage. The gate output enable signal denotes the output clock information of the gate driver 120.

[0035] The timing control unit 140 outputs various data control signals DCS, including a source start pulse, a source sampling clock and a source output enable signal for controlling the data driver 130.

[0036] In some embodiments, the source start pulse controls the start time of data sampling by one or more integrated source driver circuits (SDICs) that comprise the data driver 130. The source sampling clock is a clock signal that controls the sampling timing of data in the data driver 130. The source output enable signal controls the output timing of the data driver 130.

[0037] Furthermore, the time control unit 140 transmits digital video data to the data driver 130. The digital video data is converted by the data driver 130 into an analog data voltage and then output to each pixel PX arranged in the active areas AA.

[0038] Furthermore, the timing unit 140 outputs a power control signal PWRC to the data driver 130. The power control signal PWRC can control a driver current of one or more SDICs that form the data driver 130.

[0039] The gate driver 120 supplies gate voltages to the plurality of pixels PX. The gate driver 120 can contain multiple stages for shifting gate voltages to output the gate voltages in response to the gate control signals GCS. The multiple stages in the gate driver 120 can sequentially output gate voltages to the multiple pixels PX via the gate lines GL. The gate driver 120 can be, but is not limited to, an integrated gate driver circuit (GDIC) implemented in the inactive area NA of the display panel 110 using a gate-in-panel (GIP) technique.

[0040] The data driver 130 supplies data voltages to the majority of pixels PX. The data driver 130 can have a majority of SDICs. That is, as in Fig. As shown in Figure 1, the data driver 130 can have a first SDIC SDIC#1 configured to supply a data voltage to the first active area AA1, a second SDIC SDIC#2 configured to supply a data voltage to a second active area AA2, and an m-th SDIC SDIC#(m) configured to supply a data voltage to the m-th active area AA(m).

[0041] Each of the SDICs SDIC#1, SDIC#2, ..., SDIC#(m) can be supplied with digital video data, the data control signal DCS, and the power control signal PWRC from the time control unit 140. Each of the SDICs SDIC#1, SDIC#2, ..., SDIC#(m) can convert the digital video data into a data voltage using an analog gamma voltage in response to the data control signal DCS. Furthermore, each of the SDICs SDIC#1, SDIC#2, ..., SDIC#(m) can drive the plurality of pixels PX via the data lines DL by setting a drive current in response to the power control signal PWRC.

[0042] The multiple SDICs SDIC#1, SDIC#2, ..., SDIC#(m) can be connected to the data lines DL of the display panel 110 by a chip-on-glass (COG) process or automatic tape bonding (TAB). In some embodiments, the majority of the SDICs SDIC#1, SDIC#2, ..., SDIC#(m) can be implemented on the display panel 110 or on a separate circuit board and connected to the display panel 110.

[0043] Fig. Figure 2 is a diagram illustrating a plurality of active areas of the display device according to an embodiment of the present disclosure.

[0044] Each of the multiple active areas AA can be subdivided into a central active area CA and one or more active boundary areas EA.

[0045] The central active area CA refers to an area in which a plurality of pixel columns are arranged in a central section of a plurality of pixel columns that are arranged in each of the plurality of active areas AA.

[0046] Furthermore, the active border area EA refers to an area in which a plurality of pixel columns are arranged on an outer part of the plurality of pixel columns that are arranged in each of the plurality of active areas AA.

[0047] The boundary region EA can have an active front-boundary region FEA adjacent to a preceding active region AA, and an active back-boundary region BEA adjacent to a subsequent active region AA. That is, the active front-boundary region FEA of a given active region AA refers to a region in which a plurality of pixel columns are arranged on one side adjacent to the preceding active region AA, and a plurality of pixel columns are arranged in each of the plurality of active regions AA (e.g., arranged between the preceding active region AA(k-1) and the central active region CA of the given active region AA(k)).Furthermore, the active rear margin BEA of the given active area AA refers to an area in which a plurality of pixel columns are arranged on the other side adjacent to the next active area AA of a plurality of pixel columns arranged in each of the plurality of active areas AA (e.g. arranged between the central active area CA of the given active area AA(k) and the next active area AA(k+1)).

[0048] Thus, the rear boundary area BEA of the preceding active area AA can border the front boundary area FEA of the next active area AA. For example, the front boundary area FEA of the active area AA(k+1) borders the rear boundary area BEA of the active area AA(k). Similarly, the rear boundary area BEA of the active area AA(k-1) borders the front boundary area FEA of the active area AA(k).

[0049] For example, as in Fig. Figure 2 shows that in a k-th active region AA(k), a first pixel column up to a j-th pixel column is arranged in a k-th active front-edge region FEA(k). Furthermore, a j+1-th pixel column up to a 2j-th pixel column is arranged in a k-th central active region CA(k), and a 2j+1-th pixel column up to a 3j-th pixel column is arranged in a k-th active back-edge region BEA(k).

[0050] Similarly, in a k-1-th active region AA(k-1), the first pixel column to the j-th pixel column are arranged in a k-1-th active front-edge region FEA(k-1), the j+1-th pixel column to the 2j-th pixel column are arranged in a k-1-th central active region CA(k-1), and the 2j+1-th pixel column to the 3j-th pixel column are arranged in a k-1-th active rear-edge region BEA(k-1).

[0051] In the example of Fig. 2 The k-1th active rear edge region BEA(k-1) and the kth active rear edge region FEA(k) lie next to each other.

[0052] In some embodiments, the first active region AA1 has no preceding active region, so there is no first active front-edge region. Furthermore, the m-th active region AA(m), as the last active region, has no subsequent active region, so there is no m-th active rear-edge region.

[0053] Fig. Figure 3 is a diagram illustrating a time control device of the display device according to an embodiment of the present disclosure.

[0054] Fig. Figure 4 is a waveform diagram showing a subdata release signal and a boundary data release signal of the display device according to an embodiment of the present disclosure.

[0055] The time control device 140 comprises a data release signal generator 141, a data delay unit 142, a plurality of data comparison units 143 and a plurality of power control signal generators 144.

[0056] The data release signal generator 141 receives the DE and DCLK signals and outputs a sub-data release signal SDE and a marginal data release signal EDE to each data comparison unit 143 synchronously with the DE and DCLK signals.

[0057] For example, the data release signal generator outputs 141, as shown in the diagram of Fig. Figure 3 shows that a first subdata release signal SDE1 and a first boundary data release signal EDE1 are output to a first data comparison unit 143(1). Additionally, the data release signal generator 141 outputs an m-1th subdata release signal SDE(m-1) and an m-1th boundary data release signal EDE(m-1) to an m-1th data comparison unit 143(m-1). Furthermore, the data release signal generator 141 outputs an m-th subdata release signal SDE(m) and an m-th boundary data release signal EDE(m) to an m-th data comparison unit 143(m).

[0058] As in Fig. As shown in Figure 4, the first sub-data release signal SDE1 to the m-th sub-data release signal SDE(m) are signals that control the output timing of data voltages from the first SDIC SDIC#1 to the m-th SDIC SDIC#(m) to the first active area AA1 or to the m-th active area AA(m).

[0059] That is, as in Fig. As shown in Figure 2, a data voltage is applied to an nth pixel row for one horizontal period. Thus, the first sub-data enable signal SDE1 up to the m-th sub-data enable signal SDE(m) can be output sequentially within one horizontal period with an activation level (e.g., a high level).

[0060] As in Fig. As shown in Figure 4, the first sub-data release signal SDE1 has a turn-on level during the period from t1 to t3. Thus, the first SDIC SDIC#1 outputs a data voltage to a plurality of pixels PX located in an nth row of the first active area AA1 during the period from t1 to t3.

[0061] Furthermore, a second sub-data release signal SDE2 has a turn-on level during a period from t3 to t6. Thus, the second SDIC SDIC#2 outputs a data voltage to a plurality of pixels PX located in an nth row of the second active area AA2 during a period from t3 to t6.

[0062] Furthermore, the m-1th subdata enable signal SDE(m-1) has a turn-on level during a period from t(3m-6) to t(3m-3). Thus, an m-1th SDIC SDIC#(m-1) outputs a data voltage to a plurality of pixels PX located in an nth row of an m-1th active area AA(m-1) during the period from t(3m-6) to t(3m-3).

[0063] Furthermore, the m-th subdata enable signal SDE(m) has a turn-on level during a period from t(3m-3) to t(3m). Thus, the m-th SDIC SDIC# (m) outputs a data voltage to a plurality of pixels PX located in an n-th row of the m-th active area AA(m) during the period from t(3m-3) to t(3m).

[0064] As in Fig. As shown in Figure 4, the first boundary data release signal EDE1 to the m-th boundary data release signal EDE(m) are signals that control the output timing of data voltages from the first SDIC SDIC#1 to the m-th SDIC SDIC# (m) to the first active boundary area EA1 or to the m-th active boundary area EA(m).

[0065] In some embodiments, each data release signal EDE can have a front-edge data release signal FDE and a back-edge data release signal BDE.

[0066] However, as described above, the first active front-boundary region and the m-th active back-boundary region are not present. Therefore, a first front-boundary data release signal and an m-th back-boundary data release signal are not output.

[0067] More precisely, a second front-edge data release signal FDE2 up to an m-th front-edge data release signal FDE(m) are signals that control the output timing of data voltages from the second SDIC SDIC#2 up to the m-th SDIC SDIC#(m) to a second active front-edge region FEA2 or an m-th active front-edge region FEA(m), respectively. Furthermore, a first back-edge data release signal BDE1 up to an m-1-th back-edge data release signal BDE(m) are signals that control the output timing of data voltages from the first SDIC SDIC#1 up to the m-1-th SDIC SDIC#(m-1) to a first back-edge active region BEA1 or an m-th back-edge active region BEA(m-1), respectively.

[0068] As in Fig. As shown in Figure 4, the first data release signal BDE1 has a turn-on level during the period from t2 to t3. Therefore, the first SDIC SDIC#1 outputs a data voltage during the period from t2 to t3 to a plurality of pixels PX located in an nth row of the first active area BEA1 at the rear edge.

[0069] Furthermore, the second front-edge data release signal FDE2 has a turn-on level during a period from t3 to t4. Thus, the second SDIC SDIC#2 outputs a data voltage to a plurality of pixels PX located in an nth row of the second active front-edge region FEA2 during the period from t3 to t4.

[0070] Furthermore, a second rear-edge data release signal BDE2 has a turn-on level during a period from t5 to t6. Thus, the second SDIC SDIC#2 outputs a data voltage to a plurality of pixels PX located in an nth row of a second active rear-edge area BEA2 during the period from t5 to t6.

[0071] Furthermore, an m-1th front-edge data release signal FDE(m-1) has a turn-on level during a period from t(3m-6) to t(3m-5). Thus, the m-1th SDIC SDIC#(m-1) outputs a data voltage to a plurality of pixels PX located in an nth row of an m-1th active front-edge region FEA(m-1) during the period from t(3m-6) to t(3m-5).

[0072] Furthermore, an m-1th rear-edge data release signal BDE(m-1) has a turn-on level during a period from t(3m-4) to t(3m-3). Thus, the m-1th SDIC SDIC# (m-1) outputs a data voltage to a plurality of pixels PX located in an nth row of an m-1th active rear-edge region BEA(m-1) during the period from t(3m-4) to t(3m-3).

[0073] Furthermore, the m-th front-edge data release signal FDE(m)) has a turn-on level during a period from t(3m-3) to t(3m-2). Thus, the m-th SDIC SDIC#(m) outputs a data voltage to a plurality of pixels PX located in an n-th row of the m-th active front-edge region FEA(m) during the period from t(3m-3) to t(3m-2).

[0074] Go back to Fig. 3 receives the data delay unit 142, receives the video data and delays the video data by one horizontal period and then outputs the delayed video data.

[0075] The data delay unit 142 stores the video data in an internal memory and delays the video data by one horizontal period and then outputs the delayed video data D_data to each of the multiple data comparison units 143.

[0076] For example, the data delay unit 142 stores the video data corresponding to an nth row in an nth horizontal period and outputs the delayed video data D_Data corresponding to the nth row in an n+1-th horizontal period.

[0077] Furthermore, each of the multiple data comparison units 143 compares the video data and the delayed video data D_data corresponding to multiple active areas AA, while multiple sub-data release signals SDE have a turn-on level. Then, each of the multiple data comparison units 143 generates a multiple of comparison data CDs. In addition, each of the multiple data comparison units 143 outputs the comparison data CDs to the power control signal generators 144. In other words, the comparison data CDs can be the maximum data transition value between adjacent pixel rows located in each of the multiple active areas AA.

[0078] More precisely, the first data comparison unit 143(1) compares the video data and the delayed video data D_data corresponding to the first active area AA1 while the first sub-data release signal SDE1 has a turn-on level. Then, the first data comparison unit 143(1) outputs the maximum value of the difference between the video data and the delayed video data D_data as the first comparison data CD1.

[0079] Additionally, the m-1th data comparison unit 143(m-1) compares the video data and the delayed video data D_data corresponding to the m-1th active area AA(m-1), while the m-1th sub-data release signal SDE(m-1) has a turn-on level. Then, the m-1th data comparison unit 143(m-1) outputs the maximum value of the difference between the video data and the delayed video data D_data as the m-1th comparison data CD(m-1).

[0080] Furthermore, the m-th data comparison unit 143(m) compares the video data and the delayed video data D_data corresponding to the m-th active area AA(m), while the m-th sub-data release signal SDE(m) has a turn-on level. Then, the m-th data comparison unit 143(m) outputs the maximum value of the difference between the video data and the delayed video data D_data as the m-th comparison data CD(m).

[0081] For example, with reference to Fig. 4. The first sub-data release signal SDE1 emits a turn-on level during a time interval from t1 to t2. Thus, the maximum value of the difference between the video data and the delayed video data D_data, each corresponding to a plurality of pixel columns in the first active area AA1, is output as the first comparison data CD1 during the period from t1 to t2.

[0082] Furthermore, the m-1-th sub-data release signal SDE(m-1) has a turn-on level during a period from t(3m-6) to t(3m-3). Thus, the maximum value of the difference between the video data and the delayed video data D_data, each corresponding to a plurality of pixel columns in the m-1-th active area AA(m-1), is output as the m-1-th comparison data CD(m-1) during the period from t(3m-6) to t(3m-3).

[0083] Furthermore, the m-th sub-data release signal SDE(m) has a turn-on level during a period from t(3m-3) to t(3m). Thus, the maximum value of the difference between the video data and the delayed video data D_data, each corresponding to a plurality of pixel columns in the m-th active area AA(m), is output as the m-th comparison data CD(m) during the period from t(3m-3) to t(3m).

[0084] Furthermore, the plurality of data comparison units 143 compare the video data and the delayed video data D_data in a plurality of active edge regions EA, while a plurality of edge data enable signals EDE have a turn-on level. Then, the plurality of data comparison units 143 generate a plurality of edge comparison data ECD. In addition, the plurality of data comparison units 143 output the edge comparison data ECD to the power control signal generators 144. In other words, the edge comparison data ECD can be the maximum data transition value between adjacent pixel rows located in each of the plurality of active edge regions EA.

[0085] More precisely, the first data comparison unit 143(1) compares the video data and the delayed video data D_data corresponding to the first active boundary area EA1, while the first boundary data enable signal EDE1 has a turn-on level. Then, the first data comparison unit 143(1) outputs the maximum value of the difference between the video data and the delayed video data D_data as the first boundary comparison data ECD1.

[0086] Furthermore, the m-1th data comparison unit 143(m-1) compares the video data and the delayed video data D_data corresponding to an active m-1th active boundary area EA(m-1), while the m-1th boundary data enable signal EDE(m-1) has a turn-on level. Then, the m-1th data comparison unit 143(m-1) outputs the maximum value of the difference between the video data and the delayed video data D_data as the m-1th boundary comparison data ECD(m-1).

[0087] Furthermore, the m-th data comparison unit 143(m) compares the video data and the delayed video data D_data corresponding to the m-th active boundary area EA(m), while the m-th boundary data enable signal EDE(m) has a turn-on level. The m-th data comparison unit 143(m) then outputs the maximum value of the difference between the video data and the delayed video data D_data as the m-th boundary comparison data ECD(m).

[0088] For example, referring to Fig. 4. The first rear edge data release signal BDE1 reaches a turn-on level during a period from t2 to t3. Therefore, the video data and the delayed video data D_data corresponding to the first active rear edge area BEA1 are compared. Then, the maximum value of the difference between the video data and the delayed video data D_data is output as the first edge comparison data ECD1.

[0089] Furthermore, the m-1 front edge data release signal FDE(m-1) has a turn-on level during a period from t(3m-6) to t(3m-5). Therefore, the video data and the delayed video data D_data corresponding to the m-1 active front edge area FEA(m-1) are compared. Then, the maximum value of the difference between the video data and the delayed video data D_data is output as the m-1 edge comparison data ECD(m-1).

[0090] Furthermore, the m-1 rear edge data release signal BDE(m-1) has a turn-on level during a period from t(3m-4) to t(3m-3). Therefore, the video data and the delayed video data D_data corresponding to the m-1 active rear edge area BEA(m-1) are compared. Then, the maximum value of the difference between the video data and the delayed video data D_data is output as the m-1 edge comparison data ECD(m-1).

[0091] Furthermore, the m-th front edge data release signal FDE(m) has a turn-on level during a period from t(3m-3) to t(3m-2). Therefore, the video data and the delayed video data D_data corresponding to the m-th active front edge area FEA(m) are compared. Subsequently, the maximum value of the difference between the video data and the delayed video data D_data is output as the m-th edge comparison data ECD(m).

[0092] In some embodiments, each of the multiple data comparison units 143 outputs the generated comparison data CD and edge comparison data ECD to the power control signal generator 144 corresponding to an active area, and to the power control signal generator 144 corresponding to one or more adjacent active areas.

[0093] In particular, the first data comparator 143(1) outputs the first comparator data CD1 and the first edge comparator data ECD1 to a first power control signal generator 144(1), which corresponds to a first active area AA1. Furthermore, the first data comparator 143(1) outputs the first comparator data CD1 and the first edge comparator data ECD1 to a second power control signal generator, which corresponds to a second active area AA2 adjacent to the first active area AA1.

[0094] Furthermore, the m-1th data comparison unit 143(m-1) outputs the m-1th comparison data CD(m-1) and the m-1th edge comparison data ECD(m-1) to an m-1th power control signal generator 144(m-1), which corresponds to an m-1th active area AA(m-1). Additionally, the m-1th data comparison unit 143(m-1) outputs the m-1th comparison data CD(m-1) and the m-1th edge comparison data ECD(m-1) to an m-2th power control signal generator 144(m-2), which corresponds to an m-2th active area AA(m-2) adjacent to the m-1th active area AA(m-1). Furthermore, the m-1th data comparison unit 143(m-1) outputs the m-1th comparison data CD(m-1) and the m-1th edge comparison data ECD(m-1) to an m-th power control signal generator 144(m), which corresponds to an m-th active area AA(m) adjacent to the m-1th active area AA(m-1).

[0095] Furthermore, the m-th data comparison unit 143(m) outputs the m-th comparison data CD(m) and the m-th edge comparison data ECD(m) to the m-th power control signal generator 144(m), which corresponds to the m-th active area AA(m). Additionally, the m-th data comparison unit 143(m) outputs the m-th comparison data CD(m) and the m-th edge comparison data ECD(m) to the m-1-th power control signal generator 144(m-1), which corresponds to an m-1-th active area AA(m-1) adjacent to the m-th active area AA(m).

[0096] Fig. Figure 5 shows a lookup table (LUT) of a power control signal generator of the display device according to an embodiment of the present disclosure.

[0097] The power control signal generators 144 generate power control signals PWRC using the reference data CD and the boundary reference data ECD.

[0098] In particular, each of the power control signal generators 144 sets a first reference value SV1 for each of the received plurality of comparison data CDs by applying each of the received plurality of comparison data CDs to a first lookup table 1. LUT.

[0099] Furthermore, each of the power control signal generators 144 sets a second reference value SV2 for each of the received plurality of boundary comparison data ECD by applying each of the received plurality of boundary comparison data ECD to a second lookup table 2. LUT.

[0100] In addition, the power control signal generators 144 establish a compensation value CV by calculating a difference value DV between a first reference value SV1 of an active area and a second reference value SV2 of an adjacent active boundary area and applying the difference value DV to a third lookup table 3. LUT.

[0101] Furthermore, the power control signal generators 144 add the compensation value CV to the first reference value SV1 of the active area and output a result as a power control signal PWRC.

[0102] With reference to Fig. 3 and Fig. 5. Each power control signal generator 144 (such as the first power control signal generator 144(1), the m-1th power control signal generator 144(m-1), and the m-th power control signal generator 144(m)) sets the first reference value SV1 by comparing the comparison data CD with a plurality of thresholds stored in the first lookup table 1. LUT. For example, if the comparison data CD is equal to or less than a first threshold Th 1, the first reference value SV1 is set to 0 (LLL). If the comparison data CD is greater than the first threshold Th 1 and equal to or less than a second threshold Th 2, the first reference value SV1 is set to 1 (LLH). If the comparison data CD is greater than the second threshold Th 2 and equal to or less than a third threshold Th 3, the first reference value SV1 is set to 1 (LLH).If the comparison data CD is greater than the third threshold Th 3 and equal to or less than a fourth threshold Th 4, the first reference value SV1 is set to 2 (LHL). If the comparison data CD is greater than the fourth threshold Th 4 and equal to or less than a fifth threshold Th 5, the first reference value SV1 is set to 2 (LHL). If the comparison data CD is greater than the fifth threshold Th 5 and equal to or less than a sixth threshold Th 6, the first reference value SV1 is set to 3 (LHH). If the comparison data CD is greater than the sixth threshold Th 6 and equal to or less than a seventh threshold Th 7, the first reference value SV1 is set to 4 (HLL). If the comparison data CD is greater than the seventh threshold Th 7 and equal to or less than an eighth threshold Th 8, the first reference value SV1 is set to 4 (HLL).If the comparison data CD is greater than the eighth threshold Th 8, the first reference value SV1 is set to 4 (HLL). The first threshold Th 1 to the eighth threshold Th 8 described above are values ​​stored in a memory of each of the power control signal generators 144 (e.g., the first power control signal generator 144(1), the m-1-th power control signal generator 144(m-1), and the m-th power control signal generator 144(m)). The first threshold Th 1 to the eighth threshold Th 8 described above can vary depending on the setting.

[0103] Additionally, each power control signal generator 144 (such as the first power control signal generator 144(1), the m-1th power control signal generator 144(m-1), and the m-th power control signal generator 144(m)) sets the second reference value SV2 by comparing the boundary reference data ECD with a plurality of thresholds stored in the second lookup table 2. LUT. For example, if the boundary reference data ECD is equal to or less than the first threshold Th1, the second reference value SV2 is set to 0 (LLL). If the boundary reference data ECD is greater than the first threshold Th1 and equal to or less than the second threshold Th2, the second reference value SV2 is set to 1 (LLH). If the boundary reference data ECD is greater than the second threshold Th2 and equal to or less than the third threshold Th3, the second reference value SV2 is set to 1 (LLH).If the marginal reference data ECD is greater than the third threshold Th3 and equal to or less than the fourth threshold Th4, the second reference value SV2 is set to 2 (LHL). If the marginal reference data ECD is greater than the fourth threshold Th4 and equal to or less than the fifth threshold Th5, the second reference value SV2 is set to 2 (LHL). If the marginal reference data ECD is greater than the fifth threshold Th5 and equal to or less than the sixth threshold Th6, the second reference value SV2 is set to 3 (LHH). If the marginal reference data ECD is greater than the sixth threshold Th6 and equal to or less than the seventh threshold Th7, the second reference value SV2 is set to 4 (HLL). If the marginal comparison data ECD are greater than the seventh threshold Th 7 and equal to or less than the eighth threshold Th 8, the second reference value SV2 is set to 4 (HLL).If the boundary comparison data ECD is greater than the eighth threshold Th8, the second reference value SV2 is set to 4 (HLL). The first threshold Th1 to the eighth threshold Th8 described above are values ​​stored in the memory of the first power control signal generator 144(1), the m-1st power control signal generator 144(m-1), and the m-th power control signal generator 144(m), respectively. The values ​​of the first threshold Th1 to the eighth threshold Th8 described above can vary depending on the setting.

[0104] Then, each power control signal generator 144 (e.g., the first power control signal generator 144(1), the m-1th power control signal generator 144(m-1), and the m-th power control signal generator 144(m)) calculates the difference value DV between the first reference value SV1, which corresponds to an active area, and the second reference value SV2, which corresponds to an adjacent active area. Then, each power control signal generator (e.g., the first power control signal generator 144(1), the m-1th power control signal generator 144(m-1), and the m-th power control signal generator 144(m)) sets a compensation value CV by applying the difference value DV to the third lookup table 3. LUT.

[0105] More precisely, if the difference value DV between the first reference value SV1, corresponding to the active area, and the second reference value SV2, corresponding to the adjacent active area, is 0 (LLL), the compensation value CV is set to 0 (LLL). If the difference value DV between the first reference value SV1, corresponding to the active area, and the second reference value SV2, corresponding to the adjacent active boundary area, is 1 (LLH), the compensation value CV is set to 0 (LLL). If the difference value DV between the first reference value SV1, corresponding to the active area, and the second reference value SV2, corresponding to the adjacent active boundary area, is 2 (LHL), the compensation value CV is set to 1 (LLH).If the difference value DV between the first reference value SV1, corresponding to the active area, and the second reference value SV2, corresponding to the adjacent active boundary area, is 3 (LHH), the compensation value CV is set to 1 (LLH). If the difference value DV between the first reference value SV1, corresponding to the active area, and the second reference value SV2, corresponding to the adjacent active boundary area, is 3 (LHH), the compensation value CV is set to 1 (LLH). If the difference value DV between the first reference value SV1, corresponding to the active area, and the second reference value SV2, corresponding to the adjacent active boundary area, is 4 (HLL), the compensation value CV is set to 2 (LHL).

[0106] Furthermore, each power control signal generator 144 (e.g. the first power control signal generator 144(1), the m-1th power control signal generator 144(m-1) and the m-th power control signal generator 144(m)) adds the compensation value CV to the first reference value SV1 and outputs a result as a power control signal PWRC.

[0107] For example, the first power control signal generator 144(1) sets the compensation value CV as a function of the difference value DV between the first reference value SV1, corresponding to the first active boundary region, and the second reference value SV2, corresponding to the second active front boundary region. Then, the first power control signal generator 144(1) adds the compensation value CV to the first reference value SV1, corresponding to the first active region, and outputs a result as a first power control signal PWRC1.

[0108] The m-1th power control signal generator 144(m-1) sets the compensation value CV as a function of the difference value DV between the first reference value SV1, corresponding to the m-1th active area, and the second reference value SV2, corresponding to the m-1st active front edge area. The m-1th power control signal generator 144(m-1) then adds the compensation value CV to the first reference value SV1, corresponding to the m-1st active area, and outputs a result as the m-1th power control signal PWRC(m-1).

[0109] The m-th power control signal generator 144(m) sets the compensation value CV as a function of the difference value DV between the first reference value SV1, corresponding to the m-th active area, and the second reference value SV2, corresponding to the m-1-th active rear edge area. The m-th power control signal generator 144(m) then adds the compensation value CV to the first reference value SV1, corresponding to the m-th active area, and outputs a result as an m-th power control signal PWRC(m).

[0110] For example, if the first reference value SV1, corresponding to the m-th active region, is replaced by 0 (LLL), and the second reference value SV2, corresponding to the m-1-th active rear-edge region, is replaced by 4 (HLL), the difference value DV is 4 (HLL). Thus, the compensation value CV can be 2 (LHL). Accordingly, the m-th power control signal generator can add 144(m) 2 (LHL), which is the compensation value CV, to 0 (LLL), which is the first reference value SV1 corresponding to the m-th active region, and output 2 (LHL) as the m-th power control signal PWRC(m).

[0111] Fig. Figure 6 is a diagram illustrating an integrated source driver circuit (SDIC) of the display device according to an embodiment of the present disclosure.

[0112] Each of several SDICs contains a shift register 131, a latch unit 132, a digital-to-analog converter (DAC) 133, a buffer 134 and a power control circuit 135.

[0113] The shift register 131 receives data control signals DCS including a source start pulse and a source sampling clock from the timing control unit 140 and determines the times for sequential data sampling.

[0114] The latch unit 132 sequentially stores red, green and blue digital video data sent by the timing control unit 140 in response to a sampling signal transmitted by the shift register 131, and outputs the stored data simultaneously.

[0115] The DAC 133 converts the red, green and blue digital video data from the latch unit 132 into an analog data voltage Vdata by using an analog gamma voltage.

[0116] The buffer 134 can output the analog data voltage Vdata transmitted by the DAC 133 onto a data line.

[0117] The power control circuit (PWRC circuit) 135 is switched in response to a power control signal PWRC transmitted by the time control device 140 and controls the current supplied to the buffer 134. Thus, the PWRC circuit 135 can control the power consumption of the data driver.

[0118] Fig. Figure 7 is a circuit diagram showing a power control circuit and a buffer of the display device according to an embodiment of the present disclosure.

[0119] Referring to Fig. 7, buffer 134 can be set up by at least one working amplifier and arranged according to each of the multiple data lines DL.

[0120] Buffer 134 can amplify and output the analog data voltage Vdata received via a non-inverting input terminal +. Additionally, an inverting input terminal - of buffer 134 is connected to a data line DL, which is connected to an output terminal. A terminal V CC Buffer 134 is connected to a driver power supply VDD, and a terminal V EE is connected to the power control circuit 135.

[0121] The power control circuit 135 determines the magnitude of the drive current I to be applied to the buffer 134. SUM .

[0122] The PWRC circuit 135 features a plurality of current sources I1, ... , I7, I8, a plurality of switches SW1, ... , SW7, SW8 and a current mirror circuit with a first mirror transistor MT1 and a second mirror transistor MT2.

[0123] Each of the multiple switches SW1, ... , SW7, SW8 is connected in series with a corresponding current source from the majority of the current sources I1, ... , I7, I8. Furthermore, all switches SW1, ... , SW7, SW8 that are connected in series with a corresponding current source are connected in parallel to each other. Therefore, the magnitude of the driver current I to be output to the current mirror circuit is SUM determined depending on the on state of the several switches SW1, ... , SW7, SW8.

[0124] The first mirror transistor MT1 and the second mirror transistor MT2 form a current mirror circuit.

[0125] A gate electrode and a source electrode of the first mirror transistor MT1 are connected to a plurality of switches and are supplied with the driver current I SUM provided.

[0126] Furthermore, a gate electrode of the second mirror transistor MT2 is connected to the gate electrode of the first mirror transistor MT1. A drain electrode of the second mirror transistor MT2 is connected to terminal V. EE connected to buffer 134.

[0127] Thus, a source-drain current of the second mirror transistor MT2 is used as the driver current I. SUM determined. In addition, the driver current I output by the second mirror transistor MT2 is determined. SUM to connection V EE Buffer 134 output.

[0128] Accordingly, the power control circuit 135 controls a gain ratio of the buffer 134 in order to control the power consumption of the buffer 134.

[0129] As described above, the display device, according to one embodiment of the present disclosure, generates a power control signal depending on a difference value between reference data, which is the maximum data transition value between adjacent pixel rows located in each of a plurality of active areas, and edge reference data, which is the maximum data transition value between adjacent pixel rows located in a plurality of active edge areas. In this way, it is possible to control the intensity of a driver current of a plurality of SDICs.

[0130] The level of the data transition in an active boundary region is applied to the intensity of a driver current. Therefore, if data voltages are applied to multiple active regions to represent the same grayscale, it is possible to suppress a defect, such as block darkening at a boundary.

[0131] Furthermore, according to one embodiment of the present disclosure, the display device can adjust the intensity of a driver current of a plurality of SDICs by using comparison data that represents the maximum data transition value between adjacent pixel rows located in each of a plurality of active areas. In this way, it is possible to set an optimal driver current intensity for each active area.

[0132] Therefore, it is possible to determine an optimal drive power for each active area and thus optimize the power consumption of the display device according to an embodiment of the present disclosure.

[0133] The following describes a control method for a display device according to an embodiment of the present disclosure. The control method for a display device according to an embodiment of the present disclosure is described with reference to the display device described above according to an embodiment of the present disclosure.

[0134] Fig. Figure 8 is a flowchart to illustrate a control method for a display device according to an embodiment of the present disclosure.

[0135] As in Fig. Figure 8 shows that a control method S100 of a display device according to an embodiment of the present disclosure comprises a data release signal generation process S110, a data delay process S120, and a data comparison process S130. Furthermore, the control method S100 comprises a first reference value setting process S140, a second reference value setting process S150, a compensation value calculation process S160, and a power control signal output process S170.

[0136] In the data release signal generation process S110, a sub-data release signal SDE and a boundary data release signal EDE are generated synchronously with the DE and the DCLK.

[0137] As in Fig. As shown in Figure 4, the first sub-data release signal SDE1 to the m-th sub-data release signal SDE(m) are signals that control the output timing of data voltages from the first SDIC SDIC#1 to the m-th SDIC SDIC# (m) to the first active area AA1 or to the m-th active area AA(m).

[0138] That is, referring to Fig. 2. A data voltage is applied to an nth pixel row for one horizontal period. Thus, the first sub-data enable signal SDE1 up to the m-th sub-data enable signal SDE(m) can be output successively at a high level, i.e., a turn-on level, within one horizontal period.

[0139] Specifically, with regard to Fig. 4, the first subdata enable signal SDE1 has a turn-on level during a period from t1 to t3. Thus, the first SDIC SDIC#1 outputs a data voltage to a plurality of pixels PX located in an nth row of the first active area AA1 during the period from t1 to t3.

[0140] Furthermore, a second sub-data release signal SDE2 has a turn-on level during a period from t3 to t6. Thus, the second SDIC SDIC#2 outputs a data voltage to a plurality of pixels PX located in an nth row of the second active area AA2 during the period from t3 to t6.

[0141] Furthermore, the m-1th subdata enable signal SDE(m-1) has a turn-on level during a period from t(3m-6) to t(3m-3). Thus, an m-1th SDIC SDIC#(m-1) outputs a data voltage to a plurality of pixels PX located in an nth row of an m-1th active area AA(m-1) during the period from t(3m-6) to t(3m-3).

[0142] Furthermore, the m-th subdata enable signal SDE(m) has a turn-on level during a period from t(3m-3) to t(3m). Thus, the m-th SDIC SDIC# (m) outputs a data voltage to a plurality of pixels PX located in an n-th row of the m-th active area AA(m) during the period from t(3m-3) to t(3m).

[0143] Also, with reference to Fig. 4, the first boundary data release signal EDE1 to the m-th boundary data release signal EDE(m) signals that control an output timing of data voltages from the first SDIC SDIC#1 to the m-th SDIC SDIC#(m) to the first active boundary area EA1 or to the m-th active boundary area EA(m).

[0144] A plurality of data release signals EDE can include a plurality of front-edge data release signals FDA and a plurality of back-edge data release signals BDE.

[0145] However, as described above, the first active front-boundary region and the m-th active back-boundary region are not present. Therefore, a first front-boundary data release signal and an m-th back-boundary data release signal are not output.

[0146] More precisely, a second front-edge data release signal FDE2 up to an m-th front-edge data release signal FDE(m) are signals that control the output timing of data voltages from the second SDIC SDIC#2 up to the m-th SDIC SDIC#(m) to a second active front-edge area FEA2 or an m-th active front-edge area FEA(m). Furthermore, a first back-edge data release signal BDE1 up to an m-1-th back-edge data release signal BDE(m) are signals that control the output timing of data voltages from the first SDIC SDIC#1 up to the m-1-th SDIC SDIC#(m-1) to a first back-edge active area BEA1 or to an m-th back-edge active area BEA(m-1).

[0147] As in Fig. As shown in Figure 4, the first data release signal BDE1 has a turn-on level during the period from t2 to t3. Therefore, the first SDIC SDIC#1 outputs a data voltage during the period from t2 to t3 to a plurality of pixels PX located in an nth row of the first active area BEA1 at the rear edge.

[0148] Furthermore, the second front-edge data release signal FDE2 has a turn-on level during a period from t3 to t4. Thus, the second SDIC SDIC#2 outputs a data voltage to a plurality of pixels PX located in an nth row of the second active front-edge region FEA2 during the period from t3 to t4.

[0149] Furthermore, a second rear-edge data release signal BDE2 has a turn-on level during a period from t5 to t6. Thus, the second SDIC SDIC#2 outputs a data voltage to a plurality of pixels PX located in an nth row of a second active rear-edge area BEA2 during the period from t5 to t6.

[0150] Furthermore, an m-1th front-edge data release signal FDE(m-1) has a turn-on level during a period from t(3m-6) to t(3m-5). Thus, the m-1th SDIC SDIC#(m-1) outputs a data voltage to a plurality of pixels PX located in an nth row of an m-1th active front-edge region FEA(m-1) during the period from t(3m-6) to t(3m-5).

[0151] Furthermore, an m-1th rear-edge data release signal BDE(m-1) has a turn-on level during a period from t(3m-4) to t(3m-3). Thus, the m-1th SDIC SDIC# (m-1) outputs a data voltage to a plurality of pixels PX located in an nth row of an m-1th active rear-edge region BEA(m-1) during the period from t(3m-4) to t(3m-3).

[0152] Furthermore, the m-th front-edge data release signal FDE(m) has a turn-on level during a period from t(3m-3) to t(3m-2). Thus, the m-th SDIC SDIC#(m) outputs a data voltage to a plurality of pixels PX located in an n-th row of the m-th active front-edge region FEA(m) during the period from t(3m-3) to t(3m-2).

[0153] In the S120 data delay process, the video data is received, delayed by one horizontal period, and then output.

[0154] In the S120 data delay process, the video data is stored in an internal memory and delayed by one horizontal period, and then the delayed video data D_Data is output.

[0155] For example, the video data corresponding to an nth line is stored in an n-1th horizontal period, and the delayed video data corresponding to the nth line is output in an n+1th horizontal period.

[0156] Furthermore, in the data comparison process S130, the video data and the delayed video data D_data, corresponding to a plurality of active areas AA, are compared while a plurality of sub-data release signals SDE have a turn-on level. Then, all respective comparison data CDs are generated. In other words, the comparison data CDs can be the maximum data transition value between adjacent pixel rows located in each of the multiple active areas AA.

[0157] More precisely, in the data comparison process S130, the video data and the delayed video data D_Data, corresponding to the first active area AA1, are compared while the first sub-data release signal SDE1 has a turn-on level. Then, the maximum value of the difference between the video data and the delayed video data D_Data is output as the first comparison data CD1.

[0158] Furthermore, in the data comparison process S130, the video data and the delayed video data D_data corresponding to the m-1th active area AA(m-1) are compared, since the m-1th sub-data enable signal SDE(m-1) has a turn-on level. The maximum value of the difference between the video data and the delayed video data D_data is then output as the m-1th comparison data CD(m-1).

[0159] Furthermore, in the data comparison process S130, the video data and the delayed video data D_data, corresponding to the m-th active area AA(m), are compared, since the m-th sub-data enable signal SDE(m) has a turn-on level. The maximum value of the difference between the video data and the delayed video data D_data is then output as the m-th comparison data CD(m).

[0160] For example, referring to Fig. 4. The first sub-data release signal SDE1 emits a turn-on level during a time interval from t1 to t2. Thus, the maximum value of the difference between the video data and the delayed video data D_data, each corresponding to a plurality of pixel columns in the first active area AA1, is output as the first comparison data CD1 during the period from t1 to t2.

[0161] Additionally, the m-1-th sub-data release signal SDE(m-1) has a turn-on level during a period from t(3m-6) to t(3m-3). Thus, the maximum value of the difference between the video data and the delayed video data D_data, each corresponding to a plurality of pixel columns in the m-1-th active area AA(m-1), is output as the m-1-th comparison data CD(m-1) during the period from t(3m-6) to t(3m-3).

[0162] Furthermore, the m-th sub-data release signal SDE(m) has a turn-on level during a period from t(3m-3) to t(3m). Thus, the maximum value of the difference between the video data and the delayed video data D_data, each corresponding to a plurality of pixel columns in the m-th active area AA(m), is output as the m-th comparison data CD(m) during the period from t(3m-3) to t(3m).

[0163] Furthermore, in the data comparison process S130, the video data and the delayed video data D_data are compared in a plurality of active edge regions EA, while a plurality of edge data release signals EDE have a turn-on level. Then, a plurality of edge comparison data ECD is generated. In other words, the edge comparison data ECD can be the maximum data transition value between adjacent pixel rows located in each of the plurality of active edge regions EA.

[0164] More precisely, in the data comparison process S130, the video data and the delayed video data D_Data, corresponding to the first active boundary area EA1, are compared while the first boundary data enable signal EDE1 has a turn-on level. Then, the maximum value of the difference between the video data and the delayed video data D_Data is output as the first boundary comparison data ECD1.

[0165] Additionally, in the data comparison process S130, the video data and the delayed video data D_Data, corresponding to an m-1th active boundary area EA(m-1), are compared, while the m-1th boundary data enable signal EDE(m-1) has a turn-on level. The maximum value of the difference between the video data and the delayed video data D_Data is then output as the m-1th boundary comparison data ECD(m-1).

[0166] Furthermore, in the data comparison process S130, the video data and the delayed video data D_Data, corresponding to the m-th active boundary area EA(m), are compared, while the m-th boundary data enable signal EDE(m) has a turn-on level. The maximum value of the difference between the video data and the delayed video data D_Data is then output as the m-th boundary comparison data ECD(m).

[0167] For example, with reference to Fig. 4. The first rear-edge data release signal BDE1 reaches a turn-on level during a period from t2 to t3. Therefore, the video data and the delayed video data D_data corresponding to the first active front-edge area BEA1 are compared. Then, the maximum value of the difference between the video data and the delayed video data D_data is output as the first edge comparison data ECD1.

[0168] Furthermore, the m-1 front edge data release signal FDE(m-1) has a turn-on level during a period from t(3m-6) to t(3m-5). Therefore, the video data and the delayed video data D_data corresponding to the m-1 active front edge area FEA(m-1) are compared. Then, the maximum value of the difference between the video data and the delayed video data D_data is output as the m-1 edge comparison data ECD(m-1).

[0169] Furthermore, the m-1 rear edge data release signal BDE(m-1) has a turn-on level during a period from t(3m-4) to t(3m-3). Therefore, the video data and the delayed video data D_data corresponding to the m-1 active rear edge area BEA(m-1) are compared. Then, the maximum value of the difference between the video data and the delayed video data D_data is output as the m-1 edge comparison data ECD(m-1).

[0170] Furthermore, the m-th front edge data release signal FDE(m) has a turn-on level during a period from t(3m-3) to t(3m-2). Therefore, the video data and the delayed video data D_data corresponding to the m-th active front edge area FEA(m) are compared. Subsequently, the maximum value of the difference between the video data and the delayed video data D_data is output as the m-th edge comparison data ECD(m).

[0171] In the first reference value setting process S140, the first reference value SV1 is set by comparing the reference data CD with a plurality of thresholds stored in the first lookup table 1. LUT. For example, if the reference data CD is equal to or less than a first threshold Th 1, the first reference value SV1 is set to 0 (LLL). If the reference data CD is greater than the first threshold Th 1 and equal to or less than a second threshold Th 2, the first reference value SV1 is set to 1 (LLH). If the reference data CD is greater than the second threshold Th 2 and equal to or less than a third threshold Th 3, the first reference value SV1 is set to 1 (LLH). If the reference data CD is greater than the third threshold Th 3 and equal to or less than a fourth threshold Th 4, the first reference value SV1 is set to 2 (LHL).If the comparison data CD is greater than the fourth threshold Th 4 and equal to or less than a fifth threshold Th 5, the first reference value SV1 is set to 2 (LHL). If the comparison data CD is greater than the fifth threshold Th 5 and equal to or less than a sixth threshold Th 6, the first reference value SV1 is set to 3 (LHH). If the comparison data CD is greater than the sixth threshold Th 6 and equal to or less than a seventh threshold Th 7, the first reference value SV1 is set to 4 (HLL). If the comparison data CD is greater than the seventh threshold Th 7 and equal to or less than an eighth threshold Th 8, the first reference value SV1 is set to 4 (HLL). If the comparison data CD is greater than the eighth threshold Th 8, the first reference value SV1 is set to 4 (HLL).The first threshold Th1 to the eighth threshold Th8 described above are values ​​stored in a memory of each power control signal generator 144 (e.g., the first power control signal generator 144(1), the m-1-th power control signal generator 144(m-1), and the m-th power control signal generator 144(m)). The values ​​of the first threshold Th1 to the eighth threshold Th8 described above can vary depending on the setting.

[0172] Furthermore, in the second reference value setting process S150, the second reference value SV2 is set by comparing the marginal reference data ECD with a plurality of thresholds stored in the second lookup table 2. LUT. For example, if the marginal reference data ECD is equal to or less than the first threshold Th 1, the second reference value SV2 is set to 0 (LLL). If the marginal reference data ECD is greater than the first threshold Th 1 and equal to or less than the second threshold Th 2, the second reference value SV2 is set to 1 (LLH). If the marginal reference data ECD is greater than the second threshold Th 2 and equal to or less than the third threshold Th 3, the second reference value SV2 is set to 1 (LLH). If the marginal reference data ECD is greater than the third threshold Th 3 and equal to or less than the fourth threshold Th 4, the second reference value SV2 is set to 2 (LHL).If the marginal reference data ECD is greater than the fourth threshold Th4 and equal to or less than the fifth threshold Th5, the second reference value SV2 is set to 2 (LHL). If the marginal reference data ECD is greater than the fifth threshold Th5 and equal to or less than the sixth threshold Th6, the second reference value SV2 is set to 3 (LHH). If the marginal reference data ECD is greater than the sixth threshold Th6 and equal to or less than the seventh threshold Th7, the second reference value SV2 is set to 4 (HLL). If the marginal reference data ECD is greater than the seventh threshold Th7 and equal to or less than the eighth threshold Th8, the second reference value SV2 is set to 4 (HLL). If the marginal reference data ECD is greater than the eighth threshold Th8, the second reference value SV2 is set to 4 (HLL).The thresholds Th1 through Th8 described above are values ​​stored in the memory of each power control signal generator 144 (e.g., the first power control signal generator 144(1), the m-1th power control signal generator 144(m-1), and the m-th power control signal generator 144(m)). These thresholds can vary depending on the settings.

[0173] Then, in the compensation value calculation process S160, the difference value DV between the first reference value SV1, which corresponds to an active area, and the second reference value SV2, which corresponds to an adjacent active area, is calculated. A compensation value CV is then set by applying the difference value DV to the third lookup table (3rd LUT).

[0174] More precisely, in the compensation value calculation process S160, the compensation value CV is set to 0 (LLL) if the difference value DV between the first reference value SV1, corresponding to the active area, and the second reference value SV2, corresponding to the adjacent active boundary area, is 0 (LLL). If the difference value DV between the first reference value SV1, corresponding to the active area, and the second reference value SV2, corresponding to the adjacent active boundary area, is 1 (LLH), the compensation value CV is set to 0 (LLL). If the difference value DV between the first reference value SV1, corresponding to the active area, and the second reference value SV2, corresponding to the adjacent active boundary area, is 2 (LHL), the compensation value CV is set to 1 (LLH).If the difference value DV between the first reference value SV1, corresponding to the active area, and the second reference value SV2, corresponding to the adjacent active boundary area, is 3 (LHH), the compensation value CV is set to 1 (LLH). If the difference value DV between the first reference value SV1, corresponding to the active area, and the second reference value SV2, corresponding to the adjacent active boundary area, is 3 (LHH), the compensation value CV is set to 1 (LLH). If the difference value DV between the first reference value SV1, corresponding to the active area, and the second reference value SV2, corresponding to the adjacent active boundary area, is 4 (HLL), the compensation value CV is set to 2 (LHL).

[0175] Furthermore, in the power control signal output process S170, the compensation value CV is added to the first reference value SV1, and a result is output as the power control signal PWRC.

[0176] For example, in the power control signal output process S170, the compensation value CV is determined based on the difference value DV between the first reference value SV1, corresponding to the first active area, and the second reference value SV2, corresponding to the second active front-edge area. The compensation value CV is then added to the first reference value SV1, and the result is output as a first power control signal PWRC1.

[0177] In the power control signal output process S170, the compensation value CV is set depending on the difference value DV between the first reference value SV1, corresponding to the m-1-th active area, and the second reference value SV2, corresponding to the m-1-th active front-edge area. The compensation value CV is then added to the first reference value SV1, and the result is output as the m-1-th power control signal PWRC(m-1).

[0178] In process S170 for the output of the power control signal, the compensation value CV is set depending on the difference value DV between the first reference value SV1, corresponding to the m-th active area, and the second reference value SV2, corresponding to the m-1-th active rear edge area. The compensation value CV is then added to the first reference value SV1, corresponding to the m-th active area, and the result is output as an m-th power control signal PWRC(m).

[0179] Specifically, if the first reference value SV1, corresponding to the m-th active region, is replaced by 0 (LLL), and the second reference value SV2, corresponding to the m-1-th active rear-edge region, is replaced by 4 (HLL), the difference value DV is 4 (HLL). Thus, the compensation value CV can be 2 (LHL). Accordingly, the m-th power control signal generator 144(m) can add 2 (LHL), which is the compensation value CV, to 0 (LLL), which is the first reference value SV1 corresponding to the m-th active region, and output 2 (LHL) as the m-th power control signal PWRC(m).

[0180] Accordingly, the gain ratio of buffer 134 of an integrated source driver circuit SDIC is controlled as a function of a power control signal PWRC in order to control the power consumption of buffer 134 of the SDIC.

[0181] As described above, in the control method of a display device according to an embodiment of the present disclosure, a power control signal is generated depending on a difference value between comparison data, which is the maximum data transition value between adjacent pixel rows arranged in each of a plurality of active areas, and edge comparison data, which is the maximum data transition value between adjacent pixel rows arranged in a plurality of active edge areas. In this way, it is possible to control the intensity of a driver current for a plurality of SDICs.

[0182] The level of the data transition in an active boundary region is applied to the intensity of a driver current. Therefore, if data voltages are applied to multiple active regions to represent the same grayscale, it is possible to suppress a defect, such as block darkening, at one boundary.

[0183] Furthermore, in the control method of a display device according to an embodiment of the present disclosure, it is possible to adjust the intensity of a driver current of a plurality of SDICs using comparison data, which is the maximum data transition value between adjacent pixel rows arranged in each of a plurality of active areas. In this way, it is possible to set an optimal driver current intensity for each active area.

[0184] Therefore, it is possible to determine an optimal drive power for each active area and thus optimize the power consumption of the display device according to an embodiment of the present disclosure.

[0185] The embodiments of the present disclosure can also be described as follows:

[0186] According to one aspect of the present disclosure, a display device includes a display panel divided into a plurality of active areas. Furthermore, the display device includes a data driver configured to supply data voltages to a plurality of pixels arranged in each of the plurality of active areas. The display device also includes a timing device configured to output a power control signal to control a driver current supplied to the data driver.Each active region is subdivided into a central active region, in which a plurality of pixel columns are arranged in a central section of the plurality of pixel columns arranged in the active regions, and into one or more active periphery regions, in which a plurality of pixel columns are arranged in an outer section of the plurality of pixel columns arranged in the active region. The data driver comprises a plurality of integrated source driver circuits (SDICs), each of which is configured to supply at least one of the data voltages to one of the plurality of active regions.The timing unit generates the power control signal based on a difference between reference data, which represents the maximum data transition value between adjacent pixel rows located in each of the multiple active areas, and edge reference data, which represents the maximum data transition value between adjacent pixel rows located in the multiple active edge areas. This makes it possible to improve image quality at the boundary between the active areas.

[0187] The timing control device may include a data release signal generator configured to produce a sub-data release signal configured to control the output timing of a data voltage supplied to each of the several active areas, and a boundary data release signal configured to control the output timing of a data voltage supplied to each of the several active boundary areas; a data delay unit configured to delay video data by one horizontal period and output the delayed video data; a data comparison unit configured to compare the video data and the delayed video data and generate the comparison data and the boundary comparison data; and a power control signal generator configured to generate the power control signal using the comparison data and the boundary comparison data.

[0188] The power control signal generator can set a first reference value by applying the comparison data to a first lookup table, it sets a second reference value by applying the boundary comparison data to a second lookup table, it sets a compensation value by applying a difference value between a first reference value corresponding to an active area and a second reference value corresponding to an active boundary area adjacent to the active area to a third lookup table, and it adds the compensation value to the first reference value corresponding to the active area and outputs a result as the power control signal.

[0189] The active border area can have an active front border area adjacent to a previous active area and an active back border area adjacent to a next active area.

[0190] The power control signal generator can set the compensation value by applying a difference value between the first reference value corresponding to the active area and a second reference value corresponding to an active rear-bound area of ​​a previous active area to the third lookup table.

[0191] The power control signal generator can adjust the compensation value by applying a difference value between the first reference value corresponding to the active area and a second reference value corresponding to an active front-edge area of ​​the next active area to the third lookup table.

[0192] The data comparison unit can generate all of a plurality of comparison data by comparing video data and delayed video data corresponding to the plurality of active areas, while the sub-data release signal has a turn-on level.

[0193] The data comparison unit can generate all of a plurality of edge comparison data by comparing video data and delayed video data corresponding to the plurality of active edge areas, while the edge data release signal has a turn-on level.

[0194] Each of the multiple integrated source driver circuits can include a shift register configured to determine sequential data sampling timings in response to a data control signal, a latch unit configured to sequentially align digital video data according to the data sampling timings, a digital-to-analog converter configured to convert the digital video data into the data voltage using an analog gamma voltage, a buffer configured to output the data voltage to a data line, and a power control circuit configured to supply a driver current to the buffer in response to the power control signal.

[0195] The power control circuit can include a plurality of current sources, a plurality of switches connected to the plurality of current sources to control the plurality of current sources each, and a current mirror circuit configured to output a driver current to the buffer, determined as a function of an on-state of the plurality of switches.

[0196] According to another aspect of the present disclosure, the control method of a display device includes a data delay process for delaying video data by one horizontal period and outputting the delayed video data. Furthermore, the control method includes a data comparison process for generating comparison data and boundary comparison data by comparing the video data and the delayed video data. Additionally, the control method includes a first reference value setting process for setting a first reference value by applying the comparison data to a first lookup table. Moreover, the control method includes a second reference value setting process for setting a second reference value by applying the boundary comparison data to a second lookup table.Furthermore, the control method includes a compensation value calculation process for setting a compensation value by applying a difference value between a first reference value corresponding to an active area and a second reference value corresponding to an active boundary area adjacent to the active area to a third lookup table. The control method also includes a power control signal output process for adding the compensation value to the first reference value corresponding to the active area and outputting the result as the power control signal.

[0197] The active boundary area can have an active front boundary area adjacent to a previous active area and an active back boundary area adjacent to a next active area, and in the compensation value calculation process, the compensation value is set to the third lookup table by applying a difference value between the first reference value corresponding to the active area and a second reference value corresponding to an active back boundary area of ​​a previous active area.

[0198] The active boundary area can have an active front boundary area adjacent to a previous active area and an active back boundary area adjacent to a next active area, and in the compensation value calculation process, the compensation value is set to the third lookup table by applying a difference value between the first reference value corresponding to the active area and a second reference value corresponding to an active front boundary area of ​​a next active area.

[0199] The control method of a display device may further include, prior to the data comparison process, a data release signal generation process for generating a sub-data release signal configured to control the output timing of a data voltage supplied to each of the several active areas, and a boundary data release signal configured to determine the output timing of a data voltage supplied to each of the several active boundary areas.

[0200] In the data comparison process, each of the multiple comparison data sets can be generated by comparing video data and delayed video data corresponding to the multiple active areas, while the sub-data release signal has a turn-on level.

[0201] In the data comparison process, each of the multiple edge comparison data is generated by comparing video data and delayed video data corresponding to the multiple active edge areas, while the edge data release signal has a turn-on level.

Claims

[1] A display device (100) comprising: a display panel (110) which is divided into a plurality of active areas (AA); a data driver (130) configured to supply data voltages to a plurality of pixels (PX) arranged in each of the plurality of active areas (AA); and a timing control device (140) configured to output a power control signal (PWRC) for controlling a driver current for the data driver (130), wherein the plurality of active areas (AA) is divided into central active areas (CA), in which a plurality of pixel columns are arranged on a central section of a plurality of pixel columns that are arranged in each of the plurality of active areas (AA), and into active periphery areas (EA), in which a plurality of pixel columns are arranged on an outer section of a plurality of pixel columns that are arranged in each of the plurality of active areas (AA), the data driver (130) contains a plurality of integrated source driver circuits (SDICs), each of which is configured to supply at least one of the data voltages to one of the plurality of active areas (AA), and the timing control device (140) is configured to generate the power control signal (PWRC) as a function of a difference value (DV) between comparison data (CD), which is a maximum data transition value between adjacent pixel rows arranged in each of the multiple active areas (AA), and edge comparison data (ECD), which is the maximum data transition value between adjacent pixel rows arranged in the multiple active edge areas (EA), wherein the time control device (140) has: a data release signal generator (141) configured to generate a sub-data release signal (SDE) configured to determine an output timing of a data voltage supplied to each of the multiple active areas (AA), and a boundary data release signal (EDE) configured to determine an output timing of a data voltage supplied to each of the multiple active boundary areas (EA); a data delay unit (142) configured to delay video data (data) by one horizontal period and output the delayed video data (D_data); a data comparison unit (143) configured to compare the video data (data) and the delayed video data (D_data) and to generate the comparison data (CD) and the edge comparison data (ECD); and a power control signal generator (144) which is configured to generate the power control signal (PWRC) using the reference data (CD) and the boundary reference data (ECD). wherein the power control signal generator (144) is configured to set a first reference value (SV1) by applying the comparison data (CD) to a first lookup table, set a second reference value (SV2) by applying the boundary comparison data (ECD) to a second lookup table, set a compensation value (CV) by applying a difference value (DV) between a first reference value (SV1) corresponding to an active area (AA) and a second reference value (SV2) corresponding to an active boundary area (EA) adjacent to the active area (AA) to a third lookup table, and add the compensation value (CV) to the first reference value (SV1) corresponding to the active area (AA) and output a result as the power control signal (PWRC). [2] The display device (100) according to claim 1, wherein the active edge area (EA) has an active front edge area (FEA) adjacent to a preceding active area (AA) and an active rear edge area (BEA) adjacent to a next active area (AA). [3] The display device (100) according to claim 2, wherein the power control signal generator (144) is configured to set the compensation value (CV) by applying a difference value (DV) between the first reference value (SV1) corresponding to the active area (AA) and a second reference value (SV2) corresponding to an active rear edge area (BEA) of a previous active area (AA) to the third lookup table. [4] The display device (100) according to claim 2, wherein the power control signal generator (144) is configured to set the compensation value (CV) by applying a difference value (DV) between the first reference value (SV1) corresponding to the active area (AA) and a second reference value (SV2) corresponding to an active front edge area (FEA) of a next active area (AA) to the third lookup table. [5] The display device (100) according to any one of claims 1 to 4, wherein the data comparison unit (143) is configured to generate all of a plurality of comparison data (CD) by comparing video data (data) and delayed video data (D_data) corresponding to the plurality of active areas (AA), while the sub-data release signal (SDE) has a turn-on level. [6] The display device (100) according to any one of claims 1 to 5, wherein the data comparison unit (143) is configured to generate all of a plurality of edge comparison data (ECD) by comparing video data (data) and delayed video data (D_data) corresponding to the plurality of active edge areas (EA), while the edge data release signal (EDE) has a turn-on level. [7] The display device (100) according to any one of claims 1 to 6, wherein each of the multiple integrated source driver circuits (SDICs) comprises: a shift register (131) configured to determine sequential data sampling timings in response to a data control signal (DCS); a latch unit (132) configured to sequentially align digital video data according to the data sampling times; a digital-to-analog converter (133) configured to convert the digital video data into the data voltage using an analog gamma voltage; a buffer (134) configured to output the data voltage (Vdata) to a data line; and a power control circuit (135) which is configured to supply a driver current to the buffer (134) in response to the power control signal (PWRC). [8] The display device (100) according to claim 7, comprising the power control circuit (135): a plurality of power sources (I1, ..., I7, I8); a plurality of switches (SW1, ..., SW7, SW8) connected to the plurality of power sources (I1, ..., I7, I8) to control the plurality of power sources (I1, ..., I7, I8) respectively; and a current mirror circuit (MT1, MT2) which is set up to output a driver current, which is determined depending on an on-state of the plurality of switches (SW1, ..., SW7, SW8), to the buffer (134). [9] A control method for a display device (100) according to any one of claims 1 to 8, comprising: a data release signal generation process for generating the subdata release signal (SDE) and the boundary data release signal (EDE); a data delay process to delay video data (data) by one horizontal period and to output the delayed video data (D_data); a data comparison process to generate comparison data (CD) and edge comparison data (ECD) by comparing the video data (Data) and the delayed video data (D_Data); a first reference value setting process to set a first reference value (SV1) by applying the comparison data (CD) to a first lookup table; a second reference setting process to set a second reference value (SV2) by applying the marginal comparison data (ECD) to a second lookup table; a compensation value calculation process for setting a compensation value (CV) by applying a difference value (DV) between a first reference value (SV1) corresponding to an active area (AA) and a second reference value (SV2) corresponding to an active boundary area (EA) adjacent to the active area (AA) to a third lookup table; and a power control signal output process for adding the compensation value (CV) to the first reference value (SV1) corresponding to the active area (AA) and for outputting a result as a power control signal (PWRC), wherein the power control signal (PWRC) is generated depending on the difference value (DV) between the comparison data (CD) and the boundary comparison data (ECD). [10] The control method for a display device (100) according to claim 9, wherein the active edge area (EA) has an active front edge area (FEA) adjacent to a preceding active area (AA) and an active rear edge area (BEA) adjacent to a next active area (AA), and during the compensation value calculation process, The compensation value (CV) is set by applying a difference value (DV) between the first reference value (SV1), which corresponds to the active area (AA), and a second reference value (SV2), which corresponds to an active rear margin area (BEA) of a previous active area (AA), to the third lookup table. [11] The control method for a display device (100) according to claim 9, wherein the active edge area (EA) has an active front edge area (FEA) adjacent to a preceding active area (AA) and an active rear edge area (BEA) adjacent to a next active area (AA), and during the compensation value calculation process, The compensation value (CV) is set to the third lookup table by applying a difference value (DV) between the first reference value (SV1), which corresponds to the active area (AA), and a second reference value (SV2), which corresponds to an active front margin area (FEA) of a next active area (AA). [12] The control method for a display device (100) according to any one of claims 9 to 11, comprising: Prior to the data comparison process, a data release signal generation process is used to generate a sub-data release signal (SDE) configured to determine an output timing of a data voltage applied to each of the multiple active areas (AA), and a boundary data release signal (EDE) configured to determine an output timing of a data voltage applied to each of the multiple active boundary areas (EA). [13] The control method for a display device (100) according to claim 12, in the data comparison process, All of the respective multiple comparison data (CD) are generated by comparing video data (data) and delayed video data (D_data), which correspond to the multiple active areas (AA), while the sub-data release signal (SDE) has a turn-on level. [14] The control method for a display device (100) according to claim 12 or 13, in the data comparison process, all respective a plurality of edge comparison data (ECD) are generated by comparing video data (data) and delayed video data (D_data) corresponding to the plurality of active edge areas (EA), while the edge data enable signal (EDE) has a turn-on level.

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