DEVICE PROVIDING MULTIPLE THRESHOLD VOLTAGES AND METHOD FOR MANUFACTURING THE SAME

Abstract

A procedure (1000, 2000) that includes: Forming a dielectric layer (246) on a semiconductor workpiece; Forming a first structured layer (302) of a first dipole material on the dielectric layer (246); Performing a first thermal drive-in process (402) at a first temperature to form a diffusion feature (2002) in a first portion of the dielectric layer (246) beneath the first patterned layer (302); Forming a second structured layer (304) of a second dipole material, wherein a first portion of the second structured layer (304) is on the diffusion feature (2002) and a second portion of the second structured layer (304) is offset from the diffusion feature (2002); Performing a second thermal driving process (404) at a second temperature, wherein the second temperature is lower than the first temperature by a difference of 50°C to 250°C; and Forming a gate electrode layer (248) on the dielectric layer (246).

Description

BACKGROUND

[0001] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs, with each generation featuring smaller and more complex circuits than the previous generation. As ICs have evolved, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased. This downsizing process generally provides benefits by increasing production efficiency and reducing associated costs. Such downsizing has also increased the complexity of IC processing and manufacturing, and for these advances to be realized, similar developments in IC processing and manufacturing are required.

[0002] For example, nanosheet-based devices have been introduced in an effort to improve gate control by increasing gate-channel coupling, reducing off-state current, and reducing short-channel effects (SCEs). Nanosheet-based devices comprise a plurality of channel layers stacked together to form the transistor channels engaged by a gate structure. Nanosheet-based devices are compatible with conventional complementary metal-oxide-semiconductor (CMOS) processes, allowing them to be aggressively downsized while maintaining gate control and mitigating SCEs. However, due to the complex device structures and reduced spacing between features, it can be challenging to achieve certain functions, such as providing multiple threshold voltages, without causing penalties to other performance characteristics.Therefore, although conventional technologies have generally been adequate for their intended purposes, they are unsatisfactory in every respect.

[0003] US 2018 / 0 226 300 A1 discloses semiconductor devices. US 2020 / 0 395 461 A1 discloses a semiconductor device for improving gate-induced drain leakage and a method for manufacturing the same. US 8 357 604 B2 relates to semiconductor devices having different threshold voltage levels for transistors. US 2020 / 0 373 300 A1 discloses a method for forming a semiconductor device structure. US 9 245 759 B2 discloses a method for manufacturing a semiconductor device with dual work function. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Aspects of the present disclosure are best understood by reference to the following detailed description when taken in conjunction with the accompanying drawings. It should be noted that, consistent with industry practice, various elements are not drawn to scale. Rather, for the convenience of discussion, the dimensions of various elements may be exaggerated or reduced as desired. Fig. 1 and Fig. 14 are flow diagrams illustrating methods of manufacturing devices of the present disclosure according to some embodiments of the present disclosure. Fig. 2A and Fig. 15 are plan views of embodiments of devices of the present disclosure according to some embodiments of the present disclosure. Fig. 2B is a three-dimensional (3D) perspective view of a nanosheet-based transistor of one embodiment of a device of the present disclosure constructed in accordance with some embodiments of the present disclosure. Fig. Figure 2C is a cross-sectional view of the nanosheet-based transistor of Fig. 2A along line AA' according to some embodiments of the present disclosure. Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10, Fig. 11, Fig. 12, Fig. 16, Fig. 17, Fig. 18, Fig. 19, Fig. 20 and Fig. 21 are cross-sectional views of an embodiment of a device of the present disclosure or portions thereof constructed at various stages of manufacture in accordance with some embodiments of the present disclosure. Fig. 13, Fig. 22, Fig. 23A, Fig. 23B, Fig. 23C, Fig. 24, Fig. 25A, Fig. 25B, Fig. 26A and Fig. 26B is data illustrating various aspects of embodiments of the present disclosure. DETAILED DESCRIPTION

[0005] This disclosure is best understood by reference to the following detailed description when taken in conjunction with the accompanying drawings. It should be noted that, consistent with industry practice, various elements are not drawn to scale and are for illustrative purposes only. Rather, for the convenience of discussion, the dimensions of various elements may be exaggerated or reduced as desired.

[0006] The following disclosure provides many different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, in the following description, the fabrication of a first element over or on top of a second element may include embodiments where the first and second elements are formed in direct contact, and may also include embodiments where additional elements may be formed between the first and second elements such that the first and second elements are not in direct contact. Furthermore, the present disclosure may repeat reference numbers and / or letters in the various examples.This repetition is for simplicity and clarity and does not, in itself, prescribe any relationship between the various embodiments and / or configurations discussed.

[0007] Furthermore, spatially relative terms such as "beneath," "under," "lower," "above," "upper," and the like may be used herein to conveniently describe the relationship of one element or structure to one or more other elements or structures illustrated in the figures. The spatially relative terms are intended to include various orientations of the device in use or operation, in addition to the orientation illustrated in the figures. The device may be oriented differently (rotated 90 degrees or in a different orientation), and the spatially relative descriptions can be interpreted accordingly. Further, when a number or range of numbers is described with "about," "approximately," and the like, the term is intended to further include numbers that are within + / - 10% of the described number, unless otherwise noted.For example, the term “about 5 nm” includes the dimension range from 4.5 nm to 5.5 nm.

[0008] The present disclosure generally relates to integrated circuits and semiconductor devices, and methods of fabricating the same. More particularly, the present disclosure relates to semiconductor devices having multiple threshold voltages (Vt) (hereinafter referred to as multi-Vt devices). As advanced technology nodes continue to shrink, it becomes increasingly difficult to develop such multi-Vt devices. Typically, various additional material layers may be required to construct the devices to provide multiple threshold voltages. These material layers occupy certain spaces (and / or volumes) on the semiconductor chips, hindering the shrinking effort. In some examples, the devices may not have sufficient space to accommodate such additional material layers.For example, nanosheet-based devices (sometimes referred to as gate-all-around (GAA) devices, multi-bridged channel (MBC) devices, or other similar names) comprise a plurality of channel layers stacked one upon another. The gate stacks are formed in the very narrow spacing between vertically adjacent channel layers, where additional material layers are sometimes impractical to reliably form. Furthermore, the volume of these additional material layers can further adversely affect device performance, such as detrimentally affecting channel resistance (R). ch). Accordingly, the present disclosure provides processes and methods that enable formation of multi-Vt devices without the volume requirement. The devices presented herein may be a complementary metal-oxide-semiconductor (CMOS) device, a p-type metal-oxide-semiconductor (PMOS) device, or an n-type metal-oxide-semiconductor (NMOS) device. One of ordinary skill in the art may recognize other examples of semiconductor devices that may benefit from aspects of the present disclosure. Moreover, although the disclosure uses nanosheet-based devices as an example, one of ordinary skill in the art may recognize other examples of semiconductor devices that may benefit from aspects of the present disclosure.For example, other types of metal-oxide-semiconductor field-effect transistors (MOSFETs), such as planar MOSFETs, FinFETs, other multi-gate FETs, may benefit from aspects of the present disclosure.

[0009] Fig. 1 is a flow diagram of one embodiment of a method 1000 of the present disclosure for preparing one embodiment of a multi-Vt device 10 (or simply device 10) of the present disclosure. Fig. 2A is a top view of the device 10 according to an embodiment of the present disclosure. Fig. Figure 2B is a three-dimensional (3D) perspective view of a nanosheet-based transistor 100 representative of a component of the device 10 of Fig. 2A according to some embodiments of the present disclosure. Fig. Figure 2C is a cross-sectional view of the nanosheet-based transistor 100 of Fig. 2B along line AA' according to some embodiments of the present disclosure. Fig. 3-12 are cross-sectional views or expanded cross-sectional views of the device 10 (or portions thereof) at various stages of manufacture according to embodiments of the present disclosure.

[0010] With reference to block 1010 of Fig. 1 and on Fig. 2A-2C, an exemplary nanosheet-based multi-Vt device 10 is received. The device 10 includes a plurality of nanosheet-based transistors (or simply transistors), such as transistors 100A-100D and 100A'-100D'. In the illustrated embodiments, transistors 100A and 100A' are formed in a substrate region 102A of a semiconductor substrate 102; transistors 100B and 100B' are formed in a substrate region 102B of a semiconductor substrate 102; transistors 100C and 100C' are formed in a substrate region 102C of a semiconductor substrate 102; and transistors 100D and 100D' are formed in a substrate region 102D of a semiconductor substrate 102. Furthermore, in the illustrated embodiments, transistors 100A-100D may be configured as n-type transistors, while transistors 100A'-100D' may be configured as p-type transistors.In some embodiments, transistors 100A-100D each have a different threshold voltage; and transistors 100A'-100D' each have a different threshold voltage. Accordingly, device 10 provides n-type transistors and p-type transistors, each providing four (4) different threshold voltages. As described later, this total of eight (8) threshold voltages can be achieved by differently configuring gate dielectric layers with respect to dipole elements. Transistors 100A-100D and 100A'-100D' may have similar or different device structures. In the illustrated embodiments, transistors 100A-100D and 100A'-100D' are each nanosheet-based transistors and have similar device structures, such as those shown in FIG. Fig. 2B and Fig. 2C illustrates the device structure of transistor 100. Fig. 2A-2C have been abbreviated to provide a general picture of the device 10 and do not include all details. For example, shapes, sizes, and relative positions of the Fig. The transistors shown in Figures 2A-2C are simplified and / or conceptualized and are not intended to be limiting. Additional details are described in connection with subsequent figures.

[0011] With reference to Fig. 2B and Fig. 2C, the nanosheet-based transistor 100 (or simply transistor 100) may be representative of one or more of the transistors 100A-100D and 100A'-100D' of Fig. 2A. In other words, Fig. 2B and Fig. 2C illustrate part of Fig. 2A. As illustrated, transistor 100 includes a semiconductor substrate 102 (or simply substrate 102). Substrate 102 includes a semiconductor material, such as bulk silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenic (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and / or indium antimonide (InSb), or combinations thereof. Substrate 102 may also include a semiconductor-on-insulator substrate, such as Si-on-insulator (SOI), SiGe-on-insulator (SGOI), Ge-on-insulator (GOI) substrates. Fin structures (or fins) 104 are formed over the substrate 102, each extending longitudinally horizontally in an X direction and separated horizontally in a Y direction. The X direction and the Y direction are perpendicular to each other, and the Z direction is orthogonal (or normal) to a horizontal XY plane defined by the X direction and the Y direction.The substrate 102 may have its upper surface parallel to the XY plane. As described above, the substrate 102 includes substrate regions 102A-102D.

[0012] The fin structures 104 each include a source region 104a and a drain region 104a arranged along the X-direction. The source region 104a and the drain region 104a are collectively referred to as the source / drain regions 104a. Epitaxial source / drain features 500 are formed in or on the source / drain regions 104a of the fin structure 104. In some embodiments, the epitaxial source / drain features 500 are configured to be part of the PMOS transistor. Accordingly, the epitaxial source / drain features 500 may include any suitable p-type semiconductor materials, such as Si, SiGe, Ge, SiGeC, or combinations thereof. In some embodiments, the epitaxial source / drain features 500 are configured to be part of the NMOS transistor. Accordingly, the epitaxial source / drain features 500 may comprise any suitable n-type semiconductor materials, such as Si.The epitaxial source / drain features 500 may further be doped in-situ or ex-situ. For example, the epitaxially grown SiGe source / drain features of a PMOS may be doped with boron (B) to form Si:Ge:B source / drain features; and the epitaxially grown Si source / drain features of an NMOS may be doped with carbon to form silicon:carbon (Si:C) source / drain features, doped with phosphorus to form silicon:phosphorus (Si:P) source / drain features, or both carbon and phosphorus to form silicon-carbon-phosphorus (Si:C:P) source / drain features. Several processes, including etching and growth processes (such as epitaxial processes), may be employed to grow the epitaxial source / drain features 500. One or more annealing processes may be performed to activate the dopants in the epitaxial source / drain features 500.For example, in some embodiments, the epitaxial source / drain features 500 may converge along the Y-direction between adjacent fin structures 104 to provide a greater lateral width than a single epitaxial source / drain feature.

[0013] The fin structures 104 each further comprise a channel region 104b arranged between and connecting the source / drain regions 104a. The fin structures 104 each comprise a stack of channel layers 120 (also interchangeably referred to as "semiconductor layers 120," "suspended semiconductor layers 120," or "suspended channel layers 120"). The stack of channel layers 120 occupies the channel region 104b of the fin structures 104 and extends vertically (e.g., along the Z-direction) from the substrate 102. Each of the channel layers 120 connects a pair of epitaxial source / drain features 500. The channel layers 120 may each be in one of many different shapes, such as wire (or nanowire), foil (or nanofoil), rod (or nanorod), and / or other suitable shapes, and may be spaced apart from each other. In the illustrated embodiments, there are three channel layers 120 in the stack.However, there may be any suitable number of layers in the stack, such as 2 to 10 layers. In some embodiments, the channel layers 120 are on the nanometer scale (e.g., with at least one dimension ranging from about 1 nm to about 100 nm). Accordingly, the channel layers 120 are referred to as nanostructures, and the transistors are referred to as nanostructure (or nanofoil)-based transistors.

[0014] In some embodiments, the fin structures 104 may be formed by first forming a stack of layers over the substrate 102. The stack of layers may include alternating semiconductor layers and the semiconductor layers 120. The material compositions of the semiconductor layers and the semiconductor layers 120 are configured to exhibit etch selectivity in a subsequent etching process. For example, in some embodiments, the semiconductor layers contain silicon germanium (SiGe), while the semiconductor layers 120 contain silicon (Si). The stacks of layers (and, in some embodiments, the substrate portion below them) are then patterned together into the fin structures 104 such that the fin structure 104 each extends longitudinally along the X-direction. The patterning may be performed by any suitable method.For example, the fins may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, which may create structures having, for example, pitches smaller than those otherwise obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers or mandrels may then be used to pattern the fins.Patterning may use multiple etching processes, including dry etching and / or wet etching. The fin structures 104 may have lateral widths along the Y direction that are equal to or different from each other.

[0015] The semiconductor layers are subsequently removed and are thus also referred to as the sacrificial semiconductor layers. Meanwhile, the patterned semiconductor layers 120 later serve as the channel for transistors and are thus also referred to as the channel layers 120. The channel layers 120 can each engage with an individual gate structure 250. The gate structure 250 includes a gate dielectric layer 246 and a gate electrode layer 248. In the illustrated embodiments, the gate structure 250 further includes an interface layer 242. However, in some other embodiments, the interface layer 242 may be omitted. It should be noted that the gate structure 250 in Fig. 2B as a transparent feature to illustrate the features (such as the channel layers 120) that the gate structure 250 covers. The gate structures 250 may be configured to extend longitudinally parallel to each other, for example, each along the Y-direction. In some embodiments, the gate structures 250 each enclose the top surface and the side surfaces of each of the fin structures 104. In some embodiments, as described later, the gate structure 250 is first formed with a dummy gate stack of a different material, such as polysilicon, which is subsequently replaced with the gate dielectric layer 246 and the gate electrode layer 248 (and in some embodiments, the interface layer 242). The dummy gate stacks 240 may be formed by a procedure including deposition, lithography, patterning, and etching processes.The deposition processes may include chemical vapor deposition (CVD) processes, atomic layer deposition (ALD) processes, physical vapor deposition (PVD), other suitable methods, or combinations thereof. The gate structure 250 further includes gate spacers. Gate spacers may comprise a single layer or a multi-layer structure. For example, in the illustrated embodiment, a gate spacer layer 201 is formed over the top surface of the device, and a gate spacer layer 202 is formed over the gate spacer layer 201. The gate spacer layers 201 and 202 may each comprise silicon nitride (Si3N4), silicon oxide (SiO2), silicon carbide (SiC), silicon oxycarbide (SiOC), silicon oxynitride (SiON), silicon oxycarbon nitride (SiOCN), carbon-doped oxide, nitrogen-doped oxide, porous oxide, or combinations thereof.

[0016] The transistor 100 further includes isolation features 150 within or above the substrate 102 that separate adjacent fin structures 104 from each other. The isolation features 150 may be shallow trench isolation (STI) features. In some examples, forming the isolation features 150 includes etching trenches into the substrate 102 between the active areas (the areas where the fin structures are formed) and filling the trenches with one or more dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, other suitable materials, or combinations thereof. Any suitable methods, such as a CVD process, an ALD process, a PVD process, a plasma-enhanced CVD (PECVD) process, a plasma-enhanced ALD (PEALD) process, and / or combinations thereof, may be used to deposit the isolation features 150.The isolation features 150 may include a multi-layer structure, such as a thermal oxide liner layer over the substrate 102 and a fill layer (e.g., silicon nitride or silicon oxide) over the thermal oxide liner layer. Alternatively, the isolation features 150 may be formed using any other isolation technologies. As shown in FIG. Fig. 2B, the fin structure 104 is located above the top surface of the isolation features 150. In the illustrated embodiment, the transistor 100 further includes internal spacers 206 between the gate structures 250 and the source / drain features 500; contact etch stop layers 220 above the epitaxial source / drain features 500; and interlayer dielectric (ILD) layer 230 above the epitaxial source / drain features 500 and above the contact etch stop layers 220. Fig. 2B and Fig. 2C have been abbreviated to provide a general view of transistor 100 and do not include all of the details. Additional details of gate structures 250 are described in connection with subsequent figures.

[0017] As described above, transistor 100 is formed by replacing a dummy gate stack of gate structure 250 with gate dielectric layer 246 and gate electrode layer 248 (and in some embodiments, interface layer 242). The disclosure below describes details for forming gate dielectric layer 246. Referring again to block 1010 of Fig. 1 and on Fig. 3, a workpiece for the device 10 (or simply workpiece 10) is received. Fig. 3 illustrates only a part of the workpiece 10, which is subsequently connected to the transistors 100 of Fig. 2B and Fig. 2C is processed (e.g., one of the transistors 100A-100D and 100A'-100D'). In other words, Fig. Figure 3 illustrates the transistor 100 at an earlier processing stage than that in Fig. 2B and Fig. 2C. In particular, the transistor 100 at this processing stage has all the features described above with respect to Fig. 2B and Fig. 2C, except that the gate structure 250 includes the dummy gate stack 240 instead of the gate dielectric layer 246, the gate electrode layer 248, or the interface layer 242. The dummy gate stack 240 may include any suitable materials, such as polysilicon. In some embodiments, the dummy gate stack 240 may have a multi-layer structure. For example, in some implementations, the dummy gate stack may include a dummy gate dielectric layer and a dummy gate electrode layer.

[0018] With reference to Fig. 4, the dummy gate stack 240 is selectively removed from the gate structure 250 to form openings. The etching process may be a dry etching process, a wet etching process, or combinations thereof. The etching process may be tuned so that the dummy gate stack 240 is removed without (or only minimally) etching other features of the transistor 100. Furthermore, after removing the dummy gate stack 240, which exposes sidewall surfaces of the fin structures 104, the remaining portions of the sacrificial semiconductor layers 110 are selectively removed to form additional openings. These openings collectively form gate trenches 241. The gate trenches 241 expose portions of the channel layers 120 in 360° and further expose the top surface of the substrate 102.

[0019] Fig. 5 illustrates an expanded view of the transistor 100, in particular a portion of the gate trench 241 of the transistor 100. Referring to Fig. 5, the method 1000 continues to form an interface layer 242 in the gate trenches 241 and on the channel layers 120. In some embodiments, interface layers 242 are formed on the exposed surfaces of the channel layers 120. In some embodiments, the interface layers 242 improve the adhesion between the subsequently formed gate dielectric layer 246 and the channel layers 120. In some embodiments, the interface layer 242 has a thickness in a range of about 0.5 nm to about 1.5 nm (about 5 Å to about 15 Å). In embodiments, the interface layer 242 comprises a dielectric material, such as SiO2, HfSiO, SiON, another silicon-containing dielectric material, another suitable dielectric material, or combinations thereof.The interface layer 242 is formed by any suitable process, such as thermal oxidation, chemical oxidation, ALD, CVD, another suitable process, or combinations thereof.

[0020] With reference to block 1020 of Fig. 1 and on Fig. 5, a gate dielectric layer 246 is formed on the interface layer 242, such as directly on the interface layer 242 and contacting the interface layer 242 (e.g., interfacing therewith). Moreover, the gate dielectric layer 246 may be further formed over other surfaces exposed in the gate trenches 241. The gate dielectric layer 246 may comprise a high-k dielectric material, such as HfO2, HfSiO, HfSiO4, HfSiON, HfLaO, HfTaO, HfTiO, HfZrO, HfAlO x, ZrO, ZrO2, ZrSiO2, AlO, AlSiO, Al2O3, TiO, TiO2, LaO, LaSiO, Ta2O3, Ta2O5, Y2O3, SrTiO3, BaZrO, BaTiO3 (BTO), (Ba,Sr)TiO3 (BST), hafnia-alumina (HfO2-Al2O3) alloy, another suitable high-k dielectric material, or combinations thereof. The gate dielectric layer 246 is formed by any of the processes described herein, such as ALD, CVD, PVD, oxidation-based deposition process, another suitable process, or combinations thereof. For example, a gate dielectric layer 246 may be conformally deposited over the interface layers 242 using an ALD process, such that the gate dielectric layer 246 has a substantially uniform thickness and partially fills the gate trenches 241. The gate dielectric layer 246 may be disposed on sidewall surfaces of the inner spacers 206 and may surround the channel layers 120.In some embodiments, the gate dielectric layer 246 has a thickness of about 1 nm to about 3 nm. The gate dielectric layer 246 is formed surrounding the exposed portions of the channel layers 120 and reduces the size of the gate trenches 241. The gate dielectric layer 246 separates the channel layers 120 and the gate electrode layer, which are subsequently formed, and is critical for determining the threshold voltage of the transistor.

[0021] With reference to block 1030 of Fig. 1 and on Fig. 6, a dipole layer 302 is deposited into the gate trenches 241 or some of the gate trenches 241, as described later. As described above, the gate trenches 241 each surround portions of the channel layers 120 (e.g., the portions enclosed by the gate dielectric layer 246) in 360° and also over a portion of the topmost channel layer 120 and a portion of the substrate 102. Accordingly, the dipole layer 302 is formed on and surrounding the gate dielectric layer 246, such that the dipole layer 302 directly contacts the exposed surfaces of the gate dielectric layer 246. The dipole layer 302 may be deposited by ALD, CVD, PVD, thermal oxidation, or other suitable methods, and may be deposited at a temperature ranging from about 100°C to about 450°C at a pressure ranging from about 133 Pa to about 13332 Pa (about 1 Torr to about 100 Torr). The dipole layer 302 may comprise any suitable materials.In some embodiments, the dipole layer 302 may comprise an n-dipole material or a precursor to an n-dipole material. The n-dipole material may comprise germanium oxide (GeO2), yttrium oxide (Y2O3), lanthanum oxide (La2O3), strontium oxide (SrO), other suitable n-dipole materials, or combinations thereof. In some embodiments, the dipole layer 302 may comprise a p-dipole material or a precursor to a p-dipole material. The p-dipole material may comprise alumina (Al2O3), gallium oxide (Ga2O3), magnesium oxide (MgO), hafnium oxide (HfO2), titanium oxide (TiO2), zirconium oxide (ZrO2), zinc oxide (ZnO), other suitable p-dipole materials, or combinations thereof. As shown in FIG. Fig. 6, the dipole layer 302 is spaced apart from the channel layers 120 and from the gate dielectric layer 246 at this processing stage. As will be discussed, in a subsequent step, the dipole materials of the dipole layer 302 are thermally driven into the respective gate dielectric layer 246 so that they spread across the gate dielectric layer 246 and around the interface between the gate dielectric layer 246 and the interface layer 242. Accordingly, the dipole materials of the dipole layer 302 may thus be distributed closer to or approach surfaces of the channel layers 120. The n-type dipole material configured in this manner in an NMOS serves to lower the threshold voltage of the NMOS; whereas the n-type dipole material configured in this manner in a PMOS serves to increase the threshold voltage of the PMOS.Similarly, the p-dipole material configured in this manner in a PMOS serves to lower the threshold voltage of the PMOS; while the p-dipole material configured in this manner in an NMOS serves to increase the threshold voltage of the NMOS. Furthermore, the amount and distribution of these dipole materials further influence the magnitude of the change in threshold voltages. Accordingly, the threshold voltages of the transistors can be fine-tuned by simply engineering the presence or absence, chemical identity, and distribution of the dipole materials within the gate dielectric layer 246.

[0022] In some embodiments, the material of the dipole layer 302 can be designed based on the desired magnitude (or amount) of threshold voltage tuning. For example, using materials such as La2O3, Y2O3, or TiO2, the threshold voltage of the transistor 100 can be adjusted upwards (for p-type transistors) or downwards (for n-type transistors) within a range of about 20 mV to about 450 mV. Furthermore, the thickness of the dipole layer 302 can be further adjusted based on the desired magnitude of the threshold voltage tuning. In some embodiments, a thicker dipole layer 302 generally (all other things being equal) allows more dipole material to enter the gate dielectric layer 246 and results in a larger change in the transistor's threshold voltage.In some embodiments, the dipole layer 302 may be deposited to a substantially uniform thickness in a range of about 0.05 nm to about 1 nm (about 0.5 Å to about 10 Å) in various embodiments, such as about 0.3 nm to about 0.5 nm (about 3 Å to about 5 Å). If the thickness is too small (such as less than 0.05 nm (0.5 Å)), the dipole layer 302 may, in some cases, be too weak for Vt tuning. If the thickness is too large (such as greater than 1 nm (10 Å)), the dipole layer 302 may be too strong for Vt tuning and may create side effects such as degraded mobility in the channel layers 120.

[0023] Furthermore, as described above, device 10 includes a plurality of NMOS transistors and PMOS transistors. Each transistor may have device structures similar to those of transistor 100 described above with respect to Fig. 2B-2C and Fig. 3-6, except that only a subset of the transistors includes the dipole layer 302. Accordingly, each transistor includes a respective gate trench 241 and may, where appropriate, receive the deposition of a respective portion of the dipole layer 302 on the respective portion of the gate dielectric layer. In other words, each of the transistors 100A-100D and 100A'-100D' may include a portion 200A-200D (corresponding to portion 200 of Fig. 6) comprising the gate dielectric layer 246 and the remaining part of the gate trench 241. Furthermore, some of the parts 200A-200D may comprise the dipole layer 302, as will be described in detail later. In this regard, Fig. 7 illustrates portions 200A-200D of NMOS transistors 100A-100D for the purpose of clearly illustrating aspects of the embodiments. While portions 200A-200D are illustrated as being discontinuous from one another, it is understood that portions thereof may instead be connected to one or the other. Furthermore, it is understood that although they are illustrated side by side in a particular order, any alternative relative position is contemplated by the present disclosure. Furthermore, although not explicitly illustrated below, transistors 100A'-100D' may include gate dielectric portions and dipole layer 302 similar to those of NMOS transistors 100A-100D and may undergo similar processing steps.

[0024] With reference to Fig. 7, each of the portions 200A-200D comprises a respective portion of the gate dielectric layer 246, referred to as the gate dielectric portions 246A-246D, respectively. The dipole layer 302 is shown here as a collection of circles representing chemical compositions of the dipole layer 302. Fig. 6. The number of circles does not necessarily represent the concentrations or amounts of the chemical compounds. Although in Fig. 7, the dipole layer 302 is further formed on sidewall surfaces and bottom surfaces of the gate dielectric portions 246A-246D, similar to the dipole layer 302 formed on sidewall surfaces and bottom surfaces of the gate dielectric layer 246 of Fig. 6. In the illustrated embodiments, the dipole layer 302 is formed on surfaces of a subset, but not all, of the gate dielectric portions 246A-246D. At this processing stage, the gate dielectric portions 246B and 246D may each have a thickness d1B and d1D that may be about 1 nm to about 3 nm. In some embodiments, the thickness d1B and d1D may be similar to the thickness d1A and d1C of the respective gate dielectric portions 246A and 246C. If the thickness d1A-d1D is too small, such as less than about 1 nm, tunneling may drastically increase across the gate dielectric portions 246A-246D, causing leakage. If the thickness d1A-d1D is too large, such as larger than about 3 nm, the gate capacitances cannot be optimized.

[0025] With reference to block 1040 of Fig. 1 and on Fig. 8, a process 402 is performed to form a diffusion feature within the gate dielectric layer 246 in regions configured for a subset of the transistors 100A-100D. In some embodiments, the process 402 comprises a thermal drive process (alternatively referred to as an annealing process). In some embodiments, the dipole materials of the dipole layer 302 (e.g., dipole material La2O3) or dipole elements of the dipole layer 302 (e.g., the La and O elements of the dipole layer 302 with the dipole material La2O3) are at least partially driven into the gate dielectric layer 246. For example, the thermal drive process provides thermal energy to the workpiece 10 such that the mobility of the dipole material substantially increases and the dipole elements diffuse into regions with which they interface (such as the gate dielectric portions 246B and 246D that interface with the dipole layer 302).In one embodiment, the thermal drive-in process is a soak anneal process at a temperature in a range of about 600°C to about 1000°C, such as about 700°C to about 800°C, with O2, N2, or a mixture of O2 and N2 ambient. In another embodiment, the thermal drive-in process is a furnace anneal process at a temperature in a range of about 300°C to about 600°C with O2, N2, or a mixture of O2 and N2 ambient for about 1 second to about 30 minutes. In yet another embodiment, the thermal drive-in process is a spike anneal process.In yet another embodiment, the thermal drive-in process is a laser anneal process or a microwave anneal process at a temperature in a range of about 800°C to about 1200°C with O2, N2, NH3, H2, or a mixture thereof for about 1 millisecond to about 10 seconds. The above temperature ranges are chosen so that the thermal drive-in process does not adversely affect the existing structures and features of the device 10, yet is sufficient to cause the dipole elements to migrate (or diffuse) from the dipole layer 302 into the gate dielectric layer 246 below. In some embodiments, the dipole elements (e.g., La and O) diffuse into the gate dielectric layer 246 while maintaining their stoichiometric ratio as in the dipole layer 302 (e.g., [La]:[O] at 2:3 for La2O3).In other words, the stoichiometric ratio of the dipole elements in the gate dielectric layer 246 (e.g., the ratio of the increase in La atom concentration to the increase in O atom concentration) is substantially the same as that of the dipole elements in the dipole layer 302. In some other embodiments, the dipole elements diffuse into the gate dielectric layer 246 without maintaining the same stoichiometric ratio. Accordingly, the ratio of the dipole elements within the gate dielectric layer 246 (e.g., the ratio of the increase in La atom concentration to the increase in O atom concentration) may differ from that of the dipole layer 302. As described in detail later, the chemical identity, amount (or concentration), and distributions of the dipole elements can be further adjusted to achieve the desired threshold voltage.

[0026] The thermal drive operation of process 402 causes a portion of the dipole materials of layer 302 to diffuse into gate dielectric portions 246B and 246D in a specific manner. As a result, gate dielectric portions 246B and 246D each comprise a specific dipole material composition 2002. Accordingly, gate dielectric portions 246B and 246D may be said to comprise a diffusion feature of dipole material composition 2002 (or simply diffusion feature 2002). As will be discussed in more detail below, dipole material composition 2002 is configured differently than dipole material compositions in other gate dielectric portions in terms of chemical identities, concentrations, and / or distributions of the dipole materials (or dipole elements if the stoichiometric ratio is not maintained).This provides tunability of the threshold voltages of the respective transistors separately and potentially differently from each other. Although in . Fig. 8, in some embodiments, the thermal drive operation of process 402 is configured to form an intermixture layer at the interface of the remaining portion of dipole layer 302 and modified gate dielectric portions 246B and 246D (e.g., modified with dipole material composition 2002). For example, the intermixture layers are formed on modified gate dielectric portions 246B and 246D, each of which may comprise the dipole material of dipole layer 302 at a concentration of about 40% to about 60%. In other words, this intermix layer includes characteristics (e.g., the etch resistances) of both the gate dielectric layer 246 and the dipole layer 302. In some embodiments, the concentrations of the dipole material in the intermix layers are each greater than the dipole material in the gate dielectric portions 246B and 246D, respectively.Meanwhile, the gate dielectric portions 246A and 246C do not have such intermix layers.

[0027] As described above, at the end of the thermal drive-in process of process 402, a substantial portion of the dipole layer 302 is not driven into the gate dielectric portions 246B and 246D and therefore remains on surfaces of the gate dielectric portions 246B and 246D (e.g., on surfaces of the intermix layer on the surfaces of the gate dielectric portions 246B and 246D). Still referring to block 1040 of Fig. 1 and on Fig. 8, the process 402 continues to remove the remaining portions of the dipole layer 302 in an etching process, such that surfaces of the modified gate dielectric portions 246B and 246D (or doped gate dielectric portions 246B and 246D) are exposed. In some embodiments, the exposed surfaces of the modified gate dielectric portions 246B and 246D each comprise the dipole material of the dipole layer 302 at a concentration of less than about 40% to about 60%. The etching process of the process 402 may include one or more etching processes (or banding processes), which may be a dry etching process, a wet etching process, a reactive ion etching process, or another etching process and have a high etch selectivity with respect to the dipole layer 302 relative to the gate dielectric layer 246. In some embodiments, the etching process of process 402 is a wet etching process.It is noted that removing the remaining portions of the dipole layer 302 leaves limited spaces within the gate trenches 241 so that additional gate layers, such as another dipole layer (e.g., the dipole layer 304 described later), another gate dielectric layer (such as the gate dielectric layer 246 described later), other gate layers, or supporting layers required or beneficial for the proper functioning or enhanced functioning of the transistors, may be formed in the gate trenches 241. Accordingly, embodiments implementing the etching process of process 402 provide an improved device compared to approaches not implementing such a process.

[0028] Following process 402, gate dielectric portions 246A-246D each have a thickness d2A-d2D. As described above, because the etching process is configured to have etch selectivity with respect to dipole layer 302 relative to gate dielectric layer 246 (or unmodified gate dielectric portions 246A and 246C), thicknesses d2A and d2C are substantially the same as thicknesses d1A and d1C, respectively. However, due to the presence of a significant amount of dipole material, the etching process may deepen the intermix layer on modified gate dielectric portions 246B and 246D. Accordingly, following the etching process, the thicknesses d2B and d2D of the gate dielectric portions 246B and 246D, respectively, are reduced compared to the thicknesses d1B and d1D and compared to the thicknesses d2A and d2C.As described in detail later, reducing the thickness of the gate dielectric portions 246B and 246D reduces the channel resistance R. ch of the transistors 100B and 100D, respectively. Furthermore, as described later, the etch parameters of the etching process of process 402 can be adjusted to tune the amount of intermix layer removed, thereby tuning the remaining thickness d2B and d2D, and further to adjust the channel resistance R ch to set.

[0029] Following process 402, gate dielectric portions 246A and 246C, as well as gate dielectric portions 246B and 246D, are exposed in gate trenches 241. Furthermore, gate dielectric portions 246B and 246D may be thinner than gate dielectric portions 246A and 246C. In other words, the surfaces of the gate dielectric portions in different substrate areas are uneven (or stepped). Furthermore, gate dielectric portions 246B and 246D now have compositions that differ from those of gate dielectric portions 246A and 246C in that they have dipole material composition 2002, while gate dielectric portions 246A and 246C do not. As described above, this distinction alone (e.g.the presence and absence of the dipole material composition 2002) that the transistors 100B / 100D have threshold voltages that differ from the transistors 100A / 100C even when other aspects of the transistors are identical.

[0030] With reference to block 1050 of Fig. 1 and on Fig. 9, the method continues to form another dipole layer in the gate dielectric layer in regions configured for particular transistors. For example, another dipole layer 304 is formed over a subset of the gate dielectric portions 246A-246D. In some embodiments, the dipole layer 304 may similarly comprise an n-dipole material (e.g., GeO2, Y2O3, La2O3, SrO, other suitable n-dipole materials, or combinations thereof) or a precursor to an n-dipole material, a p-dipole material (e.g., Al2O3, Ga2O3, MgO, HfO2, TiO2, ZrO2, ZnO, other suitable p-dipole materials, or combinations thereof), or a precursor to a p-dipole material. In some embodiments, dipole layer 304 includes a dipole material that is the same as that of dipole layer 302. Having dipole layers 302 and 304 with the same dipole material simplifies processing and reduces costs.Alternatively, in some embodiments, dipole layer 304 may include a dipole material that is different from dipole layer 302. Having dipole layers 302 and 304 with different dipole materials provides further opportunities to adjust the threshold voltages of individual transistors and potentially improves functionality. In some embodiments, dipole layer 304 may be deposited to a substantially uniform thickness in a range of about 0.05 nm to about 1 nm (about 0.5 Å to about 10 Å) in various embodiments, such as from about 0.3 nm to about 0.5 nm (about 3 Å to about 5 Å). If the thickness is too small (such as less than 0.05 nm (0.5 Å)), dipole layer 304 may, in some cases, be too weak for Vt tuning.If the thickness is too large (such as greater than 1 nm (10 Å)), the dipole layer 304 may be too strong for Vt tuning and may create side effects, such as degraded mobility in the channel layers 120. In some embodiments, a thicker dipole layer 304 results in a larger change in the threshold voltage of the transistor. In some embodiments, the thickness of the dipole layer 304 may be smaller than the thickness of the dipole layer 302. For example, in some embodiments, the dipole layer 302 may have a thickness t1 and the dipole layer 304 may have a thickness t2. A difference between the thicknesses (t1-t2) may be about 0.01 nm to about 0.2 nm (about 0.1 Å to about 2 Å), for example about 0.03 nm to about 0.1 nm (about 0.3 Å to about 1 Å).In some embodiments, this difference in thickness provides more flexibility in adjusting the amount of dipole material of dipole layer 304 that subsequently diffuses into gate dielectric portions 246C and 246D. If the difference is too small, there may not be a sufficient difference in the final dipole material compositions between gate dielectric portions 246C / 246D and those of gate dielectric portions 246A / 246B. If the difference is too large, the additional material may not provide a significant difference in diffusion behavior. Alternatively, in some embodiments, thickness t1 is smaller than thickness t2 to meet certain specific design requirements (such as to create a specific threshold voltage cascade).

[0031] As described above, the dipole layer 304 is formed only on a subset of the gate dielectric portions 246A-246D (in other words, formed only for a subset of the transistors 100A-100D). In some embodiments, the dipole layer 304 is first formed over all transistors 100A-100D and then removed from certain transistor regions, such as the regions configured for transistors 100A and 100B. Accordingly, the dipole layer 304 remains only on the gate dielectric portions 246C and 246D and not on the gate dielectric portions 246A and 246B. The removal process may change the thicknesses of some of the gate dielectric portions. Accordingly, at this processing stage, the gate dielectric portions may each have thicknesses d3A-d3D.In some embodiments, the thicknesses d3A and d3B may be similar to the thicknesses d2A and d2B (due to good etch selectivity); while the thicknesses d3C and d3D may be substantially the same as the thicknesses d2C and d2D. In the illustrated embodiments, the dipole layer 304 directly interfaces with the gate dielectric portion 246C without the dipole material composition 2002 formed therein. And the dipole layer 304 further directly interfaces with the gate dielectric portion 246D with the dipole material composition 2002 formed therein. In other words, where the dipole layer 304 comprises a material different from that of the dipole layer 302, the top surface of the gate dielectric portion 246D may comprise two different dipole materials.

[0032] With reference to block 1060 of Fig. 1 and on Fig. 10, another process 404 is performed. In some embodiments, the process 404 includes a thermal drive-in process. The thermal drive-in process of the process 404 may be similar to the thermal drive-in process of the process 402 described above with respect to Fig. 8. In some embodiments, the thermal drive operation of process 404 may implement the same or different parameters than those of the thermal drive operation of process 402. In some embodiments, the thermal drive operation may implement a temperature lower than that of the thermal drive operation of process 402. For example, the thermal drive operation of process 402 may implement a dip temperature T1, and the thermal drive operation of process 404 may implement a dip temperature T2. A difference between the dip temperatures (T1-T2) may be about 50°C to about 250°C, for example, about 100°C to about 200°C.Adopting a higher annealing temperature during process 402 and a lower annealing temperature during process 404 enables better control of the diffusion behavior of the dipole materials and consequently provides more precise control of the dipole material distribution in the respective gate dielectric portions. As a result, better matching of the threshold voltages is achieved. If the temperature difference (T1-T2) is too small, this advantage may be lost; whereas, if the difference is too large, either the diffusion in the thermal drive process may become difficult to control or the diffusion in the thermal drive process may become insufficient. In some alternative embodiments, the temperature T2 may be higher than the temperature T1.For example, in some embodiments, implementing a higher temperature T2 may be useful to drive dipole materials of dipole layer 304 in an amount greater than that of dipole layer 302 and / or with a distribution wider than that of dipole layer 302. In some embodiments, such a greater amount and / or wider distribution may be useful to achieve certain threshold voltage configurations. Furthermore, in some embodiments, the thermal drive operation of process 404 may implement a time duration that is greater or lesser than that of the thermal drive operation of process 402, such that the dipole material of dipole layer 304 may migrate deeper or shallower into gate dielectric portions 246C and / or 246D than that of dipole layer 302 into gate dielectric portions 246B and / or 246D.In some embodiments, the thermal drive process of process 404 is configured to drive the dipole materials of dipole layer 304 deeper (than that of process 402 on dipole material composition 2002 at this processing stage) into the respective gate dielectric portions, despite using a lower annealing temperature and / or on a thinner dipole layer (compared to dipole layer 302). In some embodiments, the thermal drive process of process 402 may have a time duration τ1; the thermal drive process of process 404 may have a time duration τ2. In some embodiments, the time duration τ2 may be greater than the time duration τ1. For example, a difference (τ2-τ1) may be from about 1 second to about 30 minutes, such as from about 30 seconds to about 10 minutes.If the time difference is too small, the dipole material of the dipole layer 304 may not reach the desired depth; if the time difference is too large, the dipole material may diffuse too deep to reach the channel layers 120 and adversely affect device performance.

[0033] The thermal drive-in process of process 404 has two primary effects. The first effect is that the dipole material compositions 2002 are already formed within the gate dielectric portions 246B and 246D (see Fig. 12) migrate further deeper therein so that they can be distributed closer to the channel layers 120. The second effect is that the dipole materials of the dipole layer 304 diffuse into the gate dielectric portions 246C and the gate dielectric portions 246D. As a result, the gate dielectric portions 246C and 246D both comprise a specific dipole material composition 2004. The dipole material composition 2004 may be configured differently from the dipole material composition 2002, either in chemical identity or in concentrations. For example, the dipole material composition 2002 may comprise La2O3, while the dipole material composition 2004 may comprise Y2O3. Alternatively or additionally, the dipole material compositions 2002 and 2004 may both comprise the respective dipole materials (either the same or different from each other) in different concentrations.These parameters can be adjusted to tune the threshold voltage differences between the transistors.

[0034] In the gate dielectric part 246D, the dipole material composition 2002 (see Fig. 8) modified with the further diffusion of the dipole materials from the dipole layer 304, forming a dipole material composition 2042 (or diffusion feature 2042). The dipole material composition 2042 may be similar to a combination of the dipole material composition 2002 and the dipole material composition 2004. Where the materials of the dipole layer 302 and the dipole layer 304 are different, the dipole material composition 2042 comprises a mixture in the gate dielectric portion 246D. Where the materials of the dipole layer 302 and the dipole layer 304 are the same, the dipole material compositions 2002, 2004, and 2042 each comprise the same dipole material, although in different concentrations and with different distribution profiles.Dipole material composition 2042 may include the dipole material at the highest concentration, which may be similar to the sum of the concentrations in dipole material compositions 2002 and 2004. Further, in some embodiments, dipole material composition 2002 may be more deeply distributed than dipole material composition 2004 (because it has undergone two thermal drive-ins as opposed to one for dipole material composition 2004); while dipole material composition 2042 may have a broader distribution than dipole material compositions 2002 and 2004.

[0035] Still referring to Block 1060 of Fig. 1 and on Fig. 10, after the end of the thermal drive-in process, remaining portions of the dipole layer 304 on the gate dielectric layer are selectively removed in an etching process of the process 404, similar to the etching process of the process 402 described above. Accordingly, valuable space of the gate trenches 241 is not occupied by the dipole layer 304. Similar to those already described above with respect to Fig. 8, the thermal drive process of process 404 may be configured to create an intermix layer between the remaining portions of the dipole layer 304 and the gate dielectric portions 246C and 246D, which is absent in the gate dielectric portions 246A and 246B. Accordingly, the etch process may be configured to have good etch selectivity with respect to the dipole layer 304 relative to the gate dielectric layer 246. Nevertheless, the presence of the intermix layer may allow the etch process to deepen the top surfaces of the gate dielectric portions 246C and 246D. This reduces the thicknesses of the respective gate dielectric portions and the channel resistances in the transistors 100C and 100D. For example, following the etching of process 404, the gate dielectric portions 246A-246D may each have a thickness d4A-d4D.The thicknesses d4A and d4B may be substantially the same as the thicknesses d3A and d3B due to etch selectivity; while the thicknesses d4C and d4D may be smaller than the thicknesses d3C and d3D, respectively, due to the removal of the intermix layer. In some embodiments, the thickness d4C may be configured to be smaller than the thickness d4B. This enables a decreasing thickness trend from the gate dielectric portions 246A, 246B, 246C to 246D. Accordingly, as described later, a decreasing trend in the channel resistances is also achieved. This may be advantageous in applications where continuous adjustment of resistances is important. The relative size of the thickness d4C compared to the thickness d4B may be controlled by controlling the parameters of process 404 compared to process 402.For example, the thermal drive process of process 404 may be configured to be at a temperature higher than that of process 402 or for a duration longer than that of process 402. Accordingly, the intermixture layer formed on gate dielectric portion 246C may be thicker than that on gate dielectric portion 246B. As a result, a thicker portion of gate dielectric portion 246C may be formed in the etch process of process 404 (compared to that of gate dielectric portion 246B in the etch process of process 402). In some embodiments, the thickness d4B may be smaller than the thickness d4C. Such a configuration provides a zigzag trend in the channel resistances in the adjacent transistors 100A-100D and may be advantageous for controlling the overall resistance shift to remain within a certain threshold.

[0036] At this processing stage, the gate dielectric portions 246A-246D are each configured differently from one another. For example, the gate dielectric portion 246A includes no dipole material; the gate dielectric portion 246B includes the dipole material composition 2002; the gate dielectric portion 246C includes the dipole material composition 2004; and the gate dielectric portion 246D includes the dipole material composition 2004 (or the combination of dipole materials 2002 and 2004). The dipole material compositions 2002, 2004, and 2004 differ from one another in chemical identity, concentration, and / or distribution within the respective gate dielectric portion. Since each of these parameters affects the threshold voltage of the resulting transistor, transistors 100A-100D having these gate dielectric portions can provide different threshold voltages even if they have the same gate electrode layer.Furthermore, the thickness d4A may be substantially similar to the thickness d1A and may be greater than the thicknesses d4B-d4D; the thickness d4D may be smaller than the thicknesses d4B and d4C.

[0037] In some embodiments, with reference to block 1070 of Fig. 1 and Fig. 11, a process 406 is performed to further adjust the location and / or distribution of the dipole materials within the gate dielectric portions 246A-246D. In some embodiments, the process 406 includes a thermal (or annealing) process. For example, the device 10 is annealed at a temperature of about 600°C to about 1000°C, such as about 700°C to about 800°C, with O2, N2, or a mixture of O2 and N2 ambient. In another embodiment, the process 406 is a furnace anneal process at a temperature in a range of about 300°C to about 600°C with O2, N2, or a mixture of O2 and N2 ambient for about 1 second to about 30 minutes. In yet another embodiment, the process 406 is a spike anneal process. In yet another embodiment, the process 406 is a laser anneal process or a microwave anneal process.microwave anneal process) at a temperature in a range of about 800°C to about 1200°C with O2, N2, NH3, H2, or a mixture thereof for about 1 millisecond to about 10 seconds. In some embodiments, process 406 is configured to cause further migration of the dipole materials toward the channel layers 120. As described later, this may improve the effectiveness of threshold voltage tuning. In some embodiments, process 406 may be configured to cause the dipole materials within the gate dielectric portions to become randomized and achieve a normalized distribution (as opposed to a lagging distribution) so that threshold voltage control may be improved. In some embodiments, although not specifically shown, process 406 is instead performed between process 402 and process 404.In some embodiments, although not specifically illustrated, process 406 is performed both between process 402 and process 404 and following process 404. In some embodiments, process 406 is omitted.

[0038] In some embodiments, additional dipole layers are formed over a subset of the gate dielectric portions, and additional thermal drive and etch operations are performed to form transistors with additionally differentiated threshold voltages. In some embodiments, such additional dipole layers are omitted. In some embodiments (referring to the "A" branch of Fig. 1), the method 1000 continues to form the gate electrode layer 248 (block 1080 of Fig. 1) and complete the fabrication of the gate structures 250. In some other embodiments, with reference to the “B” branch of Fig. 1 and on Fig. 12, however, in some embodiments, another gate dielectric layer 246' is formed over the gate dielectric layer 246. The gate dielectric layer 246' may be similar to the gate dielectric layer 246 described above. In some embodiments, the gate dielectric layer 246' may comprise the same or a different material and undergo the same or different processing than the gate dielectric layer 246. For example, different portions of the gate dielectric layer 246' may be configured to have different dipole material compositions. In the illustrated embodiments, the gate dielectric layer 246' is configured in the same manner as the gate dielectric layer 246.For example, the gate dielectric layer 246' of the transistor portion 200A may not include any dipole materials; the gate dielectric layer 246' of the transistor portion 200B may include a dipole material composition 2002' similar to that described above with respect to FIG. Fig. 10; the gate dielectric layer 246' of the transistor portion 200C may comprise a dipole material 2004' similar to that described above with respect to Fig. 10; the gate dielectric layer 246' of the transistor portion 200D may comprise a dipole material 2042' similar to that described above with respect to Fig. 10 described dipole material 2042. Accordingly, after processing similar to those already described with respect to Fig. 7-10, the processed gate dielectric layer 246' may be similar or equal to the processed gate dielectric layer 246 described above with respect to Fig. 10. In other words, the processed gate dielectric layers 246 and 246' can be considered as sublayers of a thicker gate dielectric structure. Additional gate dielectric layers can be further formed, and the cycle of processing blocks 1020-1070 of Fig. 1 can be repeated until the desired total thickness of the gate dielectric layer is reached.

[0039] In some embodiments, forming the gate dielectric structure in a layer-by-layer approach may allow each layer (such as layer 246 and layer 246') to be thinner for better processability. Furthermore, such an approach may also allow for better control of the distributions and profiles of the dipole materials within the gate dielectric structure, thereby improving the tuning capacity and reliability of the threshold voltage. For example, the threshold voltages may be adjusted incrementally to provide better control precision. Alternatively, the gate dielectric layer 246' may comprise a material different from the gate dielectric layer 246 and / or adopt a configuration of dipole materials different from that of the gate dielectric layer 246'.In such embodiments, more substrate regions with different dipole configurations may be provided, providing even more opportunity to create multi-Vt offerings. In some embodiments, additional gate dielectric layers may be formed over the gate dielectric layer 246' and processed in a similar manner to those already described above with respect to FIG. Fig. 7-11 were described.

[0040] With reference to block 1080 of Fig. 1 and on Fig. 12, the method 1000 forms a gate electrode layer 248 over the processed gate dielectric layer(s). The gate electrode layer 248 is formed on the top surface of the gate dielectric layer 246' (or additional gate dielectric layers formed thereon). Referring again to Fig. 2B and Fig. 2C, the gate electrode layer 248 encloses the gate dielectric layer 246 above each of the channel layers 120. The gate electrode layer 248 may fully or partially fill the gate trenches 241 in various embodiments. The gate electrode layer 248, in combination with the gate dielectric layers, is designed to provide appropriate threshold voltages for the various NMOS and PMOS transistors. In some embodiments, the gate electrode layer 248 for the NMOS transistors 100A-100D comprises any suitable n-type work function metal materials, such as titanium nitride (TiN), ruthenium (Ru), iridium (Ir), osmium (Os), rhodium (Rh), or combinations thereof.The gate electrode layer 248 for the PMOS transistors 100A'-100D' comprises any suitable p-type work function metal materials, such as titanium (Ti), aluminum (Al), tantalum (Ta), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum carbide (TaC), tantalum carbide nitride (TaCN), tantalum silicon nitride (TaSiN), or combinations thereof. Although not explicitly illustrated, the gate electrode layer 248 of NMOS and / or PMOS transistors may further comprise a fill metal layer. The fill metal layer may comprise any suitable materials, such as aluminum (Al), tungsten (W), copper (Cu), cobalt (Co), nickel (Ni), platinum (Pt), ruthenium (Ru), or combinations thereof. The conductive metal layer fills the remaining spaces of the gate trenches 241. In some embodiments, a chemical mechanical polishing process is performed to expose a top surface of the ILD layer 230.Accordingly, the gate dielectric layer 246 and the gate electrode layer 248 together form the high-k metal gate stack, which replaces the original dummy gate stack 240. The high-k metal gate stack and the gate spacer layers 201 and 202 together form the new gate structures 250. The gate structures 250 engage a plurality of channel layers 120 to form a plurality of gate channels. Referring to block 1090 of FIG. Fig. 1, the method 1000 continues to complete device fabrication. For example, silicide features, contact features, via features, metal lines, and passivation layers, among others, may be formed.

[0041] In the present embodiment, the difference in the threshold voltages of the transistors can be fully tuned through the dipole material incorporations discussed above, so that a common gate electrode layer 248 can be used for all NMOS transistors (such as transistors 100A-100D) or for all PMOS transistors (such as transistors 100A'-100D'). This avoids the need to use different work function metal layers (or different gate electrode layers) to achieve the diversity in threshold voltages. Thus, embodiments of the present disclosure enable the use of a thinner work function metal layer(s) for device 10 than other approaches and are suitable for miniaturized multi-gate devices, such as nanosheet-based devices.It should be noted that the gate electrode layer 248 may include multiple sublayers, but it is still a common layer for multiple transistors (such as transistors 100A-100D or transistors 100A'-100D'). In some embodiments, the transistors 100A-100D (or the transistors 100A'-100D') may each have different gate electrode layers to provide an even further (or greater) amount of threshold voltage tuning. In some embodiments, the present disclosure may be further implemented to allow transistors of different conductivity types (e.g., NMOS and PMOS) to use the same gate electrode layers.

[0042] The embodiments provided above allow for effective tuning of the threshold voltages. Fig. 13 shows a diagram illustrating the Vt tunability according to one embodiment of the method. In this embodiment, transistors in a device (such as device 10) are provided with four different threshold voltages. In this example, by incorporating dipole material composition 2002 into transistor 100B, the threshold voltage is adjusted by -40 mV compared to transistor 100A without a dipole material. By incorporating dipole material composition 2004 into transistor 100C, the threshold voltage is adjusted by -76 mV compared to transistor 100A. Furthermore, by incorporating dipole material composition 2042 into transistor 100D, the threshold voltage is adjusted by -114 mV compared to transistor 100A. Furthermore, this tunability agrees well with the target values ​​of the threshold voltages at -40 mV, -80 mV, and -120 mV, respectively.In other words, by simply tuning the presence and / or configuration (e.g., chemical identity, concentration, and distribution) of the dipole material compositions in the gate dielectric layers, multi-Vt devices can be reliably achieved with a tuning capacitance of down to -120 mV. Furthermore, the channel resistance penalty of an NMOS device formed in this manner exhibits a reduced channel resistance penalty of approximately +0.03 kΩ fin (compared to +0.1 kΩ fin with some other approaches). Meanwhile, the channel resistance penalty of a PMOS device formed in this manner exhibits a negligible channel resistance penalty (compared to +0.2 to +0.3 kΩ fin with some other approaches). In other words, the method provides good Vt linearity, comparable leakage current (Igi), and low channel resistance penalties compared to some other approaches.Device improvements are thus obtained with the methods described here.

[0043] Embodiments of the present disclosure can be adjusted to provide even wider threshold voltage tuning capabilities without significantly increasing processing complexity. For example, Fig. 14 provides a flow diagram of an alternative embodiment of the method of the present disclosure (method 2000) for manufacturing a device 20. Fig. 15 provides a top view of an embodiment of devices (such as device 20) of the present disclosure, in accordance with some embodiments of the present disclosure. Fig. 16-21 show cross-sectional views of the device 20 at different processing stages according to the flow diagram of Fig. 14. Method 2000 enables the fabrication of device 20 with NMOS transistors having six (6) different threshold voltages and PMOS transistors having another six (6) different threshold voltages. This is in Fig. 15, the device 20 is generally similar to the device 10 of Fig. 1, except that it includes six NMOS transistors 100A-100F and six PMOS transistors 100A'-100F'. Note that reference numerals have been reused in subsequent descriptions for simplicity and clarity.

[0044] With reference to Block 2020 of Fig. 14, the method 2000 begins by receiving a workpiece on which the various transistors are formed, each with channel layers engaged by a dummy gate stack, similar to that described above with reference to Fig. 2B and Fig. 2C. The method 2000 continues to remove the dummy gate stack 240, thereby forming the gate trenches 241, similar to that of Fig. 4. With reference to Block 2030 of Fig. 14 and on Fig. 16, a gate dielectric layer 246 is formed in the gate trenches 241 around each of the channel layers 120, similar to that described above with reference to Fig. 5. Furthermore, with reference to block 2040 of Fig. 14 and on Fig. 16 dipole layers are formed on each of the gate dielectric portions 246A-246F. As shown in Fig. As illustrated in Figure 16, the dipole layers in different regions 100A-100F are configured differently. For example, gate dielectric portions 246A and 246B have no dipole layers formed thereon; gate dielectric portions 246C and 246D have dipole layer 304 thereon; and gate dielectric portions 246E and 246F have both dipole layers 302 and 304 thereon. Accordingly, at this processing stage, the surface of transistor portions 100A-100F has uneven surfaces. In other words, the material layers surrounding the gate dielectric portions 246E-246F in the transistor portions 200E-200F are thicker than those surrounding the gate dielectric portions 246C-246D in the transistor portions 200C-200D, which are thicker than those surrounding the gate dielectric portions 246A-246B in the transistor portions 200A-200B.For example, the dipole layer 302 may be similar to the dipole layer 302 described above, comprising a similar material and having a similar thickness. The dipole layers 304 may comprise the same or different materials as the dipole layers 302. Furthermore, the dipole layers 302 and 304 may be conformal and have thicknesses adjusted based on the desired threshold voltage of the transistors, as described above. In the illustrated embodiments, the dipole layer 304 has a thickness greater than the dipole layer 302 to provide a greater concentration of dipole materials in the gate dielectric portions with which it interfaces, as described in detail below.

[0045] Any suitable methods may be used to determine the configurations of the Fig. 16. For example, the dipole layer 302 may first be formed bare and / or conformally over all device regions 100A-100F and subsequently partially removed (e.g., patterned) to cover only the device regions 100A, 100B, 100E, and 100F. In other words, surfaces of the gate dielectric portions 246C and 246D in transistor portions 200C and 200D are exposed in the gate trenches 241. Dipole layer 304 is then formed on all exposed surfaces, including, for example, on the surface of dipole layer 302, on (or around) gate dielectric portions 246A-246B and 246E-246D, and on (or around) the surface of gate dielectric portions 246C and 246D. Accordingly, dipole layer 304 is spaced from gate dielectric layer 246 in transistor portions 200A, 200B, 200E, and 200F, but directly contacts gate dielectric layer 246 in transistor portions 200C and 200D.The dipole layers 302 and 304 in the device regions 100A-100B are then removed while the dipole layers in the device regions 100C-100F are retained, for example, by implementing a mask element that covers the device regions 100C-100F while exposing the device regions 100A and 100B. Any other suitable methods may alternatively be used.

[0046] With reference to Block 2050 of Fig. 14 and on Fig. 17, a process 502 is performed. The process 502 may be similar to the process 402 described above with respect to Fig. 8. For example, process 502 includes a thermal drive process that causes the dipole materials of dipole layer 302 as well as the dipole materials of dipole layer 304 to diffuse into the respective gate dielectric portions below. The thermal drive process may be similar to the thermal drive processes of process 402. For example, parameters of the thermal drive process of process 502 may be adjusted to tune the amount of the dipole materials of dipole layer 302 and / or the dipole materials of dipole 304 to be driven into the gate dielectric layer 246. The parameters may include the annealing temperature and the time duration.These parameters, together with the chemical identities of the dipole materials of the dipole layers 302 and 304 and the thicknesses of the dipole layers 302 and 304, are designed to provide suitable dipole material compositions within the respective gate dielectric portions, similar to those already discussed with respect to the device 10. In some embodiments, since the dipole layer 302 directly interfaces with the gate dielectric portions 246E and 246F, while the dipole layer 304 is spaced apart from the gate dielectric portions 246E and 246F, a larger portion of the dipole layer 302 diffuses into the gate dielectric portions 246E and 246F than the dipole layer 304. In addition, since more dipole materials are located on the gate dielectric portions 246E and 246F (e.g.both dipole layers 302 and 304) than on the gate dielectric portions 246C and 246D, a larger total amount (including dipole materials from the dipole layer 302 and the dipole layer 304) into the gate dielectric portions 246E and 246F than into the gate dielectric portions 246C and 246D.

[0047] Following the thermal drive process, gate dielectric portions 246A and 246B do not include any dipole materials. Gate dielectric portions 246C and 246D include dipole materials from dipole layer 304, but not from dipole layer 302. This combination of dipole materials is referred to as dipole material composition 2040. Gate dielectric portions 246E and 246F include dipole materials from dipole layer 304, as well as the dipole material from dipole layer 302. This combination of dipole materials is referred to as dipole material 2042. Where dipole layers 302 and 304 include different materials, dipole material composition 2040 may be a single dipole material composition, while dipole material 2042 may include a mixture.Where dipole layers 302 and 304 comprise the same materials, dipole material composition 2040 and dipole material composition 2042 may comprise the same material, although in different concentrations. Similar to those discussed above with respect to . Fig. 8, a portion of the dipole layer 302 and a portion of the dipole layer 304 remain on surfaces of the gate dielectric layer 246 at the end of the thermal drive-in process of process 502. Thereafter, still referring to block 2050 of Fig. 14, these remaining parts are removed in an etching process of process 502, similar to the etching process of process 402 described above with respect to Fig. 8 was described.

[0048] Accordingly, at this processing stage, portions of the gate dielectric layer 246 in different substrate regions have different dipole material compositions. This distinction alone enables the device 20 to provide three (3) different threshold voltages for each transistor type. In addition, similar to process 402, the thermal drive process of process 502 similarly creates an intermix layer at the interface of the gate dielectric layer and the dipole layer 302 and / or 304. In some embodiments, this intermix layer is recessed or removed during the etch process of process 502, similar to the situation in the etch process of process 402. As a result, the thicknesses of the respective gate dielectric portions may be reduced. For example, following process 502, the gate dielectric portions 246A-246F each have a respective thickness of d3A-d3F.The thickness d3A and d3B may be substantially the same as the thickness d2A and d2B (cf. Fig. 15) due to the etch selectivity implemented during the etching process of process 502. However, the thickness d3C-d3F may be smaller than the thickness d2C-d2F, respectively, due to the removal of the intermix layer.

[0049] With reference to Block 2060 of Fig. 14 and on Fig. 18, another dipole layer 306 is formed on the gate dielectric portions 246A-246F. In the illustrated embodiments, the dipole layer 306 is formed on the gate dielectric portions 246B, 246D, and 246F, but not on the gate dielectric portions 246A, 246C, and 246E. The dipole layer 306 may be similar to the dipole layers 302 and / or 304. For example, the dipole layer 306 may comprise a material similar to or different from those of the dipole layers 302 and / or 304. In some embodiments, the dipole layer 306 has a thickness that is less than the dipole layer 304, which in turn has a thickness that is less than the dipole layer 302, for reasons similar to those discussed above with respect to Fig. 8. Any suitable methods may be used to determine the Fig. 18. For example, the dipole layer 306 may be formed conformally over all device regions 100A-100F and on surfaces of the modified gate dielectric layer 246, as shown in Fig. 17. Subsequently, the dipole layer 306 is partially removed from surfaces of the gate dielectric portions 246A, 246C, and 246E, for example, by implementing a patterning process. The bottom surfaces of the remaining dipole layer 306 may form an interface with gate dielectric portions having different dipole material compositions. For example, the dipole layer 306 directly interfaces with the gate dielectric portion 246B, which does not include any dipole materials; the dipole layer 306 directly interfaces with the gate dielectric portion 246D, which includes a dipole material composition 2040; and the dipole layer 306 directly interfaces with the gate dielectric portion 246F, which includes a dipole material composition 2042.

[0050] With reference to Block 2070 of Fig. 14 and on Fig. 19, another process 504 is performed. In some embodiments, process 504 includes a thermal drive-in process similar to the thermal drive-in process of process 404. In some embodiments, the thermal drive-in process may implement the same or different parameters as those of the thermal drive-in process of process 502. In some embodiments, the thermal drive-in process of process 504 may implement a temperature that is lower than that of the thermal drive-in process of process 502. For example, the thermal drive-in process of process 502 may implement a dipping temperature T1, and the thermal drive-in process of process 504 may implement a dipping temperature T2. A difference between the dipping temperatures (T1-T2) may be about 50°C to about 250°C, for example, about 100°C to about 200°C.Adopting a higher annealing temperature during process 502 and a lower annealing temperature during process 504 enables better control of the diffusion behavior of the dipole materials and subsequently provides more precise control of the dipole material distribution in the respective gate dielectric portions. Consequently, better matching of the threshold voltages is achieved. If the temperature difference (T1-T2) is too small, this advantage may be lost; whereas, if the difference is too large, either the diffusion during the thermal drive process may become difficult to control or the diffusion during the thermal drive process may become insufficient.

[0051] Furthermore, in some embodiments, the thermal drive process of process 504 may implement a time duration that is greater or lesser than that of the thermal drive process of process 502, such that the dipole material of dipole layer 306 may migrate deeper or shallower into gate dielectric portions 246B, 246D, and / or 246F during the thermal drive process of process 502 than that of dipole layer 302 or 304 into gate dielectric portions 246C and / or 246E (see Fig. 17). In some embodiments, the thermal drive process of process 502 may have a time duration τ1; the thermal drive process of process 504 may have a time duration τ2. In some embodiments, the time duration τ2 may be greater than the time duration τ2. For example, a difference (τ2-τ1) may be about 1 second to about 30 minutes, such as about 30 seconds to about 10 minutes. In some embodiments, the thermal drive process of process 504 is configured to drive the dipole materials of dipole layer 306 deeper (than the thermal drive process of process 502) into the respective gate dielectric portions, despite using a lower anneal temperature and / or on a thinner dipole layer (compared to dipole layer 302).If the time difference is too small, the dipole material of the dipole layer 304 may not reach the desired depth; if the time difference is too large, the dipole material may diffuse too deep to reach the channel layers 120 and adversely affect device performance.

[0052] Regardless, because the dipole material compositions 2040 and 2042 in the gate dielectric portions 246C and 246E each undergo two thermal drive processes, they may migrate to an overall deeper region of the gate dielectric portions and be closer to the channel layers 120. Other parameters of the thermal drive process of process 504 may be further adjusted based on the desired threshold voltage tuning range. As the end of the thermal drive process of process 504, the gate dielectric portion 246A includes no dipole materials; the gate dielectric portion 246B includes the materials of the dipole layer 306 and not those from the dipole layers 302 or 304. This dipole material combination is referred to as the dipole material composition 2600.The gate dielectric portion 246C is not affected by the formation of the dipole layer 306 or the thermal drive process of process 504, so it retains the dipole material composition 2040 as described above. The gate dielectric portion 246D comprises the dipole material composition 2040 prior to the formation of the dipole layer 306 and the thermal drive process of process 504, and further comprises received diffusions of the materials from the dipole layer 306. Accordingly, the gate dielectric portion 246D comprises materials from the original dipole layer 304 as well as from the dipole layer 306. This combination is referred to as the dipole material composition 2040. The gate dielectric portion 246E is not affected by the formation of the dipole layer 306 or the thermal drive process of process 504, so it maintains the dipole material composition 2042 as described above.The gate dielectric portion 246F includes the dipole material composition 2042 prior to the formation of the dipole layer 306 and the thermal drive process of process 504, as well as received diffusions of the materials from the dipole layer 306. Accordingly, the gate dielectric portion 246D includes materials from the original dipole layers 302 and 304, as well as from the dipole layer 306. This combination is referred to as the dipole material composition 2642.

[0053] Still referring to Block 2070 of Fig. 14 and on Fig. 19, after the end of the thermal drive process, another etch is performed, similar to the etch of process 404 and / or process 502. The etch of process 504 not only removes the additional dipole materials above the gate dielectric layers, it also causes the thicknesses of the gate dielectric portions 246A-246F to vary from one another. For example, the gate dielectric portions 246A-246F may have thicknesses d4A-d4F, respectively, following the etch of process 504. In some embodiments, the thicknesses d4A, d4C, and d4E remain substantially the same as the thicknesses d3A, d3C, and d3E, respectively; although the thicknesses d4B, d4D, and d4F may be smaller than the thicknesses d3B, d3D, and d3F, respectively. As described above, this may be due to the formation of intermixture layers at the interface of the gate dielectric layer 246 and the dipole layer 306 in the relevant substrate regions.As also described above, such a reduction in the layer thickness of the gate dielectric parts reduces the channel resistances R. ch .

[0054] In some embodiments, dipole layers 302, 304, and 306 differ from each other in chemical identities and / or layer thicknesses. Further, as described above, parameters of the thermal drive processes of processes 502 and 504 may differ from each other. Accordingly, dipole materials 2600, 2040, 2640, 2042, and 2642 differ from each other in chemical identities, concentrations, and / or distributions within the respective portions of gate dielectric layer 246. As a result, when combined with the gate electrode layer, they each provide a unique threshold voltage that is different from each other and further different from that of transistor 100A, which does not include such dipole materials, regardless of whether the gate electrode layer is the same or different.

[0055] With reference to Block 2080 of Fig. 14 and on Fig. 20, a process 506 is performed to further adjust the location and / or distribution of the dipole materials within the gate dielectric portions 246A-246F. In some embodiments, the process 506 includes a thermal process (or annealing process). For example, the device 20 is annealed at a temperature of about 600°C to about 1000°C, such as about 700°C to about 800°C, with O2, N2, or a mixture of O2 and N2 ambient. In another embodiment, the process 506 is a furnace anneal process at a temperature in a range of about 300°C to about 600°C with O2, N2, or a mixture of O2 and N2 ambient for about 1 second to about 30 minutes. In yet another embodiment, the process 506 is a spike anneal process. In yet another embodiment, the process 506 is a laser anneal process or a microwave anneal process.microwave anneal process) at a temperature in a range of about 800°C to about 1200°C with O2, N2, NH3, H2, or a mixture thereof for about 1 millisecond to about 10 seconds. In some embodiments, process 506 is configured to cause further migration of the dipole materials toward the channel layers 120. As described later, this may improve the effectiveness of threshold voltage tuning. In some embodiments, process 506 may be configured to cause the dipole materials within the gate dielectric portions to become randomized and achieve a normalized distribution (as opposed to a lagging distribution) so that threshold voltage control may be improved. In some embodiments, although not specifically shown, process 506 is instead performed between process 502 and process 504.In some embodiments, although not specifically illustrated, process 506 is performed both between process 502 and process 504 and following process 504. In some embodiments, process 506 is omitted.

[0056] In some embodiments, additional dipole layers are formed over a subset of the gate dielectric portions, and additional thermal drive-in operations and etching operations are performed to form transistors with additionally differentiated threshold voltages. In some embodiments, such additional dipole layers are omitted. Referring to branch "A" of Fig. 14, in some embodiments, the method 2000 continues with block 2090 to form the gate electrode layer. In other embodiments, referring to branch "B" of Fig. 14, the method 2000 continues back to block 2030 to repeat the formation of another layer of the gate dielectric layer 246'. In such embodiments, with reference to Fig. 21, the additional gate dielectric layers 246' may be formed on upper surfaces of the gate dielectric layer 246, similar to that described above with respect to device 10. Further, with reference to block 2090 of Fig. 14 and on Fig. 21, the gate electrode layer 248 is formed on the top surface of the gate dielectric layer 246' (or additional gate dielectric layers formed thereon). In some embodiments, the portions of the gate electrode layer 248 that interface with the gate dielectric portions 246A-246F are identical, e.g., they have identical material compositions.

[0057] With reference to block 2100 of Fig. 14, the method 2000 continues to complete device fabrication. For example, silicide features, contact features, via features, metal lines, and passivation layers, among others, may be formed.

[0058] Fig. Figure 22 shows a diagram illustrating Vt tuning capability according to one embodiment of the method. In this embodiment, transistors in a device (such as device 20) are provided with six different threshold voltages. In this example, by incorporating dipole material 2600 into transistor 100B, the threshold voltage is adjusted by -48 mV compared to transistor 100A without a dipole material. By incorporating dipole material composition 2040 into transistor 100C, the threshold voltage is adjusted by -88 mV compared to transistor 100A.Furthermore, by incorporating dipole material composition 2640 into transistor 100D, the threshold voltage is adjusted by -121 mV compared to transistor 100A; by incorporating dipole material composition 2042 into transistor 100E, the threshold voltage is adjusted by -174 mV compared to transistor 100A; and by incorporating dipole material composition 2642 into transistor 100F, the threshold voltage is adjusted by -214 mV compared to transistor 100A. Furthermore, this tunability matches the target values ​​at -40 mV, -80 mV, -120 mV, -160 mV, and -200 mV, respectively. In other words, by simply tuning the presence and / or configuration (e.g., chemical identity, concentration, and / or distribution) of the dipole materials in the gate dielectric layers, a multi-Vt device with a tuning capacity of down to -200 mV can be reliably achieved. Furthermore, the channel resistance Rch For PMOS transistors, the fin resistance is reduced from about +0.2 kΩ to about 0.3 kΩ by implementing the present disclosure, without implementing the methods provided herein. Compared to some other approaches, the method provides good Vt linearity, comparable leakage current, and reduced channel resistance penalties, all of which lead to device improvements.

[0059] Fig. 23A-23C provide more details regarding the diffusion and distribution of the dipole materials than results from the thermal drive-in processes 402A and 404A or 502A and 504. Fig. 23A is a schematic view of the distribution of dipole materials in the gate dielectric layer 246. Line 702 represents the interface between the gate dielectric layer 246 and the interface layer 242; line 708 represents the interface between the interface layer 242 and the channel layer 120; line 710 represents the top surface of the gate dielectric layer 246 (which is also the interface between the gate dielectric layer and the subsequently formed gate electrode layer 248); line 704 represents the centerline 704 (or half-thickness line 704) of the gate dielectric layer 246; and region 706 represents a region that refers to the region with a thickness of about 1 nm to about 2 nm centered on the interface 702. In some embodiments, the dipole materials have dissimilar distributions in different transistors. For example, as in Fig. 23A, the dipole materials of transistor 100D have a broader distribution profile than the dipole materials of transistor 100E. In particular, there may be a larger amount of dipole materials distributed near the top surface 710 of gate dielectric portion 246D than that of gate dielectric portion 246E; and there may be a smaller amount of dipole materials distributed within region 706 of gate dielectric portion 246D than that of gate dielectric portion 246E. Fig. Figure 23B illustrates an example distribution of dipole materials as a function of location within the gate dielectric layer 246 and the interface layer 242, as well as other adjacent layers. Fig. 23B may have been simplified or conceptualized. The vertical axis of Fig. Figure 23B illustrates the dosage of the dipole materials as measured. In some embodiments, these thermal drive processes are designed so that some of the dipole materials can migrate through the gate dielectric layer 246 and reach the interface layer 242. Moreover, although not explicitly shown, in some embodiments, some dipole materials can further diffuse into the interface layer 242. For example, at least a portion of the dipole materials are distributed in the region 706. In some embodiments, having the dipole materials close to the channel layer 120 allows for greater tunability of the threshold voltage, even without increasing the amount of dipole moment. However, having the dipole material too close to the channel layers can adversely affect other device characteristics.In some embodiments, dipole materials within the narrow region 706 exhibit the maximum threshold voltage tuning efficiency. In other words, threshold voltages are more sensitive to the dipole materials within the region 706 than to dipole materials outside the region 706. For example, referring to FIG. Fig. 23C for a gate dielectric layer of HfO2 doped with La2O3 of the present disclosure, a linear fit of a plot of the change in threshold voltage (ΔV fb) to the ratio of the lanthanum element to the hafnium element at the interface line 702 provides a determination coefficient (R2) of about 0.98. Therefore, the threshold voltage responds not only to the chemical identities of the dipole materials, the concentrations of the dipole materials, as well as the physical locations of the dipole materials in relation to the interface 702. By utilizing this relationship, additional tunability is achieved. It is noted that the present disclosure further provides tighter control over the ΔV f compared to other approaches that do not implement any disclosure herein. For example, a similar graphical representation to that of Fig. 23C, which does not implement the methods described here, provides an R2 of less than 0.95.

[0060] With reference to Fig. 23A-23C and Fig. 24, as described above, the parameters of the dipole layers 302, 304, and 306, as well as the parameters of the thermal drive processes 502A and 504A, can be adjusted to control the location and distribution of the diffused dipole materials. In some embodiments, the materials of the dipole layers 302, 304, and 306 are identical to each other. Accordingly, the dipole materials 2600, 2040, 2640, 2042, and 2642 are also identical, although in varying amounts. In some embodiments, it is desirable to configure the adjacent transistors to have alternating (rather than continuously increasing or decreasing) dipole material concentrations. For example, with reference to Fig. 24, it may be desirable to configure the concentration (or dosage) of the dipole materials to increase in the order of the gate dielectric portions 246A < 246C < 246B < 246E < 246D < 246F. In some embodiments, this configuration maximizes processing efficiency and control accuracy. Meanwhile, it may be desirable to configure the threshold voltages of the neighboring transistors to change continuously (rather than alternately). In some embodiments, this allows for easier adjustment and selection of the threshold voltages during operation. In other words, it may be desirable to configure the threshold voltage tuning capacitance to increase in the order of the gate dielectric portions 246A < 246B < 246C < 246D < 246E < 246F.In some embodiments, this may be achieved by configuring the distribution of dipole materials in gate dielectric portions 246B, 246D, and 246F to be different from those in gate dielectric portions 246C and 246E. For example, with particular reference to FIG. Fig. 23B, the distribution of dipole materials within gate dielectric portions 246C and 246E is configured to have a peak (e.g., with the highest concentration) at or near interface line 702 (comparing the peak of curve 246C / 246E relative to line 702). In some embodiments, the distribution of dipole materials within gate dielectric portions 246C and 246E is configured to have a peak within region 706. Meanwhile, the distribution of dipole materials within gate dielectric portions 246B, 246D, and 246F is configured to have a peak at or near centerline 704 (or half-thickness line 704) of gate dielectric layer 246.Furthermore, the distribution of the dipole materials within the gate dielectric portions 246A-246F is configured to have increasing concentrations at the interface line 702 according to the order 246A < 246B < 246C < 246D < 246E < 246F. Accordingly, since the threshold voltage is most sensitive to the dipole materials within the region 706 around the interface line 702, the threshold voltage tuning capacitance order is configured in a continuous manner, although the total concentration of the dipole material is configured in an alternating manner.In some embodiments, the dipole material distribution described above is achieved by adopting a smaller layer thickness for the dipole layer 306 than the dipole layer 304, a smaller layer thickness than the dipole layer 302, a lower annealing temperature (T2) for the thermal drive process 504A than the thermal drive process 502A (T1), or a longer annealing time (t2) for the thermal drive process 504A than the thermal drive process 502A (t2), as described above. In some embodiments (not shown), the concentration of the dipole material in the gate dielectric portion 246D is lower than that in the gate dielectric portion 246E.

[0061] As described above, the etch processes 402B, 404B, 502B and / or 504B remove a portion of the relevant gate dielectric parts due to the presence of the intermix layers. Fig. 25A illustrates that following the etching process 504B, which removes the remaining portions of the dipole layer 306 on the gate dielectric portions 246B, 246D, and 246F, as well as the intermix layer thereon, the thickness of the gate dielectric portions is significantly reduced compared to other approaches that do not implement the methods of the present disclosure. For example, compared to other approaches, the thickness of the gate dielectric portions 246C and 246E is reduced by about 0.1 nm to about 0.2 nm (about 1 Å to about 2 Å), respectively. The reduction in the thickness of the gate dielectric portion results in a reduction in the channel resistances R ch . Referring to Fig. 25B, embodiments of the present disclosure illustrate reduced R chFor example, such a reduction in the channel resistance of NMOS transistors can be approximately 0.1 kΩ per fin to approximately 0.3 kΩ per fin. Additionally, the reduced gate dielectric parts enable a larger processing window and simpler manufacturing.

[0062] In some embodiments, the etch parameters (such as etch temperature, etch solution concentration, etch time, other suitable wet etch parameters, or combinations thereof) of the different etching operations (402B, 404B, 502B, and / or 504B) may be adjusted to provide a different amount of thinning of the respective gate dielectric portions. Fig. 26A and Fig.26B illustrate an effect of the etch time on the etching process 504B as an example. In the illustrated example, etch condition 1 implements an etch time of 105 s; while etch condition 2 implements an etch time of 210 s. As illustrated, etch condition 2 results in a further reduced La dosage. Furthermore, the channel resistances of the transistors with etch condition 2 are further reduced by about 0.03 kΩ fin to about 1.0 kΩ fin, such as about 0.05 kΩ fin to about 0.08 kΩ fin, compared to etch condition 1.

[0063] Although not intended to be limiting, one or more embodiments of the present disclosure provide many advantages for a semiconductor device and its fabrication. For example, the present disclosure provides methods for using dipole materials to construct transistors with threshold voltage tuning capabilities, in some cases without additional gate electrode layers (or work function metal layers). A threshold voltage tuning range of about 180 mV to about 220 mV is achieved. This represents an improvement over other approaches by about 100 mV to about 150 mV. Furthermore, since any additional dipole materials are removed after the thermal drive process, no additional volume or space is required compared to other approaches. In other words, this can be referred to as a "volumeless" approach.In some embodiments, the use of methods provided herein avoids the need to pattern work-function metal layer(s), making them highly suitable for nano-sized transistors and enabling continued downsizing. Compared to approaches that implement work-function metals while adjusting threshold voltages, where the metals often remain in the finished devices, the R. ch-Disadvantage is improved. Furthermore, in some embodiments, the large threshold voltage tuning capability of the device 10 or 20 presented herein enables the fabrication of PMOS transistors with ultra-low threshold voltages, such as those conventionally available only with silicon germanium (SiGe) channel layers. Accordingly, in some embodiments, the present disclosure can be implemented in PMOS devices without SiGe channel layers, such as with Si channel layers alone. In some embodiments, the formation of SiGe channel layers requires more complicated device processing. Accordingly, the present disclosure enables simpler and lower-cost fabrication of devices with similar threshold voltage tuning capabilities.In some other embodiments, the present disclosure may be implemented with SiGe channel layers to provide even greater threshold voltage tuning capability. Furthermore, the present embodiments may be readily integrated into existing CMOS manufacturing processes.

[0064] Methods 1000 and 2000 are merely examples and are not intended to limit the present disclosure to what is explicitly illustrated. For example, although the above disclosure describes the dielectric layers 246 being formed as part of the gate replacement process, in some alternative embodiments, the gate dielectric layers 246 may be formed at an earlier processing stage, e.g., prior to the formation of the dummy gate stacks. Additional steps may be provided before, during, or after methods 1000 or 2000, and some described steps may be replaced, eliminated, or shifted for additional embodiments of the method. Not all steps are described in detail here for simplicity.

[0065] In one exemplary aspect, the present disclosure relates to a method. The method includes forming a dielectric layer on a semiconductor workpiece, forming a first patterned layer of a first dipole material on the dielectric layer, and performing a first thermal drive process at a first temperature to form a diffusion feature in a first portion of the dielectric layer beneath the first patterned layer. The method also includes forming a second patterned layer of a second dipole material, wherein a first portion of the second patterned layer is on the diffusion feature and a second patterned layer is offset from the diffusion feature. The method further includes performing a second thermal drive process at a second temperature, wherein the second temperature is less than the first temperature.The method additionally comprises forming a gate electrode layer on the dielectric layer.

[0066] In some embodiments, the first thermal drive process is performed for a first time duration, the second thermal drive process is performed for a second time duration, and the first time duration is less than the second time duration. In some embodiments, the first patterned layer has a first thickness, the second patterned layer has a second thickness, and the first thickness is greater than the second thickness. In some embodiments, performing the first thermal drive process includes configuring the first thermal drive process to form a first intermix layer at an interface between the dielectric layer and the first patterned layer. In some embodiments, the method further includes, after performing the first thermal drive process, removing a remaining portion of the first patterned layer and the first intermix layer.In some embodiments, performing the second thermal drive process includes configuring the second thermal drive process to form a second intermix layer at an interface between the first portion of the second patterned layer and the dielectric layer and a third intermix layer at an interface between the second portion of the second patterned layer and the dielectric layer. The method further includes, after performing the second thermal drive process, removing a remaining portion of the second patterned layer, the second intermix layer, and the third intermix layer.In some embodiments, the dielectric layer is a first dielectric layer, and the method further comprises, after performing the second thermal drive process, forming a second dielectric layer on the first dielectric layer, forming a third patterned dipole layer on the second dielectric layer, and performing a third thermal drive process.In some embodiments, forming the first patterned layer comprises forming a patterned sublayer covering a first region of the dielectric layer while exposing a second region of the dielectric layer, forming another sublayer on the patterned sublayer in the first region and on and interfacing with the dielectric layer in the second region, and collectively patterning the patterned sublayer and the another sublayer to expose the dielectric layer in a subset of the first region, thereby forming the first patterned layer. In some embodiments, the semiconductor workpiece comprises a plurality of channel layers stacked vertically on a semiconductor substrate, and the dielectric layer is formed around the channel layers.

[0067] In one exemplary aspect, the present disclosure relates to a method. The method includes forming a dielectric layer on a semiconductor workpiece, forming a first patterned layer of a first dipole material on the dielectric layer, performing a first thermal drive process to drive a portion of the first dipole material into the dielectric layer, and performing a first etch process to remove a remaining portion of the first dipole material. The method also includes forming a second patterned layer of a second dipole material on the dielectric layer, wherein a first portion of the second patterned layer is disposed on a first portion of the dielectric layer without the first dipole material and a second portion of the second patterned layer is disposed on a second portion of the dielectric layer with the first dipole material.The method further comprises performing a second thermal drive-in process for a second time period, wherein the second temperature is less than the first temperature. The method additionally comprises performing a second etch process to remove a remaining portion of the first dipole material, wherein performing the first etch process includes removing an intermixture region of the dielectric layer including the first dipole material.

[0068] In some embodiments, the method further comprises forming a gate electrode layer on the dielectric layer, wherein the gate electrode layer and the dielectric layer surround a plurality of channel layers. In some embodiments, performing the second etch comprises recessing an intermixture region of the dielectric layer comprising the second dipole material. In some embodiments, performing the second etch comprises recessing an intermixture region of the dielectric layer comprising both the first dipole material and the second dipole material. In some embodiments, performing the first thermal drive comprises performing at a first temperature, and performing the second thermal drive comprises performing at a second temperature, and the first temperature is greater than the second temperature.In some embodiments, a difference between the first temperature and the second temperature is about 100°C to about 200°C.

[0069] In one exemplary aspect, the present disclosure relates to a semiconductor device. The semiconductor device comprises a semiconductor substrate, a first transistor on the semiconductor substrate, and a second transistor on the semiconductor substrate. The first transistor comprises a first channel, a first interface layer, a first gate dielectric layer on the first channel, and a first gate electrode layer on and at the interface with the first gate dielectric layer. The second transistor comprises a second channel, a second interface layer, a second gate dielectric layer on the second channel, and a second gate electrode layer on and at the interface with the second gate dielectric layer. The first gate electrode layer and the second gate electrode layer have a same composition.The first gate dielectric layer comprises a first dipole material composition having a maximum concentration at a half-thickness line of the first gate dielectric layer. The second gate dielectric layer comprises a second dipole material composition having a maximum concentration at an interface between the second gate dielectric layer and the second interface layer.

[0070] In some embodiments, the dipole material comprises one of germanium oxide (GeO2), yttrium oxide (Y2O3), lanthanum oxide (La2O3), strontium oxide (SrO), magnesium oxide (MgO), hafnium (HfO2), zirconium oxide (ZrO2), titanium oxide (TiO2), and aluminum oxide (Al2O3). In some embodiments, the second dipole material composition comprises the first dipole material composition and a third dipole material composition. In some embodiments, the first channel is one of a first plurality of channels of the first transistor, and the second channel is one of a second plurality of channels of the second transistor. In some embodiments, the semiconductor device further comprises a third transistor having a third gate dielectric layer. The third gate dielectric layer is free of the first dipole material composition and free of the second dipole material composition.

Claims

[1] A procedure (1000, 2000) which includes: Forming a dielectric layer (246) on a semiconductor workpiece; Forming a first structured layer (302) of a first dipole material on the dielectric layer (246); Performing a first thermal drive-in process (402) at a first temperature to form a diffusion feature (2002) in a first portion of the dielectric layer (246) beneath the first patterned layer (302); Forming a second structured layer (304) of a second dipole material, wherein a first portion of the second structured layer (304) is on the diffusion feature (2002) and a second portion of the second structured layer (304) is offset from the diffusion feature (2002); Performing a second thermal driving process (404) at a second temperature, wherein the second temperature is lower than the first temperature by a difference of 50°C to 250°C; and Forming a gate electrode layer (248) on the dielectric layer (246). [2] The method (1000, 2000) of claim 1, wherein the first thermal driving operation (402) is performed for a first time period, the second thermal driving operation (404) is performed for a second time period, and the first time period is less than the second time period. [3] The method (1000, 2000) of claim 1 or 2, wherein the first structured layer (302) has a first thickness and the second structured layer (304) has a second thickness, and the first thickness is greater than the second thickness. [4] The method (1000, 2000) of any preceding claim, wherein performing the first thermal drive process (402) comprises configuring the first thermal drive process (402) to form a first intermix layer at an interface between the dielectric layer (246) and the first patterned layer (302). [5] The method (1000, 2000) of claim 4, further comprising, after performing the first thermal drive-in process (402), removing a remaining portion of the first patterned layer (302) and the first intermediate mixture layer. [6] The method (1000, 2000) of any preceding claim, wherein performing the second thermal drive process (404) comprises configuring the second thermal drive process (404) to form a second intermix layer at an interface between the first portion of the second structured layer (304) and the dielectric layer (246) and a third intermix layer at an interface (702) between the second portion of the second structured layer (304) and the dielectric layer (246), and the method (1000, 2000) further comprises, after performing the second thermal drive process (404), removing a remaining portion of the second structured layer (304), the second intermix layer, and the third intermix layer. [7] The method (1000, 2000) of any preceding claim, wherein the dielectric layer (246) is a first dielectric layer (246), the method (1000, 2000) further comprising: after performing the second thermal drive-in process (404), forming a second dielectric layer (246) on the first dielectric layer (246); Forming a third structured dipole layer on the second dielectric layer (246); and Performing a third thermal driving process [8] The method (1000, 2000) according to any one of the preceding claims, wherein forming the first structured layer (302) comprises: Forming a patterned sublayer covering a first region of the dielectric layer (246) while exposing a second region of the dielectric layer (246); Forming a further sublayer on the structured sublayer in the first region and on and in interface with the dielectric layer (246) in the second region; and collectively patterning the patterned sublayer and the further sublayer to expose the dielectric layer (246) in a subset of the first region, thereby forming the first patterned layer (302). [9] The method (1000, 2000) of any preceding claim, wherein the semiconductor workpiece comprises a plurality of channel layers (120) stacked vertically on a semiconductor substrate (102), and wherein the dielectric layer (246) is formed around the channel layers (120). [10] Procedure (1000, 2000) comprising: Forming a dielectric layer (246) on a semiconductor workpiece; Forming a first structured layer (302) of a first dipole material on the dielectric layer (246); Performing a first thermal drive-in process (402) to drive a portion of the first dipole material into the dielectric layer (246); performing a first etching process to remove a remaining portion of the first dipole material; Forming a second structured layer (304) of a second dipole material on the dielectric layer (246), wherein a first portion of the second structured layer (304) is disposed on a first portion of the dielectric layer (246) without the first dipole material and a second portion of the second structured layer (304) is disposed on a second portion of the dielectric layer (246) with the first dipole material; Performing a second thermal driving process (404) for a second period of time, wherein the second temperature is less than the first temperature, and wherein a difference between the first temperature and the second temperature is 50°C to 250°C; and Performing a second etching process to remove a remaining portion of the first dipole material, wherein performing the first etching operation comprises removing an intermixture region of the dielectric layer (246) including the first dipole material. [11] The method (1000, 2000) of claim 10, further comprising forming a gate electrode layer (248) on the dielectric layer (246), wherein the gate electrode layer (248) and the dielectric layer (246) surround a plurality of channel layers (120). [12] The method (1000, 2000) of claim 10 or 11, wherein performing the second etching operation comprises recessing an intermixture region of the dielectric layer (246) comprising the second dipole material. [13] The method (1000, 2000) of claim 10 or 11, wherein performing the second etching operation comprises recessing an intermixture region of the dielectric layer (246) comprising both the first dipole material and the second dipole material. [14] The method (1000, 2000) of any one of claims 10 to 13, wherein the first structured layer (302) has a first thickness and the second structured layer (304) has a second thickness, and the first thickness is greater than the second thickness. [15] The method (1000, 2000) of any one of claims 10 to 14, wherein the first thermal driving operation (402) is performed for a first period of time, the second thermal driving operation (404) is performed for a second period of time, and the first period of time is less than the second period of time. [16] A semiconductor device comprising: a semiconductor substrate (102); a first transistor on the semiconductor substrate (102) having a first channel (120), a first interface layer (242), a first gate dielectric layer (246) on the first channel (120) and a first gate electrode layer (248) on and at the interface with the first gate dielectric layer (246); and a second transistor on the semiconductor substrate (102) having a second channel (120), a second interface layer (242), a second gate dielectric layer (246) on the second channel (120) and a second gate electrode layer (248) on and at the interface with the second gate dielectric layer (246), wherein the first gate electrode layer (248) and the second gate electrode layer (248) have the same composition, wherein the first gate dielectric layer (246) comprises a first dipole material composition having a maximum concentration at a half-thickness line (704) of the first gate dielectric layer (246), and wherein the second gate dielectric layer (246) comprises a second dipole material composition having a maximum concentration at an interface (702) between the second gate dielectric layer (246) and the second interface layer (242). [17] The semiconductor device according to claim 16, wherein the dipole material comprises one of germanium oxide (GeO2), yttrium oxide (Y2O3), lanthanum oxide (La2O3), strontium oxide (SrO), magnesium oxide (MgO), hafnium oxide (HfO2), zirconium oxide (ZrO2), titanium oxide (TiO2) and aluminum oxide (Al2O3). [18] The semiconductor device according to claim 16 or 17, wherein the second dipole material composition comprises the first dipole material composition and a third dipole material composition. [19] The semiconductor device according to any one of claims 16 to 18, wherein the first channel (120) is one of a first plurality of channels (120) of the first transistor, and the second channel (120) is one of a second plurality of channels (120) of the second transistor. [20] The semiconductor device of any one of claims 16 to 19, further comprising a third transistor having a third gate dielectric layer, wherein the third gate dielectric layer is free of the first dipole material composition and free of the second dipole material composition, and wherein the first transistor, the second transistor, and the third transistor are arranged adjacent to each other such that the concentrations of the first dipole material composition, the second dipole material composition, and a third dipole material composition of the third transistor alternate.

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