Motion-sensitive field effect transmitter, motion detection system and method

Abstract

transistor (110) comprising: a canal region (112); and a gate structure (113) adjacent to the canal region (112) and encompassing: a reservoir (114) configured to contain a conductive fluid (116); and at least one gate electrode (118, 118a, 118b, 118a) 1-n , 118b 1-n , 618) at a fixed location within the reservoir (114), wherein an orientation of the channel region (112) relative to an upper surface (119) of the conducting fluid (116) depends on a movement of the transistor (110) and wherein a contact between the at least one gate electrode (118, 118a, 118b, 118a 1-n , 118b 1-n , 618) and the conducting fluid (116) depends on the orientation of the channel region (112) relative to the upper surface (119) of the conducting fluid (116).

Description

BACKGROUND Area of ​​the invention

[0001] The present invention relates to on-chip motion sensors and in particular embodiments of a motion-sensitive field effect transistor (MSFET), a motion detection system and related methods. Description of the state of the art

[0002] Many applications running on computerized devices (e.g., smartphones, digital cameras, security systems, virtual reality (VR) systems, gaming systems, etc.) are motion-detection applications. Such motion-detection applications include, but are not limited to, automatic drive / do-not-disturb mode applications, image stabilization applications, anti-theft or other security applications, motion-detection audible applications, VR or gaming applications, etc. Motion detection is typically achieved by using a micro-electro-mechanical system (MEMS) accelerometer, which measures acceleration forces on an object without a fixed reference. Acceleration forces can be static (e.g., gravity) or dynamic (e.g., motion or vibration). Acceleration forces can also be directional.The most commonly used MEMS accelerometer is a capacitive on-chip accelerometer. Unfortunately, such accelerometers consume a significant amount (if not all) of the IC chip's surface area. A liquid metal transistor for gate control, utilizing the triboelectric effect, is known from CN 1 09 029 358 A. An accelerometer with two electrodes and a cavity between them, containing a liquid layer partially filling the cavity, is also known from EP 3 355 068 A1. Furthermore, a capacitive multi-electrode tilt sensor is known from US 5 083 383 A. A tilt sensor with a container of electrolyte fluid for wetting the sensor electrodes is also known from DE 34 11 252 A1. BRIEF SUMMARY

[0003] This document discloses embodiments of a motion-sensing field-effect transistor (MSFET) that has at least one motion-dependent electrical property, such that the MSFET can be used as a motion sensor. In particular, the disclosed MSFET can comprise a channel region positioned laterally between source / drain regions. The MSFET can further comprise a gate structure. The gate structure can comprise a reservoir with a bottom adjacent to the channel region. A conductive fluid can be contained within the reservoir and can, in particular, only partially fill the reservoir. It should be noted that the reservoir can be capped to prevent leakage of the fluid, so that the amount of fluid contained within the reservoir is fixed. The gate structure can further comprise at least one gate electrode located at a fixed position within the reservoir.Given the fixed location of each gate electrode within the reservoir and the fill level of the conducting fluid within the reservoir, contact between the gate electrodes and the conducting fluid depends on the orientation of the channel region relative to the upper surface of the conducting fluid, and the orientation of the channel region relative to the upper surface of the conducting fluid depends on a position in space and / or motion of the MSFET and, in particular, the position in space and / or motion (e.g., tilt and / or acceleration) of the chip on which the MSFET is formed.

[0004] With such an MSFET structure, an electrical property varies as a function of the total effective gate voltage applied to the conducting fluid through the gate electrode(s) (or sub-electrodes thereof), and the total effective gate voltage applied to the conducting fluid varies as a function of which of the gate electrode(s) (or, if applicable, which of the sub-electrodes thereof) is / are in contact with the conducting fluid. Since the contact between the conducting fluid and the gate electrode(s) (or sub-electrodes thereof) is motion-dependent, chip motion (e.g., chip tilt and / or acceleration) can be characterized based on the value of the electrical property measured in response to specific bias conditions. Therefore, embodiments of a motion detection system (MDS) incorporating the MSFET described above, and a motion detection method, are also disclosed here.

[0005] In particular, disclosed embodiments of an MDS can comprise a chip. The chip can comprise an MSFET, as described above. That is, the MSFET can comprise a channel region positioned laterally between source / drain regions. The MSFET can further comprise a gate structure. The gate structure can comprise a reservoir with a bottom adjacent to the channel region. A conductive fluid can be contained within the reservoir and, in particular, can only partially fill the reservoir. The gate structure can comprise at least one gate electrode located at a fixed position within the reservoir. The chip can further comprise a bias circuit electrically connected to the MSFET and configured to apply specific bias conditions to the MSFET.The chip can further include a sampling circuit electrically connected to the MSFET and configured to sample (e.g., detect and measure) an electrical property of the MSFET in response to specific bias conditions. The system can also include a controller (e.g., a processor), which may be either on-chip or off-chip, that communicates with the bias circuit and the sampling circuit and can characterize chip movement (e.g., chip tilt and / or acceleration) based on the measured value of the electrical property in response to the specific bias conditions.

[0006] Disclosed embodiments of a motion detection method may include providing a chip with an MSFET, as described above. That is, the MSFET may include a channel region positioned laterally between source / drain regions. The MSFET may further include a gate structure. The gate structure may include a reservoir with a bottom adjacent to the channel region. A conductive fluid may be contained within the reservoir and, in particular, may only partially fill the reservoir. The gate structure may further include at least one gate electrode located at a fixed position within the reservoir. The method may further include applying specific bias conditions to the MSFET. The specific bias conditions may, for example, be applied by an on-chip bias circuit electrically connected to the MSFET. The method may further include scanning (e.g.,The method may include detecting and measuring an electrical property of the MSFET in response to specific bias conditions. This electrical property can be sampled, for example, by an on-chip sampling circuit electrically connected to the MSFET. The method may further include characterizing chip motion (e.g., chip tilt and / or acceleration) based on the measured value of the electrical property in response to the specific bias conditions. This chip motion can be characterized, for example, by a controller (e.g., a processor), either on-chip or off-chip, that communicates with the bias circuit and the sampling circuit.

[0007] As further discussed in the detailed description section below, the sensitivity of the disclosed MDS and method can be improved by increasing the number of gate electrodes and / or by incorporating stacked electrically insulated sub-electrodes within each gate electrode. BRIEF DESCRIPTION OF THE MULTIPLE VIEWS OF THE DRAWINGS

[0008] The present invention will be better understood from the following detailed description with reference to the drawings, which are not necessarily drawn to scale and in which: Fig. 1 a schematic diagram illustrating embodiments of a motion detection system (MDS) comprising a motion sensing field effect transistor (MSFET) having at least one motion-dependent electrical property; Fig. Section diagrams 2A to 2C illustrate an embodiment of an MSFET that is integrated into the MDS of Fig. 1 can be included; Fig. Section diagrams 3A to 3C-2 illustrate an alternative embodiment of an MSFET that is integrated into the MDS of Fig. 1 can be included; Fig. Section diagrams 4A to 4C-2 illustrate another alternative embodiment of an MSFET that is integrated into the MDS of Fig. 1 can be included; Fig. Section diagrams 5A to 5C-2 illustrate yet another alternative embodiment of an MSFET that is integrated into the MDS of Fig. 1 can be included; Fig. Figures 6A-6D are exemplary layout diagrams for the gate electrode(s) in some MSFET implementations; Fig. Figures 7-9 are cross-sectional diagrams illustrating alternative gate electrode configurations in some MSFET implementations; Fig. 10 is a cross-sectional diagram showing the gate structure of the MSFET of Fig. 5A-5C-2 illustrated in more detail; Fig. Tables 11-12 illustrate exemplary gate electrode bias conditions and motion-dependent changes in the total effective gate voltage; Fig. 13 is a graph illustrating a relationship between changes in an electrolyte solution depth adjacent to a given gate electrode with 10 sub-electrodes and changes in the total effective voltage applied to the electrolyte solution as a function of different values ​​of f; Fig. 14 is a flowchart illustrating embodiments of a motion detection method; Fig. 15A and Fig. 15B Cross-sectional diagrams are shown, illustrating alternative cover layer shapes; and Fig. 16 is a schematic diagram illustrating a representative computer system for implementing one or more features of the disclosed motion detection system and method. DETAILED DESCRIPTION

[0009] As mentioned above, many applications running on electronic devices or systems (e.g., smartphones, digital cameras, security systems, virtual reality (VR) systems, gaming systems, etc.) are motion-sensing applications. Such motion-sensing applications include, but are not limited to, automatic drive / do not disturb mode applications, image stabilization applications, anti-theft or other security applications, motion-sensing audible applications, VR or gaming applications, etc. Motion detection is typically achieved by using a micro-electro-mechanical system (MEMS) accelerometer, which measures acceleration forces on an object without a fixed reference. Acceleration forces can be static (e.g., gravity) or dynamic (e.g., motion or vibration). Acceleration forces can also be directional.The most commonly used MEMS accelerometer is a capacitive on-chip accelerometer, which comprises a combination of both fixed and flexible capacitor plates on an integrated circuit (IC) chip. When an object (e.g., an electronic device) embedding the IC chip, and thus the MEMS accelerometer, experiences acceleration, the distance between the fixed and flexible capacitor plates changes, and consequently, so does the electrical capacitance. However, to accurately detect linear motion, the on-chip MEMS accelerometer must be relatively large (e.g., >50 micrometers (µm)), such that it occupies a significant portion (if not all) of the IC chip's surface area.

[0010] In light of the foregoing, embodiments of a motion-sensing field-effect transistor (MSFET) are disclosed herein, configured to exhibit at least one motion-dependent electrical property such that it can be used as a motion sensor. In particular, the MSFET may comprise a gate structure adjacent to a channel region comprising: a reservoir containing a conductive fluid and one or more gate electrodes located at fixed positions within the reservoir.Given the fixed location of each gate electrode within the reservoir and the fill level of the conducting fluid within the reservoir, contact between the gate electrode(s) and the conducting fluid depends on the orientation of the channel region relative to the upper surface of the conducting fluid. This orientation, in turn, depends on the position in space and / or motion of the MSFET, and especially on the position in space and / or motion (e.g., tilt and / or acceleration) of the chip on which the MSFET is formed. With such an MSFET structure, an electrical property responsive to specific bias conditions varies as a function of whether the gate electrode(s) (or, if applicable, sub-electrodes thereof) is / are in contact with the conducting fluid. Thus, the electrical property can be measured to detect chip motion (e.g., tilting, acceleration).to characterize chip tilt and / or acceleration). Also disclosed herein are embodiments of a motion detection system (MDS) incorporating such an MSFET, and embodiments of a motion detection method employing such an MSFET.

[0011] Referring to Fig. 1 herein disclose embodiments of a motion detection system (MDS) 100 and also embodiments of a motion-sensing field-effect transistor (MSFET) 110, which has at least one motion-dependent electrical property and which is integrated into the MDS 100 (e.g., as a motion sensor). Exemplary MSFET structures 110, which may be integrated into the MDS 100, include, but are not limited to, the MSFET 110.1 as described in Fig. 2A to 2C, the MSFET 110.2, as shown in Fig. 3A to 3C-2 shown, the MSFET 110.3, as in Fig. 4A to 4C-2 shown, and the MSFET 110.4, as in Fig. 5A to 5C-2 shown.

[0012] In particular, the MDS 100 can include an integrated circuit (IC) 102 chip. The MDS 100 can be entirely contained on the IC 102 (i.e., it can be a system-on-chip (SOC)). Alternatively, the MDS 100 can include components that are both on-chip and off-chip.

[0013] In any case, the chip 102 can comprise a semiconductor substrate 101. The semiconductor substrate 101 can, for example, be a bulk semiconductor substrate (e.g., a bulk silicon substrate or any other type of bulk semiconductor substrate), as illustrated. Alternatively, the semiconductor substrate 101 can be a semiconductor-on-insulator substrate (e.g., a silicon-on-insulator (SOI) substrate). Isolation regions 105 (e.g., shallow trench isolation (STI) regions) in the substrate 101 (e.g., in the top section of a bulk semiconductor substrate or in the semiconductor layer of a semiconductor-on-insulator substrate) can define an active device region for a motion-sensing field-effect transistor (MSFET) 110 (e.g., an MSFET 110.1, as shown in Fig. 2A to 2C shown; an MSFET 110.2, as in Fig. 3A to 3C-2 shown; an MSFET 110.3, as in Fig. 4A to 4C-2 shown; or an MSFET 110.4, as shown in Fig. 5A to 5C-2 shown).

[0014] The MSFET 110.1, 110.2, 110.3, 110.4 can be either an N-type MSFET or a P-type MSFET. Specifically, the MSFET 110.1, 110.2, 110.3, 110.4 can include source / drain regions 111 and a channel region 112 within the active device region, positioned laterally between the source / drain regions 111. For example, for an N-type MSFET, the source / drain regions 111 can be N+ source / drain regions doped with an N-type dopant to exhibit a relatively high conductivity level, and the channel region 112 can be a P- channel region doped with a P-type dopant to exhibit a relatively low conductivity level.For a P-type MSFET, the source / drain regions 111 can be P+ source / drain regions doped with a P-type dopant to exhibit a relatively high conductivity level, and the channel region 112 can be an N- channel region doped with an N-type dopant to exhibit a relatively low conductivity level. One or more layers of a dielectric material 106 can cover the MSFET 110.1, 110.2, 110.3, 110.4, and in particular the source / drain regions 111. The dielectric material 106 can comprise an interlayer dielectric (ILD) material. The ILD material 106 can, for example, comprise silicon dioxide, doped silicon glass (e.g., phosphosilicate glass (PSG) or boron phosphosilicate glass (BPSG)), or any other suitable ILD material.

[0015] The MSFET 110.1, 110.2, 110.3, 110.4 can further comprise a gate structure 113, and in particular a conductive fluid-containing gate structure, where the gate metal or doped polysilicon is replaced by a conductive fluid (e.g., an electrolyte solution). Specifically, the gate structure 113 can comprise a reservoir 114 (herein also referred to as a container, a microwave, a trench, a cavity, etc.) structured within the dielectric material 106 and aligned with, and having a bottom adjacent to, the channel region 112. For illustrative purposes, the side walls of the reservoir 114 are shown as being substantially vertical. However, it should be understood that the figures are not intended to be limiting and that the shape of the reservoir 114 may vary depending on the technique used to form the reservoir 114.For example, as with the reservoir used in various known ISFET structures, the reservoir 114 of the disclosed MSFETs 110.1, 110.2, 110.3, 110.4 could be angled, stepped, curved, etc. The gate structure 113 can further comprise one or more gate dielectric layers 115 (e.g., a silicon dioxide layer or another suitable gate dielectric layer) at the bottom of the reservoir 114 immediately adjacent to the channel region 112. For illustrative purposes, a gate dielectric layer 115 is shown only as being within and at the bottom of the reservoir 114. However, it should be understood that the figures are not intended to be limiting.Alternatively, for example, a gate dielectric layer 115 could conformally line the bottom and side walls of the reservoir 114, or the gate dielectric layer 115 could be a layer embedded within the dielectric material 106, and the reservoir 114 could be structured and etched such that the bottom of the reservoir 114 rests against the gate dielectric layer. The gate structure 113 can further comprise a conductive fluid 116 and one or more gate electrodes contained within the reservoir 114. Finally, the reservoir 114 can be capped (e.g., by a capping layer 107).

[0016] Experts will recognize that a conventional ion-sensitive FET (ISFET) similarly features a fluid-containing gate structure. In the case of an ISFET, the fluid can be an electrolyte solution flowing into the reservoir, so that it is immediately adjacent to the gate dielectric layer. A reference gate electrode can be in constant contact with the fluid. Specific bias conditions can be applied to the terminals of the ISFET, and an electrical response can be measured to characterize and / or identify a target in the fluid. For example, a drain current (Id) of an ISFET responding to a fixed drain / source voltage and a fixed gate voltage can be considered ion-sensitive. In this case, changes in the concentration of ions (e.g.,Changes in the concentration of hydrogen (H+) ions or other such ions within a fluid flowing into the reservoir result in changes in the surface potential at the interface between the gate dielectric layer and the fluid, and a surface potential change can result in a threshold voltage change. Such a threshold voltage change, in turn, results in a change in the drain current (Id). Thus, the ISFET can be used to measure and / or characterize a target (e.g., pH or another target) in the fluid and is often used as a biosensor.

[0017] The gate structure 113 of the MSFET 110.1, 110.2, 110.3, 110.4, while similar to the gate structure of an ISFET in that it is a fluid-containing gate structure, differs from the gate structure of an ISFET because it is specifically configured to characterize a movement (e.g. tilt and / or acceleration) of a chip 102 on which the MSFET is formed (as opposed to measuring or characterizing a target within the fluid).

[0018] In particular, in the gate structure 113, the reservoir 114 is only partially filled with a certain fixed amount of the conductive fluid 116 (e.g., filled with the conductive fluid to a certain fixed level that is less than the full volume of the reservoir). The conductive fluid 116 can be an electrolyte solution. Exemplary electrolyte solutions that could be used in the gate structure 113 include, but are not limited to, solutions of calcium chloride, potassium chloride, calcium hydroxide, and nitrogen hydroxide. Alternatively, any other suitable electrolyte solutions could be used. However, it should be understood that care should be taken to avoid electrolyte solutions with the potential to cause corrosion of exposed materials (e.g., the ILD layer and / or the cap layer). Care should also be taken to avoid solutions with the potential to cause failure of semiconductor devices.For example, an electrolyte solution containing sulfuric acid should be avoided unless the ILD layer 106 and the lid layer 107 are made of glass. Electrolyte solutions containing sodium salts should be avoided because sodium ions migrating into the semiconductor substrate could cause semiconductor device failures. Other considerations for the electrolyte solution include stability and viscosity, and optionally, additives to optimize efficiency.

[0019] The cover layer 107 can cover the reservoir 114 to prevent loss or leakage of the conductive fluid 116 from the reservoir 114, thus maintaining a constant level of conductive fluid 116 throughout. The cover layer 107 can be an insulating layer. This insulating layer could be an organic planarization layer (OPL), a spin-on glass layer, a silicon dioxide layer, a polymer layer, a Teflon layer, or any other suitable insulating layer, as discussed in more detail below. The cover layer 107 could be a single-layer structure or, alternatively, a multi-layer structure (e.g., a laminate structure). Optionally, the cover layer 107 can include a port 108 (i.e., an opening extending vertically through the cover layer 107 to the reservoir 114) to allow the addition of a fixed amount of conductive fluid 116 to the reservoir 114 (e.g.,To facilitate the injection of the conductive fluid 116 into the reservoir following the manufacturing process, as opposed to during the manufacturing process. The port 108 can be plugged (e.g., with a snap-on plug or a plug of any other suitable material type) once the conductive fluid 116 has been added to the reservoir, thus preventing any subsequent loss or leakage of the conductive fluid.

[0020] Given the fixed location of each gate electrode within reservoir 114 and the fill level 150 of the conducting fluid 116 within reservoir 114, contact between the gate electrode(s) and the conducting fluid 116 depends on the orientation of the channel region 112 relative to the upper surface 119 of the conducting fluid 116, and the orientation of the channel region 112 relative to the upper surface 119 of the conducting fluid 116 depends on a position in space and / or movement of the MSFET 110.1, 110.2, 110.3, 110.4 and, in particular, a position in space and / or movement (e.g., tilt and / or acceleration) of the chip 102 on which the MSFET is formed.

[0021] With the disclosed MSFET structure, an electrical property varies as a function of the total effective gate voltage applied to the conducting fluid 116 by the gate electrode(s) (or sub-electrodes thereof), and the total effective gate voltage applied to the conducting fluid 116 varies as a function of which of the gate electrode(s) (or, if applicable, which of the sub-electrodes thereof) is / are in contact with the conducting fluid. Since the contact between the conducting fluid 116 and the gate electrode(s) (or sub-electrodes thereof) is motion-dependent, chip motion (e.g., chip tilt and / or acceleration) can be characterized based on the value of the electrical property measured in response to specific bias conditions.

[0022] In particular, the volume of the conductive fluid 116 contained within the reservoir 114 can be any fixed proportion of the total volume of the reservoir 114 (e.g., half, two-thirds, etc.). The fixed quantity of the conductive fluid 116 can be selected such that when the chip 102 is upright (i.e., with the bottom surface of the substrate 101 being closest to the Earth's surface), horizontal (i.e., with the bottom surface of the substrate 101 parallel to the Earth's surface), and stationary (i.e.,(is not moving), at least the following conditions are met: (a) the conducting fluid 116 is immediately adjacent to and completely covers the gate dielectric layer 115 (or a portion thereof) at the bottom of the reservoir 114; (b) the exposed surface 119 of the conducting fluid 116, which is not immediately adjacent to the bottom or side walls of the reservoir 114 and which is also referred to herein as the upper surface of the conducting fluid 116, is parallel to the bottom surface of the substrate 101 (and thus parallel to the channel region 112 within the substrate 101) and is furthermore at a certain solid fill level 150 between the gate dielectric layer 115 and the top of the reservoir 114; and (c) an air- or gas-filled space 117 is also contained within the reservoir 114 between the upper surface 119 of the conducting fluid 116 and the cover layer 107 at the top of the reservoir 114.The fixed quantity of the conductive fluid 116 can further be selected such that the orientation of the channel region 112 relative to the upper surface 119 of the conductive fluid 116 varies and, in particular, responds to a movement of the chip 102 (i.e., responds to a tilting or rotation of the chip 102 in a certain direction and / or responds to an acceleration of the chip 102 in a certain direction) from parallel to angled. For example, the fixed quantity of a conductive fluid 116 can be selected such that a space 117 filled with air or gas remains within the reservoir 114 to allow the conductive fluid to move within the reservoir 114 in response to a movement (e.g., a tilting and / or acceleration) of the chip.The ratio of the volume of a conducting fluid 116 to the volume of the air- or gas-filled space 117 should be such that, if a rotational force causes the chip 102 to tilt / rotate, the upper surface 119 of the conducting fluid 116 remains parallel to the Earth's surface due to gravity acting on the conducting fluid 116. Thus, the channel region 112 is angled relative to the upper surface 119 of the conducting fluid 116. Additionally or alternatively, the ratio of the volume of a conducting fluid 116 to the volume of the air- or gas-filled space 117 should be such that, if an acceleration force causes the chip 102 to accelerate in one direction (e.g., parallel to the Earth's surface), the conducting fluid 116 slides back in the opposite direction. Thus, the channel region 112 is similarly angled relative to the upper surface 119 of the conducting fluid 116.

[0023] The number, locations and configurations of the gate electrode(s) in the reservoir 114 of the gate structure 113 of the disclosed MSFETs 110.1, 110.2, 110.3 and 110.4 vary and as a result also the motion sensitivity.

[0024] For example, with reference to Fig. 2A to 2C comprise an MSFET 110.1 comprising a single gate electrode 118. The gate electrode 118 may be made of a metal or metal alloy material. The metal or metal alloy material of the gate electrode may be preselected to avoid the possibility of corrosion and / or oxygen formation on it. Exemplary metal or metal alloy materials for the gate electrode include, but are not limited to, platinum or gold. In any case, the gate electrode 118 may be located in a fixed position within the reservoir 114.For example, the fixed location of the gate electrode 118 can be between the bottom and the top of the reservoir 114, such that when the chip 102 is upright, horizontal, and stationary, the following conditions are met: (a) the channel region 112 and the upper surface 119 of the conducting fluid 116 are parallel; (b) the upper surface 119 of the conducting fluid 116 is at a given fill level 150; and (c) the gate electrode 118 is in contact with the conducting fluid 116, as shown in . Fig. 2A is shown. The fixed location of the gate electrode 118 can furthermore be closer to a first side of the reservoir 114 than it is to a second side opposite the first side. As a result, due to an upward tilt of the chip 102 on the first side (e.g., as in Fig. 2B shown) and / or an acceleration of chip 102 in a first direction from the second side towards the first side (e.g. as in Fig. (2C shown) the channel region 112 is angled at least to a specific degree (e.g. at least to a certain specific angle (θ)) relative to the upper surface 119 of the conducting fluid 116 and the level of the conducting fluid 116 at the first side of the reservoir 114 falls, so that the gate electrode 118 is physically separated from the conducting fluid 116.

[0025] Referring to Fig. In 3A to 3C-2, an MSFET 110.2 can comprise multiple gate electrodes, and in particular at least one first gate electrode 118a and one second gate electrode 118b. Each of the gate electrodes can be made of a metal or metal alloy material. The metal or metal alloy material of the gate electrodes can be preselected to avoid the possibility of corrosion and / or oxygen formation on them. Exemplary metal or metal alloy materials for the gate electrodes include, but are not limited to, platinum or gold. In any case, the first gate electrode 118a and the second gate electrode 118b can be located at different fixed locations within the reservoir 114.For example, the fixed locations of the gate electrodes (comprising the fixed locations of the first and second gate electrodes 118a-118b) can be between the bottom and the top of the reservoir 114 and such that, when the chip 102 is upright, horizontal, and stationary, the following conditions are met: (a) the channel region 112 and the upper surface 119 of the conducting fluid 116 are parallel; (b) the upper surface 119 of the conducting fluid 116 is at a given fill level 150; and (c) all of the gate electrodes (comprising the first and second gate electrodes 118a-118b) are in contact with the conducting fluid 116, as shown in . Fig. Figure 3A shows that the fixed locations of the gate electrodes can be at different locations across the reservoir. For example, the first gate electrode 118a can be at a first location adjacent to a first side of the reservoir 114, and the second gate electrode 118b can be at a second location adjacent to a second side opposite the first side. As a result, due to an upward tilt of the chip 102 on the first side (e.g., as in Figure 3A), the gate electrodes can be located at different locations across the reservoir. Fig. 3B-1) and / or an acceleration of chip 102 in a first direction from the second side towards the first side (e.g. as in Fig. (as shown in Figure 3C-1) the channel region 112 is angled at least to a specific first degree (e.g., at least to a certain specific first angle (θ1)) relative to the upper surface 119 of the conducting fluid 116, and the level of the conducting fluid 116 on the first side of the reservoir 114 falls, so that the first gate electrode 118a is physically separated from the conducting fluid 116 (while the level of the conducting fluid 116 on the second side of the reservoir 114 is raised, so that the second gate electrode 118b remains in contact with the conducting fluid 116). Furthermore, due to an upward tilt of the chip 102 on the second side (e.g., as shown in Figure 3C-1), the level of the conducting fluid 116 on the second side (e.g., as shown in Figure 3C-1) is also raised. Fig. 3B-2 shown) and / or an acceleration of chip 102 in a second direction from the first side to the second side (e.g. as in Fig. (3C-2 shown) the channel region 112 is angled at least to a specific second degree (e.g. at least to a certain specific second angle (θ2)) relative to the upper surface 119 of the conducting fluid 116 and the level of the conducting fluid 116 on the second side of the reservoir 114 falls, so that the second gate electrode 118b is physically separated from the conducting fluid 116 (while the level of the conducting fluid 116 on the first side of the reservoir is raised, so that the first gate electrode 118a remains in contact with the conducting fluid 116).

[0026] Referring to Fig. 4A to 4C-2, an MSFET 110.3 can have several gate electrodes and in particular at least one first gate electrode 118a. 1-n and a second gate electrode 118b 1-nencompass. However, instead of each gate electrode being made entirely of a metal or metal alloy material, each gate electrode can comprise a stack of electrically insulated sub-electrodes. For example, the first gate electrode 118a 1-n comprise a stack of electrically insulated first sub-electrodes (1-n) and the second gate electrode 118b 1-nThe system may comprise a stack of electrically insulated second sub-electrodes (1-n). Each stack of electrically insulated sub-electrodes may comprise alternating layers of an insulating material and a metal or metal alloy material, such that the metal or metal alloy material of one sub-electrode is electrically insulated from the metal or metal alloy material of all other sub-electrodes in the stack. The metal or metal alloy material may be preselected to avoid the possibility of corrosion and / or oxygen formation on it. Exemplary metal or metal alloy materials include, but are not limited to, platinum or gold. In each case, as in the embodiment described above, the gate electrodes may be located at different fixed locations within reservoir 114.For example, the fixed locations of the gate electrodes (including the fixed locations of the first and second gate electrode 118a. 1-n and 118b 1-n ) between the bottom and the top of the reservoir 114 and such that when the chip 102 is upright, horizontal and stationary, the following conditions are met: (a) the channel region 112 and the upper surface 119 of the conducting fluid 116 are parallel; (b) the upper surface 119 of the conducting fluid 116 is at a given fill level 150; and (c) all of the sub-electrodes of all of the gate electrodes (including the first sub-electrodes 1-n of the first gate electrode 118a) 1-n and the second sub-electrodes 1-n of the second gate electrode 118b 1-n ) are in contact with the conductive fluid 116, as in Fig. Figure 4A shows that the fixed locations of the gate electrodes can be at different locations around the reservoir. For example, the first gate electrode can be located at 118a. 1-nat a first location adjacent to a first side of reservoir 114 and the second gate electrode 118b 1-n The second side can be located at a second location adjacent to one of the sides opposite the first. As a result, due to an upward tilt of chip 102 on the first side (e.g., as in Fig. 4B-1) and / or an acceleration of chip 102 in a first direction from the second side towards the first side (e.g. as in Fig. (4C-1 shown) the channel region 112 is angled to progressively increasing first degrees (e.g., to progressively increasing first angles (θ1)) relative to the upper surface 119 of the conducting fluid 116, and the level of the conducting fluid 116 at the first side of the reservoir 114 falls, so that the first sub-electrodes 1-n of the first gate electrode 118a 1-nin a sequence from top to bottom (i.e. 1 to n) are physically separated from the conducting fluid 116 (while the level of the conducting fluid 116 on the second side of the reservoir is raised so that the second sub-electrodes 1-n of the second gate electrode 118b 1-n (remain in contact with the conductive fluid 116). Furthermore, due to an upward tilt of the chip 102 on the second side (e.g., as in Fig. 4B-2 shown) and / or an acceleration of chip 102 in a second direction from the first side to the second side (e.g. as in Fig. (4C-2 shown) the channel region 112 is angled to progressively increasing second degrees (e.g., to progressively increasing second angles (θ2)) relative to the upper surface 119 of the conducting fluid 116, and the level of the conducting fluid 116 at the second side of the reservoir 114 falls, so that the second sub-electrodes 1-n of the second gate electrode 118b 1-nin a sequence from top to bottom (i.e. 1-n) are physically separated from the conducting fluid 116 (while the level of the conducting fluid 116 at the first side of the reservoir 114 is raised, so that the first sub-electrodes 1-n of the first gate electrode 118a 1-n (remain in contact with the conductive fluid 116).

[0027] Referring to Fig. 5A to 5C-2, an MSFET 110.4 can have multiple gate electrodes and, in particular, at least one first gate electrode 118a. 1-n and a second gate electrode 118b 1-n include. As with the MSFET 110.3, instead of each gate electrode being made entirely of a metal or metal alloy material, each gate electrode can comprise a stack of electrically insulated sub-electrodes 1-n. That is, the first gate electrode 118a 1-n can comprise a stack of electrically insulated first sub-electrodes 1-n and the second gate electrode 118b 1-nThe system may comprise a stack of electrically insulated second sub-electrodes 1-n. Each stack of electrically insulated sub-electrodes may comprise alternating layers of an insulating material and a metal or metal alloy material, such that the metal or metal alloy material of one sub-electrode is electrically insulated from the metal or metal alloy material of all other sub-electrodes in the stack. The metal or metal alloy material may be pre-selected to avoid the possibility of corrosion and / or oxygen formation on it. Exemplary metal or metal alloy materials include, but are not limited to, platinum or gold. In each case, the gate electrodes may be located at various fixed locations within reservoir 114. For example, the fixed locations of the gate electrodes (comprising the fixed locations of the first and second gate electrodes 118a) may be 1-n and 118b 1-n) between the bottom and the top of the reservoir 114 and such that, when the chip 102 is upright, horizontal, and stationary, the following conditions are met: (a) the channel region 112 and the upper surface 119 of the conducting fluid 116 are parallel; (b) the upper surface 119 of the conducting fluid 116 is at a given fill level 150; and (c) only the lower of the sub-electrodes of each gate electrode (comprising the lower of the first sub-electrodes of the first gate electrode 118a) 1-n and lower of the second sub-electrodes of the second gate electrode 118b 1-n ) are in contact with the conductive fluid 116, while the upper of the sub-electrodes of each of the first and second gate electrodes 118a 1-n and 118b 1-n above the level of the upper surface 119 of the conducting fluid 116, as shown in Fig. 5A is shown. The fixed locations of the gate electrodes can be at different locations across reservoir 114. For example, the first gate electrode can be 118a. 1-n at a first location adjacent to a first side of reservoir 114 and the second gate electrode 118b 1-n The second side can be located at a second location adjacent to one of the sides opposite the first. As a result, due to an upward tilt of chip 102 on the first side (e.g., as in Fig. 5B-1) and / or an acceleration of chip 102 in a first direction from the second side towards the first side (e.g. as in Fig. (5C-1 shown) the channel region 112 is angled to progressively increasing first degrees (e.g., to progressively increasing first angles (θ1)) relative to the upper surface 119 of the conducting fluid 116, and the level of the conducting fluid 116 at the first side of the reservoir 114 falls, so that the lower of the first sub-electrodes of the first gate electrode 118a 1-n in a sequence from top to bottom, they are physically separated from the conducting fluid 116 (while the level of the conducting fluid 116 on the second side of the reservoir 114 is raised, so that the upper of the second sub-electrodes of the second gate electrode 118b 1-n begin to contact the conductive fluid 116 in a sequence from bottom to top). Additionally, due to an upward tilt of the chip 102 on the second side (e.g., as in Fig. 5B-2 shown) and / or acceleration of chip 102 in a second direction from the first side to the second side (e.g. as in Fig. (5C-2 shown) the channel region 112 is angled to progressively increasing second degrees (e.g., to progressively increasing second angles (θ2)) relative to the upper surface 119 of the conducting fluid 116, and the level of the conducting fluid 116 at the second side of the reservoir 114 falls, so that the lower of the second sub-electrodes of the second gate electrode 118b 1-n in a sequence from top to bottom (i.e. 1-n) are physically separated from the conducting fluid 116 (while the level of the conducting fluid 116 at the first side of the reservoir 114 is raised, so that the upper of the first sub-electrodes of the first gate electrode 118a 1-n (start contacting the conductive fluid 116 from bottom to top).

[0028] It should be understood that the gate electrode(s) described above and illustrated in the drawings are not intended to be limiting.

[0029] For example, any number of one or more gate electrodes could be incorporated into an MSFET (e.g., see exemplary gate electrode(s) 618 in the layout diagrams of Fig. 6A-6D). Furthermore, if an MSFET has more than two gate electrodes, those gate electrodes 618 (whether they comprise a single electrode or a stack of electrically isolated sub-electrodes) could be evenly distributed across the width of the reservoir (e.g., as in Fig. 6C shown), placed on each side of the reservoir (e.g. as in Fig. 6D shown) etc.

[0030] Additionally, any number (e.g. 2, 3, 4 as illustrated, 5 etc.) of sub-electrodes could be placed in the stack of electrically insulated sub-electrodes in each gate electrode 118a 1-n and 118b1-n be integrated into the gate structure 113 of the MSFETs 110.3 and 110.4.

[0031] Finally, various different known processing techniques could be used to process the gate electrode(s) 118 of MSFET 110.1, 118a and 118b of MSFET 110.2, and 118a described above. 1-n and 118b 1-nof the MSFET 110.3 or 110.4 at a fixed location(s) within a reservoir 114. The illustration of the gate electrode(s) shown in the drawings allows the reader to focus on the prominent aspects of the disclosed embodiments. However, it should be understood that a support structure is also required to maintain (i.e., anchor, secure, etc.) each gate electrode at a fixed location within the reservoir 114 (i.e., relative to the bottom, top, and sides of the reservoir) despite movement (e.g., tilting and / or acceleration) of the chip 102 on which the MSFET is formed. For example, in some embodiments, as shown in the layout diagrams of Fig. As shown in Figures 6A-6D, each gate electrode 618 is a thin rod extending laterally across the full width of the interior of reservoir 114 from one side wall to the opposite side wall, with ends attached to the side walls. In the case of the Fig. In the structure shown in Figure 6D, gate electrodes traversing the reservoir in different directions can be located at different heights to avoid direct electrical connections. In other embodiments, each gate electrode 718 can be a protrusion projecting from a side wall into the interior of the reservoir 114, as shown in Figure 6D. Fig. 7 shown. In other embodiments, each gate electrode 818 can be embedded in the dielectric material 106 and can have only one vertical surface exposed to the interior of the reservoir 114, as shown in Fig. 8 shown. In other embodiments, each gate electrode 918 can be embedded in a dielectric column or column extending vertically through the interior of the reservoir 114 and having ends attached to the reservoir bottom and / or the dielectric cover layer (e.g. see Fig. 9) In any case, one or more metal or metal alloy side surfaces of each gate electrode (or each sub-electrode thereof) should be exposed to the interior of reservoir 114 to allow contact with the conductive fluid 116.

[0032] In addition to the features described above, interconnects (e.g. vias and / or wires) may be included in the dielectric material 106 and / or within dielectric support structures for the gate electrodes to provide discrete electrical connections to each gate electrode and, if applicable, to each sub-electrode within each gate electrode.

[0033] As mentioned above, with such an MSFET structure, an electrical property varies as a function of the total effective gate voltage applied to the conducting fluid through the gate electrode(s) (or sub-electrodes thereof), and the total effective gate voltage applied to the conducting fluid varies as a function of which of the gate electrode(s) (or, if applicable, which of their sub-electrodes) is / are in contact with the conducting fluid. Since the contact between the conducting fluid and the gate electrode(s) (or their sub-electrodes) is motion-dependent, chip motion (e.g., chip tilt and / or acceleration) can be characterized based on the value of the electrical property measured in response to specific bias conditions.

[0034] Therefore, referring again to Fig. 1. The disclosed motion detection system (MDS) 100 further comprises a bias circuit 199 located on the chip 102, which is electrically connected to the MSFET (e.g., to MSFET 110.1, 110.2, 110.3, or 110.4) and which is configured to apply specific bias conditions to the MSFET. The MDS 100 may further comprise a sampling circuit 198, also located on the chip 102, which is electrically connected to the MSFET (e.g., to MSFET 110.1, 110.2, 110.3, or 110.4) and which is configured to sample (e.g., detect and measure) an electrical property of the MSFET 110.1, 110.2, 110.3, or 110.4 in response to the specific bias conditions. The MDS 100 can also include a controller (e.g., a processor) that is either attached to chip 102 (e.g., see controller 190) or located away from, but communicating with, chip 102 (e.g.,(see Controller 190'), which is in particular in communication with the bias circuit 199 and the sampling circuit 198, and which can characterize a chip movement (e.g. chip tilt and / or acceleration) based on the value of the electrical property measured in response to the specific bias conditions.

[0035] As mentioned above and discussed in more detail below, motion sensitivity can be improved by increasing the number of gate electrodes within an MSFET and / or by incorporating stacked, electrically isolated sub-electrodes within each gate electrode in the MSFET. That is, an MDS 100 comprising MSFET 110.2 is more motion-sensitive (i.e., provides better chip motion characterization) than an MDS 100 comprising MSFET 110.1, an MDS 100 comprising MSFET 110.3 is more motion-sensitive than an MDS 100 comprising MSFET 110.2, and so on.

[0036] Various different operating modes could be used to utilize the MSFET as a motion sensor within the MDS 100.

[0037] In exemplary embodiments, the bias circuit 199 could be electrically connected to the source / drain regions 111 and optionally the body region of the MSFET and could be configured to apply a fixed drain / source voltage (Vds) between the source / drain regions 111. The bias circuit 199 could furthermore be electrically connected to each gate electrode and could be configured to apply a specific gate voltage to that gate electrode. In the case of multiple gate electrodes, the bias circuit 199 could be configured to apply different gate voltages to the different gate electrodes. In the case of a gate electrode comprising a stack of electrically isolated sub-electrodes, the bias circuit 199 could be electrically connected (e.g., via a corresponding bus) to each sub-electrode so that the same gate voltage is applied simultaneously to each sub-electrode of that gate electrode (e.g., see [reference]). Fig. 4A or Fig. 5A). In the case of multiple gate electrodes, each with a corresponding stack of electrically isolated sub-electrodes, the bias circuit 199 can be configured to apply the same gate voltage to all sub-electrodes in the same stack, but different gate voltages to the sub-electrodes of different stacks. As discussed in more detail below, the specific gate voltage(s) applied to the gate electrode(s) (or sub-electrodes thereof) can be preselected to achieve optimal chip motion detection sensitivity while minimizing electrode-to-electrode leakage into the conductive fluid. In these exemplary embodiments, the sampling circuit 198 could be electrically connected to the drain region of the MSFET and can be configured to sample (i.e., detect and measure) a drain current (Id).

[0038] For example, for the MSFET 110.1, which is in Fig. As shown in 2A-2C and described above, the bias circuit 199 is electrically connected to the gate electrode 118 and can be configured to apply a fixed gate voltage (V). g ) to be applied to that gate electrode 118. V gThe voltage can be set to be at or above a threshold voltage (Vt) for the MSFET 110.1. The sampling circuit 198 can be configured to detect and measure the drain current (Id). Since there is only one gate electrode, the MSFET 110.1 is either in an on state with current flowing through the channel region or in an off state with no current flowing through the channel region. Since the gate electrode is located adjacent to one side (e.g., the first side) of the reservoir, the MSFET 110.1 is only in the off state when the channel region 112 is angled by a certain degree relative to the upper surface 119 of the conducting fluid 116 (e.g., due to chip tilt and / or acceleration), such that the level of the conducting fluid 116 on the first side drops to the point where the gate electrode 118 is no longer in contact with the conducting fluid 116. Thus, in this case, when the MSFET 110.When MSFET 110.1 is in the off state, controller 190 (or 190') can characterize chip movement as either a chip tilt up to a threshold degree in one direction or a chip acceleration up to a threshold rate in one direction. When MSFET 110.1 is in the on state, controller 190 (or 190') can characterize chip movement as undetected. However, it should be understood that because there is only one gate electrode on one side of the reservoir, some chip movement (e.g., tilting to a lesser degree and / or in a different direction; chip acceleration at a lower rate and / or in a different direction) would be undetectable.

[0039] For the MSFET 110.2, which is in Fig. As shown in 3A-3C-2 and described above, the bias circuit 199 could be electrically connected to the first and second gate electrodes 118a-118b and could be configured to apply a first and a second gate voltage (V g1 or V g2 ) to be applied to the first and second gate electrodes. V g1 can vary from V g2 be (e.g. V) g1 <V g2) and both can be above the threshold voltage (Vt) of the MSFET 110.2. The sampling circuit 198 can be configured to detect and measure the drain current (Id). In this case, the controller 190 (or 190') can characterize chip movement based on the value of Id as either no detected movement, chip movement in one direction, or chip movement in a different direction. In particular, Id is at its highest level when the chip 102 is upright, horizontal, and stationary, such that both the first and second gate electrodes 118a-118b are in contact with the conductive fluid 116 and the sum of V g1 and V g2 are applied to the conductive fluid. Id is at a medium level when, due to an upward tilt of the chip 102 on the first side (e.g., as in Fig. 3B-1) and / or an acceleration of chip 102 in a first direction from the second side towards the first side (e.g. as in Fig. (as shown in Figure 3C-1) the channel region 112 is angled to at least a specific first degree (e.g., to at least a certain specific first angle (θ1)) relative to the upper surface 119 of the conducting fluid 116, and the level of the conducting fluid 116 at the first side of the reservoir 114 falls, so that the first gate electrode 118a is physically separated from the conducting fluid 116 (while the level of the conducting fluid 116 at the second side of the reservoir 114 is raised, so that the second gate electrode 118b remains in contact with the conducting fluid 116). As a result, only V g2 applied to the conductive fluid. Id is at a low level when, due to an upward tilt of chip 102 on the second side (e.g., as in Fig. 3B-2 shown) and / or an acceleration of chip 102 in a second direction from the first side to the second side (e.g. as in Fig. (as shown in 3C-2) the channel region 112 is angled at least to a specific second degree (e.g., at least to a certain specific second angle (θ2)) relative to the upper surface 119 of the conducting fluid 116, and the level of the conducting fluid 116 on the second side of the reservoir 114 falls, so that the second gate electrode 118b is physically separated from the conducting fluid 116 (while the level of the conducting fluid 116 on the first side of the reservoir is raised, so that the first gate electrode 118a remains in contact with the conducting fluid 116). As a result, only Vg1 is applied to the conducting fluid 116. Thus, in this case, the controller 190 (or 190') can characterize chip movement based on the drain current (Id) as one of the following: no detected movement (e.g.,when Id is at the highest level); a chip tilt up to a threshold in one direction or a chip acceleration up to a threshold rate in one direction (e.g., when Id is at the middle level); and a chip tilt up to a threshold in the opposite direction or a chip acceleration up to a threshold rate in the opposite direction (e.g., when Id is at the lowest level).

[0040] For the MSFET 110.3, which is in Fig. 4A-4C-2 is shown and described above, or the MSFET 110.4, which is in Fig. As shown and described above in 5A-5C-2, the bias circuit 199 could be electrically connected by a first bus to each of the first sub-electrodes (1-n) of the first gate electrode 118a 1-n and through a second bus with each of the second sub-electrodes (1-n) of the second gate electrode 118b 1-nbe connected. The bias circuit 199 can further be configured to apply the same first gate voltage (V g1 ) to each first sub-electrode and the same second gate voltage (V g2 ) to be applied to every second sub-electrode. The sampling circuit 198 can be configured to detect and measure the drain current (Id). In this case, the controller 190 (or 190') can characterize chip movement based on the value of Id as any of the following: no detected movement, chip movement to one of several possible levels in one direction, or chip movement to one of several possible levels in a different direction.

[0041] In particular, in the MSFET 110.3, due to an upward tilt of the chip 102 on the first side (e.g. as in Fig. 4B-1) and / or an acceleration of chip 102 in a first direction from the second side towards the first side (e.g. as in Fig. (4C-1 shown) the channel region 112 is angled to progressively increasing first degrees (e.g., to progressively increasing first angles (θ1)) relative to the upper surface 119 of the conducting fluid 116 and the level of the conducting fluid 116 at the first side of the reservoir 114 drops, so that the first sub-electrodes of the first gate electrode 118a 1-n in a sequence from top to bottom (i.e. 1 to n) are physically separated from the conducting fluid 116 (while the level of the conducting fluid 116 on the second side of the reservoir is raised, so that the second sub-electrodes of the second gate electrode 118b 1-n (remain in contact with the conductive fluid 116). Furthermore, due to an upward tilt of the chip 102 on the second side (e.g., as in Fig. 4B-2 shown) and / or an acceleration of chip 102 in a second direction from the first side to the second side (e.g. as in Fig. (4C-2 shown) the channel region 112 is angled to progressively increasing second degrees (e.g., to progressively increasing second angles (θ2)) relative to the upper surface 119 of the conducting fluid 116, and the level of the conducting fluid 116 at the second side of the reservoir 114 drops, so that the second sub-electrodes of the second gate electrode 118b 1-n in a sequence from top to bottom (i.e. 1-n) are physically separated from the conducting fluid 116 (while the level of the conducting fluid 116 at the first side of the reservoir 114 is raised, so that the first gate electrode 118a 1-n (remains in contact with the conductive fluid 116).

[0042] Similarly, in the MSFET 110.4, due to an upward tilt of the chip 102 on the first side (e.g., as in Fig. 5B-1) and / or an acceleration of chip 102 in a first direction from the second side towards the first side (e.g. as in Fig. (5C-1 shown) the channel region 112 is angled to progressively increasing first degrees (e.g., to progressively increasing first angles (θ1)) relative to the upper surface 119 of the conducting fluid 116 and the level of the conducting fluid 116 at the first side of the reservoir 114 drops, so that the lower of the first sub-electrodes of the first gate electrode 118a 1-n in a sequence from top to bottom, they are physically separated from the conducting fluid 116 (while the level of the conducting fluid 116 on the second side of the reservoir 114 is raised, so that the upper of the second sub-electrodes of the second gate electrode 118b 1-nbegin to contact the conductive fluid 116 in a sequence from bottom to top). Additionally, due to an upward tilt of the chip 102 on the second side (e.g., as in Fig. 5B-2 shown) and / or an acceleration of chip 102 in a second direction from the first side to the second side (e.g. as in Fig. (5C-2 shown) the channel region 112 is angled to progressively increasing second degrees (e.g., to progressively increasing second angles (θ2)) relative to the upper surface 119 of the conducting fluid 116, and the level of the conducting fluid 116 drops at the second side of the reservoir 114, so that the lower of the second sub-electrodes of the second gate electrode 118b 1-nin a sequence from top to bottom (i.e. 1-n) are physically separated from the conducting fluid 116 (while the level of the conducting fluid 116 at the first side of the reservoir 114 is raised, so that the upper of the first sub-electrodes of the first gate electrode 118a 1-n (start contacting the conductive fluid 116 from bottom to top).

[0043] Therefore, in any case, given the selection of V g1 , which is applied to each first sub-electrode, and V g2The drain current (Id), applied to every second sub-electrode, indicates how many of the first sub-electrodes and also how many of the second sub-electrodes remain in contact with the conducting fluid 116, thus indicating the total effective gate voltage applied to the conducting fluid and, in turn, the orientation of (and especially the actual angle of) the channel region 112 relative to the upper surface of the conducting fluid 116. Since a drain current (Id) is a function of the total effective gate voltage, a characterization of chip motion by the controller 190 based on the drain current (Id) can then include not only the direction of a chip tilt, but also the degree of a chip tilt, or alternatively, not only the direction of a chip acceleration, but also the rate of a chip acceleration.

[0044] In particular, a gate structure 113 of an MSFET 110.4 is described in more detail in Fig. Figure 10 shows and considers this. In this case, the total effective gate voltage applied to the conducting fluid 116 changes in response to chip movement (e.g., when the chip tilts or accelerates) because the number of first sub-electrodes of the first gate electrode 118a changes. 1-n and the number of second sub-electrodes of the second gate electrode 118b 1-n , which are in contact with the conductive fluid 116, changes. In particular, the following equations apply: V1=nVg1, V2=nVg2, V1+V2=VT V1=fV2, V1=fVT(f+1), V2=VT(f+1), Vg1=fVTn(f+1), Vg2=VTn(f+1), n2=n−n1 V1'+V2'=n1Vg1+(n−n1)Vg2=VT'=[n1n(f−1)+1]VT(f+1),and ΔVT1=(f−1)(f+1)VTn(n1−n1'), where V1 is the total possible voltage that could be applied to the conductive fluid 116 by the first sub-electrodes of the first gate electrode 118a, Vg1 the first gate voltage is applied to each first sub-electrode, V2 is the total possible voltage that could be applied to the conductive fluid 116 by the second sub-electrodes of the second gate electrode 118b, V g2 the second gate voltage is applied to every second sub-electrode, V T the total possible voltage that could be applied to the conductive fluid 116 by the first sub-electrodes and the second sub-electrodes, n is the total number of sub-electrodes in each gate electrode, n1 is the number of first sub-electrodes of the first gate electrode that are in contact with the conductive fluid 116 at any given time, n2 is the number of second sub-electrodes of the second gate electrode that are in contact with the conductive fluid 116 at any time, and f is a factor that defines the relationship between V1 and V2.

[0045] The equations presented above can be used to determine the optimal gate bias conditions, and in particular, to determine the optimal V g1 , which is to be applied to each first sub-electrode of the first gate electrode 118a of the gate structure 113 of the MSFET 110.4, and the optimal V g2 to determine the voltage to be applied to every second sub-electrode of the second gate electrode 118b of the gate structure 113 of the MSFET 110.4. The goal of these equations is to maximize the potential difference (i.e., the difference between V1 and V2) to improve chip motion detection sensitivity, while also choosing a factor f that minimizes electrode-to-electrode leakage into the conducting fluid, which would reduce the overall effective voltage and the resulting drain current.

[0046] An exemplary MSFET 110.4 is considered, where the entire possible gate voltage (V) T ) 1.5V and where n is 10 (i.e., where each gate electrode has 10 sub-electrodes). The table of Fig. Figure 11 illustrates possible V1 and V2 values ​​as a function of values ​​of different factors that can be used to calculate a V T to achieve 1.5V. As in Fig. Figure 11 illustrates that if f=1, then V1 and V2 are equal, whereas if f=0, 1, V1 and V2 have the greatest possible difference. The table of Fig. Figure 12 illustrates how (given that n1 is the number of first sub-electrodes in contact with the conducting fluid 116 at any given time and n2 is the number of second sub-electrodes in contact with the conducting fluid 116 at any given time and is equal to n-n1) changes in the level of the conducting fluid 116 adjacent to the first gate electrode 118a and concurrent changes in the level of a conducting fluid 116 adjacent to the second gate electrode 118b (e.g., due to chip tilt and / or chip acceleration) result in changes in the total effective gate voltage applied to the conducting fluid for different values ​​of f. If f=1 (i.e., if the same voltage is applied to each sub-electrode in each of the gate electrodes), then the total effective gate voltage applied to the conducting fluid is always 0.75V.In this case, the drain current (Id) remains unchanged during chip movement, and no information regarding chip movement is received. However, if f < 1, there is an asymmetrical distribution between V1 and V2. The total effective gate voltage applied to the conducting fluid 116 of the gate structure 113 of an MSFET 110.4 varies as a function of chip movement (e.g., due to chip tilt of varying degrees in different directions and / or chip acceleration at varying rates in different directions) because of the resulting orientation of the channel region relative to the upper surface of the conducting fluid. Consequently, the drain current (Id) also changes with chip movement and can be used by the controller 190 (or 190') to characterize chip movement with significant sensitivity. Fig. Figure 13 is a plot that further illustrates the relationship between changes in the depth of the electrolyte solution adjacent to a given gate electrode with n sub-electrodes (e.g., 10 sub-electrodes) and changes in the total effective voltage applied to the electrolyte solution as a function of different values ​​of f.

[0047] Those skilled in the art will recognize that on-chip bias circuits configured to apply different bias voltages to different on-chip components, and on-chip sampling circuits configured to sample electrical characteristics (e.g., a drain current (Id)) of FETs, are well known in the art. Therefore, the details of such bias and sampling circuits have been omitted from the specification to allow the reader to focus on the outstanding aspects of the disclosed embodiments.

[0048] Fig. Figure 14 is a flowchart illustrating embodiments of a motion detection method.

[0049] The procedure can involve the provision of a motion detection system (MDS), such as the one described in detail above and in Fig. The MDS 100 illustrated in Figure 1 (see process step 1402) can comprise a chip 102 and, on the chip 102, a motion-sensitive field-effect transistor (MSFET), a bias circuit 199 electrically connected to the MSFET, and a sampling circuit 198 electrically connected to the MSFET. The MDS 100 can further comprise a controller, which is either on the chip 102 (e.g., see controller 190) or remotely, but in communication with the chip 102 (e.g., see controller 190').

[0050] It should be noted that the MSFET can be any of the MSFET implementations described above, including but not limited to: the MSFET 110.1, which is described in Fig. 2A-2C is illustrated; the MSFET 110.2, which is in Fig. 3A to 3C-2 is illustrated; the MSFET 110.3, which is in Fig. 4A to 4C-2 is illustrated; or the MSFET 110.4, which is in Fig. Figures 5A to 5C-2 illustrate this. Each such MSFET 110.1-110.4 comprises: source / drain regions 111; a channel region 112 positioned laterally between source / drain regions 111; and a gate structure 113 adjacent to the channel region 112. The gate structure comprises: a reservoir 114 with a bottom adjacent to the channel region 112; a conducting fluid 116 contained within the reservoir 114, which in particular only partially fills the reservoir 114; and at least one gate electrode (e.g., see the gate electrode 118 of the gate structure 113 in MSFET 110.1; see the gate electrodes 118a-118b of the gate structure 113 of MSFET 110.2; and see the gate electrodes 118a). 1-n and 118b 1-nof the MSFETs 110.3 and 110.4) at a fixed location within the interior of the reservoir 114. Given the fixed location of each gate electrode within the reservoir and the fill level of the conductive fluid within the reservoir, contact between the gate electrode(s) (or, if applicable, sub-electrodes thereof) and the conductive fluid depends on the orientation of the channel region 112 relative to the upper surface 119 of the conductive fluid 116 and the orientation of the channel region 112 relative to the upper surface 119 of the conductive fluid 116, on a position in space and / or movement of the MSFET, and in particular on a position in space and / or movement (e.g. tilt and / or acceleration) of the chip 102 on which the MSFET is formed.

[0051] With such an MSFET structure, an electrical property varies as a function of the total effective gate voltage applied to the conducting fluid, and the total effective gate voltage applied to the conducting fluid varies as a function of which gate electrode(s) (or, if applicable, which of their sub-electrodes) is / are in contact with the conducting fluid. Since the contact between the conducting fluid and the gate electrode(s) (or their sub-electrodes) is motion-dependent, chip movement can be characterized by measuring the electrical property of the MSFET in response to specific bias conditions.

[0052] Therefore, the method further includes using the bias circuit 199 to apply specific bias conditions to the MSFET (see process step 1404), and using the sampling circuit 198 to sample (e.g., detect and measure) an electrical property of the MSFET in response to the specific bias conditions (see process step 1406). Various different operating modes could be used to operate the MSFET as a motion sensor. That is, different electrical properties could be sampled in response to different bias conditions.However, in exemplary process implementations, the specific bias conditions used in process step 1404 may include, for example, a fixed drain / source voltage (Vds) between the source / drain regions 111 and also a specific gate voltage(s) to each gate electrode (or, if applicable, to each sub-electrode thereof). It should be noted that the optimal bias conditions, and in particular optimal gate voltages, are described in more detail above with respect to the various MSFET structural configurations. Fig. 10-13 are discussed. In this case, the electrical property that is sampled in process step 1406 in response to the specific bias conditions can be a drain current (Id).

[0053] Finally, the method can further include using the controller 190 (or 190') to characterize chip motion (e.g., chip tilt and / or acceleration) based on the measured value of the electrical property (e.g., the measured drain current (Id) value) (see process step 1408). In the exemplary embodiments, a drain current (Id) varies as a function of the total effective gate voltage applied to the conductive fluid, and the total effective gate voltage applied to the conductive fluid varies as a function of which gate electrode(s) (or, if applicable, which sub-electrodes thereof) is / are in contact with the conductive fluid. Since the contact between the conductive fluid and the gate electrode(s) (or sub-electrodes thereof) is motion-dependent, chip motion can be characterized by the controller based on the drain current (Id).

[0054] For illustrative purposes, the cover layer 107 is shown in the figures as being essentially planar and extending over the reservoir 114 without being immersed in the reservoir 114. Those skilled in the art will recognize that the orientation of the cover layer 107 relative to the reservoir 114 can vary depending on the processing techniques, materials used, and / or the dimensions of the reservoir 114 and the thickness of the deposited cover layer 107.

[0055] For example, in some embodiments, the processing techniques may include forming the reservoir 114 (e.g., a trench) in the ILD layer 106 and also forming one or more electrodes in and / or adjacent to the reservoir 114 (as discussed above), filling the remaining space within the reservoir 114 with a sacrificial fill material, and removing the sacrificial fill material from above the ILD layer 106 (e.g., by performing a chemical mechanical polishing (CMP) process). Then, the capping layer 107 can be formed (e.g., deposited) over the coplanar upper surfaces of the ILD layer 106 and the sacrificial fill material within the reservoir 114 such that it is a substantially planar capping layer 107. Subsequently, a connection 108 (e.g.,an opening) is formed through the lid layer 107 to expose the sacrificial fill material, the sacrificial fill material can be selectively removed from the reservoir 114 through the port 108, the conductive fluid 116 can be added to the reservoir 114 through the port 108, and the port 108 can be plugged. It should be noted that the materials for the ILD layer 106, the lid layer 107, the electrode(s), and the sacrificial fill material should be selected such that the sacrificial fill material can be selectively removed from the reservoir 114 through the port 108 without damaging other exposed surfaces. For example, the ILD layer 106 and the lid layer 107 could be silicon dioxide, and the sacrificial fill material could be either: (a) a silicon fill material (e.g.,(a) polysilicon), which is removable following contact formation by XeF2 vapor etching or SF6 plasma etching; or (b) a polymer filler material which is removable following contact formation by oxygen plasma etching. Such processing would thus result in the lid layer 107 being substantially planar, as in . Fig. 15A (and in the other figures described above).

[0056] In other embodiments, the processing techniques may include forming the reservoir 114 (e.g., a trench) in the ILD layer 106 and also forming one or more electrodes in and / or adjacent to the reservoir 114 (as discussed above). The capping layer 107 may then be formed on the upper surface of the ILD layer 106 above the trench, thereby forming an air-filling cavity. Prior art capping techniques (e.g., borrowed from chip packaging) could be used to form this capping layer. Depending on the size of the trench opening on the upper surface of the ILD layer and also depending on the thickness of the deposited layer, such processing could result in the capping layer 107 extending into the reservoir 114 and closing or pinching off at the top of the reservoir, as shown in [reference]. Fig. Figure 15B shows that, optionally, the trench can be partially filled with the conductive fluid 116 before the cap layer is formed. Alternatively, following the formation of the cap layer, the connection 108 can be formed in the cap layer 107, the conductive fluid 116 can be added to the reservoir 114, and the connection 108 can be plugged.

[0057] It should be understood that the figures and processing techniques discussed above are not intended to be limiting. The reservoir 114 and the cover layer 107 covering the reservoir 114 can be formed using any technique suitable to ensure that, when the reservoir 114 is partially filled with the conductive fluid 116 and covered by a cover layer 107, leakage or loss of the conductive fluid 116 is prevented and an air- or gas-filled space remains within the reservoir 114, thus allowing the conductive fluid to move and for any movement to be detected as described above.

[0058] It should be understood that in the structures and processes described above, a semiconductor material refers to a material whose conductive properties can be modified by doping with an impurity. Exemplary semiconductor materials include silicon-based semiconductors (e.g., silicon, silicon germanium, silicon germanium carbide, silicon carbide, etc.) and III-V compound semiconductors (i.e., compounds obtained by combining group III elements, such as aluminum (Al), gallium (Ga), or indium (In), with group V elements, such as nitrogen (N), phosphorus (P), arsenic (As), or antimony (Sb)) (e.g., GaN, InP, GaAs, or GaP). A pure semiconductor material, and in particular a semiconductor material that is not doped with an impurity for the purpose of increasing conductivity (i.e., an undoped semiconductor material), is referred to in engineering as an intrinsic semiconductor.A semiconductor material doped with an impurity to increase its conductivity (i.e., a doped semiconductor material) is referred to in engineering as an extrinsic semiconductor and is more conductive than an intrinsic semiconductor made from the same base material. That is, extrinsic silicon is more conductive than intrinsic silicon; extrinsic silicon-germanium is more conductive than intrinsic silicon-germanium; and so on. It should also be understood that different impurities (i.e., different dopants) can be used to achieve different conductivity types (e.g., P-type conductivity and N-type conductivity), and that the dopants can vary depending on the different semiconductor materials used. For example, a silicon-based semiconductor material (e.g., silicon, silicon-germanium, etc.)A silicon-based semiconductor material is typically doped with a group III dopant, such as boron (B) or indium (In), to achieve P-type conductivity, whereas a silicon-based semiconductor material is typically doped with a group V dopant, such as arsenic (As), phosphorus (P), or antimony (Sb), to achieve N-type conductivity. A gallium nitride (GaN)-based semiconductor material is typically doped with magnesium (Mg) to achieve P-type conductivity and with silicon (Si) or oxygen to achieve N-type conductivity. Those skilled in the art will also recognize that different conductivity levels depend on the relative concentration levels of the dopant(s) in a given semiconductor region.

[0059] Also disclosed herein are embodiments of a computer program product for implementing one or more features of the motion detection systems and methods described above. In particular, the computer program product may comprise a computer-readable storage medium (or media) that contains computer-readable program instructions to cause a processor to execute aspects of the present invention.

[0060] The computer-readable storage medium can be a physical device capable of holding and storing instructions for use by an instruction-executing device. The computer-readable storage medium may, for example, comprise an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof, but is not limited to these.A non-exhaustive list of more specific examples of computer-readable storage media includes the following: a portable computer floppy disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), a DVD (digital versatile disk), a memory stick, a floppy disk, a mechanically coded device, such as punched cards or raised structures in a groove having instructions recorded thereon, and any suitable combination of the foregoing.A computer-readable storage medium, such as used herein, is not to be construed as being transient signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission media (e.g., light pulses passing through a fiber optic cable), or electrical signals transmitted through a wire.

[0061] The computer-readable program instructions described herein can be downloaded to respective computing / processing devices from a computer-readable storage medium or to an external computer or external storage device via a network, such as the internet, a local area network, a wide area network, and / or a wireless network. The network may include copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives computer-readable program instructions from the network and forwards the computer-readable program instructions for storage on a computer-readable storage medium within the respective computing / processing device.

[0062] Computer-readable program instructions for performing operations of the present invention can be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or either source code or object code written in any combination of one or more programming languages, including an object-oriented programming language such as Smalltalk, C++, or the like, and conventional procedural programming languages ​​such as the "C" programming language or similar programming languages. The computer-readable program instructions can be executed entirely on the user computer, partially on the user computer as a stand-alone software package, partially on the user computer and partially on a remote computer, or entirely on the remote computer or a server.In the latter scenario, the remote computer can be connected to the user computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection can be to an external computer (for example, via the internet using an internet service provider). In some embodiments, electronic circuits, including, for example, a programmable logic circuit, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), can execute the computer-readable program instructions by using state information from the computer-readable program instructions to personalize the electronic circuit to implement aspects of the present invention.

[0063] Aspects of the present invention are described herein with reference to flowchart diagrams and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the invention. It is understood that each block of the flowchart diagrams and / or block diagrams, and combinations of blocks in the flowchart diagrams and / or block diagrams, can be implemented by computer-readable program instructions.

[0064] These computer-readable program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, or other programmable data processing device to create a machine such that the instructions executed through the processor of the computer or other programmable data processing device provide means for implementing the functions / actions specified in the flowchart and / or block diagram block or blocks.These computer-readable program instructions may also be stored in a computer-readable storage medium capable of directing a computer, programmable data processing device, and / or other devices to operate in a particular manner, such that the computer-readable storage medium containing instructions stored therein comprises a manufacturing article comprising instructions implementing aspects of the function / action specified in the flowchart and / or block diagram block or blocks.

[0065] The computer-readable program instructions can also be loaded onto a computer, other programmable data processing device, or other device to effect a series of operational steps to be performed on the computer, other programmable device, or other device to produce a computer-implemented process, such that the instructions executed on the computer, other programmable device, or other device implement the functions / actions specified in the flowchart and / or block diagram block or blocks.

[0066] The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this respect, each block in the flowchart or block diagrams can represent a module, segment, or section of instructions that includes one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions mentioned in the block may not occur in the order shown in the figures. For example, two blocks shown consecutively may actually be executed essentially concurrently, or the blocks may sometimes be executed in reverse order, depending on the functionality involved.It is also noted that each block of the block diagrams and / or flowchart representation and combinations of blocks in the block diagrams and / or flowchart representation can be implemented by hardware-based special-purpose systems that perform the specified functions or actions, or execute combinations of special-purpose hardware and computer instructions.

[0067] Fig.Figure 16 is a schematic diagram illustrating a representative computer system for implementing one or more features of the disclosed motion detection system and method. This schematic drawing illustrates a hardware configuration of an information handling / computer system according to embodiments herein. The system comprises at least one processor or central processing unit (CPU) 10. The CPUs 10 are interconnected via a system bus 12 with various devices, such as a random access memory (RAM) 14, a read-only memory (ROM) 16, and an input / output (I / O) adapter 18. The I / O adapter 18 can be connected to peripheral devices, such as disk units 11 and tape drives 13, or other program storage devices readable by the system.The system can read the instructions according to the invention on the program storage devices and follow these instructions to execute the methodology of the embodiments described herein. The system further comprises a user interface adapter 19, which connects a keyboard 15, a mouse 17, a loudspeaker 24, a microphone 22, and / or other user interface devices, such as a touchscreen device (not shown), to the bus 12 to collect user input. Additionally, a communication adapter 20 connects the bus 12 to a data processing network 25, and a display adapter 21 connects the bus 12 to a display device 23, which may be configured as an output device, such as a monitor, printer, or transmitter.

[0068] It should be clear that the terminology used herein serves the purpose of describing the disclosed structures and procedures and is not intended to be restrictive. For example, the singular forms "a," "an," "a," and "the," "the," "the," as used herein, are intended to include the plural forms unless the context clearly indicates otherwise. Additionally, the terms "comprises," "comprehensive," "includes," and / or "including," as used herein, specify the presence of specified features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.Furthermore, as used herein, terms such as "right," "left," "vertical," "horizontal," "top," "bottom," "upper," "lower," "below," "underneath," "above," "above," "parallel," "perpendicular," etc., are intended to describe relative locations as oriented and illustrated in the drawings (unless otherwise specified). Terms such as "touching," "in direct contact," "adjacent," "directly adjacent to," "immediately adjacent to," etc., are intended to indicate that at least one element is in physical contact with another element (without other elements separating the described elements). The term "lateral" is used herein to describe the relative locations of elements and, in particular, to indicate that an element is positioned on the side of another element, as opposed to above or below the other element, as oriented and illustrated in the drawings.For example, an element positioned laterally adjacent to another element is next to the other element; an element positioned laterally immediately adjacent to another element is directly next to the other element; and an element that laterally surrounds another element is adjacent to and encompassing the outer side walls of the other element. The corresponding structures, materials, actions, and equivalents of all means or step-plus-function elements in the following claims are intended to include any structure, material, or action for performing the function in combination with other claimed elements, as specifically claimed.

[0069] The descriptions of the various embodiments of the present disclosure are presented for illustrative purposes only and are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations are obvious to those skilled in the art without altering the scope and concept of the described embodiments. The terminology used herein has been chosen to best explain the principles of the embodiments, their practical application or technical improvement over commercially available technologies, or to enable other persons skilled in the art to understand the embodiments disclosed herein.

Claims

[1] Transistor (110) comprising: a canal region (112); and a gate structure (113) adjacent to the canal region (112) and encompassing: a reservoir (114) configured to contain a conductive fluid (116); and at least one gate electrode (118, 118a, 118b, 118a) 1-n , 118b 1-n , 618) at a fixed location within the reservoir (114), wherein an orientation of the channel region (112) relative to an upper surface (119) of the conducting fluid (116) depends on a movement of the transistor (110) and wherein a contact between the at least one gate electrode (118, 118a, 118b, 118a 1-n , 118b 1-n , 618) and the conducting fluid (116) depends on the orientation of the channel region (112) relative to the upper surface (119) of the conducting fluid (116). [2] Transistor (110) according to claim 1, wherein the gate structure (113) comprises a single gate electrode (118), and wherein the fixed location of the individual gate electrode (118) within the reservoir (114) and a fill level (150) of the conducting fluid (116) within the reservoir (114) are such that: when the channel region (112) and the upper surface (119) of the conducting fluid (116) are parallel, the single gate electrode (118) is in contact with the conducting fluid (116), and when the channel region (112) is angled to at least a certain specific degree relative to the upper surface (119) of the conducting fluid (116), the single gate electrode (118) is physically separated from the conducting fluid (116). [3] Transistor (110) according to claim 1, wherein the gate structure (113) comprises: a first gate electrode (118a) adjacent to a first side of the reservoir (114); and a second gate electrode (118b) adjacent to a second side of the reservoir (114), and wherein fixed locations of the first gate electrode (118a) and the second gate electrode (118b) within the reservoir (114) and a fill level (150) of the conducting fluid (116) within the reservoir (114) are such that: when the channel region (112) and the upper surface (119) of the conducting fluid (116) are parallel, and the first gate electrode (118a) and the second gate electrode (118b) are in contact with the conducting fluid (116), when the channel region (112) is angled to a first degree relative to the upper surface (119) of the conducting fluid (116), the first gate electrode (118a) becomes physically separated from the conducting fluid (116) and the second gate electrode (118b) remains in contact with the conducting fluid (116), and when the channel region (112) is angled up to a second degree relative to the upper surface (119) of the conducting fluid (116), the second gate electrode (118b) becomes physically separated from the conducting fluid (116) and the first gate electrode (118a) remains in contact with the conducting fluid (116). [4] Transistor (110) according to claim 1, wherein the gate structure (113) comprises: a first gate electrode (118a 1-n ) comprising a stack of electrically insulated first sub-electrodes (1-n) adjacent to a first side of the reservoir (114); and a second gate electrode (118b) 1-n ) comprising a stack of electrically insulated second sub-electrodes (1-n) adjacent to a second side of the reservoir (114), and where fixed locations of the first gate electrode (118a 1-n ) and the second gate electrode (118b 1-n) within the reservoir (114) and a fill level (150) of the conducting fluid (116) within the reservoir (114) such that: when the channel region (112) and the upper surface (119) of the conducting fluid (116) are parallel, and all of the first sub-electrodes (1-n) and all of the second sub-electrodes (1-n) are in contact with the conducting fluid (116), when the channel region (112) is angled to progressively increasing first degrees relative to the upper surface (119) of the conducting fluid (116), the first sub-electrodes (1-n) become physically separated from the conducting fluid (116) in a sequence from top to bottom, and the second sub-electrodes (1-n) remain in contact with the conducting fluid (116), and when the channel region (112) is angled to progressively increasing second degrees relative to the upper surface (119) of the conducting fluid (116), the second sub-electrodes (1-n) become physically separated from the conducting fluid (116) in a sequence from top to bottom, and the first sub-electrodes (1-n) remain in contact with the conducting fluid (116). [5] Transistor (110) according to claim 1, wherein the gate structure (113) comprises: a first gate electrode (118a 1-n ) comprising a stack of electrically insulated first sub-electrodes (1-n) adjacent to a first side of the reservoir (114); and a second gate electrode (118b) 1-n ) comprising a stack of electrically insulated second sub-electrodes (1-n) adjacent to a second side of the reservoir (114), and where fixed locations of the first gate electrode (118a 1-n ) and the second gate electrode (118b 1-n) within the reservoir (114) and a fill level (150) of the conducting fluid (116) within the reservoir (114) such that: when the channel region (112) and the upper surface (119) of the conducting fluid (116) are parallel, the lower of the first sub-electrodes (1-n) and the lower of the second sub-electrodes (1-n) are in contact with the conducting fluid (116), and the upper of the first sub-electrodes (1-n) and the upper of the second sub-electrodes (1-n) are physically separated from the conducting fluid (116), when the channel region (112) is angled to progressively increasing first degrees relative to the upper surface (119) of the conducting fluid (116), the lower of the first sub-electrodes (1-n) are physically separated from the conducting fluid (116) in a sequence from top to bottom, and the upper of the second sub-electrodes (1-n) contact the conducting fluid (116) in a sequence from bottom to top, and when the channel region (112) is angled to progressively increasing second degrees relative to the upper surface (119) of the conducting fluid (116), the lower of the second sub-electrodes (1-n) are physically separated from the conducting fluid (116) in a sequence from top to bottom, and the upper of the first sub-electrodes (1-n) contact the conducting fluid (116) in a sequence from bottom to top. [6] Transistor (110) according to claim 1, wherein the gate structure (113) comprises more than two gate electrodes (618) at fixed locations within the reservoir (114). [7] Transistor (110) according to any one of claims 1 to 6, wherein a filling level (150) of the conductive fluid (116) is such that a conductive fluid (116) only partially fills the reservoir (114) and wherein the reservoir (114) is capped to prevent leakage of the conductive fluid (116). [8] System encompassing: a transistor (110) on a chip (102), wherein the transistor (110) comprises: a canal region (112); and a gate structure (113) adjacent to the canal region (112) and encompassing: a reservoir (114) configured to contain a conductive fluid (116); and at least one gate electrode (118, 118a, 118b, 118a) 1-n , 118b 1-n , 618) at a fixed location within the reservoir (114), wherein an orientation of the channel region (112) relative to an upper surface (119) of the conducting fluid (116) depends on a movement of the transistor (110) and wherein a contact between the at least one gate electrode (118, 118a, 118b, 118a 1-n , 118b 1-n , 618) and the conducting fluid (116) depends on the orientation of the channel region (112) relative to the upper surface (119) of the conducting fluid (116); a bias circuit (199) which is electrically connected to the transistor (110), wherein the bias circuit (199) is configured to apply specific bias conditions to the transistor (110), and a sampling circuit (198) which is electrically connected to the transistor (110), wherein the sampling circuit (198) is configured to sample at least one electrical property of the transistor (110) in response to the specific bias conditions. [9] System according to claim 8, wherein the gate structure (113) comprises a single gate electrode (118), wherein the fixed location of the individual gate electrode (118) within the reservoir (114) and a fill level (150) of the conducting fluid (116) within the reservoir (114) are such that: when the channel region (112) and the upper surface (119) of the conducting fluid (116) are parallel, the single gate electrode (118) is in contact with the conducting fluid (116), and when the channel region (112) is angled to at least a specific degree relative to the upper surface (119) of the conducting fluid (116), the single gate electrode (118) is physically separated from the conducting fluid (116), where the specific bias conditions include a fixed drain / source voltage (Vds) and a fixed gate voltage (V g ) include, where the electrical property is a drain current (Id), where the drain current (Id) indicates whether the transistor (110) is in an OFF state, and where the OFF state indicates that the chip (102) is tilted or that the chip (102) is accelerating. [10] System according to claim 8, wherein the gate structure (113) comprises: a first gate electrode (118a) adjacent to a first side of the reservoir (114); and a second gate electrode (118b) adjacent to a second side of the reservoir (114), wherein fixed locations of the first gate electrode (118a) and the second gate electrode (118b) within the reservoir (114) and a fill level (150) of the conducting fluid (116) within the reservoir (114) are such that: when the channel region (112) and the upper surface (119) of the conducting fluid (116) are parallel, and the first gate electrode (118a) and the second gate electrode (118b) are in contact with the conducting fluid (116), when the channel region (112) is angled by at least a first degree relative to the upper surface (119) of the conducting fluid (116), the first gate electrode (118a) is physically separated from the conducting fluid (116) and the second gate electrode (118b) remains in contact with the conducting fluid (116), and when the channel region (112) is angled by at least one second degree relative to the upper surface (119) of the conducting fluid (116), the second gate electrode (118b) is physically separated from the conducting fluid (116) and the first gate electrode (118a) remains in contact with the conducting fluid (116), where the specific bias conditions include a fixed drain / source voltage (Vds), a fixed first gate voltage (V g1 ) at the first gate electrode (118a), a fixed second gate voltage (V g2 ) at the second gate electrode (118b), where the fixed first gate voltage (V g1) less than the fixed second gate voltage (V g2 ) is, where the electrical property is a drain current (Id), and where the drain current (Id) indicates the chip tilt direction and angle or chip acceleration direction and rate. [11] System according to claim 8, wherein the gate structure (113) comprises: a first gate electrode (118a 1-n ) comprising a stack of electrically insulated first sub-electrodes (1-n) adjacent to a first side of the reservoir (114); and a second gate electrode (118b) 1-n ) comprising a stack of electrically insulated second sub-electrodes (1-n) adjacent to a second side of the reservoir (114), where fixed locations of the first gate electrode (118a 1-n ) and the second gate electrode (118b 1-n ) within the reservoir (114) and a fill level (150) of the conducting fluid (116) within the reservoir (114) such that: when the channel region (112) and the upper surface (119) of the conducting fluid (116) are parallel, and all of the first sub-electrodes (1-n) and all of the second sub-electrodes (1-n) are in contact with the conducting fluid (116), when the channel region (112) is angled to progressively increasing first degrees relative to the upper surface (119) of the conducting fluid (116), the first sub-electrodes (1-n) become physically separated from the conducting fluid (116) in a sequence from top to bottom, and the second sub-electrodes (1-n) remain in contact with the conducting fluid (116), and when the channel region (112) is angled to progressively increasing second degrees relative to the upper surface (119) of the conducting fluid (116), the second sub-electrodes (1-n) are physically separated from the conducting fluid (116) in a sequence from top to bottom, and the first sub-electrodes (1-n) remain in contact with the conducting fluid (116), where the specific bias conditions include a fixed drain / source voltage (Vds), a fixed first gate voltage (V g1 ) at each of the first sub-electrodes (1-n), a fixed second gate voltage (V) g2 ) at each of the second sub-electrodes (1-n), where the fixed first gate voltage (V g1 ) less than the fixed second gate voltage (V g2 ) is, where the electrical property is a drain current (Id), and where the drain current (Id) indicates the chip tilt direction and angle or chip acceleration direction and rate. [12] System according to claim 8, wherein the gate structure (113) comprises: a first gate electrode (118a 1-n ) comprising a stack of electrically insulated first sub-electrodes (1-n) adjacent to a first side of the reservoir (114); and a second gate electrode (118b) 1-n ) comprising a stack of electrically insulated second sub-electrodes (1-n) adjacent to a second side of the reservoir (114), where fixed locations of the first gate electrode (118a 1-n ) and the second gate electrode (118b 1-n ) within the reservoir (114) and a fill level (150) of the conducting fluid (116) within the reservoir (114) such that: when the channel region (112) and the upper surface (119) of the conducting fluid (116) are parallel, the lower of the first sub-electrodes (1-n) and the lower of the second sub-electrodes (1-n) are in contact with the conducting fluid (116), and the upper of the first sub-electrodes (1-n) and the upper of the second sub-electrodes (1-n) are physically separated from the conducting fluid (116), when the channel region (112) is angled to progressively increasing first degrees relative to the upper surface (119) of the conducting fluid (116), the lower of the first sub-electrodes (1-n) are physically separated from the conducting fluid (116) in a sequence from top to bottom, and the upper of the second sub-electrodes (1-n) contact the conducting fluid (116) in a sequence from bottom to top, and when the channel region (112) is angled up to progressively increasing second degrees relative to the upper surface (119) of the conducting fluid (116), the lower of the second sub-electrodes (1-n) are physically separated from the conducting fluid (116) in a sequence from top to bottom, and the upper of the first sub-electrodes (1-n) contact the conducting fluid (116) in a sequence from bottom to top, where the specific bias conditions include a fixed drain / source voltage (Vds), a fixed first gate voltage (V g1 ) at each of the first sub-electrodes (1-n), a fixed second gate voltage (V) g2 ) at each of the second sub-electrodes (1-n), where the fixed first gate voltage (V g1 ) less than the fixed second gate voltage (V g2 ) is, and where the electrical property is a drain current (Id), and where the drain current (Id) indicates the chip tilt direction and angle or chip acceleration direction and rate. [13] System according to claim 8, wherein the gate structure (113) comprises more than two gate electrodes (618) at fixed locations within the reservoir (114). [14] System according to any one of claims 8 to 13, wherein a filling level (150) of the conducting fluid (116) is such that the conducting fluid (116) only partially fills the reservoir (114) and wherein the reservoir (114) is covered to prevent leakage of the conducting fluid (116). [15] Procedure encompassing: Applying, by means of a bias circuit (199), specific bias conditions to a transistor (110) on a chip (102), wherein the transistor (110) comprises: a canal region (112); and a gate structure (113) adjacent to the canal region (112) and encompassing: a reservoir (114) configured to contain a conductive fluid (116); and at least one gate electrode (118, 118a, 118b, 118a) 1-n , 118b 1-n , 618) at a fixed location within the reservoir (114), wherein an orientation of the channel region (112) relative to an upper surface (119) of the conductive fluid (116) depends on a movement of the chip (102) and wherein a contact between the at least one gate electrode (118, 118a, 118b, 118a 1-n , 118b 1-n , 618) and the conducting fluid (116) depends on the orientation of the channel region (112) relative to the upper surface (119) of the conducting fluid (116); and Sampling, by means of a sampling circuit (198), at least one electrical property of the transistor (110) responding to the specific bias conditions. [16] Method according to claim 15, wherein the gate structure (113) comprises a single gate electrode (118), wherein the fixed location of the individual gate electrode (118) and a fill level (150) of the conducting fluid (116) within the reservoir (114) are such that: when the channel region (112) and the upper surface (119) of the conducting fluid (116) are parallel, the single gate electrode (118) is in contact with the conducting fluid (116), and when the channel region (112) is angled at least to a specific degree relative to the upper surface (119) of the conducting fluid (116), the single gate electrode (118) is physically separated from the conducting fluid (116), where the specific bias conditions include a fixed drain / source voltage (Vds) and a fixed gate voltage (V g ) include, where the electrical property is a drain current (Id), wherein the method further comprises determining, based on the drain current (Id), whether the transistor (110) is in an OFF state, and where the OFF state indicates that the chip (102) is tilted or accelerating. [17] Method according to claim 15, wherein the gate structure (113) comprises: a first gate electrode (118a) adjacent to a first side of the reservoir (114); and a second gate electrode (118b) adjacent to a second side of the reservoir (114), wherein fixed locations of the first gate electrode (118a) and the second gate electrode (118b) within the reservoir (114) and a fill level (150) of the conducting fluid (116) within the reservoir (114) are such that: when the channel region (112) and the upper surface (119) of the conducting fluid (116) are parallel, and the first gate electrode (118a) and the second gate electrode (118b) are in contact with the conducting fluid (116), when the channel region (112) is angled by at least a first degree relative to the upper surface (119) of the conducting fluid (116), the first gate electrode (118a) is physically separated from the conducting fluid (116) and the second gate electrode (118b) remains in contact with the conducting fluid (116), and when the channel region (112) is angled by at least one second degree relative to the upper surface (119) of the conducting fluid (116), the second gate electrode (118b) is physically separated from the conducting fluid (116) and the first gate electrode (118a) remains in contact with the conducting fluid (116), where the specific bias conditions include a fixed drain / source voltage (Vds), a fixed first gate voltage (V g1 ) at the first gate electrode (118a), a fixed second gate voltage (V g2 ) at the second gate electrode (118b), where the fixed first gate voltage (V g1) less than the fixed second gate voltage (V g2 ) is, where the electrical property is a drain current (Id), and the method further includes, based on the drain current (Id), an estimation of chip tilt direction and angle or chip acceleration direction and rate. [18] Method according to claim 15, wherein the gate structure (113) comprises: a first gate electrode (118a 1-n ) comprising a stack of electrically insulated first sub-electrodes (1-n) adjacent to a first side of the reservoir (114); and a second gate electrode (118b) 1-n ) comprising a stack of electrically insulated second sub-electrodes (1-n) adjacent to a second side of the reservoir (114), where fixed locations of the first gate electrode (118a 1-n ) and the second gate electrode (118b 1-n) within the reservoir (114) and a fill level (150) of the conducting fluid (116) within the reservoir (114) such that: when the channel region (112) and the upper surface (119) of the conducting fluid (116) are parallel, and all of the first sub-electrodes (1-n) and all of the second sub-electrodes (1-n) are in contact with the conducting fluid (116), when the channel region (112) is angled to progressively increasing first degrees relative to the upper surface (119) of the conducting fluid (116), the first sub-electrodes (1-n) become physically separated from the conducting fluid (116) in a sequence from top to bottom, and the second sub-electrodes (1-n) remain in contact with the conducting fluid (116), and when the channel region (112) is angled to progressively increasing second degrees relative to the upper surface (119) of the conducting fluid (116), the second sub-electrodes (1-n) are physically separated from the conducting fluid (116) in a sequence from top to bottom, and the first sub-electrodes (1-n) remain in contact with the conducting fluid (116), where the specific bias conditions include a fixed drain / source voltage (Vds), a fixed first gate voltage (V g1 ) at each of the first sub-electrodes (1-n), a fixed second gate voltage (V) g2 ) at each of the second sub-electrodes (1-n), where the fixed first gate voltage (V g1 ) less than the fixed second gate voltage (V g2 ) is, where the electrical property is a drain current (Id), and the method further includes, based on the drain current (Id), an estimation of chip tilt direction and angle or chip acceleration direction and rate. [19] Method according to claim 15, wherein the gate structure (113) comprises: a first gate electrode (118a 1-n ) comprising a stack of electrically insulated first sub-electrodes (1-n) adjacent to a first side of the reservoir (114); and a second gate electrode (118b) 1-n ) comprising a stack of electrically insulated second sub-electrodes (1-n) adjacent to a second side of the reservoir (114), where fixed locations of the first gate electrode (118a 1-n ) and the second gate electrode (118b 1-n ) within the reservoir (114) and a fill level (150) of the conducting fluid (116) within the reservoir (114) such that: when the channel region (112) and the upper surface (119) of the conducting fluid (116) are parallel, the lower of the first sub-electrodes (1-n) and the lower of the second sub-electrodes (1-n) are in contact with the conducting fluid (116), and the upper of the first sub-electrodes (1-n) and the upper of the second sub-electrodes are physically separated from the conducting fluid (116), when the channel region (112) is angled to progressively increasing first degrees relative to the upper surface (119) of the conducting fluid (116), the lower of the first sub-electrodes (1-n) are physically separated from the conducting fluid (116) in a sequence from top to bottom, and the upper of the second sub-electrodes (1-n) contact the conducting fluid (116) in a sequence from bottom to top, and when the channel region (112) is angled up to progressively increasing second degrees relative to the upper surface (119) of the conducting fluid (116), the lower of the second sub-electrodes (1-n) are physically separated from the conducting fluid (116) in a sequence from top to bottom, and the upper of the first sub-electrodes (1-n) contact the conducting fluid (116) in a sequence from bottom to top, where the specific bias conditions include a fixed drain / source voltage (Vds), a fixed first gate voltage (V g1 ) at each of the first sub-electrodes (1-n), a fixed second gate voltage (V) g2 ) at each of the second sub-electrodes (1-n), where the fixed first gate voltage (V g1 ) less than the fixed second gate voltage (V g2 ) is, and where the electrical property is a drain current (Id), and the method further includes, based on the drain current (Id), an estimation of chip tilt direction and angle or chip acceleration direction and rate. [20] Method according to claim 15, wherein the gate structure (113) comprises more than two gate electrodes (618) at fixed locations within the reservoir (114), and wherein a filling level (150) of the conducting fluid (116) is such that a conducting fluid (116) only partially fills the reservoir (114) and wherein the reservoir (114) is covered to prevent leakage of the conducting fluid (116).

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