Devices with silicon feedthroughs, guard rings and their manufacturing processes

Abstract

Semiconductor structure having: a semiconductor substrate (112) containing a semiconductor material; a BEOL wiring portion (114) on the semiconductor substrate, the BEOL wiring portion comprising a plurality of conductive layers and an insulating material (110); a silicon via (122) in the semiconductor substrate and in the BEOL wiring section having a diameter Da near a surface (128) of the BEOL wiring section; and a guard ring (130) having an inner surface facing the silicon feedthrough and spaced therefrom by a ring of insulating material (127) having a width Wr and completely surrounding the silicon feedthrough in the BEOL wiring section, wherein a ratio of Da to Wr is 3:1 to 7:1, wherein the guard ring comprises a plurality of guard ring elements (131a / 131b), each of the plurality of guard ring elements having an upper portion (156) and a lower portion (158), the upper portion of each of the plurality of guard ring elements having a first surface (160) and a second surface (162) spaced apart by a distance W aspaced apart from each other, wherein the first surface of the upper portion is closer to the silicon via than the second surface of the upper portion, wherein the lower portion of each of the plurality of guard ring elements has a first surface (164) and a second surface (166) spaced apart by a distance W b spaced apart from each other, wherein the first surface of the lower portion is closer to the silicon via than the second surface of the lower portion, wherein W a by W b is different, and wherein the first surface of the upper portion and the first surface of the lower portion of one of the plurality of guard ring elements are coplanar with each other around the entire inner surface of the guard ring.

Description

BACKGROUND TECHNICAL AREA

[0001] The present disclosure relates to the field of silicon feedthroughs and guard rings. STATE OF THE ART

[0002] The demand for ever-increasing computing power in electronic devices such as smartphones, tablets, desktop computers, laptops, and many other types of electronic devices has steadily increased. Integrated circuits provide the computing power for these electronic devices. One way to increase the computing power of integrated circuits is to increase the number of transistors and other integrated circuits that can be accommodated on a given area of the semiconductor substrate.

[0003] Semiconductor devices or chips (hereinafter referred to simply as "chips") may include a semiconductor substrate on which all FEOL (front-end-of-the-line) processing takes place to form the semiconductor transistors, capacitors, etc., and BEOL (back-end-of-the-line) wiring, in which multiple wiring layers are formed to interconnect the various transistors, capacitors, etc. in the semiconductor substrate. The BEOL wiring may also include input / output (I / O) pads for connecting the chip to a next package level, such as a printed circuit board or a ceramic substrate. The semiconductor substrate contains a semiconductor material, while the BEOL wiring is formed from metallic materials for wiring and dielectric material for insulation.

[0004] Today's semiconductor chips can have a through-substrate via (TSV) that extends partially or completely through the semiconductor substrate and the BEOL wiring. Such a through-substrate via can be used, for example, to connect two chips by stacking them on top of each other. In some cases, the TSV extends completely through the semiconductor substrate. TSVs can be characterized as via-first TSVs, which are formed before the formation of the individual devices, via-middle TSVs, which are formed after the formation of the individual devices but before the formation of the BEOL layers, or via-last TSVs, which are formed after or during the formation of the BEOL layers.

[0005] DE 10 2021100 457 A1 describes a semiconductor structure comprising a semiconductor substrate and an interconnect structure arranged above the semiconductor substrate. The interconnect structure comprises a dielectric structure and a plurality of metal lines stacked one above the other in the dielectric structure. A substrate via (TSV) extends through the semiconductor substrate to contact one of the plurality of metal lines. A protective jacket is arranged along outer side walls of the TSV and separates the outer side walls of the TSV from the dielectric structure of the interconnect structure.

[0006] US 2016 / 0 079 166 A1 describes a method comprising forming a back end of line (BEOL) wiring portion directly on a semiconductor base portion, wherein the BEOL wiring portion includes a plurality of layers of a metallic material and a dielectric material and no semiconductor material. The method further comprises forming a substrate via through the BEOL wiring portion and the semiconductor base portion, and forming a guard ring in the BEOL wiring portion that surrounds the substrate via in the BEOL wiring portion, wherein the substrate via in the semiconductor base portion is not surrounded by the guard ring. BRIEF DESCRIPTION OF DIFFERENT VIEWS OF THE DRAWINGS Fig. 1A and Fig. 1B are cross-sectional views showing a method of manufacturing a silicon via in a semiconductor chip. Fig. 2A to 2F are cross-sectional views illustrating a method of fabricating a silicon via and top layer metallization according to some embodiments of the present disclosure. Fig. 2G is a schematic top view of a silicon via and a guard ring according to some embodiments of the present disclosure. Fig. 3 is an exploded cross-sectional view similar Fig. 2D with two guard ring elements according to some embodiments of the present disclosure. Fig. 4A to 4E are cross-sectional views in the direction of arrow 3-3 in Fig. 3, showing various embodiments of the present disclosure of a guard ring according to the embodiments described herein. Fig. 5 is a flowchart illustrating a method according to an embodiment of the present disclosure. Fig. 6A to 6E are cross-sectional views illustrating a method according to an embodiment of the present disclosure. Fig. 7 is a cross-sectional view of a silicon via and a guard ring according to some embodiments of the present disclosure. Fig. 8 is a cross-sectional view of the silicon via and guard ring according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0007] In the following description, thicknesses and materials for various layers and structures within an integrated circuit may be described. Specific dimensions and materials are provided as examples for various embodiments. Those skilled in the art will recognize, in light of the present disclosure, that in many cases, other dimensions and materials may be used within the scope of the present disclosure.

[0008] The following disclosure provides many different embodiments or examples of implementing various features of the described subject matter. To simplify the present description, specific examples of components and arrangements are described below. These are, of course, only examples and are not to be understood as limiting. For example, the formation of a first feature over or on top of a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, but may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Furthermore, reference numerals may be repeated throughout the various examples of the present disclosure.This repetition is for simplicity and clarity and does not necessarily dictate any relationship between the various embodiments and / or configurations discussed.

[0009] Furthermore, for ease of description, spatially relative terms such as "under," "beneath," "down," "over," "upon," "above," "above," and the like may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the drawings. The spatially relative terms are intended to encompass various orientations of the device during use or operation in addition to the orientation illustrated in the drawings. The device may be oriented differently (rotated 90 degrees or in other orientations), and the spatially relative terms used herein may also be interpreted accordingly.

[0010] "Vertical direction" and "horizontal direction" are to be understood as relative directions. Thus, the horizontal direction is to be understood as substantially perpendicular to the vertical direction, and vice versa. However, it is within the scope of the present disclosure that the described embodiments and aspects can be rotated in their entirety such that the extent referred to as the vertical direction is oriented horizontally and, at the same time, the extent referred to as the horizontal direction is oriented vertically.

[0011] In the following description, certain specific details are set forth in order to provide a thorough understanding of various embodiments of the disclosure. However, those skilled in the art will understand that the disclosure may be practiced without these specific details. In other instances, well-known structures associated with electronic components and manufacturing techniques have not been described in detail in order not to unnecessarily obscure the descriptions of the embodiments of the present disclosure.

[0012] Unless the context requires otherwise, the term "comprise" and variations thereof, such as "comprises" and "comprising", shall be construed in an open, inclusive sense throughout the specification and claims, i.e., as "including, but not limited to".

[0013] The use of ordering terms such as “first,” “second,” and “third” does not necessarily imply a ranking, but may only distinguish between multiple instances of an action or structure.

[0014] When reference is made to "an embodiment" in this specification, it means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Therefore, the phrases "in an embodiment" appearing in various places throughout this specification do not necessarily all refer to the same embodiment. Moreover, the individual features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0015] As used in this specification and the appended claims, the singular forms "a," "an," and "the" include plural references unless the content clearly dictates otherwise. It should also be noted that the term "or" is generally used to include "and / or" unless the content clearly dictates otherwise.

[0016] The various advantages and purposes of embodiments according to the present disclosure, as explained above and below, are achieved by providing a semiconductor structure, a method of forming a semiconductor structure and an apparatus in the independent claims, which are further specified in the dependent claims.

[0017] In Fig. 1A and Fig. 1B shows a method for manufacturing a silicon feedthrough. In Fig. 1A shows a semiconductor chip 10 with a semiconductor substrate 12 and a BEOL wiring 14. It is conceivable that in Fig. 1A and Fig. 1B, only a portion of the semiconductor chip 10 is shown. The semiconductor substrate 12 is subjected to FEOL processing to form various individual devices, such as transistors, capacitors, and the like, within the semiconductor substrate 12. These individual devices are not shown for clarity. The BEOL wiring 14 comprises multiple layers (not shown) of electrically conductive material, such as metallic wiring, within an insulating dielectric material. Precise details of the BEOL wiring 14 are known to those skilled in the art and are not shown or described here. Fig. 1A further shows a silicon via opening 16 etched through the BEOL wiring 14 and the semiconductor substrate 12.

[0018] As in Fig. 1B, an insulating material 18 may then be deposited on the walls of the silicon via opening 16. O3 / TEOS (tetraethylorthosilicate) is used in one process for depositing the insulating material 18. A byproduct of the formation of the insulating material 18 using O3 / TEOS (tetraethylorthosilicate) is the formation of water, which may penetrate the dielectric material of the BEOL wiring 14, as indicated by arrows 20 in Fig. 1B. Water can adversely affect the insulating material of the BEOL wiring 14 and the materials that form the electrically conductive features of the BEOL. For example, the electrically conductive features of the BEOL include features that include barrier layers such as TiN, TaN, or the like, and electrically conductive metals such as copper or aluminum. If the water formed during the formation of the insulating material 18 penetrates the dielectric material of the BEOL wiring 14, it can promote oxidation of the barrier layer of the BEOL wiring features. Such oxidation weakens the barrier layer, allowing the conductive material, such as copper or aluminum, of the BEOL wiring to diffuse through the barrier layer and form metal nodules in the insulating dielectric material of the BEOL wiring 14.These metal nodules can eventually coalesce, forming an undesirable electrical pathway between BEOL wiring features within the insulating dielectric material. For example, when the BEOL wiring features are subjected to a bias voltage, such as during testing or normal operation, the BEOL metal can migrate through the weakened barrier layer and form the metal nodules.

[0019] As in Fig. As shown in Figure 1B, the silicon via opening 16 is metallized by depositing a metallic material, such as copper or aluminum, into the via opening 16 using techniques such as electroplating. The via opening 16 may also include a lining layer such as TiN or Ta / TaN.

[0020] In Fig. 2A to 2D, an embodiment of the present disclosure is illustrated. As in Fig. 2A, a semiconductor chip 110 comprises a semiconductor substrate 112 and a BEOL wiring 114 on one side of the semiconductor substrate 112. An additional wiring layer 111 lies on the opposite side of the semiconductor substrate 112 and includes a plurality of conductive elements 111a, 111b, and 111c. For the sake of clarity, the semiconductor substrate 112 is not shown in cross-section, so that structures or devices within the semiconductor substrate 112 are not visible; however, such structures or devices are present in the semiconductor substrate 112 and are schematically represented by a box 115. These structures or devices comprise semiconductor structures, such as transistors. It should be noted that in Fig. 2A to 2D only a portion of the semiconductor chip 110 is shown. Suitable materials for the semiconductor substrate 112 include, but are not limited to, Group IV semiconductors such as silicon, silicon germanium, or germanium, a III-V compound semiconductor, or a II-VI compound semiconductor. The metallization of the BEOL interconnection 114 typically includes copper, but may also include other conductive materials, such as aluminum. The dielectric insulation material of the BEOL interconnection 114 may be any suitable material, such as silicon dioxide, silicon nitride, or SiCOH (a compound of silicon, carbon, oxygen, and hydrogen).

[0021] The semiconductor substrate 112 undergoes FEOL processing to form the various individual devices, such as transistors, capacitors, and the like, within the semiconductor substrate 112. These individual devices are not shown for clarity. The BEOL wiring 114 comprises multiple layers (not shown) of metallic wiring in an insulating dielectric material. Precise details of the BEOL wiring 114 are known to those skilled in the art and need not be described in further detail. Fig. 2A is also shown the guard ring 130, which in some embodiments may be formed in the same order and simultaneously with the individual wiring layers of the BEOL wiring 114 and the connections or vias between the various metallic wiring layers. The guard ring may or may not be electrically connected to the metallization of the BEOL wiring 114. When the guard ring 130 is formed in the same order and simultaneously with the individual wiring layers of the BEOL wiring 114 and the vias therebetween, the guard ring comprises a plurality of segments or sections, designated 131a-131j.Each of these segments 131a-131j includes a wider upper portion 131u, which is formed during a process in which a layer of BEOL wiring is formed, and a narrower lower portion 131n, which is formed during a process in which the region between adjacent BEOL wiring layers is formed. The formation of the guard ring 130 will be discussed in more detail below. In one embodiment described herein, the guard ring 130 is a ring or fence made of electrically conductive material, such as a metallic material, that encloses the region in which the silicon via is formed. In the illustrated embodiment, the guard ring 130 extends at least the entire vertical length of the BEOL wiring 114.

[0022] In Fig. 2B shows a silicon via opening 116 etched through the BEOL wiring 114 using dielectric or conductive etching techniques, such as gas plasma etching. As shown in Fig. 2B, the via opening 116 extends into a portion of the additional wiring layer 111, where it terminates at the conductive feature 111b. The etching process used may be an isotropic dry etching process, such as a Bosch process. By using an isotropic etching process (as opposed to an anisotropic etching process), a recess is formed that extends both laterally and vertically. In the Bosch process, a first gas is typically introduced, which etches the substrate until the desired depth of the recess is reached; then, the first gas is turned off and a second gas is introduced, which forms a protective layer along the surface of the sidewalls. When the first gas is reintroduced, the first gas removes the protective layer at the bottom of the recess (leaving the protective layer on the sidewalls) and continues etching the substrate at the bottom of the recess.The process of introducing the first gas and the second gas is repeated until the desired depth is reached.

[0023] An etching gas such as SF6 can be used as the etchant. The process described above can be repeated as often as required to create an opening of the desired depth. After creating the opening of the desired depth, the opening can be filled with a conductive material to form a TSV 122 as shown in Fig. 2E. An insulating layer (118 in Fig. 2D) is formed along the sidewalls of the opening to create a diffusion barrier that prevents the conductive material, such as copper, from diffusing into the substrate 112 and / or one or more dielectric layers, such as the dielectric material of the additional wiring layer 111. The insulating layer 118 may be formed, for example, by physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), spin-on coating, or other suitable methods. After the insulating layer 118 is formed, a conductive material is used to form the TSV 122. The conductive material may be, for example, copper, tungsten, aluminum, silver, combinations thereof, or the like.In one embodiment, a seed layer (not shown) is formed over the insulating layer 118, and an electrodeposition process is used to fill the opening. Other suitable methods, such as electroless plating, plating, or CVD, may also be used. The process may include overfilling the opening and removing excess conductive material located outside the TSV openings, for example, by a method such as chemical mechanical polishing (CMP), etching, combinations thereof, or the like.

[0024] In Fig. 2C, the silicon via opening 116 is expanded through the semiconductor base 112 using etching techniques such as plasma etching. The silicon via opening 116 in Fig. 2C is illustrated as extending through the semiconductor base 112 and into the additional wiring layer 111. In other embodiments, the silicon via opening does not extend through the semiconductor base 112, but rather through a portion of the semiconductor base 112 to metal features on an opposite side of the Fig. 2C. The location of the silicon via opening 116 is chosen to be within the guard ring 130. While the silicon via opening 116 is illustrated as being completely etched through the BEOL wiring 114 and the semiconductor base 112, it is within the scope of the present disclosure for the silicon via opening 116 to be only partially etched through the BEOL wiring 114 and / or partially through the semiconductor base 112.

[0025] In some embodiments of the present disclosure, as in Fig. 2C, a portion of the semiconductor base 112 near the interface between the semiconductor base 112 and the BEOL wiring 114 is not removed when the silicon via opening 116 is extended through the semiconductor base 112. These remaining portions of the semiconductor base 112 are referred to as protrusions 117. Without being limited by theory, the protrusions 117 are believed to result from a portion of the semiconductor base 112 being shielded from the etchant used to etch the semiconductor base 112 to extend the silicon via opening by the portion of the insulating dielectric material of the BEOL wiring 114 that remains after the silicon via opening 116 is formed in the BEOL wiring 114. This remaining portion is shown in Fig. 2B and is located at the bottom of the silicon via opening 116 formed in the dielectric insulating material of the BEOL wiring 114. According to some embodiments of the present disclosure, a second etch step is performed to remove the protrusions 117 and form a planar wall of the silicon via opening 116. In one embodiment, the protrusions 117 are removed by the same etching process used to extend the silicon via opening 116 into the semiconductor base 112. In other embodiments, the protrusions 117 are removed by a different type of etching process than the etching process used to extend the silicon via opening 116 into the semiconductor base 112. The removal of the protrusions 117 is desirable to reduce stress concentrations in the material of the semiconductor base 112.

[0026] With reference to Fig. 2D shows the top of the silicon feedthrough opening 116 (at the top of the BEOL wiring 114) in Fig. 2D has a dimension Da representing a lateral distance between the left sidewall 119a and the right sidewall 119b of the silicon via opening 116. In some embodiments, Da is 1.5 to 3 micrometers. The bottom of the silicon via opening 116 (at the bottom of the semiconductor base 112) has a dimension Dc representing a lateral distance between the left sidewall 119a and the right sidewall 119b of the silicon via opening 116. D c is smaller than D a . Near the interface between the BEOL wiring 114 and the semiconductor base 112, the silicon feedthrough opening 116 has a dimension D b which represents a lateral distance between the left sidewall 119a and the right sidewall 119b of the silicon feedthrough opening 116. D b is smaller than Da and larger than D c . According to some embodiments of the present disclosure, sufficient removal of the projections 117 is achieved when D b greater than D c is. D b smaller than D c , as in Fig. 2C, is an indication that sufficient removal of the protrusions 117 is not achieved. As mentioned above, insufficient removal of the protrusions 117 is undesirable due to the stress concentrations that occur when protrusions 117 are present.

[0027] After successful removal of the protrusions 117 as described above, an insulating material 118, such as an oxide or a low-k dielectric material, is formed on the walls of the silicon via opening 116. The insulating material serves to electrically isolate the conductive material from the Si substrate. The insulating material used and its thickness can affect the performance of the TSV, such as its capacitance and leakage current. One method for depositing the insulating material 118 uses O3 / TEOS (tetraethyl orthosilicate). In some embodiments, the insulating material 118 may have a thickness of approximately 1 micrometer. As mentioned above, water is a byproduct of the formation of the insulating material 118, which may penetrate the dielectric material of the BEOL wiring 114.As mentioned above, water can damage the insulating material of the BEOL wiring 114 and the materials that form the electrically conductive features of the BEOL. For example, the electrically conductive features of the BEOL include features that have barrier layers, such as TiN, TaN, or the like, and electrically conductive metals, such as copper or aluminum, that are at least partially surrounded by the barrier layers. As mentioned above, if the water generated during the formation of the insulating material 118 penetrates the dielectric material of the BEOL wiring 114, it can promote the oxidation of the barrier layer of the BEOL wiring features. Such oxidation weakens the barrier layer, allowing the conductive material, such as copper or aluminum, of the BEOL wiring to diffuse through the barrier layer and form metal nodules in the insulating dielectric material of the BEOL wiring 114.For example, when the BEOL wiring features are subjected to a bias voltage, such as during testing or normal operation, the BEOL metal may migrate through the weakened barrier layer and form metal nodules. These metal nodules may eventually coalesce and form an undesirable electrical path between BEOL wiring elements within the insulating dielectric material. According to embodiments of the present disclosure, the guard ring 130 prevents water generated during the formation of the insulating layer 118 from migrating over the guard ring 130, where the water may damage the barrier layer of the BEOL wiring features.

[0028] Next, the silicon via opening 116 is metallized by depositing a metallic material 122, such as copper or aluminum, into the silicon via opening 116, resulting in the structure as shown in Fig. 2E. The silicon via opening 116 may also include an insulating layer or lining layer, for example TEOS, Ti, TiN, Ta or TaN, which may be Fig. 2E are not shown. The liner layer may have a thickness of approximately 10 nm to 100 nm. If the wall of the silicon via opening 116 is not completely covered by the cap layer, this may allow diffusion of the metallization 122, in particular copper, into the wiring layers of the BEOL wiring 114. However, the presence of the guard ring 130 prevents the metallization 122 from migrating into the functional portion of the wiring layers of the BEOL wiring 114. In another embodiment of the present disclosure, the liner layer may be omitted, since any migration of the metallization 122 into the functional portion of the BEOL wiring 114 would be prevented by the guard ring 130.

[0029] The metallized silicon feedthrough 116, as shown in Fig. 2E, may extend through the entire BEOL wiring 114 and the semiconductor substrate 112, as shown in Fig. 2E. In other embodiments of the present disclosure, the metallized silicon via 116 may extend only partially through the BEOL wiring 114 and / or the semiconductor substrate 112.

[0030] It should be noted that the metallized silicon via opening 116 may extend continuously through the BEOL wiring 114 and the semiconductor substrate 112. By "continuous," it is meant that the metallized silicon via opening 116 extends straight through the semiconductor chip 110 from or near the surface 128 of the BEOL wiring 114 to or near the surface 132 of the semiconductor substrate 112 without any lateral deflections.

[0031] In the embodiment of Fig. 2F, an upper metal layer 134 is formed over portions of the surface 128 of the BEOL wiring 114, an upper surface of the guard ring 130, and an upper surface of the metallization 122 in the silicon via opening 116. The formation of the upper metal layer 134 includes the steps of forming an insulating dielectric material over the surface 128 of the BEOL wiring 114, an upper surface of the guard ring 130, and an upper surface of the metallization 122 in the silicon via opening 116, patterning such a formed insulating dielectric material, and forming additional metallization in the patterned insulating dielectric material over the guard ring 130 and the metallization 122 in the silicon via opening 116. Although in Fig. 2F, an insulating or passivation layer, such as a combination of an oxide layer and a nitride layer, for example, a combination of an oxide layer and a layer of TEOS, Ti, TiN, Ta, or TaN, separates features of the upper metal layer 134 from the dielectric material in which the BEOL interconnection 114 is formed.

[0032] In Fig. 2F, the upper metal layer 134 comprises a portion 135 having a width W T , which essentially corresponds to the diameter D g (in Fig. 2G) of the guard ring 130. The portion 135 extends above a top surface of the metallization 122 in the silicon via opening 116 and extends above a top surface of the dielectric material between the guard ring 130 and the metallization 122 in the silicon via opening 116. Although the portion 135 electrically connects the metallization 122 to the guard ring 130, in some embodiments the guard ring 130 is an electrically inactive structure, as described above. In other embodiments, such as in Fig. 7, the upper metal layer 134 comprises a portion 135 having a width W T , which essentially corresponds to the diameter Da (in Fig. 2G) of the metallization 122 in the silicon via opening 116. The upper metal layer 134 further comprises a portion 135a above the guard ring 130, which is separated from the portion 135 by a dielectric material. Due to such a structure, the guard ring 130 is electrically insulated from the metallization 122. In another embodiment (see Fig. 8) the upper metal layer 134 comprises a section 135 with a width W T which is larger than the diameter Dg (in Fig. 2G) of the guard ring 130. According to the embodiments of the present disclosure, the ratio of D g (hereinafter referred to as Fig. 2G) to W T about 1: 0.5 to 1: 2. In other embodiments, the ratio of D g to W T about 1 : 0.75 to 1 : 1.5. If the ratio of Dg to W Tfalls below these ranges, the density (number) of TSVs in the layer comprising the BEOL wiring is reduced due to the larger relative size of the portion 135 of the metal layer 134. If the ratio of Dg to W T exceeds these ranges, the density (number) of TSVs in the layer containing the BEOL wiring is reduced due to the larger relative size of the guard ring.

[0033] In Fig. 2G shows a top view of a TSV 122 and a protective ring 130. In Fig. 2G, several metal lines 125 and several dummy metal structures 123 are present to achieve the desired metal density in the BEOL. Such a desired metal density can protect non-metallic features from acid etching and improve the flatness of the various BEOL layers by serving as a planarization stop. The TSV 122 is defined by the diameter D awhich is described in more detail below. W a is the width of a wiring portion 156 of a guard ring member 131a described below with reference to Fig. 3. The TSV 122 is separated from the guard ring 130 by a ring of insulating material 127 between the guard ring 130 and the dummy metal structures 123 and the metal lines 125. The ratio of the width W r of ring 127 to Wa is about 1 : 1 to about 1 : 1.5. W r is about 0.3 to 0.5 micrometers. If the ratio of the width W r of the ring 127 to W a falls below 1: 1.1, the potential for leakage current from the TSV 122 to the guard ring 130 increases. If the ratio of the width W r of the ring 127 to W ais greater than approximately 1:1.5, the density of the BEOL wiring is reduced due to the larger proportion of dielectric material between the TSV 122 and the guard ring 130. The guard ring 130 is electrically isolated from the dummy metal structures 123 and the metal lines 125 by a dielectric 129. The ratio of D a to W r is about 3 : 1 to about 7 : 1. If the ratio of D a to W r is below about 3:1, the performance of the TSV may be impaired. If the ratio of D a to W r is above about 7:1, the probability of a leakage current from the TSV 122 increases.

[0034] In Fig. 3 shows a portion of two elements 131a and 131b of the protective ring 130 in an enlarged view. In the embodiment of Fig. 3, the guard ring element 131a and the guard ring element 131b are identical. Therefore, only the guard ring element 131a is described below. The description of the guard ring element 131a also applies to the guard ring element 131b. The guard ring element 131a comprises a first section 150 and a second section 152. In the Fig. 3, the first portion 150 has a rectangular shape, and the second portion 152 also has a rectangular shape. The first portion 150 is a smaller rectangle than the second portion 152. The dashed line 154 in the second portion 152 is an imaginary line separating an upper portion 156 of the guard ring element 131a from a lower portion 158 of the guard ring element 131a. According to some embodiments of the present disclosure, the upper portion 156 is formed using a similar semiconductor process that forms a metal wiring layer of the BEOL wiring 114. The lower portion 158 is fabricated using a similar process that forms a via between two layers of the BEOL wiring 114.The upper portion 156 may be referred to below as a wiring portion of the guard ring element 131a, and the lower portion 158 may be referred to below as a feedthrough portion of the guard ring element 131a. The upper portion 156 includes a first surface 160 and a second surface 162 separated by a distance W. a are arranged at a distance from each other. W a is a width of the wiring section 156 of the guard ring 131a. In the Fig. 3, the distance between the first surface 160 and the metallization 122 in the silicon via opening 116 is less than the distance between the second surface 162 and the metallization 122 in the silicon via opening 116. The lower portion 158 includes a first surface 164 and a second surface 166 that are spaced apart by a distance W b are arranged at a distance from each other. W bis a width of the lead-through section 158 of the protective ring 131a. In the Fig. 3, the distance between the first surface 164 and the metallization 122 in the silicon via opening 116 is less than the distance between the second surface 166 and the metallization 122 in the silicon via opening 116. In other words, W a different from W b . In the Fig. 3, the distance between the second surface 162 and the metallization 122 in the silicon via opening 116 is greater than the distance between the second surface 166 and the metallization 122 in the silicon via opening 116. In the embodiment shown in Fig. 3, the protective ring element 131a has a dimension H b parallel to the first surfaces 160 and 164. In Fig. 3 the dimension H extends bbetween an upper surface 168 of the guard ring element 131a and a lower surface 170 of the guard ring element 131a. In the Fig. 3 illustrated embodiment, the dimensions H b some guard ring elements 131a-131j differ from each other. For example, H b of the protective ring element 131j in Fig. 3 greater than H b the other guard ring elements, for example the guard ring elements 131a-131h. For example, H b of the protective ring element 131a of H a of the guard ring element 131b. Since the guard ring element 131a and the guard ring element 131b in Fig. 3 are identical, the above description of features 150, 152, 154, 156, 158, 160, 162, 164, 166, 168, and 170 applies analogously to guard ring element 131b and to guard ring elements 131c-131j. Since guard ring element 131a and guard ring element 131b are identical, the disclosure regarding the dimensions Wa , W b and H b of the guard ring element 131a analogously for the guard ring element 131b. In some embodiments, the guard ring elements 131a-131j all have the same dimensions. In other embodiments, the guard ring elements 131a-131j each have different dimensions from one another. In further embodiments, some of the guard ring elements 131a-131j have the same dimensions and some of the other guard ring elements 131a-131j have different dimensions from one another. For example, W a of the protective ring element 131a of W a one or more of the other guard ring elements 131b-132j may be different, while the remaining guard ring elements have the same W a For example, the W b of the protective ring element 131a of W b one or more of the other guard ring elements 131b-132j may be different, while the remaining guard ring elements have the same Wb While in the embodiment in Fig. 3, ten guard ring elements are illustrated, in other embodiments of the present disclosure, the BEOL wiring 114 includes more than ten guard ring elements, and in other embodiments, the BEOL wiring 114 includes fewer than ten guard ring elements.

[0035] According to some embodiments of the present disclosure, the ratio of W a to W b about 1.8 to 1.1. In other embodiments, the ratio of W a to W b about 1.6 to 1.2. If the ratio of W a to W bis greater than 1.8, the wiring section 156 of a guard ring element 131 comes too close to adjacent wire elements of the BEOL wiring 140, thereby increasing the likelihood of an undesirable electrical path being formed between BEOL wiring features and the wiring section 156 or between adjacent BEOL wiring features. If the ratio of W a to W b falls below 1.1, the guard ring element 131 can no longer effectively protect the BEOL wiring from water that may be generated during TSV formation. In some embodiments, W a 0.15 to 0.5 micrometers. In other embodiments, W a 0.2 to 0.4 micrometers. In some embodiments, W b 0.1 to 0.4 micrometers. In other embodiments, W b 0.1 to 0.3 micrometers.

[0036] According to embodiments of the present disclosure, the first surface 160 of the guard ring element 131a and the first surface 164 of the guard ring element 131b are coplanar. In other embodiments of the present disclosure, the first surface 160 and the first surface 164 of the guard ring element 131a and the first surface 160 and the first surface 164 of the guard ring element 131b are coplanar. In further embodiments, a first surface 160 and / or a first surface 164 of one or more given guard rings is coplanar with a first surface 160 and / or a first surface 164 of one or more other guard rings. Guard ring elements with coplanar first surfaces 160 and / or first surfaces 164 of embodiments of the present disclosure are less likely to become deformed during the Fig. 2C and Fig. 2D and described above. If the guard ring has internal surfaces that are not coplanar, there is an increased likelihood that the etching to form the opening for the TSV may also etch a portion of the first surface 160 and / or the first surface 164 of a guard ring element.

[0037] The guard ring 130 can be formed in various shapes depending on the requirements of the semiconductor design. Fig. 4A to 4E are cross sections of the semiconductor chip 110 in the direction of arrows 3-3 of Fig. 3. In Fig. 4A-4E is the upper surface of the wiring section 156 of the guard ring 131j with the dimension W described above a visible; the lead-through section 158 with the dimension W b However, it lies beneath the wiring section 156 and is not visible. The TSV 116 has the dimension D described above. aThe protective ring 130A has the dimension D described above g up. In Fig. 4A, it can be seen that the guard ring 130A is rectangular in a cross-sectional view. In Fig. 4B, the guard ring 130B is square in a cross-sectional view, with the guard ring 130C in Fig. 4C is circular in cross-sectional view. Fig. 4D shows an embodiment in which the guard ring 130A is octagonal in cross-sectional view. Fig. 4E shows an embodiment in which the guard ring 130A is hexagonal in cross-sectional view. The metallized silicon via 116 may be solid, as in Fig. 4A-4E, and in other embodiments, the silicon via 116 may be hollow in the central region. Fig. 4A to 4E are only examples of cross-sectional views of guard rings and are not to be considered limiting. In Fig. 4B, Fig. 4C, Fig. 4D and Fig. 4E, the space between the TSV and the inner circumference or surface of the guard ring 130B corresponds to the dimension W r in Fig. 2G.

[0038] The dimensions of the guard ring 130C and the metallized silicon vias 116 vary depending on the design requirements of the semiconductor chip. In one embodiment, which is illustrative and not limiting, the metallized silicon vias 116 may have an outer diameter of approximately 1 to 3 micrometers. In some embodiments, the guard ring 130C ( Fig. 4B) have an outer diameter of about 2 to 4 micrometers. In some embodiments, the guard ring 130C has an inner diameter of 1.5 to 3 micrometers. In some embodiments, the distance between the opposing surfaces 164 or 160 of a guard ring element 131C and the feedthrough 116 is about 0.2 to 0.5 micrometers. If a guard ring element 131C is round, this results in an opening in the guard ring with a diameter of about 2.5 to 3.5 micrometers. In some embodiments, the ratio of W a to the inner diameter of the guard ring element 131C is approximately 1 to 1.5. If the ratio of W a to the inner diameter of the guard ring element 131C is less than about 1, the guard ring element 131C cannot effectively isolate the BEOL wiring from water that may be generated during the formation of the TSV. If the ratio of W ato the inner diameter of the guard ring element 131C is greater than about 1.5, the wiring portion of the guard ring element 131C comes too close to adjacent wire elements of the BEOL wiring 140 and increases the likelihood of forming an undesirable electrical path between the BEOL wiring features. In some embodiments, the ratio of W b to the inner diameter of the guard ring element 131C is slightly larger than 1. If the ratio of W b to the inner diameter of the guard ring element 131C is less than 1, the guard ring element 131C cannot effectively isolate the BEOL wiring from water that may be generated during the formation of the TSV.

[0039] The method 500 for manufacturing a semiconductor article with a silicon feedthrough and a guard ring is described below with reference to Fig. 5 and Fig. 6A to 6E. In a first step of the method, a semiconductor base 112 is provided, see Box 40 in Fig. 5 and Fig. 6A. In other words, a semiconductor wafer is provided with all the necessary semiconductor devices such as transistors, capacitors, and the like. It is understood that in Fig. 6A only a portion of the semiconductor wafer is shown. Next, a first BEOL wiring layer 114A is formed, which includes a metallization 140 and a dielectric material 142, as shown in Box 42 and Fig. 6B. Note that the BEOL wiring layer 114A includes a guard ring portion 144, which may or may not perform an electrical function in the BEOL wiring 114. The formation of the BEOL wiring layer 114A includes the formation of the feedthrough portion 140a and the wiring portion 140b. Once the feedthrough portion 140a and the wiring portion 140b are formed, the feedthrough portion 144a and the wiring portion 144b, or the guard ring 144, are formed. These features and the subsequent BEOL wiring layers and guard ring portions are fabricated using known techniques. Additional BEOL wiring layers are formed until a predetermined number of BEOL wiring layers are formed to meet the design requirements of the semiconductor chip, see Box 44 in Fig. 5 and Fig. 6C. As in Fig. 6C, an additional BEOL wiring layer 114C is formed, but in practice, more such BEOL wiring layers are usually formed, as indicated by dashed lines in Fig. 6C-6E. Note that the guard ring portions 144 of each BEOL wiring layer are stacked on top of the guard ring portion 144 of the preceding BEOL wiring layer. The various guard ring portions 144 form, for example, a square, rectangular, circular, or other shape as described above. Within the guard ring portions 144 is an open area 146 in which the silicon via 116 is formed. As shown in box 46 in Fig. 5 and Fig. 6D, the silicon via 116 is formed in the open area 146 (and within the guard ring portions 144), and an insulating layer 118 is formed on the surfaces of the silicon via opening 116. Finally, the silicon via opening 116 is metallized with an optional liner layer 124 and a metallization 122, see Box 48 in Fig. 5 and Fig. 6E. Semiconductor processing then continues in the conventional manner.

[0040] In one embodiment, the present disclosure describes a semiconductor structure including a semiconductor substrate having a semiconductor material. The semiconductor structure further comprises a back end of the line (BEOL) wiring portion on the semiconductor substrate. The BEOL wiring portion comprises a plurality of wiring layers comprising metal layers and insulating material. A silicon via is present in the BEOL wiring portion and the semiconductor substrate. The semiconductor structure comprises a guard ring surrounding the silicon via in the BEOL wiring portion, the guard ring comprising a plurality of guard ring elements, each of the plurality of guard ring elements comprising a first portion and a second portion. The first portion of each of the plurality of guard ring elements comprises a first surface and a second surface separated by a distance W aspaced apart from each other, wherein the first surface is closer to the silicon via than the second surface. The second portion of each of the plurality of guard ring elements has a first surface and a second surface spaced apart by a distance W b spaced apart from each other, wherein the first surface of the second portion is closer to the silicon via than the second surface of the second portion. According to some embodiments disclosed herein, W a by W b different and the first surface of one of the plurality of guard ring elements is coplanar with the first surface of another of the plurality of guard ring elements.

[0041] According to a second aspect of the embodiments disclosed herein, a method for manufacturing a semiconductor structure is provided, comprising a step of providing a semiconductor substrate containing a semiconductor material. The method further comprises a step of forming a BEOL wiring portion, wherein the BEOL wiring portion comprises a plurality of metal layers, an insulating material, and a guard ring. The guard ring comprises a plurality of guard ring elements. Each of the plurality of guard ring elements has a first portion and a second portion. The first portion of each of the plurality of guard ring elements comprises a first surface and a second surface spaced apart by a distance W aspaced apart from each other, wherein the first surface is closer to the silicon via than the second surface. The second portion of each of the plurality of guard ring elements includes a first surface and a second surface spaced apart by a distance W b spaced apart from each other, wherein the first surface of the second section is closer to the silicon via opening than the second surface of the second section. According to some embodiments, W a different from W band the first surface of one of the plurality of guard ring elements is coplanar with the first surface of another of the plurality of guard ring elements. Methods disclosed herein further include a step of forming a silicon via opening surrounded by the guard ring in the BEOL wiring portion and the semiconductor substrate. According to some embodiments of the present disclosure, the method includes metallizing the silicon via opening.

[0042] According to a third aspect of some of the embodiments described herein, a semiconductor device is provided comprising a semiconductor substrate containing a semiconductor material. The semiconductor device comprises a BEOL wiring portion on the semiconductor substrate, wherein the BEOL wiring portion comprises a plurality of metal layers and an insulating material. The semiconductor device further comprises a silicon via in the semiconductor substrate and the BEOL wiring portion, wherein the silicon via in the semiconductor substrate has a dimension D b adjacent to the BEOL wiring section and a dimension D c in the semiconductor substrate adjacent to a surface of the semiconductor substrate opposite a surface adjacent to the BEOL wiring section. In some embodiments, D b greater than D c. The device further comprises a guard ring surrounding the silicon feedthrough in the BEOL wiring section. The guard ring comprises a plurality of guard ring elements. Each of the plurality of guard ring elements has a first portion and a second portion. The first portion of each of the plurality of guard ring elements has a first surface and a second surface separated by a distance W a spaced apart from each other, wherein the first surface is closer to the silicon via than the second surface. The second portion of each of the plurality of guard ring elements includes a first surface and a second surface spaced apart by a distance W b spaced apart from each other, wherein the first surface of the second portion is closer to the silicon via than the second surface of the second portion. In some embodiments, W a different from W b .

[0043] The various embodiments described above may be combined to provide further embodiments.

Claims

[1] Semiconductor structure having: a semiconductor substrate (112) containing a semiconductor material; a BEOL wiring portion (114) on the semiconductor substrate, the BEOL wiring portion comprising a plurality of conductive layers and an insulating material (110); a silicon via (122) in the semiconductor substrate and in the BEOL wiring section having a diameter Da near a surface (128) of the BEOL wiring section; and a guard ring (130) having an inner surface facing the silicon feedthrough and spaced therefrom by a ring of insulating material (127) having a width Wr and completely surrounding the silicon feedthrough in the BEOL wiring section, wherein a ratio of Da to Wr is 3:1 to 7:1, wherein the guard ring comprises a plurality of guard ring elements (131a / 131b), each of the plurality of guard ring elements having an upper portion (156) and a lower portion (158), the upper portion of each of the plurality of guard ring elements having a first surface (160) and a second surface (162) spaced apart by a distance W aspaced apart from each other, wherein the first surface of the upper portion is closer to the silicon via than the second surface of the upper portion, wherein the lower portion of each of the plurality of guard ring elements has a first surface (164) and a second surface (166) spaced apart by a distance W b spaced apart from each other, wherein the first surface of the lower portion is closer to the silicon via than the second surface of the lower portion, wherein W a by W b is different, and wherein the first surface of the upper portion and the first surface of the lower portion of one of the plurality of guard ring elements are coplanar with each other around the entire inner surface of the guard ring. [2] A semiconductor structure according to claim 1, wherein W a greater than W band the first surface of the upper portion and the first surface of the lower portion of one of the plurality of guard ring elements are coplanar with a first surface of an upper portion and a first surface of a lower portion of another of the plurality of guard ring elements around the entire inner surface of the guard ring. [3] A semiconductor structure according to claim 1, wherein W a 10% to 80% larger than W b is. [4] A semiconductor structure according to any preceding claim, wherein one or more of the plurality of guard ring elements are in electrical communication with electrically conductive features of the BEOL portion. [5] Semiconductor structure according to one of the preceding claims, wherein a first guard ring element has a dimension H a parallel to the first surfaces of the first guard ring element and a second guard ring element has a dimension H bparallel to the first surfaces of the second guard ring element, wherein H a by H b is different. [6] A semiconductor structure according to any one of the preceding claims, wherein one or more of the plurality of guard ring elements comprise an electrically conductive material. [7] A method for producing a semiconductor structure, comprising: Providing (40) a semiconductor substrate (112) containing a semiconductor material; Forming (42) a BEOL wiring section (114), wherein the BEOL wiring section comprises a plurality of conductive layers, an insulating material (110) and a guard ring (130), wherein the guard ring comprises a plurality of guard ring elements (131a / 131b), wherein each of the plurality of guard ring elements has an upper portion (156) and a lower portion (158), wherein the upper portion of each of the plurality of guard ring elements has a first surface (160) and a second surface (162) separated by a distance W a spaced apart from each other, wherein the first surface of the upper portion is closer to a silicon via than the second surface of the upper portion, wherein the lower portion of each of the plurality of guard ring elements has a first surface (164) and a second surface (166) spaced apart by a distance W bspaced apart from each other, wherein the first surface of the lower portion is closer to the silicon via than the second surface of the lower portion, wherein W a different from W b wherein the first surface of the upper portion and the first surface of the lower portion of one of the plurality of guard ring elements are coplanar with each other around the entire inner surface of the guard ring; and Forming (46) the silicon via (122) which is completely surrounded by an inner surface of the guard ring in the semiconductor substrate and in the BEOL wiring section, wherein the inner surface of the guard ring faces the silicon via and is spaced therefrom by a ring of insulating material (127) having a width Wr, wherein the silicon via has a diameter Da near a surface (128) of the BEOL wiring section, and wherein a ratio of Da to Wr is 3:1 to 7:

1. [8] The method of claim 7, wherein forming a silicon via comprises: Removing insulating material from the BEOL wiring section; Performing a first removal step for removing a portion of the semiconductor material of the semiconductor substrate; and Performing a second removal step to remove a remaining portion of the semiconductor material of the semiconductor substrate. [9] The method of claim 8, wherein forming a silicon via further comprises: Forming an electrically conductive silicon via in the BEOL wiring portion and the semiconductor substrate. [10] The method of claim 9, wherein the silicon via in the semiconductor substrate has a dimension D b adjacent to the BEOL wiring section and a dimension D cin the semiconductor substrate adjacent to a surface of the semiconductor substrate opposite to a surface adjacent to the BEOL wiring portion, wherein D b greater than D c is. [11] The method according to any one of claims 7 to 10, wherein at least one of the plurality of metal layers and at least a part of the guard ring of the BEOL wiring portion are formed simultaneously. [12] Method according to one of claims 8 to 11, wherein a first guard ring element has a dimension H a parallel to the first surfaces of the first guard ring element and a second guard ring element has a dimension H b parallel to the first surfaces of the second guard ring element, wherein H a by H b is different. [13] Method according to one of claims 7 to 12, wherein W a greater than W b is. [14] Device comprising: a semiconductor substrate (112) containing a semiconductor material; a BEOL wiring portion (114) on the semiconductor substrate, the BEOL wiring portion comprising a plurality of conductive layers and an insulating material (110); a silicon via (122) in the semiconductor substrate and in the BEOL wiring section, wherein the silicon via has a diameter Da near a surface (128) of the BEOL wiring section, in the semiconductor substrate a dimension D b adjacent to the BEOL wiring section and a dimension D c in the semiconductor substrate adjacent to a surface of the semiconductor substrate opposite to a surface adjacent to the BEOL wiring portion, wherein D b greater than D c is; and a guard ring (130) having an inner surface facing the silicon feedthrough and spaced therefrom by a ring of insulating material (127) having a width Wr and completely surrounding the silicon feedthrough in the BEOL wiring section, wherein a ratio of Da to Wr is 3:1 to 7:1, wherein the guard ring comprises a plurality of guard ring elements (131a / 131b), each of the plurality of guard ring elements having an upper portion (156) and a lower portion (158), the upper portion of each of the plurality of guard ring elements having a first surface (160) and a second surface (162) spaced apart by a distance W aspaced apart from each other, wherein the first surface of the upper portion is closer to the silicon via than the second surface of the upper portion, and the lower portion of each of the plurality of guard ring elements has a first surface (164) and a second surface (166) spaced apart by a distance W b spaced apart from each other, wherein the first surface of the lower portion is closer to the silicon via than the second surface of the lower portion, wherein W a by W b is different, and wherein the first surface of the upper portion and the first surface of the lower portion of one of the plurality of guard ring elements are coplanar with each other around the entire inner surface of the guard ring. [15] The apparatus of claim 14, wherein the first surfaces of one of the plurality of guard ring elements are coplanar with the first surfaces of another of the plurality of guard ring elements. [16] The device of claim 14 or 15, wherein one or more of the plurality of guard ring elements comprise Cu or Al. [17] Device according to one of claims 14 to 16, wherein W a greater than W b is. [18] The device of any of claims 14 to 17, wherein one or more of the plurality of guard ring elements are in electrical communication with electrically conductive features of the BEOL portion. [19] Device according to one of claims 14 to 18, wherein a first guard ring element has a dimension H a parallel to the first surfaces of the first guard ring element and a second guard ring element has a dimension H b parallel to the first surfaces of the second guard ring element, wherein H a by H b is different. [20] The device of any one of claims 14 to 19, wherein the first surfaces of three or more of the plurality of guard ring elements are coplanar with each other.

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