Local compound layer with device in a second dielectric material and corresponding method

Abstract

IC structure (100) comprising: a device layer (102) with a device on a substrate (108); a local interconnect layer (104) above the device layer (102), the local interconnect layer (104) comprising: a first dielectric material (128) above the substrate (108), the first dielectric material (128) having a first effective dielectric constant, and a second dielectric material (150) above the device and adjacent to the first dielectric material (128), the second dielectric material (150) having a second effective dielectric constant that is less than the first effective dielectric constant; and a metal wiring layer (106) above the local interconnect layer (104), the metal wiring layer (106) comprising: a conductor to the device and within the second dielectric material (150);a through-hole (154) over the conductor and within a section of the second dielectric material (150); and a metal wire (138) over the through-hole (154) and within a section of the first dielectric material (128) located over the second dielectric material (150), wherein the conductor electrically couples the device to a metal wire (138) over the local interconnect layer (104).

Description

Technical FieldEmbodiments of the invention relate generally to integrated circuits (ICs). More particularly, the invention relates to IC structures comprising a local interconnect (LI) layer having a device and a conductor in a second dielectric material, and to corresponding methods of making the same.BackgroundIn the microelectronic industry, as well as other industries dealing with the construction of microscopic structures, there is a constant desire to reduce the size of features and microelectronic devices and / or provide a larger amount of circuitry for a given chip size. Miniaturization generally allows for higher performance (more processing per clock cycle and less heat generation) with lower power consumption and lower cost. Current technology enables the scaling of certain micro devices such as logic gates, field effect transistors (FETs), barrier bipolar junction transistors (BJTs), and atomic level capacitors. Circuit chips with millions of such devices are common.In multi-transistor devices, such as FETs, developments in device scaling are associated with technical disadvantages resulting from the spatial proximity of the devices. One of these variables is the parasitic capacitance that arises when a transistor has an electrical capacitance between its two terminals when the device is off. Parasitic capacitances may reduce the gain of a circuit and generally reduce electrical isolation between adjacent transistors within a device layer. Conventional approaches to reducing parasitic capacitance in a transistor, such as guard rings, may not be practicable if such elements do not provide a hermetic seal over the device layer. Known dielectric materials for hermetically sealing a device may not be sufficiently thermally conductive for some technical applications, e.g., amplifiers or circuits.DE 10 2019, 218 942 A1 shows structures with air gaps in metallization planes, in which a first dielectric layer covers connections which are separated by a cutout and a second dielectric layer closes this cutout in order to encapsulate the air gap.US 2018 / 0248001 A1 describes a semiconductor structure having a segmented guard ring formed in the low-k dielectric and an edge seal leading through the low-k dielectric to the substrate.VOLKSEN, W., MILLER, R.D., DUBOIS, G., Low Dielectric Constant Materials, In: Chemical Reviews, Vol. 110, 2010, No. 1, pp. 56-110 contains information on materials having a low dielectric constant.DE 10 2019,127 070 A1 discloses an integrated memory cell having a data storage structure between a lower and an upper electrode, wherein the lower electrode is electrically coupled via lower interconnect layers and a continuous sidewall spacer runs from the data storage structure to the lower electrode.SummaryProvided is an integrated circuit (IC) structure comprising: a device layer having a device on a substrate; and a local interconnect layer over the device layer, the local interconnect layer comprising: a first dielectric material over the substrate, the first dielectric material having a first effective dielectric constant, and a second dielectric material over the device and adjacent the first dielectric material, the second dielectric material having a second effective dielectric constant less than the first effective dielectric constant.There is further provided an integrated circuit (IC) structure comprising: a device layer having a first device on a substrate and a second device on the substrate horizontally remote from the first device; and a local interconnect layer over the device layer, the local interconnect layer comprising: a first dielectric material over the first device, the first dielectric material having a first effective dielectric constant, a first contact to the first device and within the first dielectric material, a second dielectric material over the second device and adjacent to the first dielectric material, the second dielectric material having a second effective dielectric constant less than the first effective dielectric constant, and a second contact to the second device and within the second dielectric material.One aspect of the invention provides a method of manufacturing an integrated circuit (IC) structure, the method comprising: forming a first dielectric material over a first device and a second device of a device layer and along a conductor over the second device, the first dielectric material having a first effective dielectric constant; forming an opening within a portion of the first dielectric material to expose the second device, the first opening lying along the conductor; and forming a second dielectric material within the opening, along the first dielectric material and along the conductor, the second dielectric material having a second effective dielectric constant less than the first effective dielectric constant.According to the invention, there is provided an apparatus according to claim 1 and a method according to claim 10.Brief Description of the DrawingsThese and other features will be more readily understood from the following detailed description of the various aspects taken in conjunction with the accompanying drawings which illustrate various embodiments of the invention, and in which: FIG. 1 shows a cross-sectional view of a device layer and a local interconnect layer in an initial state according to embodiments of the invention. FIG. 2 shows a cross-sectional view of an opening formation within a portion of a first dielectric material according to embodiments of the invention. FIG. 3 shows a cross-sectional view of a formation of a second dielectric material according to embodiments of the invention. FIG. 4 shows a cross-sectional view of a formation of a metal wiring layer over the local interconnect layer according to embodiments of the invention. FIG. 5 shows a cross-sectional view of an IC structure with a gas dielectric region within the local interconnect layer according to embodiments of the invention. FIG. 6 shows a cross-section through an IC structure with a nitride liner between the first dielectric material and the second dielectric material according to embodiments of the invention. FIG. 7 shows a cross-sectional view of an IC structure including a portion of the second dielectric material within the device layer according to embodiments of the invention.It should be understood that the drawings of the invention are not necessarily to scale. The drawings are intended to represent only typical aspects of the invention and should therefore not be considered as limiting the scope of the invention. In the drawings, like reference numerals designate like elements among the drawings.Detailed DescriptionIn the following description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific exemplary embodiments in which the present invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present invention, and it is to be understood that other embodiments may be utilized and changes may be made without departing from the scope of the present invention. The following description is therefore merely illustrative.Embodiments of the invention provide an integrated circuit (IC) structure in which a local interconnect layer (LI) includes a device and a conductor within a second, different dielectric material. The presence of a second dielectric material may reduce parasitic capacitance between the transistors therein while in a "off" state. Other portions of the LI layer may include conventional dielectric materials over other transistors in the same device layer, e.g., to ensure hermetic sealing at other locations. Embodiments of the invention may include a device layer having multiple devices, one of which is a "first device" and another a "second device" horizontally removed from the first device. Such devices may be transistors (e.g., FETs) and / or capacitors, resistors, diodes, etc.A first dielectric material of an LI layer is over the first device and a second dielectric material of the LI is over the second device. The second dielectric material has a composition having an effective dielectric constant that is less than that of the first dielectric material. A conductor to the second device is within the second dielectric material and electrically connects the second device to a metal wiring layer over the local interconnect layer. The second dielectric material may be in the form of a dielectric pillar vertically extending through portions of the LI layer and one or more metal wiring layers thereover. In this case, the term "column" (pillar) may refer to a plurality of vertically extending bodies, including rods, rods, wafers, etc., that extend continuously or discontinuously through a defined space within the LI layer and / or the overlying metal wiring layer. In this case, the dielectric pillar may extend further across the device layer than the first dielectric material, and components such as portions of one or more devices and / or conductors may be located within the dielectric pillar. During operation, the second dielectric material located over the second device reduces parasitic capacitance over the second device while it is off. Thus, the second device or devices may be integrated into amplifiers, electrical switches, and / or similar circuits that tend to have high parasitic capacitances, and the first device may be integrated into other types of circuits.Referring to FIG. 1, embodiments of the invention provide IC structures and methods of making the IC structures. FIG. 1 illustrates a preliminary structure 100 (hereinafter simply referred to as "structure") that illustrates a partially fabricated IC having a device layer 102 and a local interconnect (LI) layer 104 over the device layer 102. A portion of a metal wiring layer 106 may be over the LI layer 104, and additional metal wiring layers may be formed over the metal wiring layer 106, as described elsewhere herein. The device layer, LI layer 104, and metal wiring layer 106 may be formed substantially in accordance with conventional methods of forming transistors and overlying conductors, such as metal wires and / or vias. Such methods are well known and, apart from various techniques of the invention, will not be described further herein. The device layer 102 of the structure 100 may be formed on a substrate 108 comprising, e.g., one or more semiconductor materials. The substrate 108 may comprise any presently known or later developed semiconductor material including, without limitation, silicon, germanium, silicon carbide, and those formed substantially from one or more III-V compound semiconductors having a composition represented by the formula Al X1 Ga X2 In X3 As Y1 P Y2 N Y3 Sb Y4, where X1, X2, X3, Y1, Y2, Y3, and Y4represent relative proportions, which are each greater than or equal to zero and X1+X2+X3+Y1+Y2+Y3+Y4=1 (where 1 is the total relative molar amount). Other suitable substrates are II-VI compound semiconductors having the composition Zn A1 Cd A2 Se B1 Te B2, wherein A1, A2, B1and B2are relative proportions each of which is greater than or equal to zero and A1+A2+B1+B2=1 (1 is a total molar amount). The entirety of the substrate 108 or a portion thereof may be strained.At various locations within the substrate 108, insulating materials may be formed to electrically separate the active structures within the device layer 102. For example, as shown in FIG. 1, a plurality of shallow trench isolation regions 110 may be formed within the substrate 108 to a predetermined depth. Any known method, such as forming trenches within the substrate 108, depositing a dielectric insulator (e.g., oxide), and polishing the deposited dielectric material, may be used to form isolation regions 110 to a predetermined depth.Embodiments of the invention may include introducing dopants into the substrate 108 at selected locations. The substrate 108 may have a low doping, e.g., by pre-doping at the time of manufacture or otherwise before the isolation regions 110 are formed therein. Optionally, the substrate 108 may be pre-doped with p-type dopants or n-type dopants. When the isolation regions 110 are present, various portions of the substrate 108 may be doped (e.g., by vertical implantation of dopant ions) to form a series of active semiconductor regions 112 in the substrate 108. The dopants used to form active semiconductor regions 112 may significantly reduce the resistivity of the semiconductor material / materials in the substrate 108 at the locations where they are introduced. Some portions of the substrate 108 and the isolation regions 110 may be covered with a layer of photoresist material (not shown) at this stage to prevent regions of the substrate 108 that are not targeted for doping from being doped. Portions of the substrate 108 below the isolation regions 110 and the active semiconductor regions 112 may remain undoped or only lightly doped and thus substantially maintain their doping as determined by the substrate 108. After the semiconductor active regions 112 are formed, the photoresist materials used to form the semiconductor active regions 112 may be removed by ashing or other method known in the art for removing photoresist stripes. In the example of forming transistors on the substrate 108, each semiconductor active region 112 may define a source or drain region of a transistor in the device layer 102.The device layer 102 may include at least active components in the form of at least a first device 122 and a second device 124 on the substrate 108 and within the device layer 102. Each of the devices 122, 124 may take the form of one or more active electrical elements, such as a field effect transistor (FET) or NPN transistor, over and / or coupled to semiconductor active regions 112 as are known in the art. The devices 122, 124 are exemplarily shown as FETs in the accompanying drawings, wherein some subcomponents are located above the semiconductor active region(s) 112, but this is not required in all cases. The first device 122 and / or the second device 124, as described herein, may take the form of a transistor or other active element that may be coupled to and / or isolated from other devices and / or elements located elsewhere within the structure 100.According to various examples, the devices 122, 124 may take the form of a bipolar junction transistor (BJT), a metal oxide semiconductor (MOS) field effect transistor (MOSFET), a lightly doped drain MOS (LDMOS), a diode, a capacitor, or any active or passive device as is known in the art. The devices 122, 124 may include, for example, one or more capacitors, resistors, inductors, diodes, etc., to implement various electrical functions in further embodiments. In any case, the devices 122, 124 may be disposed horizontally apart from each other on the substrate 108 and / or separated by one or more isolation regions 110. As used herein, the term "horizontally removed" refers to one element being horizontally offset from another and separated from the other element by at least one other intervening element. In this case, the devices 122, 124 may be horizontally spaced apart from each other because portions of the substrate 108, the isolation region(s) 110, and / or active semiconductor regions 112 horizontally separate the devices 122, 124 from each other.Embodiments of the invention may include forming the structure 100 to include the first device 122 and the second device 124 in the active layer 102, substantially in accordance with conventional methods, prior to further processing the structure 100 as described herein. Such methods may include forming the LI layer 104. The LI layer 104 of the preliminary structure 100 may include, for example, a barrier layer 126 for vertically insulating the overlying materials from the underlying device layer 102. The barrier layer 126 may comprise one or more electrically insulating materials having a particularly high etch resistance. In particular, the barrier layer 126 may be formed as an "etch stop layer" configured to prevent underlying device components from being removed or altered in subsequent processing. Barrier layer 126 may therefore include, for example, a nitrogen-doped silicon carbide (SiCN) layer or other material having similar properties. The barrier layer 126 may be formed after the formation and processing of the device layer 102 is completed. The barrier layer 126 may also be formed on the top surface and the sidewalls 126A of the first device 122 and the second device 124 when conformal deposition is used. With the barrier layer 126 in place, the further processing may form additional conductive and insulating portions of the LI layer 104 and the metal wiring layer 106.In general, etching refers to removal of material from a substrate (or structures formed on the substrate) and is often performed with patterned materials (e.g., one or more masks) such that a material can be selectively removed from certain areas of the substrate while leaving the material intact in other areas of the substrate. There are generally two categories of etching processes: (i) wet etching and (ii) dry etching. The wet etching is performed with a solvent (e.g., an acid) selected to selectively dissolve a particular material (e.g., oxide) while leaving another material (e.g., polysilicon) relatively intact. This ability to selectively etch certain materials is of fundamental importance to many semiconductor fabrication processes. Wet etching generally isotropically etches a homogeneous material (e.g., oxide), but wet etching may also anisotropically etch single crystal materials (e.g., silicon wafers). The dry etching may be performed by means of a plasma. Plasma systems can operate in different modes by adjusting the plasma parameters. In ordinary plasma etching, high-energy, neutrally charged free radicals are generated, which react on the surface of the wafer. Since neutral particles attack the wafer from all angles, this process is isotropic. In ion milling or sputter etching, the wafer is blasted with high-energy noble gas ions which approach the wafer from only one direction, which is why this process is strongly anisotropic. Reactive ion etching (RIE) operates under conditions intermediate between sputtering and plasma etching and can be used to create deep, narrow structures suitable for creating similar elements, e.g., openings at targeted locations, as described herein with respect to other drawings and more generally with respect to various elements in structure 100.The LI layer 104 may additionally include a first dielectric material 128, e.g., one or more oxide-based dielectric materials, suitable for physically and electrically separating the respective regions of the conductive material in the LI layer 104. Other types of oxide- or nitride-based dielectric materials may also be suitable to differ from other dielectric materials, as described elsewhere herein. The first dielectric material 128 may include, without limitation: silicon dioxide-based dielectrics such as SiO 2; doped oxides such as phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silicate glass (FSG), or carbonaceous oxides such as SiCOH. Additionally or alternatively, dielectric materials produced by spin-on or CVD methods can also be used. Regardless of the material(s) included therein, the first dielectric material 128 may have a first effective dielectric constant that is higher than other later formed dielectric materials within the LI layer 104. Some portions of the first dielectric material 128 may be replaced with such materials as described elsewhere herein. In an example, the first dielectric material 128 may have an effective dielectric constant between about three and four. The composition of the first dielectric material 128 may be selected to hermetically seal the first device 122 thereunder. In such an example, the first dielectric material 128 may comprise BPSG and / or similar materials and would have an effective dielectric constant of about four.Portions of the LI layer 104 may include conductors in the form of contacts 130 (e.g., four such contacts in FIG. 1 ) for electrically coupling portions of the device(s) 122, 124 to other wiring levels located over the LI layer 104. The contacts 130 may include a set of first contacts 130 ato semiconductor active regions 112 of the first device 122 and a set of second contacts 130 bto semiconductor active regions 112 of the second device 124. The contacts 130 may comprise any conductive substance known or later developed that is capable of forming a conductive path between a plurality of electrically active elements. As examples, the contacts 130 may include any and / or all conductive materials such as copper (Cu), aluminum (Al), tungsten (W), cobalt (Co), titanium (Ti), etc. The first contacts 130 aand the second contacts 130 bmay therefore be structurally or indistinguishable in composition, except with respect to the device(s) 122, 124 to which they are connected. Each contact 130 may have a barrier layer 132 on its sidewalls adjacent to the dielectric material 128.The barrier coating 132 may comprise any barrier layer material known or later developed (e.g., a refractory metal coating), including, but not limited to: tantalum nitride (TaN) and tantalum; tantalum nitride, tantalum and cobalt; and magnesium (Mn), or combinations thereof. Similar coatings may also be formed on sidewalls of other conductive materials described herein. The contact(s) 130 may / may be formed, e.g., by a deposition of conductive materials in trenches in the first dielectric material 128. Such trenches within the first dielectric material 128 may be formed by forming a mask (not shown) on the first dielectric material 128 to form openings where the contact(s) 130 is / are desired. Barrier layers 132 may be formed within the first dielectric material 128 at the exposed surfaces and sidewalls within the formed openings. Optionally, portions of the barrier layer 132 may be removed (e.g., by selective etching) to expose the active semiconductor material(s) 112 thereunder to allow it / s to be silicided and / or to allow contacts 130 to be formed thereon.The vertical conductive material of the contacts 130 may be formed by, for example, depositing after the barrier layers 132 have been arranged. The first contacts 130 amay be formed together with the second contacts 130 bor separately. Forming a material by "deposition" or "deposition" may generally include any of the techniques known today or later developed that are suitable for the material to be deposited, including, but not limited to, chemical vapor deposition (CVD), low pressure CVD (LPCVD), plasma enhanced CVD (PECVD), semi-atmospheric CVD (SACVD), and high density plasma CVD (HDPCVD), rapid thermal CVD (RTCVD), ultra-high vacuum CVD (UHVCVD), reaction limited CVD (LRPCVD), metal organic CVD (MOCVD), sputter deposition, ion beam deposition, electron beam deposition, laser assisted deposition, thermal oxidation, thermal nitration, spin-on methods, physical vapor deposition (PVD), for example, Atomic layer deposition (ALD), chemical oxidation, molecular beam epitaxy (MBE), coating, evaporation.For vertically separating the LI layer 104 from the metallic wiring layers formed thereon and for providing an etch stop layer for the damascene wires formed in the layer 106, an additional barrier dielectric layer 134 may be formed on the top surfaces of the first dielectric material 128 and the contacts 130. The additional barrier layer 134 may comprise the same material as the barrier layer 126 (e.g., a nitride-based layer, an etch stop layer, etc., such as SiN, SiC, or SiCN) and / or another material having similar properties. In some cases, the additional barrier layer 134 may be omitted. In cases where an additional barrier layer 134 is formed, some portions of the metal wiring layer 106 may be formed on the additional barrier layer 134.The structure 100 may include some portions of the metal wiring layer 106 on the device layer 102 and / or the LI layer 104, while additional portions of the metal wiring layer 106 may be formed in subsequent processing stages as described herein. Thus, embodiments of the invention may be performed before, during, or after the formation of the metal wiring layer 106 on the LI layer 104. According to an example, the formation of the metal wiring layer 106 may include the formation of an inter-level dielectric (ILD) material 136) over the LI layer 104, and more particularly on an additional barrier layer 134. The ILD material 136 may have the same material composition as the first dielectric material 128, and / or may comprise any other conceivable dielectric material, such as a low dielectric constant dielectric material. The ILD material 136 may have a thickness sufficient to electrically separate conductive materials within the metal wiring layer 106 from the device layer 102 and the LI layer 104 if such conductive materials are not connected to corresponding elements in the layer(s) 102, 104. The size and composition of the ILD material 136 may also be selected to physically and electrically separate the conductive materials within the metal wiring layer 106 from the overlying conductive materials.The metallic wiring layer 106 may be formed to include additional conductive materials for connecting portions of the device layer 102 to other metallic wiring levels and / or other materials within the device layer 102. For example, the metal wiring layer 106 may include a set of metal wires 138 over the LI layer 104. The metal wires 138 may comprise tungsten (W) or, alternatively, another refractory metal and / or other currently known or later developed material suitable for use as a capacitor electrode, e.g., aluminum (Al), tantalum (Ta), silver (Ag), etc. The metal wires 138 may comprise additional portions of the barrier layer 132, and such portions may also be formed on portions of the additional barrier layer 134, the ILD material 136, etc. before forming the metal wires 138 to perform the same function as described for the contact / contacts 130. Although the metal wires 138 are exemplarily depicted below the top of the ILD material 136, the metal wire / wires 138 may / may extend laterally into or out of the plane of the cross-sectional view depicted in FIG. 1. In some cases, a diffusion barrier 140 may be formed on the metal wire(s) 138. The diffusion barrier 140 may protect the metal wire / wires 138 from diffusion of overlying metal (e.g., via) into the metal wire 138 and in some cases may also prevent vertical variation (e.g., etching) of the metal wire / wires 138 during subsequent processing. In this case, the diffusion barrier 140 may be made of cobalt tungsten phosphide (CoWP) or other diffusion inhibiting materials now known or later developed. The formation of additional wires, vias, etc. within the metallic wiring layer 106 may be performed after further processing of the layers 102, 104, 106, as described herein.Referring to FIG. 2, embodiments of the invention include removing portions of the first dielectric material 128 and second dielectric material 136 at selected locations. For example, the second device 124 may be part of a circuit where the overlying dielectric materials having a second, relatively low effective dielectric constant may improve underlying functions. In this case, portions of the first and second dielectric materials 128, 136 over the second device 124 may be selectively replaced with other, different dielectric materials. The first device 122, on the other hand, may be patterned for use with the first dielectric material 128. Embodiments of the invention may allow the first dielectric material 128 to be replaced with other materials over the second device 124, while remaining intact over the first device 122. In some embodiments, the first dielectric layer 128 is removed prior to forming the second dielectric layer 136.Methods according to the invention may include removing selected portions of the first dielectric material 128, as well as the additional barrier layer 134 and the ILD material 136 thereover, to replace them with another dielectric material. Reactive ion etching (RIE) the ILD material 138 with a mask 142 is a suitable technique to form an opening 144. The opening 144 may expose the second device 124 to the device layer 102 and thus form a free space in which a replacement dielectric may be formed for use over the second device 124. The mask 142 may be structured such that the opening 144 is at least partially overlying and thus substantially vertically aligned with the second device 124. Additionally, the mask 142 may be shaped such that the opening 144 is not formed over the first device 122. A remaining portion of the first dielectric material 128 below the metal wire(s) 138 and along the barrier layer 132 and / or the second contact(s) 130 bmay remain intact as the dielectric layer 146. The dielectric coating 146 may have a higher effective dielectric constant than subsequent dielectric materials formed in the opening 144, and may remain intact as a result of forming the opening 144 using RIE or other vertical etch technique(s). The dielectric coating 146 may be removed during the etching. In one embodiment, the dielectric coating 146 is removed by wet etching, e.g., with HF acid.FIG. 3 illustrates the fabrication of a second dielectric material, e.g., any dielectric material having a second effective dielectric constant that is less than that of the first dielectric material 128 or the first and second dielectric materials 128, 136. The second dielectric material 150 may include any of a plurality of oxide- or nitride-based dielectric materials, and in particular may include materials having an effective dielectric constant less than that of BPSG, SiO 2 and / or similar materials. Such materials may be, for example, SiCOH insulators, carbon-doped oxides, spin-on polymers and / or other materials with similar properties. In an example configuration, the second effective dielectric constant of the dielectric fill may be at most about three. The second dielectric material 150 may be formed within the opening by deposition with subsequent planarization such that the top surface of the second dielectric material 150 covers adjacent portions of the ILD material 136. The planarization of the second dielectric material 150 may be performed by chemical mechanical planarization (CMP) or other techniques (e.g., various types of controlled etching, such as reverse mask etching) to remove portions of the dielectric material to a desired depth.The second dielectric material 150 may extend vertically continuously from the second device 124 to above the diffusion barrier 140. Thus, the second dielectric material 150 may be partially within the LI layer 104 and the metal wiring layer 106 and thus horizontally adjacent to the first dielectric material 128 and the ILD material 136. Additionally, conductors such as contacts 130 (e.g., one or more second contacts 130 b) and / or metal wires 138 may be disposed within the second dielectric material 150. The second dielectric material 150 may thus take the form of a vertically extending dielectric pillar extending through the LI layer 104 and the metal wiring layer 106. When the second dielectric material 150 is in the form of a dielectric pillar, it may be horizontally adjacent to the first dielectric material 128, the barrier layer 134, and the ILD material 136. The prior selective etching of the first dielectric material 128 and the additional barrier layer 134 may allow the second dielectric material 150 to vertically extend through the LI layer 104 and the metal wiring layer 106. The additional barrier layer 134 may therefore not be present within the second dielectric material 150 and not over the second device 124.FIG. 4 illustrates the further processing to form additional portions of the metal wiring layer 106, thereby forming an IC structure 152 in accordance with embodiments of the invention. The first dielectric material 128 may have a height H 1 above the top surface J of the device layer 102 that is substantially less than the height H 2 of the second dielectric material 150 above the top surface J of the device layer 102. In some embodiments, the height H 2 may be about twice as large as the height H 1. In another example, the difference between height H 1 and height H 2 may be about one micrometer. Thus, the metallic wiring layer 106 may include portions of the second dielectric material 150, while also including an ILD material 136. The additional portions of the metallic wiring layer 106 shown in FIG. 5 may be formed after processing the second dielectric material 150 substantially in accordance with known techniques for forming such layers. For example, selected portions of the ILD material 136 and / or the second dielectric material 150 may be removed to form openings and filled with conductive material to obtain a series of vias 154.Vias 154 may be formed of any conductive material and may therefore have the same composition as contact(s) 130 and underlying metal wire(s) 138. The via(s) 154 may be formed with additional regions of the barrier layer 132 on their sidewalls, as mentioned elsewhere herein. Via(s) 154 may optionally be formed within ILD material 136 over first device 122 and within second dielectric material 150 over second device 124, before replacing portions of first dielectric material 128 and ILD material over second device 124 with second dielectric material 150.For example, further processing of the metallic wiring layer 106 may include forming a layer of additional ILD material 156 over the ILD material 136 to a desired height. Although the additional ILD material 156 is illustratively indicated as being different than the ILD material 136, the additional ILD material 156 may have the same composition as the ILD material 136. In some embodiments, there may be no visually recognizable physical interface between ILD materials 136 and 156. The thickness of the additional ILD material 156 over the ILD material 136 may be sufficient to form a set of additional metal wires 158 within the additional ILD material 156. In this case, portions of the additional ILD material 156 may be removed and replaced with additional metal wires 158 and barrier layer(s) 132 in substantially the same manner as metal wires 138 are formed within the ILD material 136. Regardless of whether additional ILD material 156 and / or additional metal wire(s) 158 is / are formed, an overlying barrier layer 160 may be formed over the top surface of the metal wiring layer 106 to physically and electrically isolate components within the metal wiring layer 106 from overlying layers or elements. The overlying barrier layer 160 may have the same composition as the barrier layer 126 and / or the additional barrier layer 134 (e.g., silicon nitride) and / or may have other insulating or etch resistant compositions (e.g., nitrogen-doped silicon carbide).FIG. 5 illustrates further embodiments of the IC structure 152 in which the second dielectric material 150 includes an air gap or region 162 with a dielectric gas. In this case, the structure and processing of the IC structure 152 may be substantially the same as other implementations described herein, except for the techniques used to form the second dielectric material 150. The dielectric gas region 162 may be formed using any presently known or later developed technique for integrating dielectric air gaps. Such techniques may include, for example, forming one or more evaporable sacrificial materials within the second dielectric material 150 and subsequently evaporating the sacrificial material / materials through pores in the second dielectric material 150. In further examples, the dielectric gas region 162 may refer to inherent porous regions when the second dielectric material 150 comprises a porous dielectric material (e.g., SiCOH).FIG. 6 illustrates further optional features of the IC structure 152 in which a set of nitride liners 164 may be formed adjacent to the second dielectric material 150. The dielectric gas region 162 is shown in dashed lines to indicate that it may also be used in other embodiments. To form nitride liners 164, portions of the barrier layer 126 over the second device 124 may be removed and subsequently replaced with nitride liners 164 at the same location before the second dielectric material 150 is formed. The nitride liners 164 may be formed by conformal deposition. In this case, portions of the nitride liner may be horizontally disposed adjacent to the first dielectric material 128, the additional barrier layer 134, and / or the ILD material 136. The formation of nitride liners 164 may help thermally and electrically isolate the second device 124 and the second dielectric material 150 from the first device 122 and the first dielectric material 128.FIG. 7 shows an IC structure 152 in which an alternative configuration of the second dielectric material 150 vertically protrudes into the device layer 102. The dielectric gas region 162 and the nitride liners 164 are shown in dashed lines in FIG. 7 to indicate that such elements may be optionally used in such an implementation. In this case, portions of the isolation region(s) 110 and / or the substrate 108 may be removed to form openings when portions of the first dielectric material 128 are removed from locations above the second device 122. The openings may then be filled with the second dielectric material 150, as described elsewhere herein. Thus, the second dielectric material 150 may optionally include a first portion 150 awithin the device layer 102 and below a bottom surface J of the first dielectric material 128. A second portion 150 bof the second dielectric material may be horizontally adjacent to the first dielectric material 128, and may optionally be horizontally separated from the first dielectric material 128 by a nitride coating 164, as described herein. For example, the presence of the first portion 150 aalong the second device 124 enables a greater thermal conductivity near the second device 124 in cases where the second dielectric material 150 has a higher thermal conductivity than the first dielectric material 128. Higher thermal conductivity may be advantageous, e.g., when the second device 124 is part of a power boost circuit.Embodiments of the invention provide various technical and commercial advantages and some examples of such advantages are discussed herein. Embodiments of the invention allow conventional dielectric materials to hermetically seal selected active components in the device layer 102 (e.g., the first device 122), while other active components (e.g., the second device 124) may be surrounded by different dielectric materials having a lower dielectric constant and / or a higher thermal conductivity. The possibility of forming the second dielectric material 150 before or during the production of the metallic wiring layer 106 makes it possible to integrate a plurality of dielectric materials 128, 150 in a production process. Moreover, some portions of the first dielectric material 128 may be intentionally left intact along the contact(s) 130 as dielectric liner(s) 146 to provide greater electrical isolation at some locations despite the presence of the second dielectric material / materials 150 having a lower effective dielectric constant. These and other technical aspects of the present invention enable different types of devices with different technical requirements to be formed in close proximity on a single substrate, e.g., low noise power amplifiers and / or circuits may be formed in the vicinity of other types of devices.The method described above is used in the production of integrated circuit chips. The resulting integrated circuit chips may be sold by the manufacturer in the form of raw wafers (i.e., as a single wafer with multiple unpackaged chips), as a bare chip, or in packaged form. In the latter case, the chip is mounted in a single chip package (e.g., a plastic carrier with terminals attached to a motherboard or other parent carrier) or in a multichip package (e.g., a ceramic carrier with surface interconnections and / or buried interconnections). In either case, the chip is then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The final product can be any product that includes integrated circuit chips, ranging from toys and other simple applications to sophisticated computer products having a display, keyboard or other input device, and a central processor.The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a," "an" and "the" also include the plural forms, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of particular features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. "Optional" means that the event or circumstance described below may or may not occur and that the description includes cases where the event occurs and cases where it does not occur.Approximation formulations as used herein in the specification and claims may be used to modify any quantitative representation that may vary permissibly without resulting in a change in the basic function to which it relates. Accordingly, a value modified by one or more terms such as "about", "about", and "substantially" is not limited to the exact value indicated. At least in some cases, the approximate formulation may correspond to the accuracy of an instrument for measuring the value. Here and throughout the specification and claims, range boundaries may be combined and / or interchanged; such ranges are identified and include all subareas included therein unless the context or language indicates otherwise. The term "about" applied to a particular value of a range refers to both values and, unless otherwise dependent on the accuracy of the measurement device, may mean + / - 10% of the stated value / values.The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed.

Claims

An IC structure (100) comprising: a device layer (102) having a device on a substrate (108); a local interconnect layer (104) over the device layer (102), the local interconnect layer (104) comprising: a first dielectric material (128) over the substrate (108), the first dielectric material (128) having a first effective dielectric constant, and a second dielectric material (150) over the device and adjacent the first dielectric material (128), the second dielectric material (150) having a second effective dielectric constant less than the first effective dielectric constant; and a metal wiring layer (106) over the local interconnect layer (104), the metal wiring layer (106) comprising: a conductor to the device and within the second dielectric material (150); a via (154) over the conductor and within a portion of the second dielectric material (150); and a metal wire (138) over the via (154) and within a portion of the first dielectric material (128) located over the second dielectric material (150), the conductor electrically coupling the device to a metal wire (138) over the local interconnect layer (104).The IC structure (100, 152) of claim 1, further comprising a dielectric coating (146) horizontally between the conductor and the second dielectric material (150), wherein the dielectric coating (146) and the first dielectric material (128) have the same material composition.The IC structure (100, 152) of claim 1, wherein the second effective dielectric constant is about three.The IC structure (100, 152) of claim 3, wherein the first effective dielectric constant is between about three and about four.The IC structure (100, 152) of claim 1, further comprising a diffusion barrier (140) on the conductor, and within the second dielectric material (150).The IC structure (100, 152) of claim 1, further comprising a region of dielectric gas (162) within the second dielectric material (150).The IC structure (100, 152) of claim 1, further comprising a nitride liner horizontally between the first dielectric material (128) and the second dielectric material (150).The IC structure (100, 152) of claim 1, wherein the second dielectric material (150) comprises: a first portion (150a) within the device layer (102) and below a bottom surface of the first dielectric material (128); and a second portion (150b) horizontally adjacent to the first dielectric material (128).The IC structure (100, 152) of claim 1, wherein a height of the second dielectric material (150) above the device is greater than a height of the first dielectric material (128) above the substrate (108).A method of forming an IC structure (100), the method comprising: forming a first dielectric material (128) over a first device (122) and a second device (124) of a device layer (102) and along a conductor over the second device (124), the first dielectric material (128) having a first effective dielectric constant; forming an opening (144) within a portion of the first dielectric material (128) to expose the second device (124), the first opening (144) lying along the conductor; and forming a second dielectric material (150) within the opening (144), along the first dielectric material (128), and along the conductor, the second dielectric material (150) having a second effective dielectric constant less than the first effective dielectric constant.The method of claim 10, further comprising forming a region of dielectric gas (162) within the second dielectric material (150).The method of claim 10, further comprising forming a nitride coating horizontally between the first dielectric material (128) and the second dielectric material (150).The method of claim 10, wherein forming the first dielectric material (128) hermetically seals the first device (122).The method of claim 10, wherein forming the second dielectric material (150) within the opening (144) comprises forming the second dielectric material (150) to have a height above the second device (124) that is greater than the height of the first dielectric material (128) above the first device (122).

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