Ferroelectric double-gate field defect transmitter and method for its manufacture

Abstract

Semiconductor structure with: a first gate electrode (120); a first ferroelectric material layer (140) over the first gate electrode (120); a semiconductor channel layer (150) above the first ferroelectric material layer (140); Source and drain electrodes that contact the semiconductor channel layer (150); a second ferroelectric material layer (240) above the semiconductor channel layer (150); and a second gate electrode (220) above the second ferroelectric material layer (240), wherein the source and drain electrodes have the following: upper source and drain electrodes (314, 315) contacting a top surface of the semiconductor channel layer (150); and lower source and drain electrodes (304, 305) that contact a bottom of the semiconductor channel layer (150).

Claims

[1] Semiconductor structure with: a first gate electrode (120); a first ferroelectric material layer (140) over the first gate electrode (120); a semiconductor channel layer (150) over the first ferroelectric material layer (140); Source and drain electrodes contacting the semiconductor channel layer (150); a second ferroelectric material layer (240) over the semiconductor channel layer (150); and a second gate electrode (220) over the second ferroelectric material layer (240), wherein the source and drain electrodes comprise: upper source and drain electrodes (314, 315) contacting a top surface of the semiconductor channel layer (150); and lower source and drain electrodes (304, 305) contacting a bottom side of the semiconductor channel layer (150). [2] A semiconductor structure according to claim 1, wherein: the upper source electrode extends through the second ferroelectric material layer (240) and contacts a top surface of the semiconductor channel layer (150); and the upper drain electrode extends through the second ferroelectric material layer (240) and contacts the top of the semiconductor channel layer (150). [3] A semiconductor structure according to claim 1 or 2, wherein the upper source electrode (314) and the upper drain electrode (315) are each laterally enclosed by a dielectric spacer material layer (325). [4] A semiconductor structure according to any one of the preceding claims, further comprising: a first dielectric material layer disposed beneath the first ferroelectric material layer (140) and laterally enclosing the first gate electrode (120); and a second dielectric material layer disposed over the second ferroelectric material layer (240) and laterally enclosing the second gate electrode (220), the upper source electrode (314) and the upper drain electrode (315) extending through the second dielectric material layer. [5] A semiconductor structure according to claim 4, wherein: the lower source electrode extends from the first dielectric material layer through the first ferroelectric material layer (140) and contacts a bottom surface of the semiconductor channel layer (150); and the lower drain electrode extends from the first dielectric material layer through the first ferroelectric material layer (140) and contacts the underside of the semiconductor channel layer (150). [6] A semiconductor structure according to claim 5, wherein the lower source electrode (304) and the lower drain electrode (305) are each laterally enclosed by a further dielectric spacer material layer (325). [7] Semiconductor structure according to one of the preceding claims, wherein the semiconductor channel layer (150) comprises an oxide semiconductor material having the formula M x M' y Zn z O, where 0 < (x, y, z) < 1, M is a first metal selected from the group consisting of indium and tin or a combination thereof, and M' is a second metal selected from the group consisting of gallium, hafnium, zirconium, titanium, aluminum, strontium, barium, scandium, magnesium, lanthanum, gadolinium, or a combination thereof. [8] A semiconductor structure according to any one of the preceding claims, wherein the first ferroelectric material layer (140) and the second ferroelectric material layer (240) comprise hafnium oxide-based ferroelectric materials. [9] Semiconductor structure according to one of the preceding claims, wherein a first seed layer (135) and / or a stress layer (130) are arranged between the first gate electrode (120) and a bottom side of the first ferroelectric material layer (140). [10] Semiconductor structure according to one of the preceding claims, wherein a second seed layer and / or an insulating layer (145) are arranged between a top side of the first ferroelectric material layer (140) and a bottom side of the semiconductor channel layer (150), and an insulating layer (145) and / or a third seed layer are arranged between a top side of the semiconductor channel layer (150) and a bottom side of the second ferroelectric material layer (240). [11] A semiconductor structure according to any one of the preceding claims, further comprising a further seed layer disposed between a top surface of the second ferroelectric material layer (240) and a bottom surface of the second gate electrode (220). [12] A semiconductor structure according to any one of the preceding claims, wherein in a common gate control mode, the first gate electrode (120) and the second gate electrode (220) are connected to a common voltage. [13] A semiconductor structure according to any one of the preceding claims, wherein in a separate gate control mode, the first gate electrode (120) and the second gate electrode (220) are connected to different voltages. [14] Semiconductor structure with: a gate electrode (120, 220); a semiconductor channel layer (150), wherein the semiconductor channel layer comprises: a first alternating stack (151) of first partial layers (152) and second partial layers (154), wherein the first partial layers (152) have a different composition than the second partial layers (154), a third sub-layer (156) above the first alternating stack (151) of first sub-layers (152) and second sub-layers (154), wherein the third sub-layer (156) has a different composition than the first sub-layers (152) and the second sub-layers (154), and a second alternating stack (153) comprising the first sub-layers (152) and the second sub-layers (154) above the third sub-layer (156), wherein each of the first sub-layers (152) of the first alternating stack (151) and the second alternating stack (153) comprises a combination of a first metal oxide material MO x and a second metal oxide material M'O xand each second sub-layer (154) of the first alternating stack (151) and the second alternating stack contains zinc oxide and the third sub-layer (156) comprises a combination of a first metal oxide material MO x , a second metal oxide material M'Ox and zinc oxide, wherein M is a first metal selected from the group consisting of indium and tin or a combination thereof and M' is a second metal selected from the group consisting of gallium, hafnium, zirconium, titanium, aluminum, strontium, barium, scandium, magnesium, lanthanum, gadolinium or a combination; a ferroelectric material layer (140, 240) disposed between the gate electrode (120, 220) and a surface of the semiconductor channel layer (150); and Source and drain electrodes contacting the semiconductor channel layer (150). [15] Semiconductor structure according to claim 14, wherein a lowermost sublayer of the semiconductor channel layer (150) is a first sublayer (152) of the first alternating stack (151), an uppermost sublayer of the semiconductor channel layer (150) is a first sublayer (152) of the second alternating stack (153) comprising first sublayers (152) and second sublayers (154), and the third sub-layer (156) is contacted by a second sub-layer (154) of the second interchangeable stack (153) on an upper side of the third sub-layer (156) and is contacted by a second sub-layer (154) of the first interchangeable stack (151) on an underside of the third sub-layer (156). [16] The semiconductor structure of claim 14 or 15, wherein the gate electrode (120, 220) is a first gate electrode (120) and the ferroelectric material layer (140, 240) is a first ferroelectric material layer (140) disposed between the first gate electrode (120) and a first surface of the semiconductor channel layer (150), the semiconductor structure further comprising: a second gate electrode (220); and a second ferroelectric material layer (240) disposed between the second gate electrode (220) and a second surface of the semiconductor channel layer (150). [17] A method for producing a semiconductor structure comprising the following steps: Producing a first gate electrode (120); Forming a first ferroelectric material layer (140) over the first gate electrode (120); forming a semiconductor channel layer (150) over the first ferroelectric material layer (140); Forming source and drain electrodes to contact the semiconductor channel layer (150); forming a second ferroelectric material layer (240) over the semiconductor channel layer (150); and Forming a second gate electrode (220) over the second ferroelectric material layer (240), wherein forming source and drain electrodes in contact with the semiconductor channel layer comprises: Forming upper source and drain electrodes so that they contact a top surface of the semiconductor channel layer (150); and Forming lower source and drain electrodes to contact a bottom surface of the semiconductor channel layer (150). [18] The method of claim 17, further comprising: Forming dielectric spacer material layers (325) to laterally enclose at least one of the upper source and drain electrodes and the lower source and drain electrodes. [19] The method of claim 17 or 18, wherein forming the semiconductor channel layer comprises: Producing a first alternating stack (151) of first partial layers (152) and second partial layers (154), which comprise a group of first partial layers (152), each comprising a combination of a first metal oxide material MO x and a second metal oxide material M'O x and a group of second sub-layers (154) each containing zinc oxide; Producing a third sub-layer (156) over the first exchange stack (151), wherein the third sub-layer (156) comprises a combination of a first metal oxide material MO x , a second metal oxide material M'O xand zinc oxide; and Producing, over the third sub-layer (156), a second alternating stack (153) of first sub-layers (152) and second sub-layers (154), which comprise a group of first sub-layers (152), each comprising a combination of a first metal oxide material MO x and a second metal oxide material M'O x and a group of second sub-layers (154) each containing zinc oxide, wherein M is a first metal selected from the group consisting of indium and tin or a combination thereof, and M' is a second metal selected from the group consisting of gallium, hafnium, zirconium, titanium, aluminum, strontium, barium, scandium, magnesium, lanthanum, gadolinium, or a combination.

Images