METHOD FOR PRODUCEING A DIELECTRIC PROTECTION LAYER IN A MIDDLE-OF-THE-LINE INTERCONNECT STRUCTURE

Abstract

Method for manufacturing an integrated chip comprising the following steps: Fabricating a transistor structure (101) over a substrate (102), wherein the transistor structure (101) has a pair of source / drain regions (104) and a gate electrode (108) between the source / drain regions (104); Creating a lower ILD layer (117) over the pair of source / drain regions (104) and around the gate electrode (108); Creating a gate capping layer (114) over the gate electrode (108); and Performing a selective etching and deposition process to selectively deposit a dielectric protective layer (1002) onto the gate capping layer (114) and, in the process, creating a contact opening (1004) in the lower ILD layer (117); and Establishing a lower source / drain contact (116) in the contact opening (1004).

Description

BACKGROUND

[0001] In the fabrication of integrated circuits (ICs), devices are manufactured on a wafer and connected by conductive interconnect layers. These conductive interconnect layers can be fabricated during so-called middle-of-the-line (MOL) or back-end-of-the-line (BEOL) processes. MOL and BEOL processes are similar in that both involve creating openings in a dielectric layer (e.g., contact holes, grooves, or vias) and then filling these openings with a conductive material.A MOL process differs from a BEOL process in that a MOL process is typically performed earlier in the manufacturing process and may refer to the process of creating contacts directly on or near device structures, such as a gate electrode or a source / drain region; whereas a BEOL process is typically performed later in the manufacturing process and may refer to the process of creating successive metallization layers and vias over the contacts formed by the MOL process.

[0002] US 2019 / 0295889A1 discloses a semiconductor device and a method for manufacturing the semiconductor. The semiconductor device comprises a substrate, a gate electrode on the substrate, a first spacer on a side wall of the gate electrode, a conductive contact on a side wall of the first spacer extending beyond an upper surface of the gate electrode, a trench defined by the upper surface of the gate electrode, an upper surface of the first spacer, and side walls of the contact, an etch stop layer extending along at least portions of the side walls of the trench and a lower surface of the trench, and a covering pattern on the etch stop layer for filling the trench.

[0003] The invention is defined in the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Aspects of the present invention are best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various elements are not shown to scale. In fact, the dimensions of the various elements may have been arbitrarily enlarged or reduced for the sake of clarity. Fig. Figure 1 shows a sectional view of some embodiments of an integrated chip with a gate capping layer over a gate electrode. The Fig. Figures 2A-2C and 3A-3B show various sectional views of some further embodiments of an integrated chip with a gate capping layer over a gate electrode. Fig. Figure 4 shows a perspective view of some embodiments of an integrated chip with a gate capping layer over a gate electrode. The Fig. Figures 5-14 show various sectional views of some embodiments of a method according to the invention for manufacturing an integrated chip with a gate capping layer over a gate electrode. The Fig. Figures 15-17 show various sectional views of some embodiments of a second method for manufacturing an integrated chip with a gate capping layer over a gate electrode. The Fig. Figures 18-22B show various sectional views of some further alternative embodiments of the second method. Fig. Figure 23 shows a flowchart of some embodiments of a method for manufacturing an integrated chip with a gate capping layer over a gate electrode. DETAILED DESCRIPTION

[0005] The following description provides many different embodiments or examples for implementing various elements of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present invention. For example, the fabrication of a first element above or on top of a second element in the following description may include embodiments in which the first and second elements are fabricated in direct contact, and it may also include embodiments in which additional elements can be fabricated between the first and second elements, such that the first and second elements are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in the various examples in the present invention.This repetition serves the purpose of simplicity and clarity and does not in itself prescribe any relationship between the various designs and / or configurations discussed.

[0006] Furthermore, to simplify the description of the relationship of an element or structure to one or more other elements or structures depicted in the figures, spatially relative terms such as "below," "under," "lower," "above," "upper," and the like may be used. These spatially relative terms are intended to cover orientations of the device during use or operation in addition to the orientation shown in the figures. The device may be oriented differently (rotated by 90 degrees or in other orientations), and the spatially relative descriptors used here can be interpreted similarly.

[0007] Integrated chips can incorporate a number of semiconductor devices (e.g., transistors) arranged on and / or within a substrate. A middle-of-the-line interconnect (MOL) structure may be placed on top of the substrate. The MOL interconnect structure includes conductive contacts, interconnect vias, and metal traces, which play a vital role in the semiconductor device and circuit performance. The integrated chip comprises a transistor structure arranged on top of a substrate, featuring a source / drain pair on the substrate and a gate electrode located between the source / drain pair. A lower interlevel dielectric (ILD) layer is placed over the source / drain pair and surrounds the gate electrode. The gate electrode may be recessed relative to the top surface of the lower ILD layer.Furthermore, a gate capping layer can be arranged on the gate electrode. By omitting the gate electrode and implementing the gate capping layer, the gate electrode is insulated and protected from adjacent conductive structural elements, and consequently, leakage loss problems can be reduced or eliminated. Additionally, the MOL interconnect structure includes conductive contacts located above the source / drain pair on opposite sides of the gate electrode. As device structural elements are subject to continuous miniaturization, the distance between different conductive contacts and interconnect structural elements decreases, and leakage currents with parasitic capacitance become a significant limiting factor for device performance.It is desirable to reduce or prevent leakage currents between contacts and other conductive structural elements, while limiting the increase in resistance and capacitance.

[0008] One challenge with the aforementioned integrated chip is the fabrication of conductive contacts without compromising the device's performance and / or lifetime. For example, during the fabrication of the MOL interconnect structure, an etching process is performed on the lower ILD layer to create conductive contact orifices and expose the top surface of the source / drain regions. A conductive material is then deposited over these regions and within the conductive contact orifices. A planarization process is subsequently performed on the conductive material until the top surface of the gate capping layer is reached, thereby creating multiple lower source / drain contacts. However, the etching process may involve treating the lower ILD and gate capping layers with one or more fluorine-based etchants.The use of one or more fluorine-based etchants can remove portions of the gate capping layer, thereby reducing its thickness and / or rounding its corners. This can lead to the formation of volatile byproducts (e.g., silicon tetrafluoride) on the gate capping layer and / or degrading the interfaces within the gate capping layer, thus reducing the structural integrity and / or lifetime of the integrated chip. Furthermore, the rounded corners of the gate capping layer can result in reduced spacing between adjacent contacts, increasing parasitic capacitance and / or leakage currents in the MOL interconnect structure. This can partially degrade the performance of the integrated chip.

[0009] Accordingly, the present invention relates to an integrated chip with an improved MOL interconnect structure and corresponding fabrication methods for improving parasitic capacitance and increasing structural integrity. Consequently, the reliability and performance of the device are improved. The integrated chip comprises a transistor structure arranged over a substrate and having a source / drain pair located on the substrate and a gate electrode between the source / drain regions. A lower interlevel dielectric layer (ILD layer) is arranged over the source / drain pair and surrounds the gate electrode. A gate capping layer is arranged on the gate electrode. Furthermore, source / drain contacts are arranged over the source / drain pair and on opposite side walls of the gate electrode.During the fabrication of the source / drain contacts, a selective etching and deposition process can be performed on the lower ILD layer and the gate capping layer to create contact orifices in the lower ILD layer and across the source / drain regions. The selective etching and deposition process is configured to selectively fabricate a dielectric protective layer along one top surface of the gate capping layer, while simultaneously selectively etching the lower ILD layer and defining the contact orifices. The conductive contacts are then fabricated within these orifices.The dielectric protective layer is configured to protect the gate capping layer while the lower ILD layer is etched and the contact orifices are formed. This reduces and / or prevents the formation of volatile byproducts, reduction in the thickness of the gate capping layer, and rounding of the gate capping layer corners. As a result, parasitic capacitance between adjacent contacts and damage to the gate capping layer are reduced, thereby improving the performance and structural integrity of the integrated chip.

[0010] Fig. Figure 1 shows a sectional view of some embodiments of an integrated chip 100 with a gate capping layer 114 located over a gate electrode 108.

[0011] In some embodiments, the integrated chip 100 comprises a transistor structure 101 arranged on / in a substrate 102. In various embodiments, the substrate 102 can be, for example, solid silicon, any type of semiconductor substrate (e.g., silicon, SiGe, etc.), a silicon-on-insulator (SOI) substrate, another suitable substrate material, and / or one or more dies on a wafer, as well as any other type of semiconductor layers, epitaxial layers, or dielectric layers associated with it or comprising them. The transistor structure 101 can be a logic device comprising a gate electrode 108 separated from the substrate 102 by a dielectric gate layer 106. A pair of source / drain regions 104 is arranged in and / or on the substrate 102 on opposite sides of the gate electrode 108.Transistor structure 101 can be a planar single-gate transistor device as well as a multi-gate transistor device, such as a fin field-effect transistor (FinFET). Furthermore, other devices, such as gate-all-around devices (GAA devices), omega-gate devices, partially depleted SOI devices (PD-SOI devices), fully depleted SOI devices (FD-SOI devices), or other suitable devices, can also be transistor structure 101.

[0012] In various embodiments, conductive contacts are connected to the gate electrode 108, the source / drain regions 104, the body contact regions (not shown), or other regions of the transistor structure 101. In various embodiments, the conductive contacts are part of a middle-of-the-line (MOL) structure located above the substrate 102 and may comprise a plurality of upper conductive contacts 120 and a plurality of lower source / drain contacts 116. In some embodiments, each conductive contact may have a lower contact structure 122 enclosed by a lower inter-level dielectric (ILD) layer 117, and / or an upper contact structure 124 enclosed by an upper ILD layer 118. The upper contact structure 124 is located above the lower contact structure 122.For example, at least a portion of the upper conductive contacts 120 can be part of the upper contact structure 124, and the lower source / drain contacts 116 can be part of the lower contact structure 122. In various embodiments, the upper conductive contacts 120 and the lower source / drain contacts 116 can be, for example, tungsten, copper, aluminum, ruthenium, titanium, tantalum, titanium nitride, tantalum nitride, another conductive material, or a combination thereof. Furthermore, a lower etch stop layer 110 can be arranged along and cover the sidewalls of the lower ILD layer 117.

[0013] In various embodiments, a sidewall spacer 112 is arranged along the gate electrode 108. The sidewall spacer 112 extends along opposite sidewalls of the gate electrode 108 and opposite sidewalls of the dielectric gate layer 106. Furthermore, the sidewall spacer 112 is arranged along the lower etch stop layer 110. In some embodiments, an upper surface of the sidewall spacer 112 is arranged above an upper surface of the gate electrode 108. Furthermore, the upper surface of the sidewall spacer 112 can be aligned with or coplanar to an upper surface of the lower etch stop layer 110. In further embodiments, the lower etch stop layer 110 can be, for example, silicon nitride, a low-k dielectric material, silicon, silicon carbonitride, another suitable dielectric material, or a combination thereof.In further embodiments, the side wall spacer 112 can, for example, be or comprise silicon nitride, silicon carbide, silicon oxide nitride, silicon oxide carbide, another suitable material or a combination thereof.

[0014] In various embodiments, the gate electrode 108 is recessed relative to a top surface of the lower ILD layer 117. A gate capping layer 114 is arranged on the gate electrode 108. A top surface of the gate capping layer 114 can be aligned with or coplanar to the top surface of the lower ILD layer 117. In further embodiments, the gate capping layer 114 can comprise a non-oxide dielectric material. For example, the gate capping layer 114 can be or comprise silicon, silicon nitride, silicon carbonitride, a non-oxide dielectric material, another suitable dielectric material, or a combination thereof. In still further embodiments, the lower etch stop layer 110 and the gate capping layer 114 can comprise the same material (e.g., silicon nitride, silicon, silicon carbonitride, or the like).The gate capping layer 114 extends continuously from the top of the lower etch stop layer 110 and the top of the side wall spacer 112 along a side wall of the side wall spacer 112 to the top of the gate electrode 108. In further embodiments, the gate capping layer 114 is T-shaped, such that a lower part of the gate capping layer 114 is enclosed by the side wall spacer 112 and an upper part of the gate capping layer 114 is located directly above the lower etch stop layer 110 and the side wall spacer 112.

[0015] In some embodiments, the lower contact structure 122 comprises the plurality of lower source / drain contacts 116 located above each source / drain region 104. In various embodiments, the lower source / drain contacts 116 each fill a slot between the sidewalls of the lower etch stop layer 110 and the gate capping layer 114 and contact these sidewalls directly. In still other embodiments, the top surfaces of the lower source / drain contacts 116 can be aligned with or coplanar to the top surface of the gate capping layer 114 and / or the top surface of the lower ILD layer 117. In further embodiments, the plurality of upper conductive contacts 120 are located directly above the lower source / drain contacts 116 and the gate electrode 108 of the transistor structure 101 and are electrically connected to them.The upper conductive contact 120, located directly above the gate electrode 108 of the transistor structure 101, extends continuously through the upper ILD layer 118 and the gate capping layer 114 to contact the gate electrode 108.

[0016] In various embodiments, a selective etching and deposition process is performed on the lower ILD layer 117 and the gate capping layer 114 during the fabrication of the lower contact structure 122 to form openings in the lower ILD layer 117 directly above corresponding source / drain regions 104. The selective etching and deposition process is configured to selectively fabricate a dielectric protective layer (not shown) along the top surface of the gate capping layer 114 while simultaneously selectively etching the lower ILD layer 117. The lower source / drain contacts 116 are then fabricated in the openings such that the top surfaces of the lower source / drain contacts 116 are aligned with or coplanar to the top surface of the gate capping layer 114.By creating the dielectric protective layer along the top surface of the gate capping layer 114 and simultaneously etching the lower ILD layer 117, damage to the gate capping layer 114 can be reduced or prevented. For example, the formation of volatile byproducts from etchants used during the selective etching and deposition process along the top surface of the gate capping layer 114 is reduced or prevented, thereby increasing the structural integrity and lifetime of the integrated chip 100. Furthermore, the dielectric protective layer prevents the corners of the gate capping layer 114 from rounding, ensuring that the upper opposing side walls of the gate capping layer 114 meet the top surface of the gate capping layer 114 at a right angle.This contributes in part to the fact that the lower source / drain contacts 116 each have a rectangular shape, thereby increasing the distance between adjacent lower source / drain contacts 116 and reducing parasitic capacitance in the lower and upper contact structures 122, 124. Furthermore, by preventing damage to the gate capping layer 114 during the fabrication of the lower source / drain contacts 116, the ability of the gate capping layer 114 to reduce or prevent damage to the gate electrode 108 during subsequent fabrication steps and / or during operation of the integrated chip 100 is enhanced. Consequently, the selective etching and deposition process improves the performance and structural integrity of the integrated chip 100.

[0017] Fig. Figure 2A shows a sectional view of some embodiments of an integrated chip 200a corresponding to some alternative embodiments of the integrated chip 100. Fig. 1, wherein the upper conductive contacts 120 comprise a cover layer 202a and a conductive body 202b. The cover layer 202a surrounds the conductive body 202b laterally and extends along a bottom surface of the conductive body 202b. In various embodiments, the cover layer 202a may have, or be configured as, a diffusion barrier layer or an adhesive layer. Furthermore, the cover layer 202a may be, for example, titanium, tantalum, titanium nitride, tantalum nitride, another conductive material, or a combination thereof. The conductive body 202b may be, for example, aluminum, copper, ruthenium, tungsten, another conductive material, or a combination thereof.

[0018] In some embodiments, the gate capping layer 114 comprises a first gate capping structure 114a laterally adjacent to a second gate capping structure 114b, wherein the first and second gate capping structures 114a, 114b are located directly above a corresponding gate electrode 108. In various embodiments, the width w1 of the first gate capping structure 114a is approximately 45 nanometers (nm), in a range of approximately 30 to 60 nm, or it has another suitable value. In various embodiments, the widths of each gate capping structure located directly above a corresponding gate electrode 108 are equal to each other and can each be approximately 45 nm, in a range of approximately 30 to 60 nm, or have another suitable value.In some embodiments, a vertical distance v1 between a top surface of the source / drain regions 104 and a top surface of the gate capping layer 114 is approximately 120 nm, in a range of approximately 80 to 160 nm, or it has another suitable value. In further embodiments, a lateral distance d1 between adjacent gate capping structures of the gate capping layer 114 is approximately 15 nm, in a range of approximately 10 to 20 nm, or it has another suitable value. In some embodiments, the lateral distance d1 can correspond to the width of a corresponding lower source / drain contact 116 arranged between the adjacent gate capping structures of the gate capping layer 114. For example, the lateral distance d1 can be equal to the width of the lower source / drain contact 116, which is located between the first gate capping structure 114a and the second gate capping structure 114b.

[0019] Fig. Figure 2B shows a sectional view of some embodiments of an integrated chip 200b according to some alternative embodiments of the integrated chip 100. Fig. 1, wherein an upper etch stop layer 204 is arranged between the lower ILD layer 117 and the upper ILD layer 118. The upper etch stop layer 204 can, for example, be or comprise silicon nitride, silicon carbide, silicon carbonitride, another suitable dielectric material, or a combination thereof. In some embodiments, the upper etch stop layer 204 can comprise the same material as the lower etch stop layer 110 and / or the same material as the gate capping layer 114. Furthermore, the plurality of upper conductive contacts 120 can comprise a body contact 206. The body contact 206 comprises a first part 206a, which is electrically connected to one of the source / drain regions 104 by a corresponding lower source / drain contact 116, and a second part 206b, which is electrically connected to the gate electrode 108.Consequently, the body contact 206 is configured to electrically connect the gate electrode 108 directly to an adjacent source / drain area 104.

[0020] Fig. Figure 2C shows a sectional view of some embodiments of an integrated chip 200c according to some alternative embodiments of the integrated chip 100. Fig. 1, in which a middle segment 117c of the lower ILD layer 117 is arranged directly between adjacent gate capping structures of the gate capping layer 114.

[0021] Fig. Figure 3A shows a sectional view of some embodiments of an integrated chip 300a according to some alternative embodiments of the integrated chip 100. Fig. 1, wherein each lower source / drain contact 116 has one or more protrusions that coincide with an adjacent rounded corner of the gate capping layer 114. The one or more protrusions of the lower source / drain contacts 116 are located directly above at least a portion of the gate capping layer 114.

[0022] In various embodiments, the plurality of lower source / drain contacts 116 comprises a first lower source / drain contact 116a. The first lower source / drain contact 116a has a first straight side wall 302 and a second straight side wall 304 opposite the first straight side wall 302. In various embodiments, the first and the second straight side walls 302, 304 are substantially straight and / or each perpendicular to a top surface of the substrate 102. In some embodiments, the first lower source / drain contact 116a comprises a body region 116br and one or more projections 306, 308 extending from the body region 116br to an adjacent rounded corner of the gate capping layer 114.The body region 116br is defined between the first straight side wall 302 and the second straight side wall 304 such that a width Wc of the body region 116br is defined between the first and the second straight side walls 302, 304. In various embodiments, the width Wc is approximately 15 nanometers (nm), in a range of approximately 10 to 20 nm, or it has another suitable value. In still further embodiments, the first lower source / drain contact 116a comprises a first projection 306 extending from the body region 116br in a first direction, and a second projection 308 extending from the body region 116br in a second direction opposite to the first.A first width Wp1 of the first projection 306 is defined from the body region 116br to an outermost point of the first projection 306, and a second width Wp2 of the second projection 308 is defined from the body region 116br to an outermost point of the second projection 308. In various embodiments, the first and second widths Wp1, Wp2 are each approximately 0.75 nm, in a range of approximately 0.5 to 1 nm, less than approximately 1 nm, or they have another suitable value.

[0023] Furthermore, in some embodiments, the ratio between the first width Wp1 and the width Wc (e.g., Wp1:Wc) is, for example, approximately 1:20, in a range of approximately 0.25:20 to 1:20, or it has another suitable value. In other embodiments, the ratio between the second width Wp2 and the width Wc (e.g., Wp2:Wc) is, for example, approximately 1:20, in a range of approximately 0.25:20 to 1:20, or it has another suitable value. If the ratios between the first and second widths Wp1, Wp2, and Wc (e.g., Wp1:Wc and Wp2:Wc) are relatively low (e.g., less than approximately 1:20), the distance between the lower source / drain contacts 116 and laterally adjacent upper conductive contacts 120 is increased in various embodiments. This partially reduces the parasitic capacitance in the lower and upper contact structures 122, 124, thereby increasing the performance of the integrated chip 300a.Consequently, in some embodiments, the width Wc of the body area 116br is approximately 20, 30, 40 times, or in a range of approximately 20 to 60 times, larger than the first and second widths Wp1, Wp2. If the ratios between the first and second widths Wp1, Wp2 and the width Wc are relatively high (e.g., greater than approximately 1:20), in yet other embodiments, the distance between the lower source / drain contacts 116 and laterally adjacent upper contacts 120 is reduced. This can increase the parasitic capacitance in the lower and upper contact structure 122, 124, thereby reducing the performance of the integrated chip 300a. It is understood that the aforementioned ratios, which refer to the integrated chip 300a, are not to be confused with other embodiments. Fig. 3A have been described, also for the structures of the Fig. 3B, Fig. 17 and Fig. 22B are applicable.

[0024] Fig. Figure 3B shows a sectional view of some embodiments of an integrated chip 300b according to some alternative embodiments of the integrated chip 200c. Fig. 2C, in which the upper corners of the gate capping layer 114, which are directly adjacent to a corresponding lower source / drain contact 116, are curved or rounded. In further embodiments, the upper corners of the gate capping layer 114, which contact the lower ILD layer 117, are not curved or rounded and have a rectangular shape.

[0025] Fig. Figure 4 shows a perspective view of an integrated chip 400 with a gate capping layer 114 located over a gate electrode 108.

[0026] In some embodiments, the integrated chip features 400 FinFET devices, nanowire devices, or other gate-all-around (GAA) devices. The substrate 102 can have a lower base portion and a plurality of upper pillars that are raised above the lower base portion, extend along a channel longitudinal direction, and are arranged parallel to one another. Epitaxial semiconductor layers can be arranged on the plurality of upper pillars of the substrate 102 and can have heavily doped regions on opposite sides from the source / drain regions 104 and lightly doped or undoped regions between the source / drain regions 104 as channel regions. A conductive layer can be arranged on the channel regions as the gate electrode 108 and separated from the channel regions by a gate dielectric (e.g.,The dielectric gate layer 106) may be separated and configured to control the current flow of the channel regions. The gate electrode 108 may extend along a transverse channel direction perpendicular to the longitudinal channel direction. The gate electrode 108 may extend to enclose sidewalls of the channel regions. As discussed in the preceding figures, in some embodiments the gate capping layer 114 is arranged on the gate electrode 108, with the lower source / drain contacts 116 arranged along sidewalls of the gate capping layer 114. The gate capping layer 114 may have a top surface that is aligned with or coplanar to the top surface of the lower source / drain contacts 116.In further embodiments, the majority of upper conductive contacts 120 extend through the upper ILD layer 118 and the upper etch stop layer 204 to contact an underlying lower source / drain contact 116 and / or a gate electrode 108.

[0027] The Fig. Figures 5-14 show sectional views 500-1400 of some embodiments of a method for manufacturing an integrated chip with a gate capping layer over a gate electrode according to the present invention. The sectional views 500-1400, which are shown in the Fig. Figures 5-14 are indeed described with reference to a procedure, but it should be understood that the figures shown in the Fig. The structures shown in Figures 5-14 are not limited to the procedure, but can be used as structures independently of the procedure. Fig. Although steps 5-14 are described as a series, it should be understood that the order of these steps can be changed in other embodiments and that the disclosed methods can also be used for other structures. In other embodiments, some of the illustrated and / or described steps can be omitted completely or partially.

[0028] As shown in section views 500 and 600 of the Fig. 5 and Fig. As shown in Figure 6, transistor structures 101 are fabricated over a substrate 102 and enclosed by a lower ILD layer 117. Each transistor structure 101 comprises a dielectric gate layer 106 over the substrate 102, a gate electrode 108 over the dielectric gate layer 106, and a pair of source / drain regions 104 located in or on the substrate 102 on opposite sides of the gate electrode 108 (see, for example, Figure 6). Fig. 6) are arranged. The gate electrode 108 can, for example, be or comprise polysilicon, aluminum, titanium, tungsten, another suitable conductive material, or a combination thereof. Furthermore, the dielectric gate layer 106 can, for example, be or comprise silicon dioxide, a high-k dielectric material, another suitable dielectric material, or a combination thereof.

[0029] In some embodiments, each transistor structure 101 can be fabricated by a substitute gate process. As shown, for example, in the sectional view 500 of Fig. As shown in Figure 5, dummy gate structures 502 are first fabricated and structured over the substrate 102. A sidewall spacer 112 is then fabricated along the dummy gate structures 502, covering or coating the sidewalls of the dummy gate structures 502. In various embodiments, the sidewall spacer 112 comprises silicon dioxide, silicon nitride, silicon carbide, aluminum oxide, aluminum nitride, another suitable dielectric material, or a combination thereof. In some embodiments, the sidewall spacer 112 may have several layers, such as main spacer walls, cover layers, and the like. In further embodiments, a process for fabricating the sidewall spacer 112 may include: deposition (e.g.,by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), etc.) of a dielectric material over the dummy gate structures 502 and the substrate 102; and performing an etching process on the dielectric material such that a top surface of the side wall spacer 112 is substantially aligned with or coplanar to top surfaces of the dummy gate structures 502.

[0030] In various embodiments, the source / drain regions 104 can each be a doped region arranged in the substrate 102. In these embodiments, a process for producing the source / drain regions 104 can include performing an ion implantation process according to a masking layer (the dummy gate structures 502 and / or the sidewall spacer 112 can, for example, act as a masking layer during the ion implantation process) to implant dopants into the substrate 102, thereby producing the source / drain regions 104. In further embodiments, the source / drain regions 104 can each be or comprise an epitaxial semiconductor material arranged on and / or in the substrate 102.In these embodiments, the source / drain regions 104 can be produced by epitaxial growth of silicon germanium or another suitable semiconductor material over / on the substrate 102. For example, the source / drain regions 104 can be produced by molecular beam epitaxy (MBE), vapor phase epitaxy (VPE), liquid phase epitaxy (LPE), another epitaxial process, or a combination thereof. In some alternative embodiments, the source / drain regions 104 can be deposited instead of grown, and the deposition can include, for example, a CVD process, a PVD process and ALD process, or another suitable deposition process. In some embodiments, the source / drain regions 104 can be doped (e.g.,(through an ion implantation process), so that the source / drain regions contain 104 doped silicon germanium or another suitable doped semiconductor material.

[0031] As shown in section view 600 of Fig. As shown in Figure 6, a lower etch stop layer 110 is produced, which covers the top surfaces of the substrate 102 and extends upwards along the side wall spacer 112. A dielectric layer (e.g., by CVD, PVD, ALD, etc.) is deposited over the transistor structures 101 and the lower etch stop layer 110, followed by a planarization process (e.g., chemical mechanical planarization (CMP)) to fabricate the lower ILD layer 117. The lower etch stop layer 110 can be fabricated by a deposition process such as CVD, PVD, ALD, or another suitable growth or deposition process. The lower ILD layer 117 can also be fabricated by plasma-enhanced CVD (PECVD), PVD, ALD, or another suitable growth or deposition process.The lower etch stop layer 110 and the lower ILD layer 117 can be planarized using a CMP process such that a top surface of the lower etch stop layer 110 is aligned with or coplanar to a top surface of the lower ILD layer 117. In various embodiments, the lower ILD layer 117 can be, for example, silicon dioxide, doped silicon dioxide, oxygen-doped silicon carbide, silicon oxide carbide, a low-k dielectric material, another dielectric material, or a combination thereof. Furthermore, the lower etch stop layer 110 can be, for example, a low-k dielectric material, silicon nitride, another dielectric material, or a combination thereof.

[0032] In further embodiments, the dummy gate structures 502 can be used for the replacement gate process. Fig. 5 are removed and replaced by the gate electrode 108, which is made of metal or another conductive material (e.g., polysilicon). Furthermore, the dielectric gate layer 106 can also be produced after the dummy gate structures 502 have been removed. To produce the gate electrode 108, stacks of metallic materials can be filled into gate openings, followed by a planarization process to remove excess material above the lower ILD layer 117. In some embodiments, the stacks of metallic materials can be titanium nitride, tantalum nitride, titanium aluminum, aluminum, tungsten, another suitable metallic material, or a combination thereof.

[0033] As shown in section view 700 of Fig. As shown in Figure 7, the gate electrode 108 is patterned such that a top surface of the gate electrode 108 is recessed below the top surface of the lower ILD layer 117. In some embodiments, a patterning process for the gate electrode 108 comprises: creating a masking layer 702 over the lower ILD layer 117, leaving the gate electrode 108 exposed; and performing an etching process along the masking layer 702 to recess the top surface of the gate electrode 108 to a position lower than the top surface of the lower ILD layer 117. In other embodiments, the etching process includes anisotropic etching, such as vertical dry etching, and the recessed top surface of the gate electrode 108 is substantially planar, as shown in Figure 7. Fig. Figure 7 shows the process. In further embodiments, the etching process includes isotropic etching, such as wet etching, and the recessed top surface of the gate electrode 108 can have a concave shape (not shown). In various embodiments, a removal process is carried out to remove the masking layer 702 (not shown).

[0034] As shown in section view 800 of Fig. As shown in Figure 8, a gate capping layer 114 is produced on the recessed gate electrode 108. In various embodiments, the gate capping layer 114 is configured to protect the gate electrode 108 during subsequent processing steps and can be referred to as a protective layer. In some embodiments, the gate capping layer 114 can be produced by a deposition process, such as a CVD process, a PVD process, an ALD process, or another suitable growth or deposition process. In other embodiments, a planarization process (e.g., a CMP process) is performed on the gate capping layer 114 such that a top surface of the gate capping layer is aligned with or coplanar to the top surface of the lower ILD layer 117.In various embodiments, the gate capping layer 114 can be or comprise silicon, silicon nitride, silicon carbonitride, another suitable dielectric material, or a combination thereof. In further embodiments, the gate capping layer 114 can be or comprise a non-oxide dielectric material.

[0035] As shown in section view 900 of Fig. As shown in Figure 9, an upper dielectric structure 908 is fabricated over the lower ILD layer 117 and the gate capping layer 114. In various embodiments, the upper dielectric structure 908 can be fabricated by depositing it over the lower ILD layer 117 using a CVD process, a PVD process, an ALD process, or another suitable growth or deposition process. Furthermore, after depositing the upper dielectric structure 908 over the lower ILD layer 117, a planarization process (e.g., a CMP process) can be performed on the upper dielectric structure 908, resulting in a substantially planar top surface.Furthermore, a masking structure 902 is fabricated over the upper dielectric structure 908, wherein the masking structure 902 comprises a hard masking layer 904 arranged along the upper dielectric structure 908 and a dielectric layer 906 located above the hard masking layer 904. In various embodiments, both the upper dielectric structure 908 and the lower ILD layer 117 comprise an oxide (e.g., silicon dioxide) that is different from a material of the gate capping layer 114. For example, the gate capping layer 114 comprises a non-oxide material.

[0036] As shown in section view 1000 of Fig. As shown in Figure 10, a selective etching and deposition process is carried out on the upper dielectric structure 908, the gate capping layer 114, and the lower ILD layer 117, forming source / drain contact openings 1004 over the source / drain regions 104 and selectively producing a dielectric protective layer 1002 along the top surface of the gate capping layer 114. In various embodiments, the selective etching and deposition process is configured such that the dielectric protective layer 1002 is selectively produced along the gate capping layer 114, while simultaneously etching the upper dielectric structure 908, the lower ILD layer 117, and / or the lower etch stop layer 110 to form the source / drain contact openings 1004.In various embodiments, the dielectric protective layer 1002 can be, for example, tungsten, boron nitride, molybdenum, another suitable material, or a combination thereof. In further embodiments, the selective etching and deposition process can include performing a selective plasma etching process on the upper dielectric structure 908, the lower ILD layer 117, and / or the etch stop layer 110, while simultaneously performing a selective CVD process to selectively produce the dielectric protective layer 1002 along the top surface of the gate capping layer 114.

[0037] In various embodiments, the selective etching and deposition process can be carried out in a processing chamber (not shown), wherein the substrate 102 is arranged in the processing chamber. In further embodiments, the selective etching and deposition process can include performing a selective etching process with a plasma etchant while simultaneously performing a selective deposition process (e.g., a selective CVD process). For example, the selective etching and deposition process can be carried out by simultaneously flowing the plasma etchant and a selective precursor gas in the processing chamber, wherein the plasma etchant is configured to selectively etch the lower ILD layer 117 and / or the etch stop layer 110, and the selective precursor gas is configured to selectively form the dielectric protective layer 1002 along the top surface of the gate capping layer 114.In various embodiments, the plasma etchant can be produced by a plasma source as an inductively coupled plasma (ICP), a capacitively coupled plasma (CCP), an electron cyclotron resonance plasma (ECR plasma) or the like.

[0038] In some embodiments, the selective etching and deposition process is carried out in the processing chamber at a temperature of approximately 100 degrees Celsius, within a range of approximately 0 degrees Celsius to 150 degrees Celsius, or at another suitable value, and at a pressure within a range of approximately 0.13 Pa to 133 Pa (1 millitorr and 1 torr), or at another suitable value. In various embodiments, the plasma etchant is produced by the plasma source at a power within a range of approximately 300 watts to 1,200 watts, within a range of approximately 50 watts to 2,000 watts, or at another suitable value. In still other embodiments, a bias is applied to a wafer clamping device (not shown) configured to hold the substrate 102 in the processing chamber.The pre-voltage can be greater than 0 volts, for example, in a range between approximately 0 and 500 volts, or have another suitable value. A carrier gas in the processing chamber can consist of hydrogen (H₂), nitrogen (N₂), and / or oxygen (O₂). In some embodiments, the selective etching and deposition process is carried out by simultaneously flowing the plasma etchant and the selective precursor gas into the processing chamber. For example, the plasma etchant can be introduced into the processing chamber through a first gas line, and the selective precursor gas can be introduced into the processing chamber through a second gas line, separate from the first.In some embodiments, defect problems can be reduced and / or prevented by introducing the plasma etchant and the selective precursor gas into the processing chamber through separate gas lines, because the plasma etchant and the selective precursor gas do not interact with each other in a single gas line. In still other embodiments, the inflow velocity of the plasma etchant into the processing chamber is greater than the inflow velocity of the selective precursor gas. In some embodiments, the initial inflow velocity of the plasma etchant into the processing chamber can be between approximately 10 standard cubic centimeters per minute (sccm) and approximately 200 sccm, or at another suitable value.In further embodiments, the selective precursor gas can be introduced into the processing chamber at a second inflow velocity between approximately 10 sccm and approximately 100 sccm, or at another suitable value. In still further embodiments, the carrier gas can be introduced into the processing chamber at an inflow velocity between approximately 100 sccm and approximately 1,000 sccm, or at another suitable value.

[0039] In various embodiments, the plasma etchant can be or comprise fluorocarbon (e.g., CF4), hydrocarbon fluoride (e.g., CHF3, CH2F2, CH3F), sulfur hexafluoride (e.g., SF6), chlorine (e.g., Cl2), boron trichloride (e.g., BCl3), hydrogen bromide (e.g., HBr), nitrogen trifluoride (e.g., NF3), another suitable etchant, or a combination thereof. In further embodiments, the selective precursor gas can be or comprise a metal fluoride (e.g., tungsten hexafluoride (WF6)), boron chloride (e.g., BCl3), dimethyl, trimethyl, another suitable precursor, or a combination thereof. In various embodiments, the selective precursor gas is introduced into the processing chamber with the carrier gas (e.g., hydrogen (H2) or nitrogen (N2)). In one embodiment, when the selective precursor gas is tungsten hexafluoride (e.g.,If the selective precursor gas contains WF6), the carrier gas can consist essentially of hydrogen (H2), and if the selective precursor gas contains boron chloride (e.g., BCl3), the carrier gas can consist essentially of nitrogen (N2). In some embodiments, by allowing the selective precursor gas to flow into the processing chamber, the dielectric protective layer 1002 is selectively produced along the top surface of the gate capping layer 114, while it is not produced on the lower ILD layer 117. This is partly due to the fact that the gate capping layer 114 contains a non-oxide dielectric material, while the lower ILD layer 117 contains an oxide. Therefore, the selective etching and deposition process is configured such that the dielectric protective layer 1002 is selectively produced along a non-oxide dielectric material.Furthermore, during the selective etching and deposition process, the dielectric protective layer 1002 is selectively produced along the gate capping layer 114 faster than it is removed and / or etched by the plasma etchant. Consequently, the dielectric protective layer 1002 can act as a hard mask layer during the selective etching and deposition process, preventing or reducing etching and / or damage to the gate capping layer 114 by the plasma etchant. This reduces the formation of volatile byproducts from the gate capping layer 114 and the plasma etchant, a reduction in the thickness of the gate capping layer 114, and rounding of the corners of the gate capping layer 114, thereby increasing the performance and structural integrity of the transistor structures 101.

[0040] In further embodiments, during the selective etching and deposition process, the lower etch stop layer 110 can be etched faster than the upper dielectric structure 908 and / or the lower ILD layer 117. In further embodiments, after the formation of the source / drain contact openings 1004, a removal process can be carried out to selectively remove the dielectric protective layer 1002 over the gate capping layer 114 (not shown). In various embodiments, the removal process can include a wet etching process and / or a dry etching process. For example, the removal process can include treating the dielectric protective layer 1002 with demineralized water, ammonia solution, hydrogen peroxide, another suitable chemical, or a combination thereof.In further embodiments, the removal process may also include treating the dielectric protective layer 1002 with a fluorine-based etchant or another suitable etchant.

[0041] As shown in section view 1100 of Fig. As shown in Figure 11, a conductive structure 1102 is located in the source / drain contact openings (1004 of Fig. 10) and over the source / drain regions 104. In various embodiments, the conductive structure 1102 can be, for example, tungsten, copper, ruthenium, aluminum, molybdenum, tantalum, titanium, another conductive material, or a combination thereof. In further embodiments, an adhesive and / or barrier layer (not shown) can be produced over the substrate 102 prior to the production of the conductive structure 1102, which facilitates bonding and / or prevents diffusion. In further embodiments, the conductive structure 1102 can be produced over the substrate 102 by depositing the conductive structure 1102 onto the source / drain regions 104 and the gate capping layer 114 using a CVD process, a PVD process, a sputtering process, an electroplating process, or another suitable deposition or growth process.In further embodiments, a metallization process can be carried out prior to the fabrication of the conductive structure 1102 to produce a semiconductor-metal composite film or semiconductor-metal composite layer (such as silicide, germanide, germanosilicide, etc.) at an interface between the conductive structure 1102 and the exposed part of the top of the source / drain regions 104, thereby providing a low-resistance contact (not shown).

[0042] As shown in section view 1200 of Fig. As shown in 12, a planarization process is carried out on the structure of Fig. 11, thereby defining a plurality of lower source / drain contacts 116. In various embodiments, the creation of the plurality of lower source / drain contacts 116 can be carried out as described in the Fig. The planarization process comprises the steps shown and / or described in Figures 9-12. In some embodiments, the planarization process may include a CMP process, an etching process, another suitable planarization process, or a combination thereof. In other embodiments, the planarization process is performed such that the top surface of the gate capping layer 114 is aligned with or coplanar to the top surfaces of the lower source / drain contacts 116.

[0043] As shown in section view 1300 of Fig. As shown in Figure 13, an upper ILD layer 118 is produced above the gate capping layer 114 and the plurality of lower source / drain contacts 116. In various embodiments, the upper ILD layer 118 can be or comprise tetraethyl orthosilicate oxide (TEOS oxide), undoped silicate glass, silicon dioxide, doped silicon dioxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), borosilicate glass (BSG), another suitable dielectric material, or a combination thereof. In still further embodiments, the upper ILD layer 118 can comprise the same material as the lower ILD layer 117. In some embodiments, the upper ILD layer 118 can be deposited using a CVD process, a PECVD process, a PVD process, an ALD process or another suitable deposition or growth process.

[0044] As shown in section view 1400 of Fig. As shown in Figure 14, a plurality of upper conductive contacts 120 are produced in the upper ILD layer 118 and above the plurality of lower source / drain contacts 116. In various embodiments, a process for producing the plurality of upper conductive contacts 120 may include: producing a masking layer (not shown) over the upper ILD layer 118; structuring the upper ILD layer 118 and / or the gate capping layer 114 according to the masking layer to define a plurality of contact openings (not shown); depositing (e.g., by CVD, PVD, sputtering, electroplating, etc.) a conductive material (e.g., aluminum, copper, tungsten, ruthenium, titanium nitride, tantalum nitride, another conductive material, or a combination thereof) over the substrate 102 and filling the plurality of contact openings; and carrying out a planning process (e.g.a CMP process) into the conductive material until a top surface of the upper ILD layer 118 is reached. In these embodiments, the structuring of the upper ILD layer 118 and / or the gate capping layer 114 can include performing a wet etching process, a dry etching process, another suitable etching process, or a combination thereof. By performing the selective etching and deposition process of . Fig. 10 to define the openings (1004 of Fig. 10) for the lower source / drain contacts 116, the damage to the gate capping layer 114 is reduced, thereby reducing and / or preventing damage to the gate electrode 108 during the manufacture of the upper conductive contacts 120 and / or during subsequent processing steps.

[0045] The Fig. Figures 15-17 show sectional views 1500-1700 of some embodiments of a second method for manufacturing an integrated chip with a gate capping layer over a gate electrode according to the present invention. For example, the Fig. 15-17 Alternative embodiments of steps that replace the steps in the Fig. 10-12 of the procedure of Fig. 5-14 can be carried out. Consequently, in some embodiments, the second method comprises a method that can be alternatively performed by the Fig. 5-9 up to the Fig. 15-17 and from the Fig. 17 up to the Fig. 13-14 progresses (i.e. the Fig. 10-12 are skipped).

[0046] As shown in section view 1500 of Fig. As shown in Figure 15, a selective etching and deposition process is carried out on the upper dielectric structure 908, the gate capping layer 114, and the lower ILD layer 117, thereby producing source / drain contact openings 1004 over the source / drain regions 104 and selectively producing the dielectric protective layer 1002 along the top surface of the gate capping layer 114. In various embodiments, the selective etching and deposition process can be carried out, as described in Figure 15. Fig. as described above. However, in some embodiments, the selective etching and deposition process can reduce the thickness of the gate capping layer 114 and / or round the corners of the gate capping layer 114. This is partly due to the fact that during the selective etching and deposition process, a first flow rate of the plasma etchant can be significantly higher than a second flow rate of the selective precursor gas. For example, the first flow rate of the plasma etchant can be between about 30 sccm and about 50 sccm, and the second flow rate of the selective precursor gas can be about 20 sccm. For ease of illustration, an upper portion of the gate capping layer 114 is shown by a dashed line, and in some embodiments, the upper portion of the gate capping layer 114 can be removed by the selective etching and deposition process.After removing the upper part of the gate capping layer 114, the dielectric protective layer 1002 is selectively produced along the exposed top surface of the gate capping layer 114, so that the dielectric protective layer 1002 matches the exposed top surface of the gate capping layer 114.

[0047] In various embodiments, the thickness of a first gate capping structure 114a of the gate capping layer 114 is reduced by a first vertical loss value 1502 of approximately 1 nanometer (nm), in a range of approximately 0.1 to 2 nm, less than approximately 2 nm, or another suitable value. In further embodiments, the thickness of a second gate capping structure 114b of the gate capping layer 114 is reduced by a second vertical loss value 1504 of approximately 1 nm, in a range of approximately 0.1 to 2 nm, less than approximately 2 nm, or another suitable value. In some embodiments, the first vertical loss value 1502 is equal to the second vertical loss value 1504. In still other embodiments, the width w1 of the second gate capping structure 114b of the gate capping layer 114 is approximately 45 nm, in a range of approximately 30 to 60 nm, or it has another suitable value.In various embodiments, the lateral spacing d1 between adjacent structures of the gate capping layer 114 is approximately 15 nm, in a range of approximately 10 to 20 nm, or it has another suitable value. Furthermore, during the selective etching and deposition process, the height of each outer corner of the exposed areas of the gate capping layer 114 can be reduced by a vertical distance 1506. In some embodiments, the vertical distance 1506 can be approximately 2.5 nm, in a range of approximately 0.1 to 5 nm, less than 5 nm, or it can have another suitable value. In still other embodiments, after the selective etching and deposition process, a removal process is carried out to remove the dielectric protective layer 1002 overlying the gate capping layer 114 (not shown).

[0048] As shown in section view 1600 of Fig. As shown in Figure 16, a conductive structure 1102 is located in the source / drain contact openings (1004 of Fig. 10) and over the source / drain regions 104. In some embodiments, an adhesive and / or barrier layer (not shown) can be produced over the substrate 102 prior to the production of the conductive structure 1102, which promotes bonding and / or prevents diffusion. In other embodiments, the conductive structure 1102 can be produced over the substrate 102 by depositing the conductive structure 1102 onto the source / drain regions 104 and the gate capping layer 114 using a CVD process, a PVD process, a sputtering process, an electroplating process, or another suitable deposition or growth process.In further embodiments, a metallization process can be carried out prior to the fabrication of the conductive structure 1102 to produce a semiconductor-metal composite film or a semiconductor-metal composite layer (such as silicide) at an interface between the conductive structure 1102 and the exposed portion of the top surface of the source / drain regions 104, thereby providing a low-resistance contact (not shown). Furthermore, the conductive structure 1102 is fabricated to align with the rounded corners of the gate capping layer 114.

[0049] As shown in section view 1700 of Fig. As shown in 17, a planarization process is carried out on the structure of Fig. 16, thereby defining a plurality of lower source / drain contacts 116. In various embodiments, the Fig. 15-17 an alternative embodiment of producing the plurality of lower source / drain contacts 116. In some embodiments, the planarization process may include a CMP process, an etching process, another suitable planarization process, or a combination thereof. By means of the conductive structure (1102 of Fig. 16) corresponds to the rounded corners of the gate capping layer 114, in further embodiments at least a part of each lower source / drain contact 116 comprises an outer projection which is located directly above an adjacent segment of the gate capping layer 114 and corresponds to its shape.

[0050] The Fig. Figures 18-22A show sectional views 1800-2200a of some embodiments of a third method for manufacturing an integrated chip with a gate capping layer over a gate electrode according to the present invention. For example, the Fig. 18-22A Alternative embodiments of steps which replace the steps in the Fig. 9-14 of the procedure of Fig. 5-14 can be carried out. Consequently, in some embodiments, the third method comprises a method that can be alternatively performed by the Fig. 5-8 up to the Fig. 18-22A progresses (i.e. the Fig. Pages 9-14 are skipped).

[0051] As shown in the sectional view 1800 from Fig. As shown in Figure 18, an upper dielectric structure 1808 is fabricated over the lower ILD layer 117 and the gate capping layer 114. In various embodiments, the upper dielectric structure 1808 can be fabricated by depositing it over the lower ILD layer 117 using a CVD process, a PVD process, an ALD process, or another suitable growth or deposition process. Furthermore, a masking structure 1802 is fabricated over the upper dielectric structure 1808, the masking structure 1802 comprising a hard masking layer 1804 arranged along the upper dielectric structure 1808 and a dielectric layer 1806 located over the hard masking layer 1804.

[0052] As shown in the 1900 section view. Fig. As shown in Figure 19, a structuring process is carried out on the upper dielectric structure 1808 according to the masking structure 1802, thereby defining a plurality of openings 1902 in the upper dielectric structure 1808. In various embodiments, the structuring process comprises performing a dry etching process, a wet etching process, another suitable etching process, or a combination thereof.

[0053] As shown in the section view 2000 from Fig. As shown in Figure 20, a selective etching and deposition process is carried out on the upper dielectric structure 1808, the gate capping layer 114, and the lower ILD layer 117, thereby producing source / drain contact openings 1004 over the source / drain regions 104 and selectively producing a dielectric protective layer 1002 along the top surface of the gate capping layer 114. In various embodiments, the selective etching and deposition process is carried out as described in Figure 20. Fig. Figure 10 shows and describes the openings. In further embodiments, the openings are (1902 of Fig. 19) is extended by the selective etching and deposition process while the source / drain contact openings 1004 are produced, and a top surface of the source / drain regions 104 is exposed. In various embodiments, after performing the selective etching and deposition process, a removal process is carried out to remove the dielectric protective layer 1002 along the top surface of the gate capping layer 114 (not shown).

[0054] As shown in section view 2100 from Fig. As shown in Figure 21, a plurality of lower source / drain contacts 116 are located in the source / drain contact openings (1004 of Fig. 20) over corresponding source / drain areas 104. In various embodiments, a process for producing the plurality of lower source / drain contacts 116 comprises the following: depositing (e.g., by a CVD process, a PVD process, a sputtering process, an electroplating process, etc.) a conductive structure (not shown) over the substrate 102, such that the conductive structure covers the source / drain contact openings (1004 of Fig. 20) fills; and performs a planarization process (e.g., a CMP process) into the conductive structure until a top surface of the gate capping layer 114 is reached. In various embodiments, the lower source / drain contacts 116 are manufactured such that top surfaces of the lower source / drain contacts 116 are aligned with or coplanar to the top surface of the gate capping layer 114 and / or the top surface of the lower ILD layer 117. In still further embodiments, the planarization process can be used to create the upper dielectric structure (1808 of Fig. 20) and / or the masking structure (1802 of Fig. 20) will be removed.

[0055] As shown in section view 2200a from Fig. As shown in Figure 22A, an upper ILD layer 118 is fabricated over the lower ILD layer 117, and a plurality of upper conductive contacts 120 are fabricated in the upper ILD layer 118. In various embodiments, the upper ILD layer 118 can be fabricated as shown in Figure 22A. Fig. 13 shown and / or described. In further embodiments, the majority of upper conductive contacts 120 can be manufactured as shown in Fig. 13 is shown and / or described.

[0056] Fig. Figure 22B shows a sectional view 2200b of some alternative embodiments of the sectional view 2200a of Fig. 22A, in which the majority of lower source / drain contacts 116 are produced over corresponding source / drain regions 104, such that each lower source / drain contact 116 has one or more projections that coincide with an adjacent rounded corner of the gate capping layer 114. In some embodiments, the selective etching and deposition process used to produce the source / drain contact openings (e.g., 1004 of Fig. 20) is used, as described in Fig. 15 is shown and / or described.

[0057] In various embodiments, the majority of lower source / drain contacts 116 have a first lower source / drain contact 116a. The first lower source / drain contact 116a has a first straight side wall 302 and a second straight side wall 304 opposite the first straight side wall 302. In some embodiments, the first lower source / drain contact 116a comprises a body region 116br and one or more projections 306, 308 extending from the body region 116br to an adjacent rounded corner of the gate capping layer 114. The body region 116br is defined between the first straight side wall 302 and the second straight side wall 304 such that a width Wc of the body region 116br is defined between the first and the second straight side wall 302, 304. In various embodiments, the width Wc is approximately 15 nm, in a range of approximately 10 to 20 nm, or it has another suitable value.In further embodiments, the first lower source / drain contact 116a comprises a first projection 306 extending from the body region 116br in a first direction, and a second projection 308 extending from the body region 116br in a second direction opposite to the first direction. A first width Wp1 of the first projection 306 is defined from the body region 116br to an outermost point of the first projection 306, and a second width Wp2 of the second projection 308 is defined from the body region 116br to an outermost point of the second projection 308. In various embodiments, the first and second widths Wp1, Wp2 are each approximately 0.75 nm, in a range of approximately 0.5 to 1 nm, less than approximately 1 nm, or they have another suitable value.

[0058] In some embodiments, the ratio between the first width Wp1 and the width Wc (e.g., Wp1:Wc) is, for example, about 1:20, in a range of about 0.25:20 to 1:20, or it has another suitable value. In other embodiments, the ratio between the second width Wp2 and the width Wc (e.g., Wp2:Wc) is, for example, about 1:20, in a range of about 0.25:20 to 1:20, or it has another suitable value. In various embodiments, when the ratios between the first and second widths Wp1, Wp2, and Wc (e.g., Wp1:Wc and Wp2:Wc) are relatively low (e.g., less than about 1:20), the distance between the lower source / drain contacts 116 and laterally adjacent upper conductive contacts 120 is increased. This partially reduces the parasitic capacitance between the lower source / drain contacts 116 and the upper conductive contacts 120.In further embodiments, if the ratios between the first and second widths Wp1, Wp2 and the width Wc are relatively high (e.g., greater than approximately 1:20), then the distance between the lower source / drain contacts 116 and laterally adjacent upper contacts 120 is reduced. This can increase the parasitic capacitance between the lower source / drain contacts 116 and the upper conductive contacts 120.

[0059] Fig. Figure 23 shows a method 2300 for manufacturing an integrated chip with a gate capping layer over a gate electrode according to the present invention. Although the method 2300 is presented and / or described here as a series of steps or events, it should be understood that the method is not limited to the sequence or steps shown. Consequently, in some embodiments, the steps can be performed in a different sequence than shown and / or can be performed simultaneously. Furthermore, in some embodiments, the steps or events shown can be subdivided into several steps and events that can be performed at different times or simultaneously with other steps or substeps.In some embodiments, some of the steps or events shown may be omitted, and other steps and events not shown may be included.

[0060] In step 2302, a transistor structure with a pair of source / drain regions and a gate electrode between the source / drain regions is fabricated. Fig. 5 and Fig. Figure 6 shows sectional views 500 and 600 according to some embodiments of step 2302.

[0061] In step 2304, a lower inter-level dielectric layer (ILD layer) is produced over the source / drain pair and around the gate electrode. Fig. Figure 6 shows the sectional view 600 according to some embodiments of step 2304.

[0062] In step 2306, a gate capping layer is produced over the gate electrode. Figures 700 and 800 show sectional views according to some embodiments of step 2306.

[0063] In step 2308, a selective etching and deposition process is performed to create a dielectric protective layer on the gate capping layer, while the lower ILD layer is etched to create a plurality of source / drain contact openings in the lower ILD layer. Fig. Figure 10 shows the sectional view 1000 according to some embodiments of step 2308. Fig. Figure 15 shows the sectional view 1500 according to some alternative embodiments of step 2308. Fig. Figure 20 shows the sectional view 2000 according to yet another alternative embodiment of step 2308.

[0064] In step 2310, a plurality of lower source / drain contacts are made in the source / drain contact openings and above the source / drain areas. Fig. 11 and Fig. Figures 12 show sectional views 1100 and 1200 according to some embodiments of step 2310. Fig. 16 and Fig. Figure 17 shows the sectional views 1600 and 1700 according to some alternative embodiments of step 2310. Fig. Figure 21 shows the sectional view 2100 according to yet another alternative embodiment of step 2310.

[0065] In step 2312, an upper ILD layer is produced over the majority of lower source / drain contacts and the lower ILD layer. Fig. Figure 13 shows the sectional view 1300 according to some embodiments of step 2312.

[0066] In step 2314, a plurality of upper conductive contacts are produced in the upper ILD layer and above the gate electrode and the lower source / drain contacts. Fig. Figure 14 shows the sectional view 1400 according to some embodiments of step 2314. Fig. Figure 22 shows the sectional view 2200 according to some alternative embodiments of step 2314.

[0067] Accordingly, in some embodiments, the invention relates to a method for manufacturing an integrated chip (and a corresponding structure) comprising the following: performing a selective etching and deposition process on a gate capping layer and a lower ILD layer to selectively produce a dielectric protective layer on the gate capping layer, while simultaneously etching the lower ILD layer to create contact openings over corresponding source / drain regions. Subsequently, lower source / drain contacts are produced in the contact openings and over the source / drain regions.

[0068] In some embodiments, the invention provides a method for fabricating an integrated chip, comprising: fabricating a transistor structure over a substrate, wherein the transistor structure has a pair of source / drain regions and a gate electrode between the source / drain regions; fabricating a lower inter-level dielectric (ILD) layer over the pair of source / drain regions and around the gate electrode; fabricating a gate capping layer over the gate electrode; and performing a selective etching and deposition process to fabricate a dielectric protective layer on the gate capping layer while fabricating a contact opening in the lower ILD layer; and fabricating a lower source / drain contact in the contact opening.

[0069] In some embodiments, the invention provides a method for fabricating an integrated chip, comprising: fabricating a transistor structure over a substrate, wherein the transistor structure has a pair of source / drain regions and a gate electrode between the source / drain regions; fabricating a lower etch stop layer and a lower inter-level dielectric layer (ILD layer) over the pair of source / drain regions and around the gate electrode over the substrate, wherein the lower ILD layer comprises a first dielectric material; recessing the gate electrode such that a top surface of the gate electrode is below a top surface of the lower etch stop layer;Fabricating a gate capping layer on the recessed gate electrode such that a top surface of the gate capping layer is oriented towards a top surface of the lower ILD layer, wherein the gate capping layer has a second dielectric material that is different from the first dielectric material; performing a selective etching and deposition process to selectively fabricate a dielectric protective layer along the top surface of the gate capping layer while simultaneously selectively etching the lower ILD layer to define contact openings over the source / drain regions, wherein the selective etching and deposition process comprises simultaneously flowing a plasma etchant at a first flow rate and a selective precursor gas at a second flow rate that is lower than the first flow rate over the substrate; performing a removal process to remove the dielectric protective layer;and establishing lower source / drain contacts in the contact openings.;

Claims

[1] Method for manufacturing an integrated chip comprising the following steps: Fabricating a transistor structure (101) over a substrate (102), wherein the transistor structure (101) has a pair of source / drain regions (104) and a gate electrode (108) between the source / drain regions (104); Creating a lower ILD layer (117) over the pair of source / drain regions (104) and around the gate electrode (108); Creating a gate capping layer (114) over the gate electrode (108); and Performing a selective etching and deposition process to selectively deposit a dielectric protective layer (1002) onto the gate capping layer (114) and, in the process, creating a contact opening (1004) in the lower ILD layer (117); and Establishing a lower source / drain contact (116) in the contact opening (1004). [2] Method according to claim 1, wherein the dielectric protective layer (1002) is produced on the gate capping layer (114) while simultaneously etching the lower ILD layer (117) to produce the contact opening (1004). [3] Method according to claim 1 or 2, wherein the selective etching and deposition process comprises simultaneously flowing a plasma etchant and a selective precursor gas over the gate capping layer (114) and the lower ILD layer (117). [4] Method according to claim 3, wherein the plasma etchant is different from the selective precursor gas. [5] Method according to claim 3 or 4, wherein a flow rate of the plasma etchant is greater than a flow rate of the selective precursor gas. [6] Method according to any of the preceding claims, wherein the selective etching and deposition process comprises carrying out a selective etching process simultaneously with a selective deposition process. [7] Method according to one of the preceding claims, wherein the selective etching and deposition process is carried out at a temperature in a range (104) between about 0 °C and 150 °C. [8] Method according to any of the preceding claims, wherein the gate capping layer (114) comprises a first dielectric material and the lower ILD layer (117) comprises a second dielectric material which is different from the first dielectric material. [9] Method according to claim 8, wherein the first dielectric material is a non-oxide dielectric material and the second dielectric material is an oxide. [10] Method for manufacturing an integrated chip comprising the following steps: Fabricating a transistor structure (101) over a substrate (102), wherein the transistor structure (101) has a pair of source / drain regions (104) and a gate electrode (108) between the source / drain regions (104); Producing a lower etch stop layer (110) and a lower ILD layer (117) over the pair of source / drain regions (104) and around the gate electrode (108) over the substrate (102), wherein the lower ILD layer (117) comprises a first dielectric material; Recessing the gate electrode (108) so that a top side of the gate electrode (108) is below a top side of the lower etch stop layer (110); Producing a gate capping layer (114) on the recessed gate electrode (108) such that a top side of the gate capping layer (114) is oriented towards a top side of the lower ILD layer (117), wherein the gate capping layer (114) has a second dielectric material that is different from the first dielectric material; Performing a selective etching and deposition process to selectively produce a dielectric protective layer (1002) along the top surface of the gate capping layer (114) while simultaneously selectively etching the lower ILD layer (117) to define contact openings (1004) over the source / drain regions (104), wherein the selective etching and deposition process comprises simultaneously flowing a plasma etchant at a first flow rate and a selective precursor gas at a second flow rate lower than the first flow rate over the substrate (102); Performing a removal process to remove the dielectric protective layer (1002); and Establish lower source / drain contacts in the contact openings (1004). [11] The method of claim 10, further comprising: Creating an upper ILD layer (118) over the lower ILD layer (117) and the lower source / drain contacts (116); and Establishing upper conductive contacts in the upper ILD layer (118), wherein the upper conductive contacts are each electrically connected to the gate electrode (108) and / or the lower source / drain contacts (116). [12] Method according to claim 10 or 11, wherein the gate capping layer (114) extends continuously from the top of the lower etch stop layer (110) to a top of the gate electrode (108). [13] Method according to any one of claims 10 to 12, wherein the dielectric protective layer (1002) is selectively produced faster along the top surface of the gate capping layer (114) than the dielectric protective layer (1002) is etched with the plasma etchant. [14] Method according to any one of claims 10 to 13, wherein the dielectric protective layer (1002) comprises a conductive material. [15] Method according to any one of claims 10 to 14, wherein the plasma etchant comprises a fluorine-based etchant and the selective precursor gas comprises a metal fluoride. [16] Method according to any one of claims 10 to 15, wherein a top surface of the lower source / drain contact (116) is oriented towards the top surface of the gate capping layer, wherein the lower source / drain contact (116) has a body region (116b) and a first projection (306), wherein the first projection (306) extends laterally from the body region (116b) to a point above a part of the gate capping layer, wherein a width of the body region (116b) is at least 20 times greater than a width of the first projection (306). [17] Method according to claim 16, wherein the first dielectric material is an oxide and the second dielectric material is a dielectric non-oxide material. [18] The method of claim 16 or 17, further comprising: Forming a sidewall spacer (112) arranged along sidewalls of the gate electrode (108); and wherein the lower etch stop layer is arranged between the side wall spacer (112) and the lower ILD layer; wherein the gate capping layer (114) extends from a top surface of the lower etch stop layer (110) along a side wall of the side wall spacer (112) to a top surface of the gate electrode (108). [19] Method according to any one of claims 16 to 18, wherein the gate capping layer (114) has a curved corner directly adjacent to the lower source / drain contact (116), wherein the first projection (306) directly contacts the curved corner and coincides with the curved corner. [20] Method according to any one of claims 16 to 19, wherein a top side of the first projection (306) is aligned with the top side of the gate capping layer (114).

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