CELL WITH ELECTROSTATIC DISCHARGE PROTECTION AND ANTENNA INTEGRATED WITH SILICON THROUGH-CONTACTING

Abstract

Semiconductor device with: a silicon through-hole TSV (202a, 202b) in a TSV zone (Z1) in a substrate (302), wherein the TSV (202a, 202b) extends through the substrate (302); an ESD cell (306a, 306b) near a first end of the TSV (202a, 202b) and in contact with the TSV zone (Z1), wherein the ESD cell (306a, 306b) has a group of diodes (412a to 412i) connected electrically in parallel with each other; an antenna pad (314, 512) which is electrically connected to a second end of the TSV (202a, 202b); an antenna (316a, 316b) electrically connected to the antenna pad (314, 512) and extending in a first direction (298), the first direction being parallel to a principal axis of the TSV (202a, 202b); and a conductive column (310a, 310b) extending parallel to the TSV (202a, 202b) on the same side of the substrate (302) as the antenna pad (314, 512) in the first direction (298), wherein a first end (311) of the conductive column (310a, 310b) is electrically connected to the antenna pad (314, 512) and a second end (313) of the conductive column (310a, 310b) is electrically connected to the group of diodes (412a to 412i) of the ESD cell (306a, 306b).

Description

background

[0001] Electrostatic discharge (ESD) in semiconductor devices is associated with increased failure rates during operation, as well as increased error rates and manufacturing costs during the production process. Semiconductor devices incorporate ESD protection devices to reduce the risk of transient high voltage damage to transistors or other circuit elements within the semiconductor devices.

[0002] Semiconductor devices are manufactured with integrated antennas for transmitting and receiving RF (radio frequency) signals to or from other devices. Antenna lines extending across the surface of a semiconductor device are a source of static electricity buildup and ESD in some manufacturing processes before the semiconductor device is encapsulated and bonded to a printed circuit board.

[0003] In some semiconductor devices, ESD protection devices and integrated antenna lines extend across the surface of the semiconductor device in adjacent areas on the surface of the semiconductor device.

[0004] US 2012 / 0295433A1 discloses an antenna diode that is formed at least partially within the depletion region around a TSV and is connected to the TSV via a metallic conductor of the first layer, while the TSV is simultaneously connected either to the gate polymer or a diffusion region of one or more transistors placed outside the depletion region.

[0005] CN 113 178 433 A describes a 3D IC package and a method for its fabrication. The 3D IC package comprises: a first IC chip with a first substrate on the back side of the first IC chip; a second IC chip stacked on the back side of the first IC chip and facing the first substrate; a TSV extending through the first substrate and electrically connecting the first and second IC chips. The TSV has a TSV cell surrounded by a TSV cell boundary; and a protection module fabricated in the first substrate, electrically connected to the TSV and located within the TSV cell. invention

[0006] The invention is defined in the claims. Brief description of the drawings

[0007] Aspects of the present invention are best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not shown to scale. Rather, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. Fig. Figure 1 is a top view of a semiconductor device 100 according to some embodiments. Fig. Figure 2 is a top view of a semiconductor device according to some embodiments. Fig. Figure 3 is a sectional view of a semiconductor device according to some embodiments. The Fig. Figures 4A to 4D are circuit diagrams of an ESD cell according to some embodiments. The Fig. 5A and Fig. Figure 5B shows top views of a semiconductor device according to some embodiments. Fig. Figure 6 is a flowchart of a method for manufacturing a semiconductor device according to some embodiments. Fig. Figure 7 is a block diagram of an EPC system (EPC: electronic process control) according to some embodiments. Fig. Figure 8 is a block diagram of an IC manufacturing plant (IC: integrated circuit) and an associated IC manufacturing process according to some embodiments. Fig. Figure 9 is a schematic representation of various processing departments defined in a chip factory, front-end or manufacturing plant for the production of IC devices, according to some embodiments. Detailed description

[0008] The following description provides many different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components, values, steps, materials, arrangements, or the like are described below to simplify the present invention. Other components, values, steps, materials, arrangements, or the like are also considered. For example, the fabrication of a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are fabricated in direct contact, and it may also include embodiments in which additional elements can be fabricated between the first and second elements such that the first and second elements are not in direct contact.Furthermore, reference numerals and / or letters may be repeated in the various examples in the present invention. This repetition serves the purpose of simplicity and clarity and does not in itself imply any relationship between the various embodiments and / or configurations discussed.

[0009] Furthermore, spatially relative terms, such as "located below," "under," "lower," "located above," "upper," and the like, can be used here to simply describe the relationship of an element or structure to one or more other elements or structures depicted in the figures. These spatially relative terms are intended to encompass orientations of the device in use or operation beyond the orientation shown in the figures. The device may be oriented differently (rotated by 90 degrees or in a different orientation), and the spatially relative descriptors used here can be interpreted accordingly.

[0010] When manufacturing semiconductor devices, care is taken to prevent damage to the devices from transient voltages that cause an electric current to flow through circuit elements within the semiconductor devices. For example, during a manufacturing process, a semiconductor device is lifted from a substrate, placed in an alignment tool, transferred to a processing chamber, and returned to the substrate. Every instance in which a wafer containing semiconductor devices is manipulated or processed during a manufacturing process presents an opportunity for static electricity to build up on the device and a current to flow through parts of the circuit within the semiconductor device.Semiconductor manufacturers use ESD protection devices in semiconductor devices to protect parts of the circuit against transient voltages and currents flowing through parts of the circuit in the semiconductor device.

[0011] Furthermore, some semiconductor devices incorporate antennas as part of their structure to enable wireless communication between electronic devices. In some cases, semiconductor devices include antennas arranged transversely across the surface of a substrate in which the semiconductor device is mounted. Similarly, ESD protection in semiconductor devices often includes circuit elements distributed transversely across the surface of a substrate in which the semiconductor device is mounted. Thus, the area of ​​a substrate allocated for an antenna or antenna array and for ESD protection of a semiconductor device is an area unavailable for other circuit elements, such as logic transistors, memory, and the like.

[0012] In some embodiments of the present invention, a semiconductor device is described that has an ESD shield integrated with an antenna array, wherein the ESD shield and the antenna array are distributed around a silicon through-hole (SOH) which penetrates a substrate of the semiconductor device. By arranging the ESD shield and the antenna array around the SOH as described below, more area is made available for circuit elements, such as logic transistors, SRAMs, and the like. This allows the overall size of the semiconductor device to be reduced.

[0013] Fig. Figure 1 is a top view of the semiconductor device 100 according to some embodiments.

[0014] In Fig. In Figure 1, a TSV 102 with a circumference C1 is arranged in a TSV zone Z1. A TSV zone is a region that encloses a TSV and provides electrical insulation from other structural elements of the semiconductor device. On the top side of a substrate, the TSV zone comprises a region of the substrate material that is bounded by cells of the semiconductor device (see, for example, an ESD cell 400 of Figure 1). Fig. 4A). On levels of the semiconductor device produced after the process for manufacturing transistors and other circuit elements, the TSV zone contains dielectric material having the same dimensions as the TSV zone on the substrate level of the semiconductor device. The TSV zone Z1 contains a TSV zone material 104 with a TSV zone boundary P1. In the semiconductor device 100, the TSV zone material 104 is a substrate semiconductor material through which the TSV 102 extends. The TSV 102 is located centrally within the TSV zone material 104, which has a first dimension D1 extending in a first direction and a second dimension D2 extending in a second direction perpendicular to the first direction. In some embodiments, the first dimension D1 is at least 4 µm and at most 6 µm. In some embodiments, the second dimension D2 is also at least 4 µm and at most 6 µm.In embodiments where the first dimension D1 and the second dimension D2 are each larger than approximately 6 µm, the area of ​​the TSV zone around the TSV does not provide additional protection against ESD damage or dielectric breakdown between diodes in the ESD protection zone and the TSV. In embodiments where the first dimension D1 and the second dimension D2 are each smaller than approximately 4 µm, the semiconductor device is at greater risk of ESD damage and dielectric breakdown due to the proximity of the TSV to ESD cells in the ESD protection zone. In some embodiments, D1 is equal to D2. In some embodiments, D1 is different from D2.

[0015] In the semiconductor device 100, ESD protection is provided by diodes (not shown, but see the ESD cell 400 of Fig. 4A) provided, which are electrically connected in parallel in an ESD protection zone Z2 that extends along the TSV zone boundary P1 and around the TSV 102. The diodes in the ESD protection zone Z2 are located in ESD cells (not shown) arranged in contact with each other in the ESD protection zone Z2. In the semiconductor device 100, the ESD protection zone Z2 has a matrix of ESD cells arranged in borders 108 that extend around the TSV zone boundary P1. In the semiconductor device 100, corners of the ESD protection zone Z2 have dummy cells that do not contain diodes. In some embodiments, the ESD protection zone extending around a TSV is square. In some embodiments, the ESD protection zone extending around a TSV is rectangular. In some embodiments, the ESD protection zone extending around a TSV has a non-rectangular shape.In some embodiments, the corners of the ESD protection zones have cells containing diodes for other circuit elements configured for ESD protection. In some embodiments, other circuit elements configured for ESD protection include capacitors.

[0016] In the semiconductor device 100, a device field 109 extends around an outer boundary of the ESD protection zone Z2 and also has a plurality of field areas 110 and 110b. The field areas 110 have a short side that is in contact with the edges 108 of the matrix of ESD cells in the TSV zone Z2. The field areas 110b have a long side that is in contact with the edges 108 of the matrix of ESD cells in the TSV zone Z2. In the semiconductor device 100, only one field area 110b is in contact with an edge 108 of the TSV zone Z2. In some embodiments, several field areas 110b are arranged with their long side in direct contact with the edge 108 of the TSV zone Z2. The field areas 110 and 110b have a long and a short dimension to accommodate circuit elements. In some embodiments, one field area contains logic transistors. In some embodiments, one field area contains memory cells.In some embodiments, a field area contains capacitors. In some embodiments, a field area contains conductive traces for transmitting signals and / or power to the semiconductor device. In some embodiments, the field area contains no circuit elements and provides a buffer around the ESD protection zone Z2 to protect the semiconductor device against ESD damage.

[0017] In the semiconductor device 100, the field region 109 is enclosed by insulating structures 112, 114, and 116. In some embodiments, the insulating structures 112, 114, and 116 can be manufactured in a single manufacturing step and can extend continuously around the field region 109. In some embodiments, the insulating structures 112, 114, and 116 are a dielectric material deposited in a substrate material. The field region 109 and the insulating structures 112, 114, and 116 are arranged in a device zone Z3, which extends around the outer boundary of the ESD protection zone Z2.

[0018] Fig. Figure 2 is a top view of a semiconductor device 200 according to some embodiments. Elements of the semiconductor device 200 that have a similar structure and function to corresponding elements in the semiconductor device 100 are designated with the same reference number increased by 100. In the semiconductor device 200, the TSV zone Z1 contains a first TSV 202a and a second TSV 202b. The first TSV 202a has a first TSV perimeter C1a. The second TSV 202b has a second TSV perimeter C1b. The TSV zone Z1 has a first dimension D1 extending in a first direction 298 and a second dimension D3 extending in a second direction 299 perpendicular to the first direction 298. In the semiconductor device 200, the second dimension D3 is approximately twice the size of the first dimension D1.

[0019] In the semiconductor device 200, several field regions 210b are arranged such that a long side of the field region 210b is in contact with an edge 208 of the TSV zone Z2. In some embodiments, only one field region 210b is arranged such that its long side is in contact with the edge 208 of the TSV zone Z2.

[0020] The semiconductor device 200 has a first TSV 202a and a second TSV 202b. A semiconductor device containing multiple TSVs shows greater space savings by integrating vertically arranged antennas connected to an antenna pad (see, for example, an antenna pad 314 of a semiconductor device 300). Fig. 3) are electrically connected, and offer greater space savings for circuit elements providing ESD protection by having a larger ESD cell perimeter in a TSV zone that encloses two TSVs instead of just one. In some embodiments, as the number of TSVs in a single TSV zone Z1 increases, the number of diodes in the ESD cells decreases (e.g., in ESD cell 400 of Fig. 4A) linearly with the increase in the area of ​​TSV zone Z2, thereby providing a similar ESD protection perimeter with a decreasing area, which is provided for separation between adjacent TSVs in the semiconductor device. In some embodiments, the number of TSVs in a single TSV zone Z1 is 1 to 10. In some embodiments, using more than 10 TSVs in a TSV zone Z1 enclosed by a single row of ESD cells reduces the ESD protection perimeter for the semiconductor device.In some embodiments of semiconductor devices, by using ESD cells that form a boundary around one or more TSVs, the area provided for [1] the TSVs, [2] the TSV zone Z1 and [3] the ESD protection is reduced by about 30% compared to semiconductor devices that have separate areas for the TSVs, the TSV isolation and the ESD protection, distributed laterally across the surface of a substrate for the semiconductor device.

[0021] Fig. Figure 3 is a sectional view of a semiconductor device 300 according to some embodiments. The semiconductor device 300 has a similar structure to the semiconductor devices 100 and 200. The top views of the semiconductor devices 100 and 200 described above are similar to the top view of the semiconductor device 300 on a top surface 305 of a substrate 302, showing the positions of ESD cells (e.g., an ESD cell 306a and an ESD cell 306b on one side of a TSV 304 opposite the ESD cell 306a). The TSV 304 extends from the top surface 305 through the substrate 302 downwards to a bottom surface 307. In the semiconductor device 300, the TSV zone Z1, the ESD protection zone Z2, and the device zone Z3 are designated in a similar manner to the description of the semiconductor device 100 above. In the sectional view of the semiconductor device 300, the TSV 304 extends over the top surface 305 of the substrate 302.In the semiconductor device 300, a first end 311 of the TSV 304 is located on one side of the substrate 302 opposite the ESD cells 306a and 306b, and a second end 313 of the TSV 304 is located on the same side of the substrate 302 as the ESD cells 306a and 306b. The TSV zone Z1 is an exclusion zone in the semiconductor device in which the circuit elements are excluded from the top surface 305 of the substrate 302. In some embodiments, the exclusion zone extends upward along the sides of the TSV to the antenna pad 314. A grounding ring 319 is provided between the ESD cells 306a and 306b on the top surface 305 of the substrate 302 and the side walls of the TSV 304. In some embodiments, the grounding ring 319 extends deeper into the substrate 302 than the ESD cells 306a and 306b.In some embodiments, the distance of the grounding ring 319 from the side walls of the TSV 304 is smaller than the smallest distance between the grounding ring 319 and the ESD cells 306a and 306b around the grounding ring 319.

[0022] The antenna pad 314 is located close to the second end 313 of the TSV 304. In the semiconductor device 300, the antenna pad 314 is in direct contact with the second end 313 of the TSV 304. In some embodiments, the antenna pad 314 is separated from the second end 313 of a TSV 311 by a layer of a dielectric material, and it is electrically connected to the TSV 311 by at least one contact or via extending from the antenna pad 314 to the second end 313 of the TSV 304.

[0023] The antenna pad 314 is electrically connected to the ESD cells 306a and 306b in the substrate 302 by a conductive column 310a or 310b, respectively. The conductive column 310a is electrically connected to the ESD cell 306a and a conductive line 312a. The conductive column 310b is electrically connected to the ESD cell 306b and a conductive line 312b. The conductive lines 312a and 312b are electrically connected to the antenna pad 314. In some embodiments, the conductive lines are directly electrically connected to the antenna pad 314.

[0024] In the semiconductor device 300, antennas 316a and 316b extend from the antenna pad 314 to the substrate 302. Antenna 316a is electrically connected to the antenna pad 314 near the conductive column 310a and is located between the conductive column 310a and the TSV 304. Antenna 316b is electrically connected to the antenna pad 314 on the same side of the substrate as the ESD cells. Antenna 316b is located between the conductive column 310b and the TSV 304.

[0025] Fig. Figure 4A is a circuit diagram of an ESD cell 400 according to some embodiments. The ESD cell 400 has a first operating voltage line 402 and a second operating voltage line 404. The first operating voltage line 402 is a VDD line, and the second operating voltage line 404 is a VSS line. The ESD cell 400 also has a signal line 406. In some embodiments, the signal line 406 acts as an input line for diodes of the ESD cell 400. A first group of transistors 408 comprises n-transistors (NMOS transistors) that are electrically connected in parallel between the second operating voltage line 404 and the signal line 406. A second group of transistors 410 comprises p-transistors (PMOS transistors) that are electrically connected in parallel between the first operating voltage line 402 and the signal line 406.The first group of transistors 408 and the second group of transistors 410 contain the same number of transistors. The transistors of the first group of transistors 408 and the second group of transistors 410 serve as diodes in the ESD cell 400. The ESD cell 400 has diodes 412a to 412i, which are electrically connected in parallel by the first supply voltage line 402, the second supply voltage line 404, and the signal line 406. In some embodiments, the number of diodes in an ESD cell 400 is at least 2 and at most 20. In some embodiments of ESD cells that have only one diode, the current-carrying capacity of the ESD cell is not sufficient to protect the semiconductor device against damage from electrostatic discharge. In embodiments of ESD cells that have more than 20 diodes, the area available for additional diodes (e.g.,The area provided for diodes 21, 22, and so on is subtracted from the area provided for logic transistors, memory, and other circuit elements, and the additional protection against damage from electrostatic discharge decreases significantly with each additional diode. The diodes of an ESD cell described here act as a pn junction for ESD protection, and they redirect an electric current associated with transient voltages having a sufficient potential (which depends on the number of diodes in the ESD cell) so that it is conducted through the diode.

[0026] In a semiconductor device 400, in response to the voltage supplied by signal line 406 being higher than the voltage on the first supply voltage line 402 (e.g., VDD), the p-transistors of the second group of transistors 410 (e.g., the p-transistors of diodes 412a to 412i) are activated so that they conduct current. In the semiconductor device 400, in response to the voltage supplied by signal line 406 being lower than the voltage on the second supply voltage line 404 (e.g., VSS), the n-transistors of the first group of transistors 408 (e.g., the n-transistors of diodes 412a to 412i) are activated so that they conduct current.

[0027] Fig. Figure 4B is a circuit diagram of an ESD cell 420 with a structure similar to that of the ESD cell 400 described above. For clarity, elements of the semiconductor device 420 that have a similar structure or function to a corresponding element of the semiconductor device 400 are designated with the same reference number. In the ESD cell 420, a signal line 406 is electrically connected to an output of a first diode 409 and an input of a second diode 411. The input of the first diode 409 is electrically connected to ground (e.g., a second supply voltage line 404). The output of the second diode 411 is electrically connected to a first supply voltage line 402 (e.g., VDD). The first diode 409 functionally corresponds to the second group of transistors 408 of the semiconductor device 400. The second diode 411 functionally corresponds to the first group of transistors 410 of the semiconductor device 400.

[0028] Fig. 4C is a circuit diagram of a semiconductor device 450 according to some embodiments. In the semiconductor device 450, elements that have a similar structure and function to a corresponding element of the semiconductor device 400 are designated with the same reference number increased by 50. In the semiconductor device 450, the gate electrodes of p-transistors in a first group of transistors 460 are not electrically connected in parallel with a first supply voltage line 452. The gate electrodes of the p-transistors are floating gate electrodes. Likewise, in the semiconductor device 450, the gate electrodes of n-transistors in a second group of transistors 458 are not electrically connected in parallel with a second supply voltage line 454. Rather, the gate electrodes of the n-transistors in the second group of transistors 458 are floating gate electrodes.

[0029] According to theory and belief, the floating gate electrodes of the p-transistors of the first group of transistors 460 and the floating gate electrodes of the n-transistors in the second group of transistors 458 have a residual capacitance that changes only slowly with respect to the duration of an ESD event occurring in the semiconductor device 450.Thus, the floating gate electrodes of the p-transistors in the first group of transistors 460 and the floating gate electrodes of the n-transistors in the second group of transistors 458 apply a bias to channel regions of the transistors, which changes only slowly with respect to the duration of an ESD event in the semiconductor device 450, and the transistors of the first group of transistors 460 and the transistors of the second group of transistors 458 function as diodes with a different bias than in the semiconductor device 400, in which the gate electrodes are pulled towards the supply voltage lines.Therefore, the semiconductor device 450 exhibits a different degree of sensitivity to ESD events than the semiconductor device 400, and it has an interconnect structure near the transistors of the first group of transistors 460 and the second group of transistors 458, which has a reduced complexity compared to the interconnect structure near the first group of transistors 410 and the second group of transistors 408 of the semiconductor device 400.

[0030] Fig. Figure 4D is a circuit diagram of an ESD cell 470 with a structure similar to that of the ESD cell 400 described above. Elements of the semiconductor device 470 that have the same structure or function as a corresponding element of the semiconductor device 420 are designated with the same reference number increased by 50. In the ESD cell 470, a signal line 456 is electrically connected to an output of a first diode 459 and an input of a second diode 461. The input of the first diode 459 is electrically connected to ground (e.g., a second supply voltage line 454). The output of the second diode 461 is electrically connected to a first supply voltage line 452 (e.g., VDD). The first diode 459 functionally corresponds to the second group of transistors 458 of the semiconductor device 450. The second diode 461 functionally corresponds to the first group of transistors 460 of the semiconductor device 450.

[0031] Fig. Figure 5A is a top view of a semiconductor device 500 according to some embodiments.

[0032] In the semiconductor device 500, a TSV 508a has a circumference C1 within a grounding ring 506. The TSV 508a has a diameter D7. The grounding ring 506 has a boundary P3. A sectional view of the semiconductor device 500 corresponds to a sectional view along a top surface 305a of the substrate 302 in the semiconductor device 300 described above.

[0033] The TSV zone Z1 is an area on the top surface of a semiconductor substrate 502 that contains the grounding ring 506. A distance D8 is the smallest distance measured between the grounding ring 506 and the circumference C1 of the TSV 508a. In some embodiments, the separation distance D8 is at least 0.3 µm and at most 1 µm. In some embodiments, a semiconductor device with a separation distance D8 between the grounding ring 506 and the TSV 508a of less than 0.3 µm is at increased risk of dielectric breakdown.In some embodiments, a semiconductor device having a separation distance D8 between the grounding ring and the TSV of more than 1 µm is at increased risk of ESD damage to transistors or circuit elements in the front end of the semiconductor device layout and / or of induced parasitic capacitance affecting transistors or other circuit elements near a TSV zone around the grounding ring in a substrate.

[0034] TSV zone Z1 has a boundary P1 that extends around the grounding ring 506 and the TSV 508a. A separation distance D5 corresponds to the smallest distance between a front end of an FEOL exclusion zone (FEOL: Front End of Line) (not shown, but corresponding to the shape of TSV zone Z1) around the TSV 508a. In some embodiments, the separation distance D5 is at least 1 µm and at most 2 µm. In some embodiments, a semiconductor device with a separation distance D5 of less than 1 µm is at increased risk of dielectric breakdown between the TSV and circuit elements in the transistor area of ​​the semiconductor device.In some embodiments, a semiconductor device having a separation distance D5 of more than 2 µm is associated with an increased die area and higher manufacturing costs, without offering the advantage of increased protection against dielectric breakdown or ESD damage between the TSV and circuit elements (conductive traces or vias) in the back end of the semiconductor device.

[0035] A boundary P2 within the boundary P1 corresponds to a boundary or outer edge of a BEOL exclusion zone 504 (BEOL: Back End of Line) projected onto the TSV zone Z1. In some embodiments, a separation distance D6 is the smallest dimension of the BEOL exclusion zone 504 projected onto the TSV zone Z1. In some embodiments, the separation distance D6 is 0.5 µm to 1.5 µm. In some embodiments, BEOL exclusion zones with a separation distance D6 greater than 1.5 µm are associated with a space-wasting semiconductor device layout, higher manufacturing costs, and an enlarged die area.In some embodiments, BEOL exclusion zones with a separation distance of less than 0.5 µm are associated with an increased risk of dielectric breakdown between the TSV and conductive traces or contacts / vias in the back end of the semiconductor device interconnect structure.

[0036] An ESD cell 510 is in direct contact with the boundary P1 of the TSV zone Z1 around the TSV 508a. In some embodiments, ESD cells extend around the entire boundary P1 of the TSV zone Z1. In some embodiments, ESD cells are in contact with the sides of the TSV zone Z1, and dummy cells are arranged at the corners of the TSV zone Z1.

[0037] Fig. Figure 5B is a top view of a semiconductor device 530 according to some embodiments. In the semiconductor device 530, an antenna pad 512 is arranged at one end of the TSV 508b, which is located on the same side of the substrate as the ESD cells (see, for example, the antenna pad 314 and the ESD cell 306a in the semiconductor device 300 of Fig. 3) In the semiconductor device 530, the antenna pad 512 is arranged above the end of the TSV 508b. In some embodiments, the antenna pad 512 is in direct contact with the end of a silicon via. In other embodiments, an antenna pad is spaced from the end of a TSV and is electrically connected to the TSV by a plurality of contacts (see, for example, contacts 514).

[0038] Fig. Figure 6 is a flowchart of a method 600 for manufacturing a semiconductor device according to some embodiments.

[0039] Method 600 comprises step 602 in which a matrix of ESD cells is fabricated over a substrate. An ESD cell in a semiconductor device has a plurality of diodes connected electrically in parallel to modulate currents generated by transient voltages in order to reduce ESD damage. In some embodiments, the diodes in an ESD cell have planar transistors along one top surface of a semiconductor substrate. In some embodiments, the diodes in the ESD cell have fin field-effect transistors (FinFETs) having fins of semiconductor material etched from the semiconductor substrate. In some embodiments, the diodes in the ESD cell have gate-all-around transistors (GAA transistors) fabricated over a substrate.In some embodiments, the semiconductor material of the substrate is intrinsic silicon, doped silicon, silicon germanium, gallium arsenide, or another semiconductor material used in the manufacture of transistors. In some embodiments, the substrate used to manufacture GAA transistors comprises silicon, silicon germanium, or silicon dioxide, or it is a silicon-on-insulator (SOI) substrate or another substrate suitable for the fabrication of three-dimensional integrated circuits or GAA transistors.

[0040] A diode in an ESD cell comprises an NMOS transistor electrically connected to a VDD supply voltage line and a signal line, and a PMOS transistor electrically connected to the signal line and a VSS supply voltage line. In an ESD cell with multiple diodes, each NMOS transistor is electrically connected in parallel to the VDD supply voltage line and the signal line, and each PMOS transistor is electrically connected in parallel to the VSS supply voltage line and the signal line.

[0041] In some embodiments, the semiconductor material channel region of the transistors comprises intrinsically conductive silicon, silicon germanium, gallium arsenide or other semiconductor materials known to those skilled in the art.

[0042] In some embodiments, the VSS operating voltage line and the VDD operating voltage line are located on the same side of the substrate. In some embodiments, the VSS operating voltage line and the VDD operating voltage line are located on opposite sides of the substrate. In some embodiments, the operating voltage lines are manufactured by electrochemical deposition of copper. In some embodiments, the operating voltage lines comprise aluminum or copper-aluminum alloys.

[0043] The procedure 600 further includes a step 604 in which a matrix of zone boundary elements is produced.

[0044] In some embodiments, the zone boundary elements include portions of dielectric material deposited in openings etched into a semiconductor material substrate to electrically isolate elements of the semiconductor device outside the TSV zone from elements of the semiconductor device within the TSV zone. For example, in some embodiments, a zone boundary element (e.g., an isolation structure) is fabricated by depositing a layer of dielectric material over transistors in the ESD cells and performing an etching process to expose a portion of the semiconductor material or substrate beneath the dielectric material around a boundary of the TSV zone.Furthermore, an etching process is performed to create a trench in the semiconductor material or substrate along the boundary of the TSV zone, and a deposition process is carried out to deposit dielectric material into the opening in the substrate or semiconductor material and into the opening created by a layer of dielectric material deposited over the ESD cells. This reduces electrical interference between the transistors in the ESD cells, between the TSV and semiconductor device components, such as SRAMs or logic transistors, outside the TSV zone. In some embodiments, the deposition of the dielectric material into an opening in the substrate or semiconductor material around the boundary of the TSV zone is performed using a CVD process (CVD: chemical evaporation).In some embodiments, the dielectric material deposited in the opening in the substrate or semiconductor material is silicon dioxide, silicon nitride, silicon oxide nitride, and the like. In some embodiments, a high-k dielectric material is deposited in the opening in the substrate or semiconductor material to electrically isolate the TSV and / or the ESD cells from elements of the semiconductor device through the surface of the substrate or semiconductor material outside the TSV zone.

[0045] The process 600 further includes a step 606 in which a grounding ring is produced for a silicon via.

[0046] In some embodiments, the grounding ring is produced by etching an opening in a substrate or semiconductor material around the TSV. In some embodiments, the grounding ring is produced by etching the substrate or semiconductor material around the TSV, and a layer of dielectric material is deposited over the ESD cells around the boundary of the TSV zone. In some embodiments, the grounding ring comprises a conductive material such as titanium, tantalum, platinum, palladium, cobalt, or tungsten, which is deposited into the opening and separated from the substrate or semiconductor material by a coating material. In some embodiments, the coating material is titanium nitride, tantalum nitride, cobalt, silicon nitride, silicon oxide nitride, or the like. The coating material is deposited by CVD or atomic layer deposition (ALD). In some embodiments, the conductive material for the grounding ring is deposited by sputtering.In some embodiments, a CMP step (CMP: chemical-mechanical polishing) is performed to remove excess coating material and / or conductive material from the top surface of the substrate and / or the layer of dielectric material that has been deposited over the ESD cells.

[0047] The process 600 further includes a step 608 in which an interconnect structure of the semiconductor device is manufactured.

[0048] In step 608, a plurality of layers of dielectric material are deposited over the ESD cells of the semiconductor device, and conductive traces and vias are created in openings therein. In some embodiments, an interconnect structure in a semiconductor device extends from circuit elements on a surface of the substrate, such as logic transistors, SRAMs, and the like, through a plurality of layers of dielectric material to a top surface of the semiconductor device.

[0049] Method 600 further comprises a step 610 in which, in some embodiments, a conductive column is produced in the semiconductor device.

[0050] In some embodiments, the fabrication of the conductive column in the semiconductor device is performed in conjunction with the fabrication of an interconnect structure of the semiconductor device, wherein the conductive column comprises contacts, vias, and conductive traces or conductive trace segments extending from the ESD cells to one end of the TSV above the ESD cells. In some embodiments, the fabrication of a conductive column in the semiconductor device includes the fabrication of an ESD HARC (high aspect ratio contact). A high aspect ratio contact, or HARC, is fabricated by performing an etching process through multiple layers of a semiconductor device such that the opening created for the HARC has a smooth and / or continuous sidewall from a top to a bottom of the ESD HARC.In some embodiments, a coating material is deposited in the opening for the ESD-HARC, and a conductive material is also deposited in the opening. In some embodiments, the conductive material for the ESD-HARC is copper, aluminum, cobalt, tungsten, platinum, palladium, or the like.

[0051] The procedure 600 further includes a step 612 in which an antenna is produced through the interconnect structure.

[0052] In some embodiments, antenna fabrication through the interconnect structure includes fabricating an antenna HARC in the BEOL exclusion zone between the conductive column and a sidewall of the TSV. An antenna HARC is fabricated by performing an etching process through multiple layers of a semiconductor device such that the opening created for the antenna HARC has a smooth and / or continuous sidewall along a substantial portion of the antenna HARC sidewall. In some embodiments, a coating material is deposited in the opening for the antenna HARC, and a conductive material is deposited in the opening above the coating. In some embodiments, the conductive material for the antenna HARC is copper, aluminum, cobalt, tungsten, platinum, palladium, or the like. In some embodiments, the coating is deposited, for example, by a CVD or ALD process.In some embodiments, the conductive material is deposited in the antenna HARC by sputtering.

[0053] In some embodiments, the antenna HARC is separated from the substrate and / or the layer of dielectric material that is first deposited over the ESD cells by an etch stop layer. Unlike a conductive column HARC, the antenna HARC has a smaller dimension, extending parallel to a principal axis of the TSV, than the conductive column or the portion of the TSV on the same side of the substrate as the ESD cells produced in step 602 of process 600.

[0054] The process 600 further includes a step 614 in which a silicon through-hole (SOH) is produced.

[0055] In some embodiments, the fabrication of a TSV by a semiconductor device comprises the following: depositing a layer of structuring material over a layer of dielectric material; transferring a structure onto the layer of structuring material; and exposing a top surface of the dielectric material through openings in the layer of structuring material corresponding to the transferred structure. The fabrication of a TSV by a semiconductor device further comprises the following: performing a first etching process through the layer of dielectric material to expose a substrate beneath the layer of dielectric material; and performing a second etching process to create an opening extending through the entire substrate.

[0056] The fabrication of a TSV by a semiconductor device further comprises the deposition of a conductive material in the opening through the entire substrate and through the layer of dielectric material. In some embodiments, the TSV is filled with copper, aluminum, or an alloy of copper and aluminum.

[0057] Procedure 600 further includes step 616, in which an antenna pad is manufactured.

[0058] The antenna pad is fabricated by performing the following steps: depositing a layer of patterning material over a layer of dielectric material; transferring a structure onto the layer of patterning material; and exposing a top surface of the dielectric material through openings in the layer of patterning material corresponding to the transferred structure. Fabricating the antenna pad further involves performing an etching process through the layer of dielectric material to expose [1] an end of the TSV on the same side of the substrate as the ESD cells, or [2] contacts or vias fabricated in direct contact with the end of the TSV on the same side of the substrate as the ESD cells (see, for example, contacts 512 in [reference]). Fig. 5B). The fabrication of the antenna pad further comprises depositing a conductive antenna pad material into the opening created during the etching process to expose the TSV end of the contacts that are in direct contact with the TSV end. In some embodiments, the deposit of the conductive antenna pad material comprises applying a coating layer and performing copper electroplating. In some embodiments, the deposit of the conductive antenna pad material comprises performing a sputtering process to fill the antenna pad opening.

[0059] Method 600 further comprises a step 618 in which the antenna pad is electrically connected to the antenna and the conductive column. In some embodiments, the electrical connection of the antenna pad to the antenna is carried out in step 616, in which the antenna and the TSV are each exposed during the deposition of the conductive antenna pad material, or the vias are electrically connected to the ends of the antenna and the column.

[0060] In some embodiments, the antenna pad is electrically connected to a conductive column by a conductive conductor in the same layer of dielectric material as the antenna pad. In some embodiments, the conductive antenna pad material is deposited in a trench that is created above the TSV during the antenna pad opening process, at the time when the antenna pad opening is filled with the conductive antenna pad material.

[0061] Fig. Figure 7 is a block diagram of an EPC system 700 (EPC: electronic process control) according to some embodiments. Methods for generating cell layout diagrams corresponding to some embodiments of the GAA structures described above are used, for example, with the EPC system 700 according to some embodiments of this system. In some embodiments, the EPC system 700 is a general-purpose computing device with a hardware processor 702 and a non-volatile, machine-readable storage medium 704. The storage medium 704 is encoded, among other things, with computer program code 706, i.e., a set of executable instructions; that is, it stores the computer program code 706 (or the instructions).The execution of the computer program code 706 with the hardware processor 702 is carried out (at least partially) with an EPC tool that implements at least some of the procedures described here according to one or more of the structures and procedures mentioned here.

[0062] The hardware processor 702 is electrically connected to the machine-readable storage medium 704 via a bus 718. The hardware processor 702 is also electrically connected to an I / O interface 712 via the bus 718. Furthermore, a network interface 714 is electrically connected to the hardware processor 702 via the bus 718. The network interface 714 is connected to a network 716, enabling the hardware processor 702 and the machine-readable storage medium 704 to connect to external elements via the network 716. The hardware processor 702 is configured to execute the computer program code 706, which is encoded in the machine-readable storage medium 704, so that the EPC system 700 can be used to perform at least some of the specified processes and / or procedures.In one or more embodiments, the 702 hardware processor is a main processor (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC) and / or another suitable processing unit.

[0063] In one or more embodiments, the machine-readable storage medium 704 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device). The machine-readable storage medium 704 comprises, for example, a semiconductor or solid-state memory, a magnetic tape, a removable disk, a random-access memory (RAM), a solid-state memory (ROM), a rigid magnetic disk, and / or an optical disk. In one or more embodiments in which optical disks are used, the machine-readable storage medium 704 is a compact disc read-only memory (CD-ROM), a compact disc read / write (CD-R / W), and / or a digital video disk (DVD).

[0064] In one or more embodiments, the storage medium 704 stores the computer program code 706, which is configured so that the EPC system 700 (where processing is at least partially carried out by the EPC tool) can be used to perform some or all of the specified processes and / or procedures. In one or more embodiments, the storage medium 704 also stores information that facilitates the performance of some or all of the specified processes and / or procedures. In one or more embodiments, the storage medium 704 stores process control data 708, which in some embodiments includes control algorithms, process variables and constants, setpoint ranges, setpoints, programming control data, and code for performing SPC- and / or MPC-based control (SPC: statistical process control; MPC: model predictive control) of various processes.

[0065] The EPC system 700 features the I / O interface 712. The I / O interface 712 is connected to external circuitry. In one or more embodiments, the I / O interface 712 includes a keyboard, keypad, mouse, trackball, touchpad, touchscreen, and / or cursor keys for sending information and commands to the hardware processor 702.

[0066] The EPC system 700 also features the network interface 714, which is connected to the hardware processor 702. The network interface 714 allows the EPC system 700 to communicate with the network 716, to which one or more other computer systems are connected. The network interface 714 includes wireless network interfaces, such as Bluetooth, Wi-Fi, WiMAX, GPRS, or WCDMA, or wired network interfaces, such as Ethernet, USB, or IEEE-1364. In one or more embodiments, some or all of the specified processes and / or procedures are implemented in two or more EPC systems 700.

[0067] The EPC system 700 is configured to send and receive information to and from manufacturing tools 720, which include ion implantation tools, etching tools, deposition tools, coating tools, washing tools, cleaning tools, CMP tools, testing tools, control tools, transport system tools, and / or heat treatment tools. These tools perform a defined set of manufacturing steps to produce the desired integrated circuit devices. The information includes operational data, parameter data, test data, and / or functional data used to control, monitor, and / or evaluate the execution, progress, and / or completion of the specific manufacturing process. The process tool information is stored on and retrieved from the machine-readable storage medium 704.

[0068] The EPC system 700 is configured to receive information via the I / O interface 712. The information received via the I / O interface 712 includes commands, data, programming data, design rules (which specify, for example, layer thicknesses, separation distances, specific structure and layer resistances and structure sizes), process performance curves, target ranges, setpoints, and / or other parameters for processing by the hardware processor 702. This information is sent to the hardware processor 702 via the bus 718. The EPC system 700 is also configured to receive user interface (UI) information via the I / O interface 712. This information is stored on the machine-readable medium 704 as a user interface (UI) 710.

[0069] In some embodiments, some or all of the specified processes and / or procedures are implemented as an independent software application for execution by a processor. In some embodiments, some or all of the specified processes and / or procedures are implemented as a software application that is part of another software application. In some embodiments, some or all of the specified processes and / or procedures are implemented as a plug-in for a software application. In some embodiments, at least one of the specified processes and / or procedures is implemented as a software application that is part of an EPC tool. In some embodiments, some or all of the specified processes and / or procedures are implemented as a software application used by the EPC System 700.

[0070] In some embodiments, the processes are implemented as functions of a program stored on a non-volatile, machine-readable recording medium. Examples of non-volatile, machine-readable recording media include external / removable and / or internal / built-in storage units, such as an optical disc like a DVD, a magnetic disk like a hard drive, a semiconductor memory like a ROM, RAM, and / or a memory card, or the like.

[0071] Fig. Figure 8 is a block diagram of an IC manufacturing system 800 (IC: integrated circuit) and an associated IC manufacturing process according to some embodiments for manufacturing IC devices. In some embodiments, based on a layout diagram (A), one or more semiconductor masks and / or (B) at least one component in a layer of an integrated semiconductor circuit are manufactured using the manufacturing system 800.

[0072] In Fig. Figure 8 of the IC manufacturing system 800 comprises units such as a design house 820, a mask house 830, and an IC manufacturer (“microchip factory”) 850, which interact with each other in the design, development, and manufacturing cycles and / or in the services associated with the manufacture of an IC device 860. After the manufacturing process for producing a plurality of IC devices on a wafer has been completed, the wafer is optionally transferred, depending on the device, to a back end or back end of line (BEOL) 880 for programming, electrical testing, and packaging to obtain finished IC device products. The units in the manufacturing system 800 are connected by a communication network. In some embodiments, the communication network is a single network. In other embodiments, the communication network comprises several different networks, such as an intranet and the Internet.

[0073] The communication network comprises wired and / or wireless communication channels. Each unit interacts with one or more of the other units, providing services to and / or receiving services from one or more of the other units. In some embodiments, two or more of the units—Design House 820, Mask House 830, and IC Factory 850—are owned by a single larger company. In some embodiments, two or more of the units—Design House 820, Mask House 830, and IC Factory 850—exist side-by-side in a shared facility and utilize common resources.

[0074] The design house (or design team) 820 generates an IC design layout diagram 822. The IC design layout diagram 822 contains various geometric structures designed for an IC device 860. The geometric structures correspond to structures of metal, oxide, or semiconductor layers that form the various components of the IC device 860 to be manufactured. The different layers together form various IC structural elements.

[0075] For example, part of the IC design layout diagram 822 features various IC structural elements, such as an active region, a gate electrode, a source and drain, metal traces or vias of an interlayer connection, and openings for bond pads to be fabricated in a semiconductor substrate (such as a silicon wafer) and various material layers arranged on the semiconductor substrate. The design house 820 implements a suitable design procedure for generating the IC design layout diagram 822. The design procedure includes one or more of the steps logic design, physical design, and placement and routing. The IC design layout diagram 822 is represented in one or more data files containing information about the geometric structures. The IC design layout diagram 822 can be represented, for example, in a GDSII file format or a DFII file format.

[0076] The structure of a modified IC design layout diagram is adapted using a suitable method to, for example, reduce the parasitic capacitance of the integrated circuit compared to that of an integrated circuit in a non-modified IC design layout diagram. The modified IC design layout diagram reflects the results of changing the positions of conductive traces in the layout diagram and, in some embodiments, of inserting structural elements associated with capacitive isolation structures into the IC design layout diagram to further reduce the parasitic capacitance compared to IC structures that lack the modified IC design layout diagram's structural elements for creating capacitive isolation structures.

[0077] In the mask house 830, mask data preparation 832 and mask fabrication 844 are performed. The mask house 830 uses the IC design layout diagram 822 to fabricate one or more masks (or photomasks or reticles) 845, which are to be used to fabricate the various layers of the IC device 860 according to the IC design layout diagram 822. The mask house 830 performs mask data preparation 832, in which the IC design layout diagram 822 is translated into a representative data file (RDF). During mask data preparation 832, the RDF is made available for mask fabrication 844. In mask fabrication 844, a mask writer is used. A mask writer converts the RDF into an image on a substrate, such as the mask 845 or a semiconductor wafer 853.The IC design layout diagram 822 is manipulated during mask data preparation 832 so that it corresponds to certain properties of the mask writer and / or meets the requirements of the IC factory 850. In . Fig. Figure 8 shows the mask data preparation 832 and the mask production 844 as separate elements. In some embodiments, the mask data preparation 832 and the mask production 844 can be referred to collectively as mask data preparation.

[0078] In some embodiments, the mask data preparation 832 includes optical proximity correction (OPC), which employs lithographic enhancement methods to compensate for image defects such as those that may arise from diffraction, interference, other process effects, or the like. The OPC adjusts the IC design layout diagram 822. In some embodiments, the mask data preparation 832 includes further resolution enhancement methods (RET), such as off-axis exposure, partial resolution support elements, phase-shift masks, other suitable methods, and the like, or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, in which the OPC is treated as an inverse imaging problem.

[0079] In some embodiments, during mask data preparation 832, a mask rule checker (MRC) verifies the IC design layout diagram 822, which has undergone processes in the OPC, against a set of mask generation rules that include certain geometric and / or connectivity constraints to ensure sufficient margins to accommodate variability in semiconductor manufacturing processes and the like. In some embodiments, the MRC modifies the IC design layout diagram 822 to compensate for constraints encountered during mask fabrication 844 that may undo some of the modifications made by the OPC.

[0080] In some embodiments, the mask data preparation 832 includes a lithographic process check (LPC) in which the processing is simulated that is implemented by the IC factory 850 to manufacture the IC fixture 860. In the LPC, this processing is simulated based on the IC design layout diagram 822 to generate a simulated manufactured fixture, such as the IC fixture 860. The processing parameters in the LPC simulation may include: parameters associated with various processes of the IC manufacturing cycle; parameters associated with tools used to manufacture the ICs; and / or other aspects of the manufacturing process. Various factors are considered in the LPC, such as intermediate image contrast, depth of field (DOF), mask defect improvement factor (MEEF), other suitable factors, and the like, or combinations thereof.In some embodiments, if, after the creation of a simulated manufactured device by the LPC, the simulated device deviates too much from compliance with the design rules in terms of shape, the OPC and / or the MRC must be repeated to further improve the IC design layout diagram 822.

[0081] It is understood that the foregoing description of the mask data preparation 832 has been simplified for clarity. In some embodiments, the mask data preparation 832 includes further functions, such as a logical operation (LOP) to modify the IC design layout diagram 822 according to the manufacturing rules. Furthermore, the processes used for the IC design layout diagram 822 during the mask data preparation 832 can be performed in various other sequences. After the mask data preparation 832 and during the mask manufacturing 844, a mask 845 or a group of masks 845 is manufactured based on the modified IC design layout diagram 822. In some embodiments, the mask manufacturing 844 includes performing one or more lithographic exposures based on the IC design layout diagram 822.In some embodiments, an electron beam or a multi-electron-beam mechanism is used to generate a structure on the mask 845 based on the modified IC design layout diagram 822. The mask 845 can be fabricated using various technologies. In some embodiments, the mask 845 is fabricated using binary technology. In some embodiments, a mask structure has opaque and transparent regions. A radiation beam, such as an ultraviolet (UV) beam, used to expose the photosensitive material layer (e.g., photoresist) deposited on a wafer, is blocked by the opaque region and passes through the transparent regions. In one example, a binary mask variant of the mask 845 has a transparent substrate (e.g., quartz glass) and an opaque material (e.g., chromium) deposited in the opaque regions of the binary mask.

[0082] In another example, the mask 845 is fabricated using phase-shift technology. In a phase-shift mask variant (PSM variant) of the mask 845, various elements in the structure created on the phase-shift mask are configured to have a phase difference suitable for increasing resolution and image quality. In various examples, the phase-shift mask can be a mask with a reduced phase shift or a mask with a variable phase shift. The masks produced by the mask fabrication process 844 are used in various processes. These masks are used, for example, in an ion implantation process to create different doped regions in the semiconductor wafer 853, in an etching process to create different etched regions in the semiconductor wafer 853, and / or in other suitable processes.The IC factory 850 further includes a wafer fabrication facility 852. The IC factory 850 is an IC manufacturing operation with one or more production sites for manufacturing several different IC products. In some embodiments, the IC factory 850 is a semiconductor manufacturing facility. For example, one production site may handle the front-end manufacturing of multiple IC products (FEOL manufacturing), while a second production site may handle the back-end manufacturing for interconnecting and packaging the IC products (BEOL manufacturing), and a third production site may provide other services for the manufacturing operation.

[0083] Wafer fabrication 852 comprises the fabrication, on a semiconductor substrate, of a structured layer of a mask material comprising one or more layers of photoresist, polyimide, silicon oxide, silicon nitride (e.g., Si3N4, SiON, SiC, SiOC), or combinations thereof. In some embodiments, the mask 845 has only one layer of mask material. In some embodiments, the mask 845 has multiple layers of mask materials.

[0084] In some embodiments, the mask material is structured by exposure to an exposure source. In some embodiments, the exposure source is an electron beam source. In some embodiments, the exposure source is a lamp that emits light. In some embodiments, the light is ultraviolet light (UV light). In some embodiments, the light is visible light. In some embodiments, the light is infrared light. In some embodiments, the exposure source emits a combination of different types of light (UV light, visible light, and infrared light).

[0085] Following the mask structuring steps, areas not covered by the mask, such as fins in open regions of the structure, are etched to modify the dimensions of one or more structures in the exposed areas. In some embodiments, the etching is performed by plasma etching or with a liquid chemical etching solution. The chemicals of the liquid chemical etching solution include one or more etchants, such as citric acid (C6H8O7), hydrogen peroxide (H2O2), nitric acid (HNO3), sulfuric acid (H2SO4), hydrochloric acid (HCl), acetic acid (CH3CO2H), hydrofluoric acid (HF), buffered hydrofluoric acid (BHF), phosphoric acid (H3PO4), aluminum fluoride (NH4F), potassium hydroxide (KOH), ethylenediaminepyrocatechol (EDP), tetramethylammonium hydroxide (TMAH), or combinations thereof.

[0086] In some embodiments, the etching process is a dry etching process or a plasma etching process. Plasma etching of a substrate material is carried out using halogen-containing reactive gases that are excited by an electromagnetic field to dissociate into ions. Reactive or etching gases include, for example, CF4, SF6, NF3, Cl2, CCL2F2, SiCl4, BCl2, or a combination thereof, but other semiconductor material etching gases are also within the scope of the invention. Ions are accelerated by alternating electromagnetic fields or by fixed bias voltages according to plasma etching methods known in the field so that they impact the exposed material.

[0087] In some embodiments, the exposed structures in the functional areas are subjected to an oxygen-containing atmosphere during the etching process to oxidize an outer portion of the exposed structures. Subsequently, a chemical trimming process, such as plasma etching or wet etching, is performed to remove the oxidized material, leaving a modified structure. In some embodiments, oxidation followed by a chemical trimming process is used to provide greater dimensional selectivity for the exposed material and to reduce the risk of accidental material removal during a manufacturing process. In some embodiments, the exposed structures comprise nanolayers and / or gate structures of GAA devices, with the gate structures embedded in a dielectric support medium that covers the sides of the gate structures.In some embodiments, the exposed parts of the gate structures of the functional area are the top and side walls of the gate structures, which are located above a top surface of the dielectric support medium, wherein the top surface of the dielectric support medium has been recessed to a level below the top surface of the nanolayer stacks, but still covers a lower part of the side walls of the nanolayer stack.

[0088] In IC Factory 850, the masks 845, manufactured by Mask House 830, are used to manufacture IC Device 860. Thus, IC Factory 850 uses, at least indirectly, the IC Design Layout Diagram 822 to manufacture IC Device 860. In some embodiments, IC Factory 850 manufactures the semiconductor wafer 853 using the masks 845 to produce IC Device 860. In some embodiments, IC manufacturing includes performing one or more lithographic exposures based, at least indirectly, on IC Design Layout Diagram 822. The semiconductor wafer 853 has a silicon substrate or other suitable substrate on which layers of material are produced. The semiconductor wafer 853 further features one or more different doped regions, dielectric structural elements, multi-layer interconnects, and the like (which are produced in later manufacturing steps).

[0089] Fig. Figure 9 is a schematic representation of various processing departments defined in a chip factory, front-end, or IC manufacturing facility, according to some embodiments described in Fig. 7, particularly in blocks 708 and 720, and in Fig. 8, in particular in block 850, are proposed. The machining sections used in the FEOL-IC fixture manufacturing include a wafer transport system 902 for conveying the wafers between the different machining sections. In some embodiments, the wafer transport is carried out using an EPC system according to Fig.7 is integrated and is used to provide process control operations that ensure the wafers are processed at the correct time and transported sequentially to the appropriate processing sections as defined by the process flow. In some embodiments, the EPC system also provides control and / or quality assurance and parameter data for the proper operation of the specified processing equipment. The various processing sections, which perform, for example, photolithographic steps 904, etching steps 906, ion implantation steps 908, cleaning / removal steps 910, CMP steps 912, epitaxial growth steps 914, deposition steps 916, and heat treatments 918, are interconnected by the wafer transport system 902.

[0090] Details regarding IC manufacturing systems and related IC manufacturing processes can be found, for example, in the following documents, each incorporated by reference: U.S. Patent No. 9,256,709, issued on February 9, 2016; U.S. Pre-Finalization Publication No. 20150278429, issued on October 1, 2015; U.S. Pre-Finalization Publication No. 20140040838, issued on February 6, 2014; and U.S. Patent No. 7,260,442, issued on August 21, 2007.

[0091] The present invention describes a semiconductor device in which an antenna array is arranged vertically (e.g., parallel to a main axis of a semiconductor device) in a front-end-of-line (FEOL) and back-end-of-line (BEOL) exclusion zone of the semiconductor device around the semiconductor device. The antenna array is arranged partially or completely around the circumference of the semiconductor device. A grounding ring extends around the semiconductor device in the same plane as the substrate top surface in the semiconductor device. ESD protection for the semiconductor device is provided by ESD cells arranged in the substrate plane within the semiconductor device. The ESD cells comprise a plurality of diodes connected electrically in parallel and connected by a conductive pillar to an antenna pad at an upper end of the semiconductor device (e.g., the end on the same side of the substrate as the ESD cells). The ESD cells are electrically connected to the antenna array via the antenna pad.The number of diodes in the ESD cells is at least 2 and at most 20. In some embodiments, the conductive column and the antennas of the antenna group are high aspect ratio contacts (HARCs) or HARC structures.

[0092] Aspects of the present invention relate to a semiconductor device comprising: a silicon through-hole (TSV) in a TSV zone in a substrate, wherein the TSV extends through the substrate; an ESD cell near a first end of the TSV and in contact with the TSV zone, the ESD cell comprising a group of diodes connected electrically in parallel; an antenna pad electrically connected to a second end of the TSV; an antenna electrically connected to the antenna pad and extending in a first direction, the first direction being parallel to a principal axis of the TSV; and a conductive pillar extending parallel to the TSV on the same side of the substrate as the antenna pad in the first direction.wherein a first end of the conductive column is electrically connected to the antenna pad and a second end of the conductive column is electrically connected to the group of diodes of the ESD cell. In some embodiments, the antenna pad is in direct contact with the second end of the TSV. In some embodiments, the antenna is arranged with a first separation distance from the TSV, and the conductive column is arranged with a second separation distance from the TSV, the second separation distance being greater than the first separation distance. In some embodiments, the semiconductor device further comprises a group of antenna lines extending parallel to the TSV with the first separation distance from the TSV and distributed around a circumference of the TSV.wherein the first separation distance is a smaller distance than the smallest distance between the TSV and a boundary of the TSV zone. In some embodiments, the semiconductor device further comprises a group of ESD cells near the first end of the TSV, wherein the group of ESD cells is arranged along a boundary of the TSV zone and extends around the TSV zone. In some embodiments, the number of diodes in each ESD cell is at least 2 and at most 20. In some embodiments, the conductive column comprises a group of vias and conductor segments. In some embodiments, the antenna comprises a conductive material with a smooth sidewall.

[0093] Aspects of the present invention relate to a method for fabricating a semiconductor device comprising the following steps: fabricating an ESD cell for the semiconductor device over a substrate, wherein the ESD cell comprises several diodes connected in parallel; fabricating a conductive column electrically connected to the ESD cell of the semiconductor device; fabricating a silicon via (TSV) extending through the substrate, wherein the TSV extends through the substrate in a TSV zone with a TSV zone boundary, and a first end of the TSV is arranged on the same side of the substrate as the ESD cell, and a second end of the TSV is arranged on a different side of the substrate than the ESD cell; fabricating an antenna extending parallel to the TSV on the same side of the substrate as the ESD cell;and fabricating an antenna pad in electrical connection with the TSV, the antenna, and the conductive column. In some embodiments, fabricating an ESD cell includes fabricating the ESD cell along the TSV zone boundary outside the TSV zone. In some embodiments, fabricating the antenna further includes fabricating the antenna between the TSV zone boundary and a side wall of the TSV. In some embodiments, fabricating the antenna further includes performing an etching process to create a high aspect ratio contact through dielectric material over the substrate. In some embodiments, the method further includes steps to fabricate a grounding ring over the substrate near the ESD cells and the TSV zone.

[0094] Aspects of the present invention relate to a semiconductor device comprising: a silicon through-hole (TSV) extending through a substrate and a TSV zone of a semiconductor device interconnect structure; a group of ESD cells near a first side of the substrate, wherein the group of ESD cells extends around a circumference of the TSV and each ESD cell of the group of ESD cells comprises a group of diodes connected electrically in parallel, and a first end of the TSV is located on a different side of the substrate than the group of ESD cells and a second end of the TSV is located on the same side of the substrate as the group of ESD cells; a group of conductive pillars, wherein a first end of each conductive pillar is electrically connected to an ESD cell and a second end of each conductive pillar is located near the second end of the TSV; an antenna pad,wherein the antenna pad is located near the second end of the TSV and is electrically connected to the second end of the TSV and the conductive columns of the group of conductive columns; and a group of antennas,which extend through the TSV zone parallel to the TSV and are electrically connected to the antenna pad. In some embodiments, each ESD cell in the group of ESD cells has the same number of diodes. In some embodiments, the number of diodes in each ESD cell is at least 2 and at most 20. In some embodiments, each antenna in the group of antennas further comprises a high-aspect-ratio antenna contact (antenna HARC). In some embodiments, each conductive column in the group of conductive columns further comprises a high-aspect-ratio ESD contact (ESD HARC). In some embodiments, each conductive column in the group of conductive columns further comprises a plurality of contacts and conductive lines.which electrically connect a corresponding ESD cell of the group of ESD cells to the antenna pad. In some embodiments, the antenna pad is in direct contact with the second end of the TSV.

Claims

[1] Semiconductor device with: a silicon through-hole TSV (202a, 202b) in a TSV zone (Z1) in a substrate (302), wherein the TSV (202a, 202b) extends through the substrate (302); an ESD cell (306a, 306b) near a first end of the TSV (202a, 202b) and in contact with the TSV zone (Z1), wherein the ESD cell (306a, 306b) has a group of diodes (412a to 412i) connected electrically in parallel with each other; an antenna pad (314, 512) which is electrically connected to a second end of the TSV (202a, 202b); an antenna (316a, 316b) electrically connected to the antenna pad (314, 512) and extending in a first direction (298), the first direction being parallel to a principal axis of the TSV (202a, 202b); and a conductive column (310a, 310b) extending parallel to the TSV (202a, 202b) on the same side of the substrate (302) as the antenna pad (314, 512) in the first direction (298), wherein a first end (311) of the conductive column (310a, 310b) is electrically connected to the antenna pad (314, 512) and a second end (313) of the conductive column (310a, 310b) is electrically connected to the group of diodes (412a to 412i) of the ESD cell (306a, 306b). [2] Semiconductor device according to claim 1, wherein the antenna pad (314, 512) is in direct contact with the second end of the TSV (202a, 202b). [3] Semiconductor device according to claim 1, wherein the antenna (316a, 316b) is arranged with a first separation distance from the TSV (202a, 202b) and the conductive column (310a, 310b) is arranged with a second separation distance from the TSV (202a, 202b), wherein the second separation distance is greater than the first separation distance. [4] Semiconductor device according to claim 3, further comprising a group of antenna lines extending parallel to the TSV (202a, 202b) with the first separation distance from the TSV (202a, 202b) and distributed around a circumference of the TSV (202a, 202b), wherein the first separation distance is a smaller distance than a minimum distance between the TSV (202a, 202b) and a boundary of the TSV zone (Z1). [5] Semiconductor device according to one of the preceding claims, further comprising a group of ESD cells (306a, 306b) near the first end of the TSV (202a, 202b), wherein the group of ESD cells (306a, 306b) is arranged along a boundary of the TSV zone (Z1) and extends around the TSV zone (Z1). [6] Semiconductor device according to any of the preceding claims, wherein the number of diodes in each ESD cell (306a, 306b) is at least 2 and at most 20. [7] Semiconductor device according to one of the preceding claims, wherein the conductive column (310a, 310b) comprises a group of vias and conductor segments. [8] Semiconductor device according to one of the preceding claims, wherein the antenna (316a, 316b) has a conductive material with a smooth side wall. [9] Method for manufacturing a semiconductor device comprising the following steps: Manufacturing an ESD cell (306a, 306b) for the semiconductor device over a substrate (302), wherein the ESD cell (306a, 306b) has several diodes connected in parallel with each other; Producing a conductive column (310a, 310b) that is electrically connected to the ESD cell (306a, 306b) of the semiconductor device; Fabricating a silicon via, TSV (202a, 202b), such that it extends through the substrate (302), wherein the TSV (202a, 202b) extends through the substrate (302) in a TSV zone (Z1) with a TSV zone boundary and a first end (311) of the TSV (202a, 202b) is arranged on the same side of the substrate (302) as the ESD cell (306a, 306b) and a second end (313) of the TSV (202a, 202b) is arranged on a different side of the substrate (302) than the ESD cell (306a, 306b); Constructing an antenna (316a, 316b) such that it extends parallel to the TSV (202a, 202b) on the same side of the substrate (302) as the ESD cell (306a, 306b); and Producing an antenna pad (314, 512) such that it is electrically connected to the TSV (202a, 202b), the antenna (316a, 316b) and the conductive column (310a, 310b). [10] Method according to claim 9, wherein the fabrication of an ESD cell (306a, 306b) further comprises fabricating the ESD cell (306a, 306b) along the TSV zone boundary outside the TSV zone (Z1). [11] Method according to claim 10, wherein the production of the antenna (316a, 316b) further comprises the production of the antenna (316a, 316b) between the TSV zone boundary and a side wall of the TSV (202a, 202b). [12] Method according to any one of claims 9 to 11, wherein the production of the antenna (316a, 316b) further comprises carrying out an etching process to produce a high aspect ratio contact through dielectric material over the substrate (302). [13] Method according to any one of claims 9 to 12, further comprising producing a grounding ring (319) over the substrate (302) in the vicinity of the ESD cells (306a, 306b) and the TSV zone (Z1). [14] Semiconductor device with: a silicon through-hole TSV (202a, 202b) extending through a substrate (302) and a TSV zone (Z1) of a semiconductor device interconnect structure; a group of ESD cells (306a, 306b) near a first side of the substrate (302), the group of ESD cells (306a, 306b) extending around a circumference of the TSV (202a, 202b), each ESD cell (306a, 306b) of the group of ESD cells (306a, 306b) having a group of diodes (412a to 412i) connected electrically in parallel, and a first end (311) of the TSV (202a, 202b) being located on a different side of the substrate (302) than the group of ESD cells (306a, 306b), and a second end (313) of the TSV (202a, 202b) being located on the same side of the substrate (302) as the group of ESD cells (306a, 306b). 306b) is ordered; a group of conductive columns (310a, 310b), wherein a first end (311) of each conductive column (310a, 310b) is electrically connected to an ESD cell (306a, 306b) and a second end (313) of each conductive column (310a, 310b) is arranged near the second end of the TSV (202a, 202b); an antenna pad (314, 512), wherein the antenna pad (314, 512) is arranged near the second end of the TSV (202a, 202b) and is electrically connected to the second end of the TSV (202a, 202b) and the conductive columns (310a, 310b) of the group of conductive columns (310a, 310b); and a group of antennas (316a, 316b) extending through the TSV zone (Z1) parallel to the TSV (202a, 202b) and electrically connected to the antenna pad (314, 512). [15] Semiconductor device according to claim 14, wherein each ESD cell (306a, 306b) of the group of ESD cells (306a, 306b) has the same number of diodes. [16] Semiconductor device according to claim 15, wherein the number of diodes in each ESD cell (306a, 306b) of the group of ESD cells (306a, 306b) is at least 2 to at most 20. [17] Semiconductor device according to any one of claims 14 to 16, wherein each antenna (316a, 316b) of the group of antennas (316a, 316b) further comprises an antenna contact with a high aspect ratio. [18] Semiconductor device according to any one of claims 14 to 17, wherein each conductive column (310a, 310b) of the group of conductive columns (310a, 310b) further comprises a high aspect ratio ESD contact. [19] Semiconductor device according to any one of claims 14 to 18, wherein each conductive column (310a, 310b) of the group of conductive columns (310a, 310b) further comprises a plurality of contacts and conductive lines that electrically connect a corresponding ESD cell (306a, 306b) of the group of ESD cells (306a, 306b) to the antenna pad (314, 512). [20] Semiconductor device according to one of claims 14 to 19, wherein the antenna pad (314, 512) is in direct contact with the second end of the TSV (202a, 202b).

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