IC CHIP STRUCTURES AND METHODS FOR THEIR MANUFACTURE

Abstract

Method for manufacturing an integrated chip structure comprising the following steps: Production (1902) of a first-material intermediate layer (1304) over a substrate; Production (1904) of a second-material interlayer (1306) on the first-material interlayer (1304); Structuring (1906) the second-material interlayer (1306) to produce an insulating layer (106); Structuring (1908) the first-material intermediate layer (1304) to produce a first-material layer (104) with an outermost side wall (104s) inset inwards from an outermost side wall (106s) of the insulating layer (106); Performing (1912) an ion bombardment process on the insulating layer (106) to remove one or more atoms from the insulating layer (106); and Performing (1914) a redeposition process to redeposit the one or more atoms on the outermost side wall (104s) of the first material layer (104) and to produce a self-filling spacer (112) under the insulating layer (106), wherein the self-filling spacer (112) is produced by a plurality of cycles, each comprising the ion bombardment process (1912) followed by the re-deposition process (1914).

Description

BACKGROUND

[0001] Modern integrated chips are manufactured on semiconductor wafers using hundreds of sequential process steps. Two common process steps in integrated chip manufacturing are deposition and patterning. A deposition process is a process in which a material is deposited onto a wafer. A patterning process is a process in which a mask is created over a material, and the material is then etched according to the mask to remove selected areas of the material.

[0002] US Patent 2008 / 0116493 A1 discloses a method for manufacturing a multilayer spacer with a depression no larger than the thickness of the first spacer sublayer. US Patent 2008 / 0220584 A1 discloses a method for forming integrated circuit structures using a sputtering process to fill valleys on the insulating layer. US Patent 2003 / 0011080 A1 discloses a method for manufacturing oxide film spacers, wherein cavities in the oxide film spacers are filled with dielectric material. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Aspects of this disclosure are best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not shown to scale. In fact, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. Fig. Figure 1 shows a sectional view of some embodiments of an integrated chip structure having a double-layer structure with a self-filling spacer configured to reduce stress on an overlying layer. The Fig. Figures 2A-2B show some embodiments of an integrated chip structure that has a double-layer structure with a self-filling spacer. The Fig. Figures 3A-3C show some embodiments of an integrated chip structure comprising a transistor device enclosed by a sidewall spacer having a self-filling spacer. The Fig. Figures 4A-4B show sectional views of some further embodiments of an integrated chip structure comprising a transistor device enclosed by a sidewall spacer having a self-filling spacer. Fig. Figure 5 shows a sectional view of some further embodiments of an integrated chip structure comprising a transistor device enclosed by a sidewall spacer having a self-filling spacer. Fig. Figure 6 shows a sectional view of some further embodiments of an integrated chip structure comprising a transistor device enclosed by a sidewall spacer having a self-filling spacer. Fig. Figure 7 shows a sectional view of some further embodiments of an integrated chip structure comprising a transistor device enclosed by a sidewall spacer having a self-filling spacer. The Fig. Figures 8A-8B show sectional views of some further embodiments of an integrated chip structure comprising a transistor device enclosed by a sidewall spacer having a self-filling spacer. Fig. Figure 9 shows a sectional view of some further embodiments of an integrated chip structure comprising a transistor device enclosed by a sidewall spacer having a self-filling spacer. Fig. Figure 10 shows a sectional view of some embodiments of an integrated chip structure comprising various types of devices having sidewall spacers, each with a self-filling spacer. The Fig. Figures 11-18B show sectional views illustrating some embodiments of a method for manufacturing an integrated chip structure comprising a transistor device enclosed by a sidewall spacer having a self-filling spacer. Fig. Figure 19 shows a flowchart of some embodiments of a method for manufacturing an integrated chip structure having a double-layer structure with a self-filling spacer. DETAILED DESCRIPTION

[0004] The following description provides many different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present invention. For example, the fabrication of a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are fabricated in direct contact, and it may also include embodiments in which additional elements can be fabricated between the first and second elements, such that the first and second elements are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in the various examples in the present invention.This repetition serves the purpose of simplicity and clarity and does not in itself prescribe any relationship between the various designs and / or configurations discussed.

[0005] Furthermore, spatially relative terms, such as "located below," "under," "lower," "located above," "upper," and the like, can be used here to simply describe the relationship of an element or structure to one or more other elements or structures depicted in the figures. These spatially relative terms are intended to encompass orientations of the device in use or operation beyond the orientation shown in the figures. The device may be oriented differently (rotated by 90 degrees or in a different orientation), and the spatially relative descriptors used here can be interpreted accordingly.

[0006] During the fabrication of an integrated chip structure, multiple layers can be deposited on top of each other in a single manufacturing process before the layers are patterned. For example, during the fabrication of a sidewall spacer, a first layer is deposited over a substrate and along one side of an electrode (e.g., a gate electrode). Subsequently, a second layer is deposited over the first layer. The first and second layers are then patterned using one or more etching processes to fabricate the sidewall spacer. Due to differences in the etch selectivities between the first and second layers, the one or more etching processes may laterally etch the first layer faster than the second layer.If the first layer is etched faster than the second layer, this can cause the second layer to overhang the first layer and form a cavity on one side of the multilayer structure.

[0007] Overhanging the first layer of a second layer can cause problems during subsequent manufacturing processes. For example, when another layer is fabricated on top of the first and second layers, the additional layer is built continuously along multiple surfaces (such as a top, bottom, and sidewall) of the overhanging portion of the second layer. However, as the thickness of the additional layer increases, its surface area is enlarged, and the additional layer expands to cover this larger area. This expansion creates stress in the additional layer. This stress can cause cracks in the additional layer, leading to structural instability in the integrated chip structure. This structural instability can then lead to reliability issues.For example, if cracks form in the walls of a sidewall spacer located near metal structural elements (e.g., a conductive contact), metal can penetrate the cracks, leading to undesirable conductive paths that can cause reduced reliability (e.g., increased time-dependent dielectric breakdown), short circuits, and even yield losses and / or failure of integrated chips.

[0008] The present disclosure relates to an integrated chip structure comprising a self-filling spacer configured to fill a cavity formed during an etching process in a sidewall of a bilayer structure, in order to reduce stress on a layer located above the bilayer structure. In some embodiments, the integrated chip structure may have a first-material layer arranged over a substrate and having an outermost sidewall. An insulating layer is arranged above the first-material layer. The insulating layer extends from a position lateral directly above the first-material layer to a position lateral beyond the outermost sidewall of the first-material layer, thus defining a cavity located beneath the insulating layer. A self-filling spacer is arranged within the cavity.A dielectric layer is positioned above the insulating layer and along the sidewalls of both the insulating layer and the self-filling spacer. Because the self-filling spacer fills the cavity beneath the insulating layer, the dielectric layer is not formed along the underside of the insulating layer, thus reducing stress on the dielectric layer. Reducing stress on the dielectric layer mitigates cracking in the dielectric layer, thereby reducing damage to the dielectric layer and improving the reliability of the integrated chip structure.

[0009] Fig. Figure 1 shows a sectional view of some embodiments of an integrated chip structure 100, which has a double-layer structure with a self-filling spacer.

[0010] The integrated chip structure 100 comprises a substrate 102. In various embodiments, the substrate 102 can comprise any type of semiconductor body (e.g., silicon, SiGe, SOI (silicon on insulator), etc.), such as a semiconductor wafer and / or one or more dies on a wafer, as well as any other type of semiconductor and / or epitaxial layers associated therewith. In some embodiments, the substrate 102 can comprise one or more dielectric layers, one or more inter-level dielectric layers (ILD layers), and / or one or more interconnects arranged over a semiconductor body.

[0011] A multilayer structure is arranged over the substrate 102. The multilayer structure comprises a first-material layer 104 arranged over the substrate 102 and an insulating layer 106 arranged over the first-material layer 104. The first-material layer 104 and the insulating layer 106 are made of different materials. The first-material layer 104 has an outermost sidewall 104s that is indented (e.g., laterally recessed) from an outermost sidewall 106s of the insulating layer 106 by a non-zero distance 108, such that the insulating layer 106 overhangs the first-material layer 104. In some embodiments, the non-zero distance 108 can be in a range between approximately 30% and approximately 100% of the thickness of the first-material layer 104.The overhang of the insulating layer 106 forms a cavity 110, which is defined by the outermost side wall 104s of the first material layer 104 and a bottom surface of the insulating layer 106.

[0012] A self-filling spacer 112 is arranged in the cavity 110. The self-filling spacer 112 fills the cavity 110, so that the underside of the insulating layer 106 and the outermost side wall 104s of the first-material layer 104 are covered. In some embodiments, the insulating layer 106 and the self-filling spacer 112 completely cover an outermost edge of the first-material layer 104. In these embodiments, the self-filling spacer 112 has a non-zero thickness 114 along the outermost edge of the first material layer 104. In some embodiments, the non-zero thickness is less than the non-zero distance 108. In some embodiments, the insulating layer 106 and the self-filling spacer 112 together form a smooth outer surface facing away from the first material layer 104.In some embodiments, the insulating layer 106 and the self-filling spacer 112 have the same material, which extends continuously from a position in the insulating layer 106 to a position along the outermost side wall 104s of the first material layer 104.

[0013] A further layer is arranged above the insulating layer 106 and along an outermost side wall of the self-filling spacer 112. In some embodiments, the further layer may comprise a dielectric layer 116, which is arranged above the insulating layer 106 and along the outermost side walls of both the insulating layer 106 and the self-filling spacer 112. Because the self-filling spacer 112 fills the cavity 110 located beneath the insulating layer 106, the dielectric layer 116 does not extend along the underside of the insulating layer 106. Since the dielectric layer 116 does not extend along the underside of the insulating layer 106, stress on the dielectric layer 116 is reduced, thereby decreasing the formation of cracks in the dielectric layer 116.By reducing the formation of cracks in the dielectric layer 116, reliability problems of the integrated chip structure 100 can be mitigated, and the performance and / or yield of the integrated chip structure 100 can be improved.

[0014] Fig. Figure 2A shows a sectional view of some embodiments of an integrated chip structure 200, which has a double-layer structure with a self-filling spacer.

[0015] The integrated chip structure 200 comprises a device structure 202 arranged on a substrate 102. In various embodiments, the device structure 202 can comprise a transistor-gate structure, a memory device (e.g., a resistive random access memory device (RRAM), a magnetoresistive random access memory device (MRAM), a conductive bridging random access memory device (CBRAM), a magnetic tunnel junction device (MTJ), etc.), a passive device (e.g., a capacitor, an inductor, etc.), or the like.

[0016] A sidewall spacer 204 is arranged on opposite sides of the device structure 202. In some embodiments, the sidewall spacer 204 can have a plurality of layers stacked on top of each other. For example, in some embodiments, the sidewall spacer 204 can have a first-material layer 104 arranged between a lower dielectric layer 206 and an insulating layer 106. The lower dielectric layer 206 is arranged above the substrate 102 and along a sidewall of the device structure 202. The first-material layer 104 is arranged along a sidewall and a top surface of the lower dielectric layer 206, and the insulating layer 106 is arranged along a sidewall and a top surface of the first-material layer 104.In some embodiments, the first material layer 104 comprises a vertically extending segment 104v that extends along the side wall of the device structure 202, and a horizontally extending segment 104h that projects outward from a side wall of the vertically extending segment 104v. The first material layer 104 has an outermost side wall 104s that is laterally indented from an outermost edge of the insulating layer 106, such that a cavity 110 is formed beneath an outer edge of the insulating layer 106.

[0017] In some embodiments, the lower dielectric layer 206 may comprise and / or be a first dielectric material, such as an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride), or the like. In some embodiments, the first-material layer 104 may comprise and / or be a conductive or non-conductive material. In various embodiments, for example, the first-material layer 104 may comprise and / or be a metal, a metal alloy, an oxide, a nitride, a carbide, an oxide nitride, an oxide carbide, a polymer, a metal oxide, a metal nitride, or the like. In some embodiments, the insulating layer 106 may comprise and / or be a second dielectric material, such as an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride), a carbide, an oxide nitride, an oxide carbide, a polymer, or the like.

[0018] A self-filling spacer 112 is arranged along the outermost side wall 104s of the first-material layer 104 and beneath a bottom surface of the insulating layer 106. The self-filling spacer 112 extends from a position directly beneath the bottom surface of the insulating layer 106 to an outer edge of the insulating layer 106, thus filling the cavity 110. In some embodiments, the self-filling spacer 112 can extend further from a position directly beneath the first-material layer 104 to a position laterally beyond an outermost edge of the first-material layer 104. The self-filling spacer 112 comprises at least one of the materials of the insulating layer 106. The self-filling spacer 112 has a first side wall facing the first-material layer 104, which contacts a side wall of the first-material layer 104.The self-filling spacer 112 also has a second side wall that faces away from the first material layer 104.

[0019] A dielectric layer 116 is arranged on the insulating layer 106 and along the second side wall of the self-filling spacer 112. In some embodiments, the dielectric layer 116 may comprise a nitride (e.g., silicon nitride, silicon oxide nitride, or the like), a carbide (e.g., silicon carbide, silicon oxide carbide, or the like), or other similar materials. In some embodiments, the dielectric layer 116 is configured to act as an etch stop layer. In some embodiments, the outer edge of the insulating layer 106 may be rounded.While a rounded shape of the outer edge of the insulating layer 106 without the self-filling spacer 112 would lead to a relatively large stress on the dielectric layer 116 (since it would increase the extent of the dielectric layer 116), the self-filling spacer 112 reduces stress on the dielectric layer 116 by filling the cavity 110 under the insulating layer 106.

[0020] An inter-level dielectric structure (ILD structure) 118 is arranged on the dielectric layer 116. In some embodiments, the ILD structure 118 may comprise one or more silicon dioxide, carbon-doped silicon dioxide (SiCOH), phosphosilicate glass (PSG), boron phosphosilicate glass (BPSG), fluorosilicate glass (FSG), undoped silicate glass (USG), or the like. The ILD structure 118 laterally encloses one or more interconnects 208 that extend through the ILD structure 118 to contact the device structure 202 and / or source / drain regions 308. In some embodiments, the one or more interconnects 208 may have conductive contacts. To increase the density of transistor devices in an integrated chip, one or more interconnects 208 can be positioned at a small distance from an outer side wall of the side wall spacer 204 (e.g.from an outer side wall of the first material layer 104 and / or the insulating layer 106). The self-filling spacer 112 reduces the probability of metal from the one or more interconnects 208 forming in cracks in the dielectric layer 116, thereby mitigating electrical short circuits and / or reliability problems (e.g., time-dependent dielectric breakdown) in the integrated chip structure 200.

[0021] Fig. Figure 2B shows a top view 210 of some embodiments of the integrated chip structure 200 of Fig. 2A. Top view 210 of Fig. 2B was built along line AA' by Fig. 2A taken while the section view of Fig. 2A along line BB' from Fig. 2B was taken.

[0022] As shown in plan view 210, the first material layer 104 and the self-filling spacer 112 enclose the device structure 202 in a closed loop. The outermost side wall 104s of the first material layer 104 extends in a closed path located directly beneath the insulating layer (not shown), such that the self-filling spacer 112 extends continuously around an outer circumference of the first material layer 104 in a ring shape, extending along a first direction 212 and along a second direction 214, which is perpendicular to the first direction 212.

[0023] Fig. Figure 3A shows a sectional view of some embodiments of an integrated chip structure 300, which includes a transistor having a sidewall spacer with a self-filling spacer.

[0024] The integrated chip structure 300 comprises a transistor device arranged in a substrate 102. The transistor device includes a gate structure 302 arranged above the substrate 102. The gate structure 302 has a gate electrode 304 separated from the substrate 102 by a gate dielectric 306. Source / drain regions 308 are arranged in the substrate 102 on opposite sides of the gate structure 302. In some embodiments, one or more isolation structures 310 are arranged in the substrate 102 and surround the source / drain regions 308. In some embodiments, one or more isolation structures 310 may have a shallow trench isolation (STI) structure.

[0025] A sidewall spacer 204 is arranged on opposite sides of the gate structure 302. In some embodiments, the sidewall spacer 204 may have a first-material layer 104 arranged between a lower dielectric layer 206 and an insulating layer 106. The lower dielectric layer 206 is arranged above the substrate 102 and along a sidewall of the device structure 202. The first-material layer 104 is arranged along a sidewall and a top surface of the lower dielectric layer 206, and the insulating layer 106 is arranged along a sidewall and a top surface of the first-material layer 104.

[0026] A self-filling spacer 112 is arranged along an outermost side wall 104s of the first-material layer 104 and beneath a bottom surface of the insulating layer 106. In some embodiments, the self-filling spacer 112 can be substantially triangular in shape, as shown in the sectional view. In other embodiments, the self-filling spacer 112 can be a different shape (e.g., trapezoidal, inverted trapezoidal, inverted triangle, rectangle, square, or the like). A dielectric layer 116 is arranged on the insulating layer 106 and the self-filling spacer 112, and an ILD structure 118 is arranged on the dielectric layer 116.

[0027] Fig. Figure 3B shows a sectional view 312 of a segment of the integrated chip structure 300, which is located in Fig. 3A is shown.

[0028] As shown in section view 312, the self-filling spacer 112 can have a bottom surface that is wider than a top surface of the self-filling spacer 112. In some embodiments, the self-filling spacer 112 can have a bottom surface that has a first width 314. The self-filling spacer 112 extends beyond an outermost edge of the first material layer 104 by a second width 316, which is smaller than the first width 314. In some embodiments, the self-filling spacer 112 can have a first side wall 112s1 facing the first material layer 104 and a second side wall 112s2 facing away from the first material layer 104. In some embodiments, the first side wall 112s1 can be an inclined side wall.For example, the first side wall 112s1 can be oriented at a first angle 318 which, measured by the self-filling spacer 112, is an acute angle with respect to the underside of the self-filling spacer 112. In some further embodiments, the first side wall 112s1 can be curved. In some embodiments, the second side wall 112s2 can be substantially vertical with respect to the underside of the self-filling spacer 112 (e.g., measured by the self-filling spacer 112, oriented at an angle 320 of approximately 90°).

[0029] In some embodiments, the insulating layer 106 can have a first part 106a, which is arranged along an interface with a top surface of the first-material layer 104, and a second part 106b, which is arranged along an opposite outer surface of the insulating layer 106. The first part 106a is a first material and / or comprises it. The second part 106b is the first material and / or comprises one or more additional atoms and / or ions (e.g., argon, oxygen, or the like). For example, the first part 106a can comprise an insulating material (e.g., an oxide, a nitride, a carbide, or the like), while the second part 106b can comprise the insulating material (e.g., the oxide, the nitride, the carbide, or the like) together with one or more additional atoms and / or ions (e.g., argon, oxygen, or the like).In some embodiments, one or more of the additional atoms and / or ions may contain the same element that is in the insulating material (e.g. oxygen), so that the second part 106b has a higher concentration of the element than the first part 106a.

[0030] Fig. Figure 3C shows a diagram 322 illustrating several embodiments of a concentration 324 of one or more additional atoms and / or ions as a function of their position in the insulating layer 106. As shown in diagram 322, the concentration 324 of one or more additional atoms and / or ions in the first part 106a of the insulating layer 106 has a first value that is low (e.g., essentially 0). However, in the second part 106b of the insulating layer 106, the concentration 324 of the one or more additional atoms and / or ions has a second value that is significantly higher than the first value. The higher concentration of the one or more additional atoms and / or ions is due to the redeposition of atoms from the insulating layer 106 together with one or more additional atoms and / or ions used to remove the atoms from the insulating layer 106.

[0031] In some embodiments, the self-filling spacer 112 can be made of the same material as the second part 106b of the insulating layer 106. In these embodiments, the self-filling spacer 112 can comprise the first material along with one or more additional atoms and / or ions. In some embodiments, the self-filling spacer 112 can have a maximum width that is greater than the maximum thickness of the second part 106b of the insulating layer 106. The greater maximum width of the self-filling spacer 112 allows the insulating layer 106 and the self-filling spacer 112 to form a smooth outer surface.

[0032] Fig. Figure 4A shows a sectional view of some further embodiments of an integrated chip structure 400, which has a transistor device enclosed by a sidewall spacer having a self-filling spacer.

[0033] The integrated chip structure 400 comprises a transistor device with a gate structure 302 arranged on a substrate 102. A sidewall spacer 204 is arranged on opposite sides of the gate structure 302. In some embodiments, the sidewall spacer 204 comprises a first-material layer 104 arranged between a lower dielectric layer 206 and an insulating layer 106. A self-filling spacer 112 is arranged along an outermost sidewall 104s of the first-material layer 104. A dielectric layer 116 is arranged on the insulating layer 106 and on a sidewall of the self-filling spacer 112, and an ILD structure 118 is arranged on the dielectric layer 116.

[0034] In some embodiments, a field plate contact 402 extends through the ILD structure 118, the dielectric layer 116, and the insulating layer 106 to contact the first material layer 104. In these embodiments, the first material layer 104 is a conductive material, so that the first material layer 104 is configured to act as a field plate for the transistor device. In some embodiments, one or more interconnects 208 (e.g., conductive contacts) extend through the ILD structure 118 to contact the gate structure 302 and the source / drain regions 308 on opposite sides of the gate structure 302. The self-filling spacer 112 reduces the probability that metal which is present during the manufacture of one or more interconnects 208 (e.g., during the manufacture of a conductive contact over the outermost right of the source / drain regions 308 of Fig. 4A) is deposited, is present in unwanted cracks in the dielectric layer 116, thereby reducing an electrical short circuit between the field plate and a nearest source / drain area 308.

[0035] Fig. Figure 4B shows a sectional view of some further embodiments of an integrated chip structure 404, which has a transistor device enclosed by a sidewall spacer having a self-filling spacer.

[0036] The integrated chip structure 404 comprises a transistor device with a gate structure 302 arranged over a substrate 102. A sidewall spacer 204 is arranged on opposite sides of the gate structure 302. In some embodiments, the sidewall spacer 204 comprises a first-material layer 104 arranged between a lower dielectric layer 206 and an insulating layer 106. A self-filling spacer 112 is arranged along an outermost sidewall 104s of the first-material layer 104. A dielectric layer 116 is arranged on the insulating layer 106 and on a sidewall of the self-filling spacer 112, and an ILD structure 118 is arranged on the dielectric layer 116.

[0037] A field plate layer 406 is arranged above the dielectric layer 116 and along one side of the gate structure 302. The field plate layer 406 comprises a conductive material, such as copper, aluminum, tungsten, or the like. In some embodiments, a field plate contact 402 extends through the ILD structure 118 to contact the field plate layer 406. In these embodiments, the dielectric layer 116 separates the field plate layer 406 both laterally and vertically from the sidewall spacer 204. The self-filling spacer 112 reduces the likelihood that metal deposited during the fabrication of the field plate layer 406 is present in unwanted cracks in the dielectric layer 116.

[0038] Fig. Figure 5 shows a sectional view of some further embodiments of an integrated chip structure 500, which includes a transistor device having a sidewall spacer with a self-filling spacer.

[0039] The integrated chip structure 500 comprises a transistor device with a gate structure 302 arranged on a substrate 102. A sidewall spacer 204 is arranged on opposite sides of the gate structure 302. In some embodiments, the sidewall spacer 204 has a first-material layer 104 arranged between a lower dielectric layer 206 and an insulating layer 106. An outermost sidewall 104s of the first-material layer 104 is oriented, measured through the first-material layer 104, at an obtuse angle 502 with respect to a bottom surface of the first-material layer 104.

[0040] A self-filling spacer 112 is arranged along the outermost side wall 104s of the first material layer 104. The self-filling spacer 112 comprises a first side wall 112s1, which abuts the outermost side wall 104s of the first material layer 104, and a second side wall 112s2, which faces away from the first material layer 104. In some embodiments, the first side wall 112s1 and the second side wall 112s2 can be inclined side walls. For example, the first side wall 112s1, as measured by the self-filling spacer 112, can be oriented at an acute angle 504 with respect to a bottom surface of the self-filling spacer 112. The second side wall 112s2 can be aligned at an acute angle 506 with respect to a bottom of the self-filling spacer 112, as measured by the self-filling spacer 112.The acute angle 504 of the first side wall 112s1 and the acute angle 506 of the second side wall 112s2 essentially give the self-filling spacer 112 the shape of a triangle.

[0041] Fig. Figure 6 shows a sectional view of some further embodiments of an integrated chip structure 600, which has a transistor device having a sidewall spacer with a self-filling spacer.

[0042] The integrated chip structure 600 comprises a sidewall spacer 204 arranged on opposite sides of a gate structure 302, which is positioned over a substrate 102. In some embodiments, the sidewall spacer 204 includes a first-material layer 104 positioned between a lower dielectric layer 206 and an insulating layer 106. The first-material layer 104 has an outermost sidewall 104s which, measured through the first-material layer 104, is oriented at an acute angle 602 with respect to a bottom surface of the first-material layer 104.

[0043] A self-filling spacer 112 is arranged along the outermost side wall 104s of the first material layer 104. The self-filling spacer 112 comprises a first side wall 112s1, which abuts the outermost side wall 104s of the first material layer 104, and a second side wall 112s2, which faces away from the outermost side wall 104s of the first material layer 104. In some embodiments, the first side wall 112s1 may be an inclined side wall. For example, the first side wall 112s1, as measured by the self-filling spacer 112, may be oriented at an obtuse angle 604 with respect to a bottom surface of the self-filling spacer 112. In some embodiments, the second side wall 112s2 is essentially vertical with respect to a bottom side of the self-filling spacer 112 (e.g., as measured by the self-filling spacer 112, oriented at an angle of approximately 90°).The obtuse angle 604 of the first side wall 112s1 and the angle 606 of the second side wall 112s2 give the self-filling spacer 112 the shape of an inverted triangle.

[0044] Fig. Figure 7 shows a sectional view of some further embodiments of an integrated chip structure 700, which has a transistor device having a sidewall spacer with a self-filling spacer.

[0045] The integrated chip structure 700 comprises a sidewall spacer 204 arranged on opposite sides of a gate structure 302, which is positioned over a substrate 102. In some embodiments, the sidewall spacer 204 has a first-material layer 104 located between a lower dielectric layer 206 and an insulating layer 106. The first-material layer 104 has an outermost sidewall 104s which, measured through the first-material layer 104, is oriented at an acute angle 702 with respect to a bottom surface of the first-material layer 104.

[0046] A self-filling spacer 112 is arranged along the outermost side wall 104s of the first material layer 104. The self-filling spacer 112 comprises a first side wall 112s1, which abuts the outermost side wall 104s of the first material layer 104, and a second side wall 112s2, which faces away from the first material layer 104. In some embodiments, the first side wall 112s1 and the second side wall 112s2 can be inclined side walls. For example, the first side wall 112s1, as measured by the self-filling spacer 112, can be oriented at an obtuse angle 704 with respect to a bottom surface of the self-filling spacer 112. The second side wall 112s2 can be aligned at an acute angle 706 with respect to a bottom of the self-filling spacer 112, as measured by the self-filling spacer 112.

[0047] Fig. Figure 8A shows a sectional view of some further embodiments of an integrated chip structure 800, which includes a transistor device having a sidewall spacer with a self-filling spacer.

[0048] The integrated chip structure 800 comprises a sidewall spacer 204 arranged on opposite sides of a gate structure 302, which is positioned over a substrate 102. In some embodiments, the sidewall spacer 204 includes a first-material layer 104 positioned between a lower dielectric layer 206 and an insulating layer 106. The first-material layer 104 has an outermost sidewall 104s having a serrated profile 802. The serrated profile 802 of the first-material layer 104 is shown in the sectional view 806 of Fig. 8B shown, which is part of the 800 series integrated chip structure. Fig. 8A represents. As shown in section view 806, the serrated profile of the outermost side wall comprises surfaces 808-810 extending along different and intersecting directions to form a plurality of recesses 812 in the outermost side wall of the first-material layer 104.

[0049] A self-filling spacer 112 is arranged along the outermost side wall of the first material layer 104. The self-filling spacer 112 comprises a first side wall 112s1, which abuts the outermost side wall 104s of the first material layer 104, and a second side wall 112s2, which faces away from the first material layer 104. In some embodiments, the first side wall may have a serrated profile that interlocks with the serrated profile 802 of the first material layer 104.

[0050] In some embodiments, which are in Fig. As shown in Figure 8A, the second side wall of the self-filling spacer 112 is substantially vertical with respect to a bottom surface of the self-filling spacer 112 (e.g., measured through the self-filling spacer 112, oriented at an angle 804 of approximately 90°). In other embodiments, shown in section 900 of Fig. As shown in Figure 9, the second side wall of the self-filling spacer 112, measured through the self-filling spacer 112, is aligned at an acute angle 902 with respect to a bottom side of the self-filling spacer 112.

[0051] Fig. Figure 10 shows a sectional view of some embodiments of an integrated chip structure 1000, which has different types of devices having sidewall spacers, each with a self-filling spacer.

[0052] The integrated chip structure 1000 comprises a sidewall spacer 204 arranged on opposite sides of a gate structure 302, which is positioned over a substrate 102. In some embodiments, the sidewall spacer 204 includes a first-material layer 104 positioned between a lower dielectric layer 206 and an insulating layer 106. A self-filling spacer 112 is arranged along the outermost sidewall of the first-material layer 104. A dielectric layer 116 is positioned over the insulating layer 106 and on one sidewall of the self-filling spacer 112. An ILD structure 118 is positioned over the dielectric layer 116. One or more interconnects 208 are arranged within the ILD structure 118.

[0053] A first further ILD structure 1002 is arranged on the ILD structure 118, and a first further interconnect 1004 is arranged within the first further ILD structure 1002. In some embodiments, the first further interconnect 1004 may have an interconnect wire made of a conductive material (e.g., copper, aluminum, tungsten, or the like). A lower insulation structure 1006 is arranged on the first further ILD structure 1002. A storage device 1008 is arranged above the lower insulation structure 1006. The storage device 1008 has a lower electrode 1010, which is separated from an upper electrode 1014 by a data storage layer 1012 configured to store a data state. The lower electrode 1010 extends through the lower insulation structure 1006 to contact the first further interconnect 1004.In some embodiments, the storage device 1008 may include an MRAM device, an RRAM device, a CBRAM device, or other similar devices.

[0054] A storage device sidewall spacer 1016 is arranged on opposite sides of the storage device 1008. In some embodiments, the storage device sidewall spacer 1016 comprises a further first-material layer 1018, which is arranged between a further lower dielectric layer 1022 and a further insulating layer 1020. A further self-filling spacer 1024 is arranged along an outermost sidewall of the further first-material layer 1018. A further dielectric layer 1026 is arranged above the further insulating layer 1020 and on a sidewall of the further self-filling spacer 1024. An upper ILD structure 1028 is arranged above the further dielectric layer 1026. An upper interconnect 1030 is arranged in the upper ILD structure 1028.

[0055] It is understood that in different embodiments, the Integrated Chip Structure 1000 can be arranged in different packaging types. For example, the Integrated Chip Structure 1000 can be arranged in a SoIC package (SoIC: small outline integrated circuit), an InFO package (InFO: integrated fan out), an InFO Pop package (InFO Pop: integrated fan out package on package), a CoWoS package (CoWoS: chip on wafer on substrate), or the like.

[0056] The Fig. Figures 11-18B represent sectional views 1100-1804 showing some embodiments of a method for manufacturing an integrated chip structure comprising a transistor device having a sidewall spacer with a self-filling spacer. Although the Fig. 11-18B in relation to a procedure, it is understood that the structures described in the Fig. 11-18B are disclosed, are not limited to the procedure, but can be used as structures independently and separately from the procedure.

[0057] As shown in section view 1100 of Fig. As shown in Figure 11, a substrate 102 is provided. In various embodiments, the substrate 102 can comprise any type of semiconductor body (e.g., silicon, SiGe, SOI (silicon on insulator), etc.), such as a semiconductor wafer and / or one or more dies on a wafer, as well as any other type of semiconductor and / or epitaxial layers associated with it. In some embodiments, the substrate 102 can comprise one or more dielectric layers, one or more inter-level dielectric layers (ILD layers), and / or one or more interconnects arranged over a semiconductor body.

[0058] In some embodiments, a device structure 202 is fabricated over the substrate 102. In some embodiments, the device structure 202 can include a gate structure 302 fabricated over the substrate 102. In these embodiments, the gate structure 302 can be fabricated by depositing a gate dielectric 306 over the substrate 102 and depositing a gate electrode 304 over the gate dielectric 306. The gate electrode 304 and the gate dielectric 306 are then structured to fabricate the gate structure 302. In some embodiments, the gate structure 302 can be fabricated in an active region defined by one or more isolation structures 310 (e.g., shallow trench isolation structures (STI structures)) fabricated in the substrate 102.

[0059] As shown in section view 1200 of Fig. As shown in Figure 12, dopants 1202 are implanted into the substrate 102 to create source / drain regions 308 on opposite sides of the gate structure 302. In various embodiments, the dopants 1202 can have an n-type dopant (e.g., arsenic, phosphorus, or the like) or a p-type dopant (e.g., boron or the like).

[0060] As shown in section view 1300 of Fig. As shown in Figure 13, a lower dielectric interlayer 1302 can be fabricated over the substrate 102 and along one or more sidewalls of the gate structure 302. A first-material interlayer 1304 is fabricated over the lower dielectric interlayer 1302, and a second-material interlayer 1306 is fabricated on top of the first-material interlayer 1304.

[0061] In some embodiments, the lower dielectric interlayer 1302, the first-material interlayer 1304, and the second-material interlayer 1306 can be produced by deposition processes (e.g., a PVD process (physical vapor deposition), a CVD process (chemical vapor deposition), a PE-CVD process (plasma-enhanced CVD), or the like). In some embodiments, the lower dielectric interlayer 1302 can be produced by a first deposition process followed by a first etching process to recess the lower dielectric interlayer 1302 beneath a top surface of the gate structure 302.In some embodiments, the first material interlayer 1304 can be produced by a second deposition process, followed by a second etching process to recess the first material interlayer 1304 beneath the top surface of the gate structure 302. In some embodiments, the second material interlayer 1306 can be produced by a third deposition process, followed by a third etching process to recess the second material interlayer 1306 beneath the top surface of the gate structure 302.

[0062] As shown in section view 1400 of Fig. As shown in Figure 14, one or more etching processes are carried out on the first-material intermediate layer (e.g., Figure 1304 of Fig. 13) carried out to produce a first material layer 104, and on the second material intermediate layer (e.g. 1306 of Fig. 13) is carried out to produce an insulating layer 106. The one or more etching processes are configured to etch the first-material interlayer laterally faster than the second-material interlayer, causing the first-material layer 104 to have an outermost sidewall 104s that is indented (e.g., laterally recessed) from an outermost sidewall of the insulating layer 106 by a non-zero distance 108. The recessed outermost sidewall of the first-material layer 104, together with a bottom surface of the insulating layer 106, defines a cavity 110 located directly beneath the insulating layer 106.

[0063] In various embodiments, one or more etching processes can be carried out such that the first-material interlayer and / or the second-material interlayer are treated with one or more etchants 1402. In some embodiments, the one or more etchants 1402 can comprise a dry etchant used in a dry etching process, a wet etchant used in a wet etching process, or a combination thereof. For example, in some embodiments, the second-material interlayer can be etched according to a dry etching process, and the first-material interlayer can be etched according to a wet etching process. In some embodiments, the wet etching process can include a hydrogen fluoride etchant (HF etchant) used to remove the second-material interlayer and expose the substrate 102.Since the first-material interlayer and the second-material interlayer are different materials with different etch selectivities, the first-material interlayer is etched laterally at a faster rate than the second-material interlayer, causing the outermost sidewall 104s of the first-material layer 104 to be laterally indented from an outermost sidewall of the insulating layer 106. In other embodiments, the first-material interlayer and the second-material interlayer can both be etched according to a dry etching process or according to a wet etching process. In some embodiments, the first etching process and the second etching process can comprise the same etching process (e.g., a single dry etching process or a single wet etching process).

[0064] As shown in section view 1500 of Fig. As shown in Figure 15, atoms 1503 (e.g., ions) are removed from the insulating layer 106. In some embodiments, the atoms 1503 can be ionized and removed from the insulating layer 106 by an ion bombardment process. In these embodiments, ions 1501 can be accelerated in a plasma 1502 toward the insulating layer 106. When the ions 1501 contact the insulating layer 106, they will ionize the atoms 1503 and / or knock them out of the insulating layer 106. In various embodiments, the ions 1501 can be argon ions, oxygen ions, or the like. In some embodiments, the insulating layer 106 can be bombarded with an ion dose in the range of approximately 0.8 × 10⁻⁶. 11 ions / cm² 3 and about 1.5 × 10 11 ions / cm² 3The removal of atoms 1503 from the insulating layer 106 reduces the thickness of the insulating layer 106 from a first thickness to a second thickness that is smaller than the first thickness.

[0065] In some embodiments, the atoms 1503 can be removed by generating a capacitively coupled plasma (CCP) in a process chamber 1504. In some embodiments, the CCP can be generated using a high-frequency CCP plasma system comprising a first electrode 1506 and a second electrode 1508 arranged on opposite sides of the substrate 102 and coupled to a power system 1509. In some embodiments, the first electrode 1506 is coupled to a first power source 1510, and the second electrode 1508 is coupled to a second power source 1512. The first power source 1510 can be a high-frequency power source configured to operate at a first frequency (e.g.,The first power source 1510 operates at a frequency of approximately 60 MHz, and the second power source 1512 can be a low-frequency power source configured to operate at a second frequency (e.g., approximately 2 MHz) lower than the first frequency. In some embodiments, the first electrode 1506 and the second electrode 1508 can be operated to ignite the plasma 1502 from a working gas (e.g., argon, oxygen, or the like) introduced into the process chamber 1504 from a gas source 1514 at a flow rate in the range of approximately 100 sccm (standard cubic centimeters per minute) to approximately 500 sccm. In some embodiments, the first power source 1510 and the second power source 1512 can each operate with the working gas at a power in the range of approximately 50 watts (W) to approximately 600 W.In some embodiments, the process chamber 1504 can be maintained at a temperature in a range between approximately 55 °C and approximately 65 °C.

[0066] As shown in section view 1600 of Fig. As shown in Figure 16, the atoms 1503 that have been ionized and / or removed from the insulating layer 106 are redeposited along the outermost side wall 104s of the first-material layer 104 to form a self-filling spacer 112 in the cavity 110. The self-filling spacer 112 comprises at least one of the materials of the insulating layer 106. In some embodiments, the self-filling spacer 112 may also comprise one or more additional materials (e.g., argon, oxygen, or the like) from the ions produced in the ion bombardment process (shown in Figure 16). Fig. 15) can be used.

[0067] In some embodiments, the atoms 1503 that have been removed from the insulating layer 106 are also redeposited onto the insulating layer 106, such that redeposited material extends continuously from a position in the cavity 110 to a position along a side wall and / or a top surface of the insulating layer 106. In these embodiments, the outer surfaces of the insulating layer can have a higher concentration of one or more additional materials (e.g., argon, oxygen, or the like) than inner regions of the insulating layer 106. In some embodiments, the atoms 1503 can be redeposited in situ upon removal of the atoms 1503 from the insulating layer 106. In some embodiments, the redeposition of the atoms 1503 that have been removed from the insulating layer 106 increases the thickness of the insulating layer 106 from a second thickness to a third thickness.

[0068] In some embodiments, the atoms 1503 can be redeposited by applying a first power to the first electrode 1506 and a second power to the second electrode 1508. In some embodiments, the first power can be in a range between about 50 W and about 600 W. In some embodiments, the second power can be in a range between about 50 W and about 400 W. In some embodiments, the process chamber 1504 can be maintained at a temperature in a range between about 55 °C and about 65 °C during the redeposition process. In some embodiments, a vacuum pump 1516 can be operated to maintain the process chamber 1504 at a pressure in a range between about 4 Pa ​​and about 20 Pa (about 30 mTorr and about 150 mTorr) during the redeposition process.

[0069] In some embodiments, the self-filling spacer 112 can be produced by a plurality of cycles, each of which involves an ion bombardment process (e.g., as in Fig. 15) include a redeposition process (e.g., as shown in Fig. (as shown in Figure 16). By performing multiple such cycles, the redeposited material can be produced with a greater thickness in the cavity 110 than over the insulating layer 106, resulting in a smooth surface along the sides of the insulating layer 106 and the self-filling spacer 112. This is because, in each cycle, the ion bombardment process removes the redeposited material from a top and side wall of the insulating layer 106 at a higher rate than in the cavity 110.

[0070] As shown in section view 1700 of Fig. As shown in Figure 17, a dielectric layer 116 is produced above the insulating layer 106 and along the side walls of the insulating layer 106 and the self-filling spacer 112. The dielectric layer 116 may comprise an oxide, a nitride, a carbide, or the like. The dielectric layer 116 extends continuously from a position along the side wall of the self-filling spacer 112 to a position above the insulating layer 106. Since the self-filling spacer 112 fills the cavity 110 and forms a smooth surface with the insulating layer 106, stress on the dielectric layer 116 is reduced during production, thus minimizing cracking in the dielectric layer 116. In some embodiments, the dielectric layer 116 is essentially free of cracks. Reducing cracks in the dielectric layer 116 improves the performance and / or reliability of the integrated chip structure.In some embodiments, the dielectric layer 116 can be produced by a deposition process (e.g., a PVD process, a CVD process, a PE-CVD process, or the like). In some embodiments, one or more metal silicide parts can be produced above the device structure 202 and / or the source / drain regions 308 before the dielectric layer 116 is produced, and the metal silicide parts will contact the subsequently produced one or more interconnects 208 (e.g., one or more contacts).

[0071] In some embodiments, an ILD structure 118 can be fabricated over the dielectric layer 116. In some embodiments, the ILD structure 118 can be fabricated by a deposition process (e.g., a PVD process, a CVD process, a PE-CVD process, or the like). In various embodiments, the ILD structure 118 can comprise one or more silicon dioxide, carbon-doped silicon dioxide (SiCOH), phosphosilicate glass (PSG), boron phosphosilicate glass (BPSG), fluorosilicate glass (FSG), undoped silicate glass (USG), or the like.

[0072] As shown in the sectional views of 1800 and 1804 of the Fig. As shown in Figures 18A-18B, one or more interconnects 208 can be manufactured in the ILD structure 118.

[0073] In some embodiments, shown in section view 1800 of Fig. As shown in Figure 18A, the one or more interconnects 208 can be fabricated by performing a structuring process that defines one or more openings 1802 (e.g., a via hole and / or a trench) in the ILD structure 118. In some embodiments, the dielectric layer 116 is located directly and laterally between the self-filling spacer 112 and one of the nearest openings 1802. In some embodiments, the dielectric layer 116 defines a side wall of the openings 1802.

[0074] In some embodiments, shown in section view 1804 of Fig. As shown in Figure 18B, one or more conductive materials are arranged in the one or more openings 1802. Since the self-filling spacer 112 reduces cracks in the dielectric layer 116, the one or more conductive materials do not fill cracks in the dielectric layer, thus mitigating reliability problems. A planarization process (e.g., a CMP process) is subsequently performed to remove excess of the one or more conductive materials and to define the one or more interconnects 208 in the ILD structure 118. In some embodiments, the one or more conductive materials may be aluminum, copper, tungsten, or the like.

[0075] Fig. Figure 19 shows a flowchart of some embodiments of a method 1900 for manufacturing an integrated chip structure having a self-filling spacer.

[0076] Although Method 1900 is presented and described here as a series of steps or events, it should be understood that the presented sequence of these steps or events should not be interpreted in a restrictive sense. For example, some steps may occur in different sequences and / or concurrently with other steps or events than those presented and / or described here. Furthermore, not all of the steps presented here need implement one or more aspects or embodiments of the description, and one or more of the steps described here may be carried out in one or more separate steps and / or phases.

[0077] In step 1902, a first-material intermediate layer is produced over a substrate. Fig. Figure 13 shows a sectional view 1300 of some embodiments according to step 1902.

[0078] In step 1904, a second-material interlayer is produced over the first-material interlayer. Fig. Figure 13 shows a sectional view 1300 of some embodiments according to step 1904.

[0079] In step 1906, the second-material interlayer is structured with a first etching process to produce an insulating layer. Fig. Figure 14 shows a sectional view 1400 of some embodiments according to step 1906.

[0080] In step 1908, the first-material interlayer is structured by a second etching process to produce a first-material layer with an outermost sidewall indented by an outermost sidewall of the insulating layer. The second etching process creates a cavity beneath the insulating layer. In various embodiments, the first and second etching processes may be different processes or the same process. Fig. Figure 14 shows a sectional view 1400 of some embodiments according to step 1908.

[0081] In step 1910, a self-filling spacer is produced in the cavity. In some embodiments, the self-filling spacer can be produced using steps 1912-1914.

[0082] In step 1912, an ion bombardment process is carried out on the insulating layer to remove atoms and / or ions from the insulating layer. Fig. Figure 14 shows a sectional view 1400 of some embodiments according to step 1912.

[0083] In step 1914, a redeposition process is carried out to redeposit the atoms and / or ions from the insulating layer along the outermost sidewall of the first-material layer to produce the self-filling spacer. Fig. Figure 15 shows a sectional view 1500 of some embodiments according to step 1914.

[0084] In step 1916, a dielectric layer is produced above the insulating layer and along one side wall of the self-filling spacer. Fig. Figure 16 shows a sectional view 1600 of some embodiments according to step 1916.

[0085] In step 1918, an interlayer dielectric structure (ILD structure) is fabricated over the dielectric layer. Fig. Figure 17 shows a sectional view 1700 of some embodiments according to step 1918.

[0086] In step 1920, one or more interconnects can be created in the ILD structure. Fig. Figures 18A-18B show sectional views 1800 and 1804 of some embodiments according to step 1920.

[0087] Accordingly, in some embodiments, the present disclosure relates to an integrated chip structure with a self-filling spacer configured to fill a cavity produced during an etching process in a side wall of a bilayer structure in order to reduce stress on a layer located above the bilayer structure.

[0088] The invention is defined by the main patent claim and the dependent patent claims. Further embodiments of the invention are described by the dependent patent claims.

Claims

[1] Method for manufacturing an integrated chip structure comprising the following steps: Production (1902) of a first-material intermediate layer (1304) over a substrate; Production (1904) of a second-material interlayer (1306) on the first-material interlayer (1304); Structuring (1906) the second-material interlayer (1306) to produce an insulating layer (106); Structuring (1908) the first-material intermediate layer (1304) to produce a first-material layer (104) with an outermost side wall (104s) inset inwards from an outermost side wall (106s) of the insulating layer (106); Performing (1912) an ion bombardment process on the insulating layer (106) to remove one or more atoms from the insulating layer (106); and Performing (1914) a redeposition process to redeposit the one or more atoms on the outermost side wall (104s) of the first material layer (104) and to produce a self-filling spacer (112) under the insulating layer (106), wherein the self-filling spacer (112) is produced by a plurality of cycles, each comprising the ion bombardment process (1912) followed by the re-deposition process (1914). [2] Method according to claim 1, wherein the first material intermediate layer (1304) comprises a conductive material. [3] Method according to claim 1 or 2, wherein the first material intermediate layer comprises a metal. [4] Method according to any of the preceding claims, wherein the second material interlayer (1306) comprises a dielectric material. [5] Method according to any of the preceding claims, further comprising: Producing (1916) a dielectric layer (116) over the insulating layer (106) and along the outermost side walls of the insulating layer (106) and the self-filling spacer (112), and Fabrication (1918) of an interlayer dielectric structure (118) over the dielectric layer (116). [6] Method according to claim 5, further comprising: Establishing a field plate contact (402) extending through the interlayer dielectric structure (118), the dielectric layer (116) and the insulating layer (106) to contact the first material layer (104). [7] Method according to any of the preceding claims, wherein the ion bombardment process and the re-deposition process are carried out in situ. [8] Method according to any of the preceding claims, wherein carrying out the ion bombardment process comprises: Igniting a plasma from an argon gas to produce argon ions; and Bombardment of the insulating layer with argon ions. [9] Method according to any of the preceding claims, wherein carrying out the ion bombardment process comprises: Igniting a plasma from an oxygen gas to produce oxygen ions; and Bombardment of the insulating layer with oxygen ions. [10] Method for manufacturing an integrated chip structure comprising the following steps: Manufacturing a device structure (202) over a substrate (102); Forming a first dielectric layer (1302) along a side wall (204) of the device structure (302); Production (1902) of a first-material interlayer (1304) on the first dielectric layer; Production (1904) of a second-material interlayer (1306) on the first-material interlayer; Structuring (1906) the second-material interlayer (1306) to produce an insulating layer (106); Structuring (1908) the first-material interlayer (1304) to produce a first-material layer (104) having an outermost sidewall (104s) that is set back laterally from an outermost sidewall (106s) of the insulating layer (106) by a cavity located beneath the insulating layer (106), wherein, viewed in a top view, the cavity encloses an outer perimeter of the first-material layer (104); Fabrication (1910) of a self-filling spacer (112) in the cavity after structuring the first-material interlayer (1304), wherein the self-filling spacer (112) is fabricated by a plurality of cycles, each comprising an ion bombardment process (1912) followed by a redeposition process (1914); and Forming (1916) a dielectric layer (116) over the self-filling spacer (112) and the insulating layer (106). [11] Method according to claim 10, wherein the dielectric layer (116) is arranged along outermost side walls of the insulating layer (106) and the self-filling spacer (112). [12] Method according to claim 11, further comprising: Fabrication (1918) of an interlayer dielectric structure (118) over the dielectric layer (116). [13] Method according to claim 12, further comprising: Establishing a field plate contact (402) extending through the interlayer dielectric structure (118), the dielectric layer (116) and the insulating layer (106) to contact the first material layer (104). [14] Method according to any one of claims 10 to 13, wherein the first material interlayer (1304) and the second material interlayer (1306) comprise different materials. [15] Method according to any one of claims 10 to 13, wherein the first material intermediate layer (1304) comprises a conductive material. [16] Method according to any one of claims 10 to 15, wherein the first material intermediate layer comprises a metal. [17] Method according to any one of claims 10 to 16, wherein the second material interlayer (1306) comprises a dielectric material. [18] Method according to any one of claims 10 to 17, wherein the insulating layer (106) comprises a first part arranged along an interface with the first material layer (104) and a second part arranged along an opposite outer surface of the insulating layer (106), wherein the first part comprises a first material and the second part comprises the first material and one or more further materials. [19] Integrated chip structure with: a first-material layer (104) arranged over a substrate (102) and having an outermost side wall (104s); an insulating layer (106) arranged above the first material layer (104), wherein the insulating layer (106) extends laterally from a position directly above the first material layer (104) to a position laterally beyond the outermost side wall (104s) of the first material layer (104), such that a cavity is defined which is located below the insulating layer (106); a spacer (112) arranged in the cavity and comprising at least one of the materials of the insulating layer (106); and a dielectric layer (116) arranged above the insulating layer (106) and along an outermost side wall (112s2) of the spacer (112), wherein the insulating layer (106) and the spacer (112) completely cover an outermost edge of the first material layer (104). [20] Integrated chip structure according to claim 19, wherein the spacer (112) comprises a first side wall (112s1) in contact with the first material layer (104) and a second side wall (112s2) opposite the first side wall, wherein the second side wall (112s2) has an inclined side wall with respect to a bottom of the spacer (112).

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