Slotted shields for use with an electro-optical phase shifter

Abstract

Structure (10), comprising: a semiconductor substrate (22); a waveguide core (12) on the semiconductor substrate (22), the waveguide core (12) comprising a phase shifter (17); and a connecting structure (26) over the waveguide core (12) and the semiconductor substrate (22), the connecting structure (26) comprising: a first slotted shield (28) and a first transmission line (44) connected to the phase shifter (17), wherein the first slotted shield (28) comprises a first plurality of segments (30) and a first plurality of slots (31) laterally separating the first plurality of segments (30), and wherein the first slotted shield (28) is arranged between the first transmission line (44) and the semiconductor substrate (22), wherein the first slotted shield (28) further comprises a second plurality of segments (32) and a second plurality of slots (33) laterally separating the second plurality of segments (32), wherein the first plurality of segments (30) is spaced from the second plurality of segments (32) by a first gap (G1), and the first gap (G1) is disposed above the waveguide core (12), a second transmission line (46) laterally spaced from the first transmission line (44), and the second plurality of segments (32) is arranged between the second transmission line (46) and the semiconductor substrate (22), a first plurality of connections (36) connecting the first transmission line (44) to the first plurality of segments (30) of the first slotted shield (28), and a second plurality of connections (38) connecting the second transmission line (46) to the second plurality of segments (32) of the first slotted shield (28), wherein the first plurality of segments (30) and the second plurality of segments (32) are arranged on opposite side edges of the waveguide core (12), and the first gap (G1) is smaller than a second gap between the first transmission line (44) and the second transmission line (46).

Description

background

[0001] The present invention relates to photonic chips and, in particular, to structures with an electro-optical phase shifter.

[0002] Photonic chips are used in many applications and systems, including, but not limited to, data communication systems and data processing systems. A photonic chip integrates optical components, such as waveguides, optical switches, optical power splitters, and directional couplers, with electronic components, such as field-effect transistors, into a unified platform. Integrating both components on the same chip can reduce layout area, cost, and operational overhead, among other benefits.

[0003] An electro-optical phase shifter can be used to modulate the phase of an optical signal propagating in a waveguide core. The phase is modulated under the control of a high-frequency signal provided by a transmission line. The electro-optical bandwidth of the phase shifter can be affected by the attenuation of the high-frequency signal in the semiconductor substrate, which results from the proximity of the transmission line to the semiconductor substrate. In particular, the propagation of electric field lines into the semiconductor substrate is a primary cause of signal attenuation.

[0004] Better structures with an electro-optical phase shifter are required.

[0005] Document US 2021 / 0 055 581 A1 relates to a silicon-based electro-optical modulator comprising: a silicon substrate layer, an insulating layer, and an optical waveguide layer stacked one after the other; traveling-wave electrodes disposed over the optical waveguide layer; and a metal grating structure disposed over the optical waveguide layer and periodically configured along a direction in which an electrical signal propagates in the traveling-wave electrodes.

[0006] Document US 2019 / 0 025 615 A1 relates to an optical modulator comprising: an Si optical modulator having an input optical waveguide, two arm waveguides that branch and guide the light introduced from the input optical waveguide, an output optical waveguide that combines the light guided through the two arm waveguides and outputs the combined light, two signal electrodes for applying radio frequency signals, each arranged in parallel with the two arm waveguides, and a DC electrode for applying a bias voltage provided between the two signal electrodes; and at least one ground electrode arranged in parallel with the two signal electrodes.

[0007] The document ROFOUGARAN, Ahmadreza [et al.]: A 1 GHz CMOS RF front-end IC for a direct-conversion wireless receiver. In: IEEE journal of solid-state circuits, Vol. 31, 1996, No. 7, pp. 880-889 describes the gate electrode resistance of MOSFETs and the non-quasi-static (NQS) effect for RF operation. The vertical current paths between the silicide layer and the polysilicon are considered in the gate electrode. The vertical current paths are not effective in long-channel devices but become more significant in short-channel devices. The gate resistance, including vertical current paths, can well reproduce practical RF characteristics. By carefully separating the above-mentioned gate electrode resistance and the NQS effect, the small-signal gate-source admittance can be analyzed using a 130 nm CMOS process. Summary

[0008] The above object is achieved by a structure according to claim 1. u Short description of the drawings

[0009] The accompanying drawings, which are incorporated in this specification, illustrate various embodiments of the invention and, together with the general description of the invention above and the detailed description of the embodiments below, serve to illustrate embodiments of the invention. In the drawings, like reference numerals refer to like features throughout the different views. Fig. Figure 1 is a plan view of a structure in a first manufacturing phase of a method which is not part of the invention. Fig. Figure 2 is a cross-sectional view of the structure taken generally along line 2-2 in Fig. 1. Fig. 3 is a plan view of the structure in a Fig. 1 following manufacturing phase. Fig. 4 is a cross-sectional view of the structure taken generally along line 4-4 in Fig. 3. Fig. Figure 4A is a cross-sectional view of the structure taken generally along line 4A-4A in Fig. 3. Fig. 5 is a plan view of the structure in a Fig. 3 following manufacturing phase. Fig. Figure 6 is a cross-sectional view of the structure taken generally along line 6-6 in Fig. 5. Fig. Figure 6A is a cross-sectional view of the structure taken generally along line 6A-6A in Fig. 5. Fig. 7 is a cross-sectional view of a structure according to alternative embodiments of the invention. Fig. Figure 8 is a plan view of a structure according to alternative embodiments of the invention. Fig. 9 is a plan view of a structure according to alternative embodiments of the invention. Detailed description

[0010] With reference to Fig. 1 and Fig. 2 and according to embodiments of the invention, a structure 10 includes a waveguide core 12 aligned along a longitudinal axis 14 and an electro-optic phase shifter 17 connected to a portion of the waveguide core 12. In one embodiment, the electro-optic phase shifter 17 may be formed in a ridged portion of the waveguide core 12. In one embodiment, the electro-optic phase shifter 17 may include a doped region 16 and a doped region 18 of opposite conductivity types separated by an intrinsic region to define a pin junction. The doped region 16 may be formed in the ridged portion of the waveguide core 12 by a masked ion implantation process, and the doped region 18 may be formed in the ridged portion of the waveguide core 12 by a separate masked ion implantation process.In one embodiment, the semiconductor material of doped region 16 may be doped with a p-type dopant (e.g., boron) providing p-type electrical conductivity, and the semiconductor material of doped region 18 may be doped with an n-type dopant (e.g., arsenic) providing n-type electrical conductivity. Heavily doped regions (not shown) with reduced electrical resistance may be formed in a portion of doped region 16 and in a portion of doped region 18 and used to make electrical contacts for biasing electro-optic phase shifter 17. In alternative embodiments, electro-optic phase shifter 17 may include a junction with a different configuration.

[0011] The waveguide core 12 may be formed from a semiconductor material, e.g., single-crystal silicon. In one embodiment, the semiconductor material may originate from a single-crystal device layer of a silicon-on-insulator (SOI) substrate, which further comprises a dielectric layer 20 formed by a buried oxide layer, and a semiconductor substrate 22 made of a semiconductor material, e.g., single-crystal silicon. The waveguide core 12 may be patterned from the device layer during front-end-of-line processing using lithography and etching techniques. In one embodiment, the waveguide core 12 may directly contact the dielectric layer 20. In one embodiment, the waveguide core 12 may be indirectly disposed on the semiconductor substrate 22, with the dielectric layer 20 located between the waveguide core 12 and the semiconductor substrate 22.

[0012] With reference to the Fig. 3, Fig. 4 and Fig. 4A, in which like reference numerals refer to like features in the Fig. 1 and Fig. 2, in a subsequent manufacturing phase, an interconnect structure 26 is formed over the dielectric layer 20 by middle-of-line and back-end-of-line processing. A dielectric layer 24 of the interconnect structure 26 may be formed over the waveguide core 12 and the dielectric layer 20. The dielectric layer 24 may be formed from silicon dioxide deposited by chemical vapor deposition and planarized by chemical mechanical polishing.

[0013] The interconnect structure 26 may include multiple interconnect levels, which may be formed over the dielectric layer 24 using deposition, polishing, lithography, and etching techniques characteristic of a damascene process. In particular, for each interconnect level, an interlayer dielectric layer may be deposited and patterned using lithography and etching techniques to define trenches and vias coated with a barrier layer (e.g., a bilayer of tantalum and tantalum nitride) and filled with a planarized conductor (e.g., copper or aluminum) to define lines and vias connecting the lines in the various interconnect levels. Each interlayer dielectric layer of the interconnect structure 26 may be formed from an inorganic dielectric material, e.g., silicon dioxide or a low-dielectric-constant dielectric material, e.g.,deposited by chemical vapor deposition.

[0014] A slotted shield 28 is formed in a wiring level of the interconnect structure 26 and disposed over the waveguide core 12. In one embodiment, the slotted shield 28 may be formed in a dielectric interlayer 34 of a wiring level of the interconnect structure 26. In one embodiment, the wiring level of the interconnect structure 26 with the slotted shield 28 may represent the wiring level closest to the waveguide core 12 (i.e., the first metallic wiring level). The slotted shield 28 comprises segments 30 separated by slots 31 and laterally spaced apart. The slotted shield 28 also comprises segments 32 separated by slots 33 and laterally spaced apart.

[0015] Segments 30 are laterally spaced from segments 32 by a gap G1 disposed above waveguide core 12 and overlapping with waveguide core 12 and electro-optic phase shifter 17. More specifically, each segment 30 terminates with an end face 64 adjacent to one edge of gap G1, and each segment 32 terminates with an end face 66 adjacent to an opposite edge of gap G1. Gap G1 is located laterally between end faces 64 and end faces 66. The width of gap G1, which can be measured between the edges, is chosen so that segments 30, 32 do not overlap with waveguide core 12.Gap G1, which may extend the entire length of the portion of waveguide core 12 including doped regions 16, 18, prevents the conductor of slotted shield 28 from being disposed directly over any portion of waveguide core 12 to minimize adverse performance effects, such as optical reflection and absorption. In one embodiment, gap G1 may have a uniform width dimension determined by the distance between end faces 64, 66.

[0016] The segments 30, 32 may be formed from the conductor (e.g., copper) used to form the wiring plane in which the slotted shield 28 is located. The segments 30 and the segments 32 may be spaced at a specific pitch, and in one embodiment, the segments 30 and the segments 32 may be equally spaced. The segments 30 may have a line width w1, and pairs of the segments 30 may be spaced apart by spaces or slots 31 to define a series of slotted lines. The segments 32 may have a line width w2, and pairs of the segments 32 may be spaced apart by spaces or slots 33 to define a further set of slotted lines.In one embodiment, the line widths w1, w2 of the segments 30, 32 may be on the order of one micrometer, and the width dimensions s1, s2 of the slots 31, 33 between the segments 30, 32 may be on the order of one micrometer. In one embodiment, the segments 30, 32 and the slots 31, 33 may be drawn close to the minimum line width and gap width of the fundamental rule to optimize shielding at high frequencies, such as radio frequencies. In one embodiment, the line widths w1, w2 may be less than or equal to 1 micrometer for operation at frequencies from 10 GHz to 100 GHz. The respective arrangement of the segments 30, 32 as interrupted slotted lines effectively suppresses eddy currents during operation.

[0017] Increasing the line widths w1, w2 of the segments 30, 32 may increase the shielding provided by the slotted shield 28, while increasing the width dimensions s1, s2 of the slots 31, 33 may reduce the capacitance with other metallizations in the interconnect structure 26. In an embodiment where shielding and capacitance are balanced, the line width w1 of the segments 30 may be equal to or substantially equal to the width dimension s1 of the slots 31, and the line width w2 of the segments 32 may be equal to or substantially equal to the width dimension s2 of the slots 33.

[0018] Each segment 30 of the slotted shield 28 is aligned along a longitudinal axis 60 and has a length in a direction transverse to its line width w1. Each slot 31 of the slotted shield 28 is aligned along a longitudinal axis 61, which may be aligned parallel to the longitudinal axis 60. In the illustrative embodiment, the segments 30 and the slots 31 have a rectangular shape from a vertical perspective. In one embodiment, the longitudinal axis 60 of each segment 30 and the longitudinal axis 61 of each slot 31 may be aligned at an angle θ1 relative to an x-axis of an xy coordinate system. In the illustrative embodiment, the angle θ1 is equal to 90°. In one illustrative embodiment, the angle θ1 may be greater than or equal to 45°. In one embodiment, the angle θ1 may be in a range from 45° to 90°. An inclination angle θ1 of 90° can effectively maximize the eddy current suppression.

[0019] Each segment 32 of the slotted shield 28 is aligned along a longitudinal axis 62 and has a length in a direction transverse to its line width w2. Each slot 33 of the slotted shield 28 is aligned along a longitudinal axis 63, which may be aligned parallel to the longitudinal axis 62. In the illustrative embodiment, the segments 32 and the slots 33 have a rectangular shape when viewed vertically. In one embodiment, the longitudinal axis 62 of each segment 32 and the longitudinal axis 63 of each slot 33 may be aligned at an angle θ2 relative to the x-axis of an xy coordinate system. In the illustrative embodiment, the angle θ2 is equal to 90°. In one illustrative embodiment, the angle θ2 may be greater than or equal to 45°. In one embodiment, the angle θ2 may be within a range of 45° to 90°. An inclination angle θ2 of 90° can be effective to maximize eddy current suppression.

[0020] In one embodiment, the longitudinal axes 62 of the segments 32 can each be aligned with the longitudinal axes 60 of the segments 30. In one embodiment, the longitudinal axes 63 of the slots 33 can each be aligned with the longitudinal axes 61 of the slots 31.

[0021] Portions of the connections 36, 38 to the doped regions 16, 18 are formed by middle-of-line and back-end-of-line processing in the dielectric layer 24 and the interlayer dielectric layer 34. The connections 36, 38 extend through the gap G1 separating the segments 30 and the segments 32, and the connections 36, 38 include metal pads, which may be segmented, positioned within the gap G1 over the opposite side edges of the waveguide core 12.

[0022] With reference to the Fig. 5, Fig. 6 and Fig. 6A, in which like reference numerals refer to like features in the Fig. 3, Fig. 4 and Fig. 4A, in a subsequent manufacturing phase, additional wiring levels of the interconnect structure 26 are formed above the wiring level with the slotted shield 28. These additional wiring levels include a plurality of interlayer dielectrics 45, which may be formed of silicon dioxide, and transmission lines 42, 44, 46, which may be arranged in the uppermost wiring level of the interconnect structure 26. The vias and lines in the intermediate plurality of wiring levels between the slotted shield 28 and the transmission lines 44, 46 complete the interconnect 36, which couples the doped region 16 of the electro-optic phase shifter 17 to the transmission line 44, and the interconnect 38, which couples the doped region 18 of the electro-optic phase shifter 17 to the transmission line 46.The transmission lines 42, 46 can be coupled to a reference potential equal to ground, to a reference potential greater than ground or the reference ground of the circuit, or to a reference potential less than ground or the reference ground of the circuit.

[0023] The transmission line 44 provides a signal electrode connected to a signal source, e.g., a driver 48. The driver 48 includes components, such as a driver amplifier, configured to provide data in the form of radio-frequency signals to the transmission line 42 to modulate the effective refractive index of the waveguide core 12. The radio-frequency signals propagate along the longitudinal axis 54 of the transmission line 44. The transmission line 44 is physically coupled to the doped region 16 of the electro-optic phase shifter 17 via the interconnect 36. The transmission line 46 is physically coupled to the doped region 18 of the electro-optic phase shifter 17 via the interconnect 38. The driver 48 provides a radio-frequency signal to the electro-optic phase shifter 17, which changes the phase of the optical signals propagating in the waveguide core 12.

[0024] The connections 36, 38 in the wiring levels of the connection structure 26 can enable a lateral offset of the transmission lines 44, 46 relative to the waveguide core 12 and the gap G1 in the slotted shield 28 ( Fig. 3). Segments 30 and slots 31 can be arranged between transmission lines 42, 44 and semiconductor substrate 22 such that transmission lines 42, 44 overlap segments 30 and slots 31, respectively. Segments 32 and slots 33 can be arranged between transmission line 46 and semiconductor substrate 22 such that transmission line 46 overlaps segments 32 and slots 33. Segments 30, 32 and slots 31, 33 can reduce or prevent the attenuation of high-frequency signals into semiconductor substrate 22 caused by the proximity of transmission lines 42, 44, 46 to semiconductor substrate 22.

[0025] The transmission line 42 may extend longitudinally in alignment with a longitudinal axis 52, the transmission lines 44 may extend longitudinally in alignment with a longitudinal axis 54, and the transmission line 46 may extend longitudinally in alignment with a longitudinal axis 56. In one embodiment, the longitudinal axes 52, 54, 56 may be aligned parallel to the longitudinal axis 14 of the waveguide core 12. In one embodiment, the longitudinal axes 52, 54, 56 may be aligned parallel to each other.

[0026] The longitudinal axis 60 of each segment 30 and the longitudinal axis 61 of each slot 31 of the slotted shield 28 ( Fig. 4) may be oriented transversely to the longitudinal axes 52, 54 of the transmission lines 42, 44. The longitudinal axes 52, 54 of the transmission lines 42, 44 may be considered to be aligned with the x-axis of the xy coordinate system, such that the longitudinal axes 60, 61 of the segments 30 and the slots 31 are inclined at the angle θ1 relative to the longitudinal axes 52, 54 of the transmission lines 42, 44. In the illustrative embodiment, the longitudinal axes 60, 61 of the segments 30 and slots 31 are oriented perpendicular (i.e., θ1=90°) to the longitudinal axes 52, 54 of the transmission lines 42, 44. In an alternative embodiment, the longitudinal axes 60, 61 of the segments 30 and slots 31 may be aligned relative to the longitudinal axes 52, 54 of the transmission lines 42, 44 at an angle θ1 that is greater than or equal to 45°.In an alternative embodiment, the longitudinal axes 60, 61 of the segments 30 and slots 31 may be aligned relative to the longitudinal axes 52, 54 of the transmission lines 42, 44 at an angle θ1 that is within a range of 45° to 90°.

[0027] The longitudinal axis 62 of each segment 32 and the longitudinal axis 63 of each slot 33 of the slotted shield 28 ( Fig. 4) may be oriented transversely to the longitudinal axis 56 of the transmission line 46. The longitudinal axis 56 of the transmission line 46 may be considered to be aligned with the x-axis of the xy coordinate system such that the longitudinal axes 62, 63 of the segments 32 and the slots 33 are inclined at an angle θ1 relative to the longitudinal axis 56 of the transmission line 46. In the illustrative embodiment, the longitudinal axes 62, 63 of the segments 32 and the slots 33 are oriented perpendicular (i.e., θ2=90°) to the longitudinal axis 56 of the transmission line 46. In an alternative embodiment, the longitudinal axes 62, 63 of the segments 32 and the slots 33 may be oriented relative to the longitudinal axis 56 of the transmission line 46 at an angle θ2 that is greater than or equal to 45°.In an alternative embodiment, the longitudinal axes 62, 63 of the segments 32 and slots 33 may be aligned relative to the longitudinal axis 56 of the transmission line 46 at an angle θ2 ranging from 45° to 90°.

[0028] The segments 30, 32 of the slotted shield 28 are arranged in the interconnect structure 26 to avoid contact with the other metallization in the interconnect structure 26. The gap G1 between the segments 30, 32 provides a passage through the slotted shield 28 for the connections 36, 38 between the transmission lines 44, 46 and the electro-optic phase shifter 17. In one embodiment, the slotted shield 28 may be arranged in the first metal level of the interconnect structure 26 closest to the semiconductor substrate 22 to minimize capacitance with the transmission lines 42, 44, 46.In an alternative embodiment, the slotted shield 28 may be arranged in one of the dielectric interlayers 45 of a wiring level above the first wiring level of the interconnect structure 26 and is not limited to being located in the wiring level closest to the semiconductor substrate 22.

[0029] The slotted shield 28 can be used to reduce the attenuation of high-frequency signals at a fixed impedance. The slotted shield 28 can represent a cost-effective solution compared to alternative approaches for reducing high-frequency signal attenuation. The segments 30, 32 of the slotted shield 28 are separated from the transmission lines 42, 46 by the dielectric material of the dielectric interlayers 45 of the interconnect structure 26.

[0030] With reference to Fig. 7 and according to alternative embodiments, the segments 30, 32 of the slotted shield 28 may be connected to the transmission lines 42, 46 by corresponding connections 72, 76 formed in the dielectric interlayers 45 of the interconnect structure 26. The connections 72 may be in the form of through-holes that establish physical and electrical connections between the segments 30 and the transmission line 42, and the connections 76 may be in the form of through-holes that establish physical and electrical connections between the segments 32 and the transmission line 46. In one embodiment, the connections 72 may directly connect the segments 30 to the transmission line 42, and the connections 76 may directly connect the segments 32 to the transmission line 46.

[0031] With reference to Fig. 8 and according to alternative embodiments, the structure 10 may include another slotted shield 78 similar to the slotted shield 28 and disposed at a higher wiring level within the interconnect structure 26. The slotted shield 78 may include segments 80, 82 and slots 81, 83 similar in arrangement and construction to the segments 30, 32 and slots 31, 33. The segments 80 are separated by slots 81, and the segments 82 are separated by slots 83. The segments 80 are laterally spaced from the segments 82 by a gap G2 disposed above the waveguide core 12 and above the gap G1 in the slotted shield 28. The gap G2 overlaps with the waveguide core 12 and the gap G1 in the slotted shield 28. In one embodiment, the gap G2 may completely overlap with the gap G1 in the slotted shield 28.

[0032] Each segment 80 includes an end face 84, and each segment 82 includes an end face 86. The gap G2 is located laterally between the end faces 84 and the end faces 86. The end faces 84 end adjacent to one edge of the gap G2, and the end faces 86 end adjacent to an opposite edge of the gap G2. The width dimension of the gap G2 is selected such that the segments 80, 82, in addition to the segments 30, 32, do not overlap with the waveguide core 12.

[0033] The segments 80, 82 may be formed from the conductor (e.g., copper) used to form the wiring plane in which the slotted shield 78 is located. The segments 80 may have a line width w3 and be spaced apart by spaces or slots 81 of width s3 to define a series of slotted lines. The segments 82 may have a line width w4 and be spaced apart by spaces or slots 83 of width dimension s4 to define a further set of slotted lines. The segments 80 may be offset relative to the segments 30 of the underlying slotted shield 28, such that the segments 80 are arranged, for example, to overlap the slots 31 between the segments 30.Likewise, the segments 82 may be offset relative to the segments 32 of the underlying slotted shield 28, such that the segments 82 overlap, for example, with the slots 33 between the segments 32. In one embodiment, the line width w3 of the segments 80 may be equal to or substantially equal to the width dimension s3 of the slots 81, and the line width w4 of the segments 82 may be equal to or substantially equal to the width dimension s4 of the slots 83 to balance shielding and capacitance.

[0034] Each segment 80 has a longitudinal axis 90 and each slot 81 has a longitudinal axis 91, which are aligned transversely to the longitudinal axes 52, 54 of the transmission lines 42, 44. The longitudinal axes 52, 54 of the transmission lines 42, 44 can be considered to be aligned with the x-axis of the xy coordinate system, such that the longitudinal axes 90, 91 of the segments 80 and the slots 81 are inclined at an angle θ3 relative to the longitudinal axes 52, 54 of the transmission lines 42, 44. In the illustrative embodiment, the longitudinal axes 90, 91 of the segments 80 and slots 81 are aligned perpendicular (i.e., θ3=90°) to the longitudinal axes 52, 54 of the transmission lines 42, 44. In an alternative embodiment, the longitudinal axes 90, 91 of the segments 80 and slots 81 may be aligned relative to the longitudinal axes 52, 54 of the transmission lines 42, 44 at an angle θ3 that is greater than or equal to 45°.In an alternative embodiment, the longitudinal axes 90, 91 of the segments 80 and slots 81 may be aligned relative to the longitudinal axes 52, 54 of the transmission lines 42, 44 at an angle θ3 that is within a range of 45° to 90°.

[0035] Each segment 82 has a longitudinal axis 92, and each slot 83 has a longitudinal axis 93, which are aligned transversely to the longitudinal axis 56 of the transmission line 46. The longitudinal axis 56 of the transmission line 46 can be considered to be aligned with the x-axis of the xy coordinate system, such that the longitudinal axes 92, 93 of the segments 82 and slots 83 are inclined by the angle θ4 relative to the longitudinal axis 56 of the transmission line 46. In the illustrative embodiment, the longitudinal axes 92, 93 of the segments 82 and slots 83 are aligned perpendicular (i.e., θ4=90°) to the longitudinal axis 56 of the transmission line 46. In an alternative embodiment, the longitudinal axes 92, 93 of the segments 82 and the slots 83 may be aligned relative to the longitudinal axis 56 of the transmission line 46 at an angle θ4 that is greater than or equal to 45°.In an alternative embodiment, the longitudinal axes 92, 93 of the segments 82 and slots 83 may be aligned relative to the longitudinal axis 56 of the transmission line 46 at an angle θ4 that is in a range of 45° to 90°.

[0036] With reference to Fig.9 and according to alternative embodiments, the segments 30 in a group 68 may have a length that is shorter than the length of the adjacent segments 30 that do not belong to the group 68. Likewise, the segments 32 in a group 70 may have a length that is shorter than the length of the adjacent segments 32 that do not belong to the group 70. The gap G1 has a varying width with position along the longitudinal axis 14 due to the variation in the length of the segments 30 and the variation in the length of the segments 32 (and the displacement of some of the end surfaces 64, 66). The length variation of the segments 30, 32 may be used to create exclusion areas for the metal pads associated with one or more of the interconnects 36, 38. In an alternative embodiment, the segments 30 in the group 68 and / or the segments 32 in the group 70 may be omitted from the slotted shield 28.

[0037] The processes described above are used in the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in the form of a raw wafer (e.g., a single wafer containing multiple unpackaged chips), as a bare chip, or in packaged form. The chip can be integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of an intermediate or final product. The final product can be any product that includes integrated circuit chips, such as computer products with a central processor or smartphones.

[0038] Reference in this document to terms modified by approximations such as "approximately," "about," and "substantially" is not intended to be limited to the exact value. The approximate formula may correspond to the accuracy of an instrument used to measure the value and, unless otherwise dependent on the instrument's accuracy, may represent + / - 10% of the stated value(s).

[0039] Reference to terms such as "vertical," "horizontal," etc., is provided here only by way of example and not by way of limitation, to provide a frame of reference. As used herein, "horizontal" is defined as a plane parallel to a conventional plane of a semiconductor substrate, regardless of its actual three-dimensional spatial orientation. The terms "vertical" and "normal" refer to a direction perpendicular to the just-defined horizontal. The term "lateral" refers to a direction within the horizontal plane.

[0040] A feature that is "connected" or "coupled" to another feature may be directly connected or coupled to the other feature, or there may instead be one or more intervening features. A feature may be "directly connected" or "directly coupled" to another feature if there are no intervening features. A feature may be "indirectly connected" or "indirectly coupled" to another feature if there is at least one intervening feature. A feature that is "on" or "in contact" with another feature may be directly on or in direct contact with the other feature, or there may instead be one or more intervening features. A feature may be "directly on" or in "direct contact" with another feature if there are no intervening features.A feature can be "indirectly on" or in "indirect contact" with another feature if there is at least one intervening feature. Different features can overlap if one feature extends over another feature and covers a portion of it.

[0041] The description of the various embodiments of the present invention is for illustrative purposes, but is not intended to be exhaustive or limited to the described embodiments. Many modifications and changes will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein has been chosen to best explain the principles of the embodiments, practical application, or technical improvement over current technology, or to enable others not skilled in the art to understand the embodiments described herein.

Claims

[1] Structure (10), comprising: a semiconductor substrate (22); a waveguide core (12) on the semiconductor substrate (22), the waveguide core (12) comprising a phase shifter (17); and a connecting structure (26) over the waveguide core (12) and the semiconductor substrate (22), the connecting structure (26) comprising: a first slotted shield (28) and a first transmission line (44) connected to the phase shifter (17), wherein the first slotted shield (28) comprises a first plurality of segments (30) and a first plurality of slots (31) laterally separating the first plurality of segments (30), and wherein the first slotted shield (28) is arranged between the first transmission line (44) and the semiconductor substrate (22), wherein the first slotted shield (28) further comprises a second plurality of segments (32) and a second plurality of slots (33) laterally separating the second plurality of segments (32), wherein the first plurality of segments (30) is spaced from the second plurality of segments (32) by a first gap (G1), and the first gap (G1) is disposed above the waveguide core (12), a second transmission line (46) laterally spaced from the first transmission line (44), and the second plurality of segments (32) is arranged between the second transmission line (46) and the semiconductor substrate (22), a first plurality of connections (36) connecting the first transmission line (44) to the first plurality of segments (30) of the first slotted shield (28), and a second plurality of connections (38) connecting the second transmission line (46) to the second plurality of segments (32) of the first slotted shield (28), wherein the first plurality of segments (30) and the second plurality of segments (32) are arranged on opposite side edges of the waveguide core (12), and the first gap (G1) is smaller than a second gap between the first transmission line (44) and the second transmission line (46). [2] The structure (10) of claim 1, wherein the first gap (G1) has a first edge and a second edge located opposite the first edge above the first gap (G1), the first plurality of segments (30) terminates adjacent the first edge, and the second plurality of segments (32) terminates adjacent the second edge. [3] The structure (10) of claim 1, wherein the phase shifter (17) comprises a first doped region (16) having n-type conductivity and a second doped region (18) having p-type conductivity, the first plurality of interconnections (36) extend through the first gap (G1) from the first doped region (16) of the waveguide core (12) to the first transmission line (44), and the second plurality of interconnections (38) extend through the first gap (G1) from the first doped region (16) of the waveguide core (12) to the second transmission line (46). [4] The structure (10) of claim 1, wherein the interconnect structure (26) comprises a second slotted shield (78) disposed between the first slotted shield (28) and the first transmission line (44). [5] The structure (10) of claim 4, wherein the second slotted shield (78) includes a third plurality of segments (80) and a third plurality of slots (81) laterally separating the third plurality of segments (80), and the third plurality of segments (80) is disposed between the first transmission line (44) and the first plurality of segments (30) of the first slotted shield (28). [6] The structure (10) of claim 1, wherein the interconnect structure (26) comprises a first wiring level and a second wiring level, the first wiring level comprises the first slotted shield (28), the second wiring level comprises the first transmission line (44), and the first wiring level is closer to the semiconductor substrate (22) than the second wiring level.

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