Semiconductor package with a housing body with grooves formed therein

Abstract

Semiconductor packages, including: a housing body (2) comprising a first main surface (4), a second main surface (6) opposite the first main surface (4), and a side surface (8) extending between the two main surfaces (4, 6); a first die pad (10A) encapsulated in the housing body (2), wherein the first die pad (10A) is at least partially uncovered by the housing body (2) at the first main surface (4); a second diepad (10B) encapsulated in the housing body (2), wherein the second diepad (10B) is at least partially uncovered by the housing body (2) at the first main surface (4); a first semiconductor chip (22A) which is encapsulated in the housing body (2) and arranged on the first die pad (10A); a second semiconductor chip (22B) which is encapsulated in the housing body (2) and arranged on the second die pad (10B); at least one connecting conductor (12) which is encapsulated in the housing body (2) and protrudes from the housing body (2) at the side surface (8), wherein: the first die pad (10A), the second die pad (10B) and the at least one connecting conductor (12) are part of a dual-gauge conductor frame, and a thickness of at least one connecting conductor (12) is less than at least one of the thicknesses of the first die pad (10A) or the second die pad (10B); a first groove (14) formed in the first main surface (4), wherein the first groove (14) is arranged between the first die pad (10A) and the second die pad (10B); a second groove (16A) formed in the first main surface (4), wherein the second groove (16A) is arranged between the at least one connecting conductor (12) and at least one of the first die pad (10A) or the second die pad (10B); and an electrical connecting element (24) which is encapsulated in the housing body (2) and extends over the first groove (14) between the first die pad (10A) and the second die pad (10B), wherein a depth of the first groove (14) is less than or equal to at least one of the thickness of the first die pad (10A) or one of the thickness of the second die pad (10B).

Description

Technical field

[0001] The present disclosure relates to semiconductor packages comprising a housing body with grooves formed therein. Furthermore, the present disclosure relates to methods for manufacturing such semiconductor packages. background

[0002] Various semiconductor devices can operate at high voltages. Such semiconductor devices, as well as the applications and equipment in which they are used, may need to meet electrical insulation requirements specified in relevant safety standards. One or more components of a semiconductor device may be encapsulated in a housing, so the semiconductor device may also be referred to as a semiconductor package. To ensure the safe operation of a semiconductor package, one or more minimum creepage distances may need to be maintained between conductive parts protruding from the package. Manufacturers and developers of semiconductor packages are constantly striving to improve their products and the processes used to manufacture them.It may therefore be desirable to develop semiconductor packages that meet all safety requirements stipulated by the relevant safety standards. In particular, it may be desirable to protect the semiconductor packages from harmful leakage currents along the surfaces of the package body.

[0003] Publication US 2020 / 0343166 A1 concerns conductor frames for semiconductor packages.

[0004] Publication US 2015 / 0102479 A1 concerns an electrically insulating thermal interface on a discontinuity of an encapsulation structure.

[0005] Publication US 2020 / 0273802 A1 concerns a housing for a multi-chip power semiconductor device.

[0006] Publication US 2019 / 0378785 A1 relates to a semiconductor device and an associated manufacturing process. Brief description

[0007] One aspect of the present disclosure relates to a semiconductor package. The semiconductor package comprises a package body comprising a first principal surface, a second principal surface opposite the first principal surface, and a side surface extending between the two principal surfaces. The semiconductor package further comprises a first die pad encapsulated in the package body, the first die pad being at least partially uncovered by the package body at the first principal surface. The semiconductor package further comprises a second die pad encapsulated in the package body, the second die pad being at least partially uncovered by the package body at the first principal surface. The semiconductor package further comprises a first semiconductor chip encapsulated in the package body and arranged on the first die pad.The semiconductor package further comprises a second semiconductor chip encapsulated within the package body and arranged on the second die pad. The semiconductor package further comprises at least one interconnect conductor encapsulated within the package body and projecting from the side face of the package body. The first die pad, the second die pad, and the at least one interconnect conductor form part of a dual-gauge conductor frame. The thickness of the at least one interconnect conductor is less than at least one thickness of the first die pad or one thickness of the second die pad. The semiconductor package further comprises a first groove formed in the first main face, the first groove being located between the first die pad and the second die pad.The semiconductor package further comprises a second groove formed in the first main surface, the second groove being arranged between the at least one terminal conductor and at least one of the first die pads or the second die pad. The semiconductor package further comprises an electrical interconnect encapsulated in the package body, extending across the first groove between the first die pad and the second die pad. The depth of the first groove is less than or equal to at least one of the thicknesses of the first die pad or the second die pad.

[0008] One aspect of the present disclosure relates to a method for manufacturing a semiconductor package. The method comprises providing a first die pad, a second die pad, and at least one connecting conductor. The first die pad, the second die pad, and the at least one connecting conductor are part of a dual-gauge conductor frame. The thickness of the at least one connecting conductor is less than at least one thickness of the first die pad or one thickness of the second die pad. The method further comprises placing a first semiconductor chip on the first die pad. The method further comprises placing a second semiconductor chip on the second die pad. The method further comprises placing an electrical connecting element extending between the first die pad and the second die pad.The method further comprises encapsulating the first die pad, the second die pad, the first semiconductor chip, the second semiconductor chip, the electrical connector, and the at least one connecting conductor in a housing body, wherein the housing body comprises a first main surface, a second main surface opposite the first main surface, and a side surface extending between the two main surfaces, wherein: the first die pad is at least partially uncovered by the housing body at the first main surface, the second die pad is at least partially uncovered by the housing body at the first main surface, and the at least one connecting conductor projects from the housing body at the side surface. The method further comprises forming a first groove in the first main surface, wherein the first groove is arranged between the first die pad and the second die pad. The electrical connector extends over the first groove.The depth of the first groove is less than or equal to at least one thickness of the first die pad or one thickness of the second die pad. The method further comprises forming a second groove in the first main surface, wherein the second groove is arranged between the at least one connecting conductor and at least one of the first die pads or the second die pad. Brief description of the drawings

[0009] The accompanying drawings are included to aid in the further understanding of aspects. The drawings illustrate aspects and, together with the description, serve to explain the principles of the aspects. Other aspects and many of the intended benefits of aspects are easily appreciated when better understood by reference to the detailed description that follows. The elements in the drawings are not necessarily to scale with each other. Identical reference symbols may denote corresponding similar parts. Fig. 1 contains the Fig. Figures 1A to 1D schematically show a perspective view, a top view, a first cross-sectional side view and a second cross-sectional side view of a semiconductor package 100 according to the disclosure. Fig. Figure 2 schematically shows a top view of a semiconductor package 200 according to the disclosure. Fig. Figure 3 schematically shows a cross-sectional side view of a semiconductor package 300 according to the disclosure. Fig. Figure 4 schematically shows a cross-sectional side view of a semiconductor package 400 according to the disclosure. Fig. 5 contains the Fig. 5A and Fig. 5B, which schematically show a perspective view and a top view of a semiconductor package 500 according to the disclosure. Fig. Figure 6 schematically shows a top view of a semiconductor package 600 according to the disclosure. Fig. Figure 7 schematically shows a cross-sectional side view of a semiconductor package 700 according to the disclosure. Fig. Figure 8 schematically shows a cross-sectional side view of a semiconductor package 800 according to the disclosure. Fig. Figure 9 schematically shows a cross-sectional side view of a semiconductor package 900 according to the disclosure. Fig. Figure 10 schematically shows a perspective view of a semiconductor package 1000 according to the disclosure. Fig. Figure 11 schematically shows a cross-sectional side view of a semiconductor package 1100 according to the disclosure. Fig. Figure 12 schematically shows a top view of a semiconductor package 1200 according to the disclosure and a diagram of a circuit that may be implemented in the semiconductor package 1200. Fig. Figure 13 schematically shows a top view of a semiconductor package 1300 according to the disclosure and a diagram of a circuit that may be implemented in the semiconductor package 1300. Fig. Figure 14 shows a flowchart of a process for manufacturing a semiconductor package according to the disclosure. Detailed description

[0010] The following detailed description refers to the accompanying drawings, which illustrate certain aspects in which the disclosure can be implemented. In this context, directional terminology such as "top," "bottom," "front," "back," etc., may be used in relation to the orientation of the described figures. Since the components of the described devices can be positioned in a number of different orientations, the directional terminology serves only for illustration and is in no way restrictive. Other aspects may be used, and structural or logical modifications may be made, without departing from the concept of the present disclosure. Therefore, the following detailed description is not to be understood in a restrictive sense.

[0011] Fig. 1 contains the Fig. Figures 1A to 1D schematically show a semiconductor package 100 according to the disclosure. Fig. 1A and Fig. Figure 1B shows a perspective view or a top view of a semiconductor package 100. Furthermore, the Fig. 1C a first cross-sectional side view of the semiconductor package 100 along a line in the Fig. 1B indicated dashed line b-b', while the Fig. 1D a second cross-sectional side view of the semiconductor package 100 along a line in the Fig. 1B indicates the dashed line aa'.

[0012] The semiconductor package 100 can have a package body 2 with a first main surface 4, a second main surface 6 opposite the first main surface 4, and several side surfaces 8A to 8D extending between the two main surfaces 4 and 6. In the illustrated example, the package body 2 can have an exemplary number of four side surfaces 8A to 8D. A first die pad 10A and a second die pad 10B can be at least partially encapsulated in the package body 2. Both the first die pad 10A and the second die pad 10B can be uncovered by the material of the package body 2 at the first main surface 4.

[0013] The semiconductor package 100 can further contain one or more semiconductor chips, which may be at least partially encapsulated in the package body 2. In particular, the semiconductor package 100 can contain a first semiconductor chip arranged on the first die pad 10A and a second semiconductor chip arranged on the second die pad 10B. In the Fig. In the example shown in Figure 1, each of the semiconductor chips can be arranged on the underside of the respective die pad and can be covered by the housing body 2. Accordingly, the semiconductor chips can be arranged in the Fig. 1. Not be visible to a viewer.

[0014] The semiconductor package 100 can further contain several leads (or pins) 12, which may be at least partially encapsulated in the package body 2. The leads 12 may protrude from the package 2 at one or more of the side faces 8A to 8D of the package 2. In the example of the Fig. 1. The semiconductor package 100 can have four sets 12A to 12D of lead wires, each set having, for example, a number of four lead wires. In other examples, the number of lead wires per set can vary. The lead wires 12 and the die pads 10A, 10B can form part of a lead frame. In the example shown, the lead wires 12 can be bent downwards, so that the semiconductor package 100 can be designed to be mounted on a printed circuit board (PCB) (not shown) using a surface-mount technology. The sets of lead wires 12B and 12C can be located on opposite sides of the first die pad 10A. Similarly, the sets of lead wires 12A and 12D can be located on opposite sides of the second die pad 10B.

[0015] The semiconductor package 100 can further comprise a first groove 14 formed in the first main surface 4 of the package body 2, wherein the first groove 14 can be arranged between the first die pad 10A and the second die pad 10B. In the example of the Fig. 1. The first groove 14 can extend substantially in the y-direction. Furthermore, the semiconductor package 100 can have a second groove 16A and a third groove 16B formed in the first main surface 4. These grooves 16A and 16B can be arranged between the terminal conductors 12 and at least one of the first die pad 10A or the second die pad 10B. In the example of the Fig. 1. The grooves 16A and 16B can extend substantially in the x-direction. The second groove 16A can be located either between the set of connecting conductors 12A and the second die pad 10B, or between the set of connecting conductors 12B and the first die pad 10A. Similarly, the third groove 16B can be located between the set of connecting conductors 12C and the first die pad 10A, as well as between the set of connecting conductors 12D and the second die pad 10B.

[0016] As discussed above, the semiconductor package 100 can contain one or more semiconductor chips. In this context, it should be noted that in this description the terms "chip," "semiconductor chip," "die," and "semiconductor die" may be used interchangeably. In general, the semiconductor chips described herein may be made of an elemental semiconductor material (e.g., Si), a wide-bandgap semiconductor material, or a compound semiconductor material (e.g., SiC, GaN, SiGe, GaAs). In particular, each of the semiconductor chips arranged on the first die pad 10A and the second die pad 10B may contain or be equivalent to a power semiconductor component and may therefore be referred to as a power semiconductor chip. Here, the term "power semiconductor chip" may refer to a semiconductor chip that provides at least one of the properties of high-voltage blocking or high-current conductivity.A power semiconductor chip can be designed for high currents with a maximum current rating of a few amperes, such as 10 A, or a maximum current rating of up to 100 A or more. Similarly, the voltages associated with such current ratings can range from a few volts to several tens, hundreds, or even thousands of volts.

[0017] Power semiconductor chips can be used in any type of power application, such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), half-bridge circuits, power modules with a gate driver, etc. Power chips can, for example, contain or be part of a power device, such as a power MOSFET, a low-voltage (LV) MOSFET, a power IGBT (Insulated Gate Bipolar Transistor), a power diode, a superjunction power MOSFET, etc. In this case, the power semiconductor chips can be used specifically in half-bridge configurations and / or boost configurations, such as buck-boost converters or boost converters. Such configurations can, for example, include a SiC MOSFET and / or a SiC diode.The configurations can be used for industrial-grade products, such as those integrated into servo motor inverters or PFC (Power Factor Correction) amplifier stages. Applications include automotive, industrial drive, EV (Electric Vehicle) charging, and more. Exemplary circuits designed to be implemented in a semiconductor package according to this disclosure are shown in conjunction with the following. Fig. 12 and Fig. 13 shown and described.

[0018] The housing body 2 can be made of a material containing at least one of the following: a mold compound, an epoxy, a filled epoxy, a glass fiber-filled epoxy, an imide, a thermoplastic, a thermosetting polymer, a polymer blend, a laminate, etc. Various techniques can be used to encapsulate the components of the arrangement in the housing body 2, for example, at least one of compression molding, injection molding, powder molding, liquid molding, map molding, lamination, etc. In a non-restrictive example, a mold compound forming the housing body 2 can have a CTI (Comparative Tracking Index) value greater than approximately 600 V. The semiconductor housing of the Fig. 1 can, for example, correspond to a QDPAK (Quadruple DPAK) semiconductor package. As will be shown later, semiconductor packages according to the disclosure can provide increased tracking resistance and robust encapsulation.

[0019] The housing body 2 can form a housing (or package) for the encapsulated components and can therefore be designed to protect the encapsulated components of the semiconductor package 100 from external influences, such as moisture or mechanical shocks. As already discussed, the die pads 10A and 10B and the connection leads 12A to 12D can be at least partially uncovered by the material of the housing body 2. In this way, semiconductor chips located inside the semiconductor package 100 can be electrically accessible from outside the housing body 2 via the die pads 10A, 10B and / or the connection leads 12A to 12D. Exemplary electrical connections between the semiconductor chips and the die pads 10A, 10B, as well as between the semiconductor chips and the connection leads 12A to 12D, are described in the context of the Fig. 12 and Fig. 13 were shown and discussed.

[0020] The first die pad 10A and the second die pad 10B can be designed to operate at different electrical potentials. For example, die pads 10A and 10B can correspond to the drain contacts of different power transistors (see e.g. Fig. 12) and can therefore be at different electrical potentials during operation of the semiconductor package 100. To prevent a short circuit between the exposed surfaces of the die pads 10A and 10B, a minimum creepage distance between the die pads 10A and 10B may need to be maintained. In general, a creepage distance can be defined as the shortest distance along the surface of a solid insulating material between two conductive parts. A minimum creepage distance may depend, for example, on at least one of the material properties, effective voltage values, pollution levels, etc.

[0021] In the example of the Fig. 1. A creepage path can extend between the first diepad 10A and the second diepad 10B along a surface of the housing body 2. An exemplary path of such a creepage path 18 is shown in the side view of the Fig. 1C is represented by a dashed line. The first groove 14 can be designed to increase the creepage distance 18 along the housing body 2 between the first die pad 10A and the second die pad 10B. That is, by providing the first groove 14 in the housing body 2, the risk of a short circuit between the die pads 10A and 10B, and thus a malfunction of the semiconductor housing 100, can be avoided or at least reduced.

[0022] Similarly, one or more of the terminal conductors 12 and at least one of the first die pad 10A or the second die pad 10B can be designed to operate at different electrical potentials. For example, one or more of the terminal conductors 12D can have a gate contact and / or a source contact of a power transistor, while the second die pad 10B can correspond to a drain contact of the power transistor (see e.g. Fig. 12). An exemplary creepage distance 18 between one of the connecting conductors 12 and one of the die pads 10A, 10B can extend along a path which in the side view of the Fig. 1D is indicated by a dashed line. The second groove 16A and the third groove 16B can be designed to provide a creepage distance along the housing body 2 between the connecting conductor 12 and the die pads 10A, 10B, as shown in the Fig. They are displayed in 1D, can be enlarged, and can thus reduce the risk of a short circuit.

[0023] Viewed in the z-direction (see, for example, the top view of the Fig. 1B) The shape of the grooves 14, 16A, and 16B can depend on the electrical potentials that can be applied to the die pads 10A, 10B, and the terminals 12 during operation of the semiconductor package 100. Since each of the die pads 10A, 10B, and the terminals 12 can be designed to operate at different electrical potentials, minimum creepage distances may need to be provided between any of these components. Accordingly, in the example of the Fig. 1. The first groove 14, the second groove 16A, and the third groove 16B form an H-shape. In this case, each of the first groove 14, the second groove 16A, and the third groove 16B can extend along an entire side at least one of the first die pad 10A or the second die pad 10B.

[0024] Measured in the z-direction, the depth of a given groove can depend on the required minimum creepage distance between electrically conductive parts separated by the groove. For example, the depths of grooves 14, 16A, and 16B can range from approximately 0.1 mm to approximately 5.0 mm, and in particular from approximately 0.2 mm to approximately 2.0 mm. In one example, grooves 14, 16A, and 16B can have identical depths. In another example, the depth of the first groove 14 can differ from the depths of the second groove 16A and the third groove 16B. In the specific example of Fig. 1. The depths of the second groove 16A and the third groove 16B can be smaller than the depth of the first groove 14.

[0025] Furthermore, when measured in the z-direction, the grooves 14, 16A, and 16B may have different depths compared to the thicknesses of the die pads 10A and 10B. In the Fig. 1C can have a depth of the first groove 14 essentially equal to the thicknesses of the first die pad 10A and the second die pad 10B, while in the Fig. In 1D, the depth of the grooves 16A / 16B can be less than the thickness of the die pads 10A / 10B. In the cross-sectional side views of the Fig. 1C and Fig. In example 1D, grooves 14, 16A, and 16B can have a trapezoidal shape. In other examples, grooves 14, 16A, and 16B can have different shapes, e.g., circular, rectangular, square, elliptical, etc.

[0026] The semiconductor package 200 of the Fig. 2 can at least partially be the semiconductor package 100 of the Fig. 1. be similar. In the example of the Fig. 2. The first groove 14, the second groove 16A, and the third groove 16B can form an S-shape. Since the set of connecting conductors 12A and the second die pad 10B can be designed to operate at similar electrical potentials, no minimum creepage distance and therefore no groove between these components may be required. The same can apply to the set of connecting conductors 12C and the first die pad 10A.

[0027] The semiconductor package 300 of the Fig. 3 can fit 100 of the semiconductor package Fig. 1. be at least partially similar. Compared to the Fig. 1C can have a depth of the first groove 14 smaller than the thicknesses of the die pads 10A and 10B. This can lead to a reduced creepage distance 18 between the first die pad 10A and the second die pad 10B compared to the example of the Fig. 1C. The depth of the first groove 14 may be reduced in the case of smaller values ​​of the required minimum creepage distance.

[0028] The semiconductor package 400 of the Fig. 4 can fit 100 of the semiconductor package Fig. 1. be at least partially similar. Compared to the Fig. 1C can have a depth of the first groove 14 greater than the thicknesses of the die pads 10A and 10B. This can lead to a larger creepage distance 18 between the first die pad 10A and the second die pad 10B compared to the example of the Fig. 1C. The depth of the first groove 14 may be increased in the case of higher values ​​of the required minimum creepage distance.

[0029] The Fig. 5A and Fig. Figure 5B shows a perspective view or a top view of a semiconductor package 500 according to the disclosure. The semiconductor package 500 of Fig. 5 can fit 100 of the semiconductor package Fig. 1 be at least partially similar. The semiconductor package 500 can have one or more fourth grooves 20 formed in one or more of the side faces 8A to 8D of the package body 2. Each of the fourth grooves 20 can be arranged between connecting conductors 12 projecting from the package body 2. In the example of the Fig. 5. A first of the fourth grooves 20 can be arranged between the first set of connecting conductors 12A and the second set of connecting conductors 12B. Furthermore, a second of the fourth grooves 20 can be arranged between the third set of connecting conductors 12C and the fourth set of connecting conductors 12D.

[0030] The terminals 12 of the semiconductor package 500 can be designed to operate at different electrical potentials. For example, terminals of the second set of terminals 12B can be connected to a source electrode of a power transistor, while terminals of the first set of terminals 12A can be connected to a drain electrode of a power transistor (see e.g. Fig. 12). Each of the fourth grooves 20 can be designed to increase a creepage distance along the housing body 2 between connecting conductors 12 separated by the respective fourth groove 20 (see dashed lines).

[0031] The semiconductor package 600 of the Fig. 6 can be added to the semiconductor package 500 of the Fig. 5 are at least partially similar. In the example of the Fig. 6. A first of the fourth grooves 20 can overlap with the second groove 16A, while a second of the fourth grooves 20 can overlap with the third groove 16B. Due to the overlaps, creepage distances shown by dashed lines can differ from the Fig. 5 may be enlarged, so that the risk of short circuits and malfunctions of the semiconductor package 600 may be further reduced.

[0032] The semiconductor package 700 of the Fig. 7 can fit 100 of the semiconductor package Fig. 1. at least partially similar. In contrast to the previously described figures, the Fig. Figure 7 explicitly describes the first semiconductor chip 22A and the second semiconductor chip 22B, which are arranged on the first die pad 10A and the second die pad 10B, respectively. The semiconductor package 700 can contain an electrical connecting element 24, which is encapsulated in the package body 2 and extends over the first groove 14 between the first die pad 10A and the second die pad 10B. The electrical connecting element 24 can, for example, comprise at least one of a wire, a clip, a strip, etc. In the example of the Fig. 7. The first semiconductor chip 22A and the second semiconductor chip 22B can be electrically connected via the first die pad 10A and the electrical connecting element 24. In particular, one end of the electrical connecting element 24 can be connected to a source electrode of the second semiconductor chip 22B, while the other end of the electrical connecting element 24 can be connected to the first die pad 10A, which can be coupled to a drain electrode of the first semiconductor chip 22A (see, e.g., Figure 7). Fig. 12).

[0033] In the example of the Fig. The first die pad 10A, the second die pad 10B, and the connecting conductors 12 (not shown) can be parts of a dual-gauge frame. Measured in the z-direction, the thickness of the connecting conductors 12 can be less than at least the thickness of the first die pad 10A or the second die pad 10B. In one example of a dual-gauge frame, the thickness of at least one of the die pads 10A and 10B can be approximately 0.9 mm, while the thickness of the connecting conductors 12 can be approximately 0.5 mm or 0.6 mm. In another example, the thickness of at least one of the die pads 10A or 10B can be approximately 1.27 mm, while the thickness of the connecting conductors 12 can be approximately 0.5 mm or 0.6 mm. In yet another example, the thickness of at least one of the die pads 10A or 10B may be approximately 2.0 mm (or even more), while the thickness of the connecting conductors 12 may be approximately 0.5 mm or 0.6 mm.In some examples, the thickness of the connecting conductor can range from approximately 0.1 mm to approximately 0.2 mm.

[0034] Measured in the z-direction, the depth of the first groove 14 can be less than or equal to at least one thickness of the first die pad 10A or one thickness of the second die pad 10B. In the example of the Fig. 7. The depth D of the first groove 14 can essentially correspond to the thicknesses T of the two die pads 10A and 10B. Due to such values ​​of T and D, the electrical connector 24 can be of only a short length to form the electrical connection (such as a wire loop) across the first groove 14. In contrast, conventional arrangements with thinner die pads may require longer electrical connectors to bridge the first groove 14. A reduced length of the electrical connector 24 can lead to improved performance of the semiconductor package 700 by increasing a maximum rated current and / or reducing inductance and resistance.

[0035] The semiconductor package 800 of the Fig. 8 can be at least partially similar to the semiconductor packages described above. The depth of the first groove 14 can be greater than at least one thickness of the first die pad 10A or one thickness of the second die pad 10B. In the example of the Fig. 8. The depth D' of the first groove 14 can be greater than the thickness T of the die pads 10A and 10B. The first groove 14 with an increased depth D' can allow a dimension X' of the die pads 10A and 10B to be extended in the x-direction towards the first groove 14, while simultaneously providing a required minimum creepage distance between the die pads 10A and 10B. The increased dimension X' can result in an increased area of ​​the die pads 10A and 10B, thereby providing improved heat dissipation, for example, towards a heat sink (not shown) that may be positioned over exposed areas of the die pads 10A and 10B.

[0036] The semiconductor package 900 of the Fig. 9 can at least partially be the semiconductor package 800 of the Fig. 8 similar. As in connection with the Fig. As explained in Figure 8, increasing the depth D' of the first groove 14 can provide an extension of the die pads 10A and 10B towards the first groove 14 while still maintaining a required minimum creepage distance between the die pads 10A and 10B. Positioning the die pads 10A and 10B closer to the first groove 14 can allow a reduction in dimension L' of the semiconductor package 900 in the x-direction while essentially maintaining the size of the die pads 10A and 10B, thus providing the required heat dissipation.

[0037] The semiconductor package 1000 of the Fig. 10 can at least partially be the semiconductor package 100 of the Fig. 1. The semiconductor package 1000 can contain one or more optical markings 26, which can be arranged on at least one of the first groove 14, the second groove 16A, or the third groove 16B. Each of the grooves 14, 16A, and 16B can provide suitable and secure areas for the arrangement of the optical markings 26. In one example, an optical marking 26 can be equivalent to or include a laser marking. An optical marking 26 can, for example, contain at least one geometric shape or image (such as a rectangle, circle, ellipse, company logos, etc.), character, number, etc. An optical marking 26 can, for example, contain product-related information, such as one or more lot or batch numbers, a production date, a company name, a data matrix code designed to provide secure traceability of the individual device, etc. In the example of the Fig. 10 The semiconductor package 1000 may have an exemplary number of five optical markings, including a circle, a rectangle and three strings (see “HXXYYWW”, “12345678”, “INFINEON”).

[0038] The semiconductor package 1100 of the Fig. 11 can add 100 of the semiconductor package Fig. 1 be at least partially similar. The semiconductor package 1100 can contain an electrically insulating filler material 28 arranged over at least one of the first die pad 10A or the second die pad 10B. The electrically insulating filler material 28 can be arranged in at least one of the first groove 14, the second groove 16A, or the third groove 16B. For the sake of simplicity, in the Fig. Figure 11 shows only an arrangement of the electrically insulating filler material 28 in the first groove 14, while the other grooves of the arrangement are not shown. The electrically insulating filler material 28 can, for example, contain a polymer and / or a resin, which may or may not contain ceramic fillers. Typically, the electrically insulating filler material 28 can be or contain a thermal interface material (TIM), such as a silicone-based gap filler.

[0039] The semiconductor package 1100 can further include a heat sink 30 arranged above the electrically insulating filler material 28. The heat sink 30 can be in thermal contact with at least one of the top surfaces of the first die pad 10A or the second die pad 10B that are not covered by the material of the package body 2. In the example of the Fig. 11 The semiconductor package 1100 can correspond to a top-cooled device. In conventional arrangements (not shown), a thermal film can bridge the first groove 14, with a creepage distance between the die pads 10A and 10B extending along the thermal film. In contrast, the creepage distance 18 of the Fig. 11 extend over the entire area of ​​the first groove 14, thus providing an increased length. Double insulation can be provided by insulating the heat sink 30 with a tape, in particular adhesive tape. The tape material can contain epoxy, in particular at least one of polyimide, silicone, etc. Such a heat sink insulating layer can be tested before applying a gap filler to ensure its insulating properties.

[0040] The left part of the Fig. Figure 12 shows a top view of a semiconductor package 1200 according to the disclosure, while the right part of the Fig. Figure 12 shows a diagram of a circuit that can be implemented in the semiconductor package 1200. For example, the semiconductor package 1200 can be at least partially similar to the semiconductor package 100. Fig. 1. Similar to the first semiconductor chip and the second semiconductor chip of the semiconductor package 1200, each can contain a first power transistor 32A and a second power transistor 32B, respectively, each having a gate, a source, and a drain (see G1, S1, D1 and G2, S2, D2). Optionally, each of the power transistors 32A and 32B can have a Kelvin connection (see K1 and K2). The first power transistor 32A and the second power transistor 32B can be connected in series to form a low-side switch and a high-side switch of a half-bridge circuit. The mapping of the terminals and the exposed die pad areas of the semiconductor package 1200 to the individual electrical contacts of the circuit is shown in the left part of the Fig. 12 are given.

[0041] The left part of the Fig. Figure 13 shows a top view of a semiconductor package 1300 according to the disclosure, while the right part of the Fig. Figure 13 shows a diagram of a circuit that can be implemented in the semiconductor package 1300. For example, the semiconductor package 1300 can be at least partially similar to the semiconductor package 100. Fig. 1. The semiconductor package 1300 can contain a first semiconductor chip with a power transistor 32 having a gate, a source, and a drain (see G1, S1, D1) and a second semiconductor chip with a power diode 34 having an anode and a cathode (see A and K). The power transistor 32 and the power diode 34 can each form part of a boost configuration. The mapping of the leads and the exposed die pad areas of the semiconductor package 1300 to the individual electrical contacts of the circuit is shown in the left part of the Fig. 13. It is noted that the exemplary applications of the Fig. 12 and Fig. 13 are not exhaustive. Other applications may include or be based on two diodes, or an IGBT and a diode on a chip carrier, or a CoolMOS, or a GaN component, etc.

[0042] Fig. Figure 14 shows a flowchart of a process for manufacturing a semiconductor package according to the disclosure. The process is described in general terms to qualitatively specify aspects of the disclosure and may include further aspects. The process can be extended to include any of the aspects described in connection with other examples according to the disclosure. The process can be used to manufacture any semiconductor package according to the disclosure described herein.

[0043] In 38, a first die pad, a second die pad, and at least one connecting conductor can be provided. In 40, a first semiconductor chip can be arranged on the first die pad. In 42, a second semiconductor chip can be arranged on the second die pad. In 44, the first die pad, the second die pad, the first semiconductor chip, the second semiconductor chip, and the at least one connecting conductor can be encapsulated in a package body. The package body can have a first main surface, a second main surface opposite the first main surface, and a side surface extending between the two main surfaces. The first die pad can be uncovered by the package body at the first main surface. The second die pad can be uncovered by the package body at the first main surface. The at least one connecting conductor can protrude from the package body at the side surface.In example 46, a first groove can be formed in the first main surface, and this first groove can be located between the first die pad and the second die pad. In example 48, a second groove can be formed in the first main surface, and this second groove can be located between the at least one connecting conductor and at least one of the first or second die pads. In one example, the first and second grooves can be separate. In other examples, the first and second grooves can be connected or continuous. In these cases, the grooves can merge into one another. Continuous grooves can provide simpler gap filler dispensing, where, for example, only one point of gap filler is required. Furthermore, continuous grooves can provide better flow characteristics of the gap filler. Examples

[0044] The following section explains semiconductor packages and methods for manufacturing semiconductor packages using examples.

[0045] Example 1 is a semiconductor package comprising: a package body comprising a first principal surface, a second principal surface opposite the first principal surface, and a side surface extending between the two principal surfaces; a first die pad encapsulated in the package body, the first die pad being at least partially uncovered by the package body at the first principal surface; a second die pad encapsulated in the package body, the second die pad being at least partially uncovered by the package body at the first principal surface; a first semiconductor chip encapsulated in the package body and arranged on the first die pad; a second semiconductor chip encapsulated in the package body and arranged on the second die pad; and at least one terminal conductor encapsulated in the package body and projecting from the package body at the side surface.a first groove formed in the first main surface, wherein the first groove is arranged between the first die pad and the second die pad; and a second groove formed in the first main surface, wherein the second groove is arranged between the at least one connecting conductor and at least one of the first die pad or the second die pad.

[0046] Example 2 is a semiconductor package according to Example 1, wherein: the first diepad and the second diepad are designed to operate at different electrical potentials, and the at least one terminal conductor and at least one of the first diepad or the second diepad are designed to operate at different electrical potentials.

[0047] Example 3 is a semiconductor package according to Example 1 or 2, wherein: the first groove is designed to increase a creepage distance along the package body between the first die pad and the second die pad, and the second groove is designed to increase a creepage distance along the package body between the at least one terminal conductor and at least one of the first die pad or the second die pad.

[0048] Example 4 is a semiconductor package according to any of the preceding examples, wherein: the first die pad, the second die pad and the at least one terminal conductor are part of a dual-gauge conductor frame, and the thickness of the at least one terminal conductor is less than at least one thickness of the first die pad or one thickness of the second die pad.

[0049] Example 5 is a semiconductor package according to any of the preceding examples, further comprising: an electrical interconnect encapsulated in the package body and extending over the first groove between the first die pad and the second die pad, wherein the depth of the first groove is less than or equal to at least one of the thickness of the first die pad or the thickness of the second die pad.

[0050] Example 6 is a semiconductor package according to any one of Examples 1 to 4, wherein the depth of the first groove is greater than at least one of the thickness of the first die pad or the thickness of the second die pad.

[0051] Example 7 is a semiconductor package according to one of the preceding examples, wherein the depth of the second groove is less than the depth of the first groove.

[0052] Example 8 is a semiconductor package according to one of the preceding examples, wherein at least one of the first groove depth or second groove depth is in a range of 0.1 mm to 5.0 mm.

[0053] Example 9 is a semiconductor package according to any of the preceding examples, wherein each extends from the first groove and the second groove along an entire side of at least one of the first diepad or the second diepad.

[0054] Example 10 is a semiconductor package according to any of the preceding examples, further comprising: at least one additional terminal conductor encapsulated in the package body and extending from the package body at another side face of the package body, and a third groove formed in the first main face, wherein the third groove is arranged between the at least one additional terminal conductor and at least one of the first die pad or the second die pad.

[0055] Example 11 is a semiconductor package according to Example 10, wherein the first groove, the second groove and the third groove form an S-shape or an H-shape.

[0056] Example 12 is a semiconductor package according to one of the preceding examples, further comprising: a fourth groove formed in the side surface of the package body, wherein the fourth groove is arranged between a first terminal conductor and a second terminal conductor of the at least one terminal conductor.

[0057] Example 13 is a semiconductor package according to Example 12, wherein the fourth groove overlaps with the second groove.

[0058] Example 14 is a semiconductor package according to one of the preceding examples, wherein each of the first semiconductor chip and the second semiconductor chip comprises a power semiconductor.

[0059] Example 15 is a semiconductor package according to any of the preceding examples, wherein: the first semiconductor chip comprises a first power transistor forming a low-side switch of a half-bridge circuit, and the second semiconductor chip comprises a second power transistor connected in series with the first power transistor forming a high-side switch of the half-bridge circuit.

[0060] Example 16 is a semiconductor package according to any of Examples 1 to 15, wherein: the first semiconductor chip includes a power transistor forming part of a boost configuration, and the second semiconductor chip includes a power diode connected in series with the power transistor forming part of the boost configuration.

[0061] Example 17 is a semiconductor package according to any of the preceding examples, further comprising: a heat sink arranged above the first main surface, wherein the heat sink is in thermal contact with at least one of the uncovered parts of the first die pad and the second die pad.

[0062] Example 18 is a semiconductor package according to Example 17, further comprising: an electrically insulating filler material arranged between the heat sink and at least one of the first die pad or the second die pad, wherein the filler material is arranged in at least one of the first groove or the second groove.

[0063] Example 19 is a semiconductor package according to any of the preceding examples, further comprising: an optical marker arranged on at least one of the first groove or the second groove.

[0064] Example 20 is a semiconductor package comprising: a package body comprising a first principal surface, a second principal surface opposite the first principal surface, and a side surface extending between the two principal surfaces; a first die pad encapsulated in the package body, the first die pad being at least partially uncovered by the package body at the first principal surface; a second die pad encapsulated in the package body, the second die pad being at least partially uncovered by the package body at the first principal surface; a first semiconductor chip encapsulated in the package body and arranged on the first die pad; a second semiconductor chip encapsulated in the package body and arranged on the second die pad; a first groove formed in the first principal surface, the first groove being arranged between the first die pad and the second die pad;and an electrical connecting element encapsulated in the housing body and extending over the first groove between the first die pad and the second die pad, wherein the depth of the first groove is less than or equal to at least one thickness of the first die pad or one thickness of the second die pad.

[0065] Example 21 is a method for manufacturing a semiconductor package, the method comprising: providing a first die pad, a second die pad, and at least one connecting conductor; arranging a first semiconductor chip on the first die pad; arranging a second semiconductor chip on the second die pad; encapsulating the first die pad, the second die pad, the first semiconductor chip, the second semiconductor chip, and the at least one connecting conductor in a package body, the package body comprising a first major surface, a second major surface opposite the first major surface, and a side surface extending between the two major surfaces, wherein: the first die pad is at least partially uncovered by the package body at the first major surface, the second die pad is at least partially uncovered by the package body at the first major surface, and the at least one connecting conductor extends out of the package body at the side surface;Forming a first groove in the first main surface, wherein the first groove is arranged between the first die pad and the second die pad; and forming a second groove in the first main surface, wherein the second groove is arranged between the at least one connecting conductor and at least one of the first die pad or the second die pad.

[0066] As used in this description, the terms "connected," "coupled," "electrically connected," and / or "electrically coupled" do not necessarily mean that elements must be directly connected or coupled to each other. Intermediate elements may be provided between the "connected," "coupled," "electrically connected," or "electrically coupled" elements.

[0067] Furthermore, the word "over," used in reference to, for example, a layer of material formed or arranged "over" a surface of an object, can be used here to mean that the layer of material can be arranged "directly on," for example, in direct contact with the implied surface (e.g., formed, deposited, etc.). The word "over," used in reference to, for example, a layer of material formed or arranged "over" a surface, can also be used here to mean that the layer of material can be arranged "indirectly" on the implied surface (e.g., formed, deposited, etc.), with, for example, one or more additional layers arranged between the implied surface and the layer of material.

[0068] Where the terms "have," "contain," "exhibit," "with," or variations thereof are used either in the detailed description or in the claims, these terms shall be inclusive in a manner similar to the term "comprise." That is to say, as used herein, the terms "have," "contain," "exhibit," "with," "comprise," and the like are open terms that indicate the presence of specified elements or features but do not exclude additional elements or features. The articles "a," "an," and "the" shall include both the plural and the singular unless the context otherwise indicates.

[0069] Furthermore, the word "exemplary" is used herein to serve as an example, instance, or illustration. Any aspect or design described herein as "exemplary" is not necessarily to be interpreted as being advantageous over other aspects or designs. Rather, the use of the word "exemplary" is intended to illustrate concepts concretely. As used in this application, the term "or" is intended to mean an inclusive "or" and not an exclusive "or." That is to say, unless otherwise stated or clear from the context, "X uses A or B" is intended to mean one of the natural inclusive permutations. That is to say, if X uses A; uses X B; or X uses both A and B, then "X uses A or B" is satisfied under any one of the aforementioned cases.Furthermore, the articles “a” and “an”, as used in this application and the attached claims, can generally be interpreted as meaning “one or more”, unless otherwise specified or it is clear from the context to refer to a single form. In addition, at least one of A and B or the like generally means A or B or both A and B.

[0070] Devices and methods for manufacturing devices are described herein. Comments made in connection with a described device may also apply to a corresponding method, and vice versa. For example, if a particular component of a device is described, a corresponding method for manufacturing the device may involve an act of providing the component in a suitable manner, even if this act is not expressly described or illustrated in the figures.

Claims

[1] Semiconductor package, comprising: a housing body (2) comprising a first main surface (4), a second main surface (6) opposite the first main surface (4), and a side surface (8) extending between the two main surfaces (4, 6); a first die pad (10A) encapsulated in the housing body (2), wherein the first die pad (10A) is at least partially uncovered by the housing body (2) at the first main surface (4); a second diepad (10B) encapsulated in the housing body (2), wherein the second diepad (10B) is at least partially uncovered by the housing body (2) at the first main surface (4); a first semiconductor chip (22A) which is encapsulated in the housing body (2) and arranged on the first die pad (10A); a second semiconductor chip (22B) which is encapsulated in the housing body (2) and arranged on the second die pad (10B); at least one connecting conductor (12) which is encapsulated in the housing body (2) and protrudes from the housing body (2) at the side surface (8), wherein: the first die pad (10A), the second die pad (10B) and the at least one connecting conductor (12) are part of a dual-gauge conductor frame, and a thickness of at least one connecting conductor (12) is less than at least one of the thicknesses of the first die pad (10A) or the second die pad (10B); a first groove (14) formed in the first main surface (4), wherein the first groove (14) is arranged between the first die pad (10A) and the second die pad (10B); a second groove (16A) formed in the first main surface (4), wherein the second groove (16A) is arranged between the at least one connecting conductor (12) and at least one of the first die pad (10A) or the second die pad (10B); and an electrical connecting element (24) which is encapsulated in the housing body (2) and extends over the first groove (14) between the first die pad (10A) and the second die pad (10B), wherein a depth of the first groove (14) is less than or equal to at least one of the thickness of the first die pad (10A) or one of the thickness of the second die pad (10B). [2] Semiconductor package according to claim 1, wherein: the first diepad (10A) and the second diepad (10B) are designed to operate at different electrical potentials, and which at least one connecting conductor (12) and at least one of the first die pad (10A) or the second die pad (10B) are designed to operate at different electrical potentials. [3] Semiconductor package according to claim 1 or 2, wherein: the first groove (14) is designed to increase a creepage distance (18) along the housing body (2) between the first die pad (10A) and the second die pad (10B), and the second groove (16A) is designed to increase a creepage distance (18) along the housing body (2) between the at least one connecting conductor (12) and at least one of the first die pad (10A) or the second die pad (10B). [4] Semiconductor package according to one of the preceding claims, wherein the depth of the second groove (16A) is less than the depth of the first groove (14). [5] Semiconductor package according to one of the preceding claims, wherein at least one of the depth of the first groove (14) or of the depth of the second groove (16A) is in a range of 0.1 mm to 5.0 mm. [6] Semiconductor package according to one of the preceding claims, wherein each of the first groove (14) and the second groove (16A) extends along an entire side of at least one of the first die pad (10A) or the second die pad (10B). [7] Semiconductor housing according to any one of the preceding claims, further comprising: at least one further connecting conductor (12) which is encapsulated in the housing body (2) and protrudes from the housing body (2) at a further side surface (8) of the housing body (2), and a third groove (16B) formed in the first main surface (4), wherein the third groove (16B) is arranged between the at least one further connecting conductor (12) and at least one of the first die pad (10A) or the second die pad (10B). [8] Semiconductor package according to claim 7, wherein the first groove (14), the second groove (16A) and the third groove (16B) form an S-shape or an H-shape. [9] Semiconductor housing according to any one of the preceding claims, further comprising: a fourth groove (20) formed in the side surface (8) of the housing body (2), wherein the fourth groove (20) is arranged between a first connecting conductor and a second connecting conductor of the at least one connecting conductor (12). [10] Semiconductor package according to claim 9, wherein the fourth groove (20) overlaps with the second groove (16A). [11] Semiconductor package according to any of the preceding claims, wherein each of the first semiconductor chip (22A) and the second semiconductor chip (22B) comprises a power semiconductor. [12] Semiconductor package according to any one of the preceding claims, wherein: the first semiconductor chip (22A) includes a first power transistor (32A) that forms a low-side switch of a half-bridge circuit, and the second semiconductor chip (22B) includes a second power transistor (32B) which is connected in series with the first power transistor (32A) and forms a high-side switch of the half-bridge circuit. [13] Semiconductor package according to any one of claims 1 to 12, wherein: the first semiconductor chip (22A) includes a power transistor (32) which forms part of a boost configuration, and the second semiconductor chip (22B) includes a power diode (34) which is connected in series with the power transistor (32) and forms part of the boost configuration. [14] Semiconductor package according to any one of the preceding claims, further comprising: a heat sink (30) arranged above the first main surface (4), wherein the heat sink (30) is in thermal contact with at least one of the uncovered parts of the first die pad (10A) and the second die pad (10B). [15] Semiconductor housing according to claim 14, further comprising: an electrically insulating filler material (28) arranged between the heat sink (30) and at least one of the first die pad (10A) or the second die pad (10B), wherein the filler material (28) is arranged in at least one of the first groove (14) or the second groove (16A). [16] Semiconductor housing according to any one of the preceding claims, further comprising: an optical marker (26) arranged on at least one of the first groove (14) or the second groove (16A). [17] Method for manufacturing a semiconductor package, the method comprising: Providing a first die pad (10A), a second die pad (10B) and at least one connecting conductor (12), wherein: the first die pad (10A), the second die pad (10B) and the at least one connecting conductor (12) are part of a dual-gauge conductor frame, and a thickness of at least one connecting conductor (12) is less than at least one of the thicknesses of the first die pad (10A) or the second die pad (10B); Arranging a first semiconductor chip (22A) on the first die pad (10A); Arranging a second semiconductor chip (22B) on the second die pad (10B); Arranging an electrical connecting element (24) extending between the first die pad (10A) and the second die pad (10B); Encapsulating the first die pad (10A), the second die pad (10B), the first semiconductor chip (22A), the second semiconductor chip (22B), the electrical connecting element (24) and the at least one connecting conductor (12) in a housing body (2), wherein the housing body (2) comprises a first main surface (4), a second main surface (6) opposite the first main surface (4), and a side surface (8) extending between the two main surfaces (4, 6), wherein: the first die pad (10A) is at least partially uncovered by the housing body (2) at the first main surface (4), the second die pad (10B) is at least partially uncovered by the housing body (2) at the first main surface (4), and which at least one connecting conductor (12) protrudes from the housing body (2) at the side surface (8); Forming a first groove (14) in the first main surface (4), wherein the first groove (14) is arranged between the first die pad (10A) and the second die pad (10B), wherein the electrical connecting element (24) extends over the first groove (14) and the depth of the first groove (14) is less than or equal to at least one thickness of the first die pad (10A) or one thickness of the second die pad (10B); and Forming a second groove (16A) in the first main surface (4), wherein the second groove (16A) is arranged between the at least one connecting conductor (12) and at least one of the first die pad (10A) or the second die pad (10B).

Images