Secondary cross-coupling action in storage device with semicircular drain-side select gate and countermeasure

Abstract

Storage device (100), comprising: Memory cells (MC, 682, 683) connected to one of a plurality of word lines (WLLO-WLL10) and arranged in chains (NS1, NS2) and configured to maintain a threshold voltage; wherein each of the chains (NS1, NS2) has a plurality of drain-side select-gate transistors (SGD, SGDT) on a drain-side of one of the chain strings and includes one of a plurality of upper drain-side select-gate transistors (SGDT) connected to one of a plurality of bit lines (BL0, BL1, ...) and coupled to the memory cells (MC, 682, 683) of one of the chains (NS1, NS2); and Control means (110, 122) which are coupled to the multitude of word lines (WLL0-WLL10) and the multitude of bit lines (BL0, BL1, ...) and the multitude of drain-side select-gate transistors (SGDT) and are configured for: Applying an unselected overvoltage to an unselected plurality of upper drain-side select-gate (SGDT) transistors during a storage operation, and Simultaneous application of a selected overvoltage to selected of the plurality of upper drain-side select-gate transistors (SGDTs) during the storage operation, wherein the unselected overvoltage is intentionally different from the selected overvoltage, wherein the control means (110, 122) are further set up to adaptively adjust the selected overvoltage based on a transistor threshold voltage of the plurality of upper drain-side select-gate transistors (SGDTs).

Description

AREA

[0001] The present application relates to non-volatile storage devices and the operation of non-volatile storage devices. BACKGROUND

[0002] This section provides background information regarding the technology associated with the present disclosure and is therefore not necessarily prior art.

[0003] Semicircular drain-side select-gate (SC-SGD) memory technology offers several advantages, including a reduced chip size. SC-SGD is manufactured using etching technology to cut memory holes, giving them their semicircular shape and separating a block or row into multiple strings. Depending on the manufacturing process, certain inefficiencies can occur. For example, cutting a memory hole will remove at least some sections of the SC-SGD, such as the metal layer that otherwise shields electrical fields from the channel and / or charge-trap layer. Thus, the SC-SGD can be affected by a neighboring electrical field, potentially causing a parasitic transistor to leak along the SC-SGD transistor.In some cases, this leads to a measuring amplifier erroneously determining that the SC-SGD is conducting, which can interfere with certain measurement operations. Due to etching variation, some dies may be truncated onto an SGD layer, while others may be truncated onto layers forming dummy word lines. Consequently, electric fields, such as those introduced by weak erase bias on the dummy word lines from the word line cycle, are known to distort (e.g., turn down) the threshold voltage of SC-SGDs, thus altering the overall threshold voltage of a memory structure. Accordingly, there is a need for improved non-volatile memory devices and operating procedures.

[0004] Furthermore, the disclosures of US 2021 / 0 296 360 A1 and DE 11 2020 000 174 T5 may be helpful for understanding the present invention.

[0005] US 2021 / 0 296 360 A1 relates to a three-dimensional dual-density memory array. In one embodiment, a three-dimensional (3D) dual-density array comprises a chain of memory devices configured such that a first set of memory devices forms a first channel and a second set of memory devices forms a second channel. The array also includes a plurality of word lines coupled to the chain of memory devices. Each word line is coupled to a memory device forming the first channel and a memory device forming the second channel. The array also includes at least one drain selection gate that couples the first and second channels to a bit line.

[0006] DE 11 2020 000 174 T5 discloses a device with a memory array comprising a first set of NAND chains and a second set of NAND chains, wherein the first set of NAND chains and the second set of NAND chains are connected by a common bit line. The first set of NAND chains is connected to a first source line, and the second set of NAND chains is connected to a second source line. One or more control circuits communicate with the memory array, wherein the one or more control circuits are configured to identify a first word line within the memory array, which is connected to a first group of memory cells associated with the first set of NAND chains and to a second group of memory cells associated with the second set of NAND chains.The one or more control circuits are configured to determine a first forward voltage and a second forward voltage that differs from the first forward voltage, wherein the one or more control circuits are configured to cause the first group of memory cells to be programmed while the first forward voltage is applied to other word lines that differ from the first word line within the memory array, and to cause the second group of memory cells to be programmed while the second forward voltage is applied to the other word lines within the memory array. SUMMARY

[0007] This section provides a general summary of the present disclosure and is not a comprehensive disclosure of its full scope of protection or all of its features and benefits.

[0008] One purpose of the present disclosure is to provide a storage device and a method for operating the storage device which address and overcome the aforementioned disadvantages.

[0009] Accordingly, the present invention relates to a storage device according to claim 1, a control device according to claim 8 and a method according to claim 11.

[0010] Advantageous embodiments may include features of pending claims.

[0011] Further areas of application will become apparent from the description given herein. The description and specific examples in this summary serve only for illustration and are not intended to limit the scope of protection of this disclosure. DRAWINGS

[0012] The drawings described herein serve only to illustrate selected embodiments and not all possible implementations, and are not intended to limit the scope of protection of the present disclosure. Fig. 1A is a block diagram of an exemplary storage device according to the aspects of the disclosure; Fig. 1B a block diagram of an exemplary control circuit, which includes a programming circuit, a counting circuit and a determining circuit according to the aspects of the disclosure; Fig. Figure 2 illustrates schematic views of three types of memory architectures that use staggered memory chains according to the principles of revelation. Fig. 3A illustrates a cross-section of exemplary floating-gate memory cells in NAND chains according to the aspects of the disclosure; Fig. 3B illustrates a cross-section along a contact line that is in Fig. 3A is shown, according to the aspects of revelation; Fig. 4A and Fig. Figure 4B illustrates a non-volatile memory in which a charge-trapping memory cell uses a non-conductive dielectric material instead of a conductive floating gate to store charge in a non-volatile manner, according to the points of view of the disclosure; Fig. Figure 5 illustrates an example block diagram of the data capture block of Fig. 1 according to the aspects of revelation; Fig. Figure 6A is a perspective view of a set of blocks in an exemplary three-dimensional configuration of the memory array of Fig. 1 according to the aspects of revelation; Fig. Figure 6B illustrates an exemplary cross-sectional view of a section of one of the blocks of Fig. 6A according to the aspects of revelation; Fig. Figure 6C illustrates a diagram of the storage hole diameter in the stack of Fig. 6B according to the aspects of revelation; Fig. 6D illustrates a detailed view of a region of the stack of Fig. 6B according to the aspects of revelation; Fig. 7A illustrates a schematic top view of a storage array with a plurality of storage holes according to the points of view of the disclosure; Fig. 7B illustrates a cross-section of the storage array according to the aspects of the disclosure; Fig. 8A and Fig. Figure 8B illustrates an alternative storage structure without dummy holes according to the principles of revelation; Fig. Figure 9 illustrates an embodiment of a storage array with storage holes that are cut to different sizes based on the SHE cutting process according to the aspects of the disclosure; Fig. 10 illustrates a memory structure showing multiple memory holes cut by a SHE, according to the aspects of revelation; Fig. Figure 11 illustrates a graph showing the Vt distribution for a memory structure with memory holes according to the aspects of the revelation; Fig. 12 illustrates a circuit diagram that demonstrates transistors for a selected gate and an unselected gate according to the aspects of the disclosure; Fig. Figure 13 shows a cross-sectional view of adjacent selected chains and non-selected chains including drain-side select-gate SGD transistors associated with a memory hole cut by the SHE, and the resulting NSI and NCC effects according to the points of view of the disclosure; Fig. Figure 14 shows a further cross-sectional view of adjacent selected chains and non-selected chains, including drain-side select-gate transistors associated with a memory hole cut by the SHE, together with a corresponding top view of a section of the memory device according to the points of view of the disclosure; Fig. Figure 15 shows a threshold voltage distribution of semicircular drain-side-gate transistors and full-circle drain-side-gate transistors according to the aspects of the disclosure; Fig. Figure 16 shows the threshold voltage for a subthreshold of the threshold voltage for the semicircular drain-side select-gate transistors and full-circle transistors according to the aspects of the disclosure; Fig. 17A shows another cross-sectional view of adjacent selected chains and non-selected chains, including drain-side select-gate transistors associated with a memory hole cut by the SHE, together with a corresponding top view of a section of the memory device during a programming operation according to the points of disclosure; Fig. Figure 17B shows a corresponding perspective view of the adjacent selected chains and unselected chains of Fig. 17A, including the multitude of drain-side select-gate transistors coupled to one of a multitude of bit lines during the programming process, according to the points of disclosure; Fig. 18A shows a further cross-sectional view of adjacent selected chains and non-selected chains, including drain-side select-gate transistors associated with a memory hole cut by the SHE, together with a corresponding top view of a section of the memory device during a read operation according to the points of disclosure; Fig. Figure 18B shows a perspective view of the adjacent selected chains and unselected chains of Fig. 18A, including the drain-side select-gate transistors coupled to the bit line during the read operation, according to the points of disclosure; Fig. Figure 19A shows a further cross-sectional view of adjacent selected chains and non-selected chains, including drain-side select-gate transistors associated with a memory hole cut by the SHO, together with a corresponding top view of a section of the memory device during a programming operation in which the non-selected high voltage is electrically separated from the selected high voltage according to the terms of the disclosure; Fig. Figure 19B shows a perspective view of the adjacent selected chains and unselected chains of Fig. 19A, including the drain-side select-gate transistors coupled to the bit line during the programming process, with a different unselected high voltage and a selected high voltage according to the aspects of the disclosure; Fig. Figure 20A shows a further cross-sectional view of adjacent selected chains and non-selected chains, including drain-side select-gate transistors associated with a memory hole cut by the SHO, together with a corresponding top view of a section of the memory device during one of the read and verification operations, in which the non-selected high voltage is electrically separated from the selected high voltage according to the terms of the disclosure; Fig. Figure 20B shows a perspective view of the adjacent selected and unselected chains of Fig. 20A, which include drain-side select-gate transistors coupled to a different unselected high voltage and a selected high voltage according to aspects of the invention during one of the read and verification processes; Fig. Figure 21 shows threshold voltage distributions of the upper drain-side select-gate transistors with relatively lower and higher threshold voltages together with corresponding upper final threshold voltages according to the aspects of the disclosure; Fig. 22 and Fig. 23 show exemplary groups of chains and corresponding NCC and NSI effects when each of the chains is selected according to aspects of the revelation; and Fig. 24 and Fig. 25 illustrate steps of a procedure for operating the storage device in accordance with the aspects of the disclosure;

[0013] For clarity, identical reference numerals have been used, where possible, to denote identical elements common to the figures. It is considered that elements disclosed in one embodiment may be advantageously used in other embodiments without specific mention. DETAILED DESCRIPTION

[0014] The following description provides details to facilitate an understanding of the present disclosure. In some cases, specific circuits, structures, and techniques have not been described or shown in detail to avoid obscuring the disclosure.

[0015] In general, this disclosure relates to non-volatile storage devices of a type well suited for use in many applications. The non-volatile storage device and the associated methods of this disclosure are described in conjunction with one or more embodiments. However, the disclosed specific exemplary embodiments serve only to describe the inventive concepts, features, advantages, and problems with sufficient clarity to enable the person skilled in the art to understand and implement the disclosure. In particular, the exemplary embodiments are presented to ensure that this disclosure is thorough and fully conveys the scope of protection to the person skilled in the art. Numerous specific details are given, such as examples of specific components, devices, and methods, to facilitate a thorough understanding of embodiments of this disclosure.It will be obvious to the person skilled in the art that specific details need not be included, that exemplary embodiments can be embodied in many different forms, and that none should be interpreted in such a way as to limit the scope of protection of the disclosure. In some exemplary embodiments, well-known processes, well-known device structures, and well-known technologies are not described in detail.

[0016] In some memory devices, memory cells are connected together in a block or subblock, as in NAND chains. A NAND chain has a number of memory cells connected in series between one or more drain-side select-gate SG transistors (SGD transistors) on the drain side of the NAND chain, connected by a bit line, and one or more source-side select-gate SG transistors (SGS transistors) on the source side of the NAND chain, connected by a source line. Furthermore, the memory cells can be arranged with a common control gate line (e.g., word line) that acts on a control gate. A set of word lines extends from the source side of a block to the drain side of a block. Memory cells can also be connected in other types of chains and in other ways.

[0017] In a 3D memory structure, memory cells can be arranged in vertical chains within a stack, where the stack has alternating conductive and dielectric layers. The conductive layers act as word lines connected to the memory cells. The memory cells can include data storage cells suitable for storing user data and dummy or non-data storage cells unsuitable for storing user data.

[0018] Before programming certain non-volatile memory devices, the memory cells are typically erased. For some devices, the erasure process removes electrons from the floating gate of the memory cell being erased. Alternatively, the erasure process removes electrons from a charge-trapping layer.

[0019] Each memory cell can be assigned a data state according to write data in a programming instruction. Based on its data state, a memory cell either remains in the erased state or is programmed into a programmed state. For example, in a memory device with three bits per cell, there are eight data states, including the erased state and the programmed state.

[0020] During a programming operation, memory cells are programmed according to a word line programming sequence. For example, programming might begin on the word line at the source side of the block and continue on the word line at the drain side of the block. In one approach, each word line is fully programmed before the next one is programmed. For example, a first word line, WL0, is programmed using one or more programming pulses until programming is complete. Next, a second word line, WL1, is programmed using one or more programming pulses until programming is complete, and so on. A programming pulse might include a set of increasing programming voltages applied to the word line in appropriate programming loops or programming verification iterations.Verification processes or stages can be performed after each programming voltage to determine whether the memory cells have completed programming. Once programming is complete for a memory cell, it can be excluded from further programming, while programming continues for other memory cells in subsequent programming loops.

[0021] When generating various rows and strings for a memory structure, a cutting operation (e.g., Shallow Hole Etch or SHE) can be used. The SHW cut can divide a block (in memory) into multiple chains within the block. While the SHE can form / define the chains, the SHE cut can also split a chain, i.e., cut the edge memory holes in a chain in half (or roughly into two equal halves). In this respect, both the SGD and the channel are divided. However, because the cells are cut, the polychannel is exposed to a neighboring SGD electric field. The channel region near the neighboring SGD can easily be turned on during memory operations (i.e., NAND operation), which can lead to "SGD backfeed." In particular, half-circle SGD (SC-SGD) exhibits a lower threshold voltage Vt compared to full-circle SGD (FC-SGD), resulting in a wider Vt distribution of the SGD threshold voltage.This effect is known as the "neighbor SGD interference effect" (NSI). In addition, there is also a neighbor cross-coupling effect (NCC effect), where the secondary neighbor SGDT / dummy can couple with the SGD layer. These NSI and NCC effects can influence the drive-up or lock-down during programming operations and can also lead to leakage current, thus affecting the acquisition process (e.g., read or verification operations).

[0022] Several aspects of this disclosure can be implemented in the form of a device, a system, a process, or a computer program. Therefore, aspects of this disclosure can be implemented entirely in hardware or software (including, but not limited to, firmware, resident software, microcode, or the like) or be a combination of hardware and software components, which may generally be referred to as a "circuit," "module," "device," or "system." Furthermore, various aspects of this disclosure can take the form of a computer program process, which may be embodied, for example, in one or more non-transitory, computer-readable storage media that store computer-readable and / or executable program code.

[0023] Furthermore, various terms are used to refer to specific system components. Different companies may refer to the same or similar component by different names, and this description is not intended to distinguish between components that differ in name but not in function. Where various functional units described in the following disclosure are referred to as "modules," such characterization is not intended to unduly restrict the range of possible implementation mechanisms. For example, a "module" could be implemented as a hardware circuit incorporating custom VLSI (very large scale integration) circuitry or gate arrays, or commercially available semiconductors including logic chips, transistors, or other discrete components.In another example, a module can also be implemented in a programmable hardware device such as a field-programmable gate array (FPGA), programmable array logic, programmable logic device, or the like. Furthermore, a module can also be implemented, at least partially, by software executed by various types of processors. For example, a module can have a segment of executable code containing one or more physical or logical blocks of computer instructions that translate into an object, process, or function. It is also not necessary for the executable sections of such a module to be physically located together; they can also have different instructions stored in different locations which, when executed together, constitute the identified module and fulfill its stated purpose.The executable code may consist of a single instruction or a set of multiple instructions, but it may also be distributed across different code segments, different programs, multiple storage devices, etc. In a software or sub-software module implementation, the software sections may be stored on one or more computer-readable and / or executable storage media, which may include, but are not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor-based system, device, or any suitable combination thereof.In general, for the purposes of this disclosure, a computer-readable and / or executable storage medium can be any tangible and / or non-transitory storage medium capable of containing and / or storing a program for use by or in conjunction with a system, device, processor or instruction-executing apparatus.

[0024] Similarly, for the purposes of this disclosure, the term "component" can encompass any tangible, physical, and non-transient device. For example, a component may be in the form of a hardware logic circuit incorporating custom VLSI circuits, gate arrays, or other integrated circuits, or it may consist of commercially available semiconductors including logic chips, transistors, or other discrete components, or of other suitable mechanical and / or electronic devices. Furthermore, a component may also be implemented in programmable hardware devices such as field-programmable gate arrays (FPGAs), programmable array logic, programmable logic devices, and so forth.Furthermore, a component may comprise one or more silicon-based integrated circuit devices, such as chips, dies, die layers, and packages, or other discrete electrical devices arranged in an electrical communication configuration with one or more other components via electrical conductors, e.g., on a printed circuit board (PCB) or the like. Accordingly, a module, as defined above, may in certain embodiments be embodied by a component or implemented as a component, and in some cases, the terms module and component may be used interchangeably.

[0025] When the term "circuit" is used here, it includes one or more electrical and / or electronic components that form one or more conductive paths allowing electric current to flow. A circuit can be configured as a closed-loop or open-loop system. In a closed-loop configuration, the circuit components may provide a feedback path for the electric current. In contrast, in an open-loop configuration, the circuit components can still be considered a circuit even if they do not include a feedback path for the electric current. For example, an integrated circuit can be considered a circuit regardless of whether the integrated circuit is connected to ground (as a feedback path for electric current) or not.In certain exemplary embodiments, a circuit may comprise a set of integrated circuits, a single integrated circuit, or a section of an integrated circuit. For example, a circuit may include custom VLSI circuits, gate arrays, logic circuits, and / or other forms of integrated circuits, and may include commercially available semiconductors such as logic chips, transistors, or other discrete devices. In another example, a circuit may comprise one or more silicon-based integrated circuit devices, such as chips, dies, die layers, and packages, or other discrete electrical devices, arranged in an electrical communication configuration with one or more other components via electrical conductors, for example, a printed circuit board (PCB).A circuit could also be implemented as a synthesized circuit in terms of a programmable hardware device such as a field-programmable gate array (FPGA), programmable array logic, and / or programmable logic devices, etc. In other exemplary embodiments, a circuit may comprise a network of non-integrated electrical and / or electronic components (with or without integrated circuit devices). Accordingly, a module, as defined above, may in certain embodiments be embodied by a circuit or implemented as such.

[0026] It is understood that the embodiments disclosed herein may, in some examples, include one or more microprocessors and certain stored computer program instructions that control the one or more microprocessors to implement, in conjunction with certain non-processor circuits and other elements, some, most, or all of the functions disclosed herein. Alternatively, some or all of the functions could be implemented by a state machine that does not include any stored program instructions, or in one or more application-specific integrated circuits (ASICs) or field-programmable gate arrays (FPGAs) in which each function, or some combinations of certain functions, are implemented as custom logic. A combination of these approaches may also be used.Furthermore, subsequent references to a “controller” are defined as including individual circuit components, an application-specific integrated circuit (ASIC), a microcontroller with control software, a digital signal processor (DSP), a field-programmable gate array (FPGA) and / or a processor with control software, or combinations thereof.

[0027] Furthermore, the terms "program," "software," "software application," and the like, as they may be used herein, refer to a sequence of instructions designed to be executed on a computer-implemented system. Accordingly, a "program," "software," "application," "computer program," or "software application" may include a subroutine, a function, a procedure, an object procedure, an object implementation, an executable application, an applet, a servlet, source code, object code, a shared library / dynamic load library, and / or any other sequence of specific instructions designed to be executed on a computer system.

[0028] Furthermore, the terms "couple," "coupled," or "coupled," where used herein, are to be understood as either a direct or indirect connection. Thus, if a first device couples to, or is coupled to, a second device, this connection may be made by a direct connection or by an indirect connection via other devices (or components) and connections.

[0029] Regarding the use of expressions such as "an embodiment," "one (1) embodiment," "an exemplary embodiment," "a particular embodiment," or similar terms, these terms are intended to indicate that a specific feature, structure, function, process, or property described in connection with the embodiment is included in at least one embodiment of the present disclosure. Therefore, formulations such as "in one (1) embodiment," "in an embodiment," "in an exemplary embodiment," etc., may refer to the same embodiment, but need not; they mean "one or more, but not all, embodiments," unless expressly stated otherwise.Furthermore, the terms “including”, “with”, “including”, and variations thereof are used in an open manner and should therefore be interpreted as meaning “including, but not limited to…”, unless expressly stated otherwise. Moreover, an element preceded by “includes…” does not, without further qualification, preclude the existence of additional identical elements in the process, procedure, system, article, or facility in question that include the element.

[0030] The terms "a" and "the" also refer to "one or more" unless expressly stated otherwise. Furthermore, the phrase "at least one of A and B," as it may be used herein and / or in the following claims, where A and B are variables indicating a particular object or attribute, indicates a choice of A or B, or both A and B, similar to the phrase "and / or." If such a phrase contains more than two variables, it is defined as including only one of the variables, any one of the variables, any combination (or subcombination) of any one of the variables, and all of the variables.

[0031] Furthermore, the terms "approximately" or "about" are applied here to all numerical values, whether or not they are explicitly stated. These terms generally refer to a range of numerical values ​​that a person skilled in the art would consider equivalent to the stated values ​​(e.g., because they exhibit the same function or result). In certain cases, these terms may include numerical values ​​rounded to the nearest significant figure.

[0032] Furthermore, an enumeration of elements set forth herein does not imply that some or all of the enumerated elements are mutually exclusive and / or mutually inclusive, unless expressly stated otherwise. Moreover, the term "sentence," as used herein, is to be understood as meaning "one or more," and in the case of "sentences," it is to be understood as meaning a multiple of (or a multitude of) "one or more" and / or "one or more" according to set theory, unless expressly stated otherwise.

[0033] The following detailed description refers to the accompanying drawings, which form an integral part thereof. It is understood that the foregoing summary is for illustrative purposes only and is in no way intended to be limiting. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features will become clear with reference to the subsequent drawings and the detailed description. The description of elements in each figure may refer to elements in subsequent figures. Identical reference numbers may refer to identical elements in the figures, including alternative exemplary embodiments of the same elements.

[0034] Fig. Figure 1A is a block diagram of an exemplary storage device. The storage device 100 can include one or more storage dies 108. The storage die 108 includes a memory structure 126 consisting of memory cells, such as an array of memory cells, a control circuit 110, and read / write circuits 128. The memory structure 126 is addressable via word lines through a row decoder 124 and via bit lines through a column decoder 132. The read / write circuits 128 include several capture blocks SB1, SB2, ... SBp (capture circuitry) and enable the parallel reading or programming of a side of memory cells. Typically, a control 122 is contained in the same storage device 100 (e.g., a removable memory card) as the one or more storage dies 108.Commands and data are transmitted between the host 140 and the controller 122 via a data bus 120 and between the controller and the one or more memory dies 108 via lines 118.

[0035] The memory structure 126 can be two-dimensional or three-dimensional. The memory structure 126 can comprise one or more arrays of memory cells, including a three-dimensional array. The memory structure 126 can be a monolithic three-dimensional memory structure in which multiple memory layers are formed above (and not within) a single substrate, such as a wafer, without intervening substrates. The memory structure 126 can comprise any type of non-volatile memory monolithically formed in one or more physical layers of arrays of memory cells, which have an active region located above a silicon substrate. The memory structure 126 can be contained within a non-volatile memory device that includes circuitry associated with the operation of the memory cells, regardless of whether the associated circuitry is located above or within the substrate.

[0036] The control circuit 110 works in conjunction with the read / write circuits 128 to perform memory operations on the memory structure 126 and includes a state machine 112, an on-chip address decoder 114, and a power control module 116. The state machine 112 provides die-level control of memory operations.

[0037] A storage region 113, for example, can be allocated for programming parameters. These parameters can include a program voltage, a bias voltage for the program voltage, position parameters specifying the positions of the memory cells, parameters for the thickness of the contact leads, a verification voltage, and / or similar parameters. The position parameters can specify the position of a memory cell within the entire array of NAND flash memory, the position of a memory cell within a specific group of NAND flash memory, the position of a memory cell in a specific plane, and / or similar parameters. The parameters for the thickness of the contact leads can specify the thickness of the contact leads, the substrate or material from which the contact leads are made, and / or similar parameters.

[0038] The on-chip address decoder 114 provides an address interface between the address used by the host or memory controller and the hardware address used by decoders 124 and 132. The power control module 116 controls the power and voltages supplied to the word lines and bit lines during memory operations. It can include drivers for word lines, SGS and SGD transistors, and source lines. The sampling blocks can include bit line drivers in one approach. An SGS transistor is a select-gate transistor at the source end of a NAND flash memory, and an SGD transistor is a select-gate transistor at the drain end of a NAND flash memory.

[0039] In some embodiments, some of the components can be combined. In various designs, one or more of the components (alone or in combination), which differ from the memory structure 126, can be considered as at least one control circuit configured to perform the operations described herein. The control circuit can, for example, include one or a combination of control switching logic 110, state machine 112, decoder 114 / 132, power control module 116, acquisition blocks SBb, SB2, ..., SBp, read / write circuits 128, controller 122, and so on.

[0040] The control circuits can include a programming circuit configured to perform a program and check operation on a set of memory cells, wherein the one set of memory cells comprises memory cells assigned to represent one data state from a plurality of data states, and memory cells assigned to represent another data state from the plurality of data states; wherein the program and check operation comprises a plurality of program and check iterations; and wherein, in each program and check iteration, the programming circuit performs programming for the one word line, after which the programming circuit applies a check signal to the one word line. The control circuits can also include a counter circuit configured to determine the number of memory cells that have passed a verification test for the one data state.The control circuits may also include a determination circuit which is set up to determine, on the basis of an amount by which the counter reading exceeds a threshold, a specific program and test iteration from the multitude of program and test iterations in which a test for a different data state is performed for the memory cells allocated to represent a different data state.

[0041] Fig. 1B is, for example, a block diagram of an exemplary control circuit 150, which includes a programming circuit 151, a counting circuit 152 and a determination circuit 153.

[0042] The off-chip controller 122 can include a processor 122c, storage devices (memory) such as ROM 122a and RAM 122b, and an error correction code engine (ECC engine) 245. The ECC engine can correct a number of read errors caused when the upper tail of a Vth distribution becomes too high. However, in some cases, uncorrectable errors may occur. The techniques provided herein reduce the probability of uncorrectable errors.

[0043] The storage device(s) 122a, 122b contain code, such as a set of instructions, and the processor 122c is operable to execute the set of instructions and provide the functionality described herein. Alternatively or additionally, the processor 122c can access code from a storage device 126a of the memory structure 126, such as a reserved area of ​​memory cells in one or more word lines. Code can be used, for example, by the controller 122 to access the memory structure 126, such as for programming, reading, and erasing operations. The code can include boot code and control code (e.g., a set of instructions). The boot code is software that initializes the controller 122 during a boot or start-up process and enables the controller 122 to access the memory structure 126.The code can be used by the controller 122 to control one or more memory structures 126. At startup, the processor 122c retrieves the boot code from the ROM 122a or the storage device 126a for execution. The boot code initializes the system components and loads the control code into RAM 122b. Once the control code is loaded into RAM 122b, it is executed by the processor 122c. The control code contains drivers for performing basic tasks, such as controlling and allocating memory, prioritizing instruction processing, and controlling input and output ports.

[0044] In general, the control code may include instructions to perform the functions described herein, including the steps of the flowcharts explained below, and to provide the voltage waveforms, including those explained below.

[0045] In one embodiment, the host is a computing device (e.g., a laptop, desktop computer, smartphone, tablet, digital camera) that includes one or more processors, one or more processor-readable storage devices (RAM, ROM, flash memory, hard disk drive, solid-state memory) that store processor-readable code (e.g., software) for programming the one or more processors to perform the procedures described herein. The host may also include additional system memory, one or more input / output interfaces, and / or one or more input / output devices that communicate with the one or more processors.

[0046] Other types of non-volatile memory in addition to NAND flash memory can also be used.

[0047] Semiconductor memory devices include volatile memory devices, such as Dynamic Random Access Memory (DRAM) or Static Random Access Memory (SRAM), non-volatile memory devices, such as Resistive Random Access Memory (ReRAM), Electrically Erasable Programmable Read-Only Memory (EEPROM), flash memory (which can also be considered a subset of EEPROM), ferroelectric random access memory (FRAM), and magnetoresistive random access memory (MRAM), and other semiconductor elements capable of storing information. Each type of memory device can have different configurations. For example, flash memory devices can be configured in either a NAND or NOR configuration.

[0048] The memory devices can be composed of passive and / or active elements in any combination. As a non-limiting example, passive semiconductor memory elements include ReRAM device elements, which in some embodiments include a resistance-switching storage element such as an anti-fuse or phase-change material and optionally a control element such as a diode or transistor. Furthermore, as a non-limiting example, active semiconductor memory elements include EEPROM and flash memory device elements, which in some embodiments include elements containing a charge storage region, such as a floating gate, conductive nanoparticles, or a dielectric charge storage material.

[0049] Multiple memory elements can be arranged in series or such that each element is individually accessible. As a non-restrictive example, flash memory devices in a NAND configuration (NAND memory) typically contain memory elements connected in series. A NAND chain is an example of a set of transistors connected in series, comprising memory cells and SG transistors.

[0050] A NAND memory array can be configured to consist of multiple memory chains, where each chain comprises several memory elements sharing a single bit line and accessed as a group. Alternatively, memory elements can be configured so that each element is individually accessible, such as a NOR memory array. NAND and NOR memory configurations are examples, and memory elements can be configured in other ways. The semiconductor memory elements, which are placed in and / or on top of a substrate, can be arranged in two or three dimensions, such as a two-dimensional or three-dimensional memory structure.

[0051] In a two-dimensional memory structure, the semiconductor memory elements are arranged in a single plane or a single memory device plane. Typically, in a two-dimensional memory structure, memory elements are arranged in a plane (e.g., in a plane in the xy direction) that extends substantially parallel to a major face of a substrate that supports the memory elements. The substrate can be a wafer over or in which the layer of memory elements is formed, or it can be a support substrate that is attached to the memory elements after they have been formed. As a non-restrictive example, the substrate can include a semiconductor, such as silicon.

[0052] The memory elements can be arranged in an ordered array at the individual storage device level, such as in a multitude of rows and / or columns. However, the memory elements can also be arranged in irregular or non-orthogonal configurations. Each memory element can have two or more electrodes or contact lines, such as bit lines and word lines.

[0053] A three-dimensional storage array is arranged such that storage elements occupy multiple levels or multiple storage device levels, forming a structure in three dimensions (i.e. in the x, y, and z directions, with the z direction being essentially perpendicular and the x and y directions being essentially parallel to the main surface of the substrate).

[0054] As a non-restrictive example, a three-dimensional storage structure can be arranged vertically as a stack of multiple two-dimensional storage device levels. As another non-restrictive example, a three-dimensional storage array can be arranged as multiple vertical columns (e.g., columns extending substantially perpendicular to the main surface of the substrate, i.e., in the y-direction), with each column containing multiple storage elements. The columns can be arranged in a two-dimensional configuration, e.g., in an xy-plane, resulting in a three-dimensional arrangement of storage elements with elements on multiple vertically stacked storage levels. Other configurations of storage elements in three dimensions can also form a three-dimensional storage array.

[0055] As a non-restrictive example, in a three-dimensional arrangement of NAND chains, the memory elements can be interconnected to form a NAND chain within a single horizontal (e.g., xy) memory device plane. Alternatively, the memory elements can be interconnected to form a vertical NAND chain spanning multiple horizontal memory device planes. Other three-dimensional configurations can be considered, with some NAND chains containing memory elements within a single memory plane, while other chains containing memory elements spanning multiple memory planes. Three-dimensional memory arrays can also be configured in a NOR configuration and in a ReRAM configuration.

[0056] Typically, in a monolithic three-dimensional storage array, one or more storage device layers are formed on top of a single substrate. Optionally, the monolithic three-dimensional storage array can also have one or more storage layers at least partially within the single substrate. As a non-restrictive example, the substrate can be a semiconductor, such as silicon. In a monolithic three-dimensional array, the layers that form the individual storage device layers of the array are usually formed on top of the layers of the underlying storage device layers of the array. However, layers of adjacent storage device layers in a monolithic three-dimensional storage array can be shared, or there can be intermediate layers between storage device layers.

[0057] Two-dimensional arrays can also be formed separately and then packed together to create a non-monolithic, multi-layered memory device. For example, non-monolithic stacked memories can be constructed by forming memory layers on separate substrates and then stacking the memory layers on top of each other. The substrates can be thinned or removed from the memory device layers before stacking, but because the memory device layers are initially formed on separate substrates, the resulting memory arrays are not monolithic three-dimensional memory arrays. Furthermore, multiple two-dimensional or three-dimensional memory arrays (monolithic or non-monolithic) can be formed on separate chips and then packed together to form a stacked-chip memory device.

[0058] Fig. Figure 2 illustrates schematic views of three types of memory architectures that use staggered memory chains. For example, reference number 201 shows a schematic view of a first exemplary memory architecture, reference number 203 shows a schematic view of a second exemplary memory architecture, and reference number 205 shows a schematic view of a third exemplary memory architecture. In some embodiments, as shown, the memory architecture may include an array of staggered NAND chains.

[0059] Fig. Figure 2 illustrates blocks 200, 210 of memory cells in an exemplary two-dimensional configuration of memory array 126. Fig. 1. The memory array 126 can include many such memory blocks 200, 210. Each example block 200, 210 includes a number of NAND chains and corresponding bit lines, e.g., BL0, BL1, ..., which are shared by the blocks. Each NAND chain is connected at one end to a drain-side select gate (SGD), and the control gates of the drain-select gates are connected via a common SGD line. The NAND chains are connected at their other end to a source-side select gate (SGS), which in turn is connected to a common source line 220. Sixteen word lines, for example, WL0-WL15, extend between the SGDs and the SGSs. In some cases, dummy word lines, which do not contain user data, may also be used in the memory array alongside the select-gate transistors. Such dummy word lines can shield the marginal data word line from certain marginal effects.

[0060] One type of non-volatile memory that can be provided in the memory array is floating-gate memory, such as the type described in Fig. 3A and Fig. 3B is shown. However, other types of non-volatile memory can also be used. As discussed in more detail below, another example, shown in Fig. 4A and Fig. Figure 4B shows a charge-trapping memory cell that uses a non-conductive dielectric material instead of a conductive floating gate to store charge non-volatilely. A three-layer dielectric of silicon oxide, silicon nitride, and silicon oxide (“ONO”) is positioned between a conductive control gate and the surface of a semiconducting substrate above the memory cell channel. The cell is programmed by injecting electrons from the cell channel into the nitride, where they are trapped and stored in a confined area. This stored charge then modifies the threshold voltage of a section of the cell channel in a detectable manner. The cell is erased by injecting hot holes into the nitride.A similar cell can be provided in a split-gate configuration, where a doped polysilicon gate extends over a section of the memory cell channel, thereby forming a separate selection transistor.

[0061] Another approach uses NROM cells. Two bits, for example, are stored in each NROM cell, where a dielectric ONO layer extends across the channel between source and drain diffusion. The charge for one data bit is localized in the dielectric layer adjacent to the drain, and the charge for the other data bit is localized in the dielectric layer adjacent to the source. Multi-state data storage is achieved by separately reading binary states from the physically separated charge storage areas within the dielectric. Other types of non-volatile memory are also known.

[0062] Fig. Figure 3A illustrates a cross-section of exemplary floating-gate memory cells 300, 310, and 320 in NAND chains. In this figure, the direction of a bit line or NAND chain runs inwards, and the direction of a word line runs from left to right. As an example, the word line 324 extends across NAND chains that enclose the respective channel regions 306, 316, and 326. Memory cell 300 includes a control gate 302, a floating gate 304, a tunnel oxide layer 305, and the channel region 306. Memory cell 310 includes a control gate 312, a floating gate 314, a tunnel oxide layer 315, and the channel region 316. Memory cell 320 includes a control gate 322, a floating gate 321, a tunnel oxide layer 325, and the channel region 326. Each memory cell 300, 310, 320 is located in a separate NAND chain. An interpolar dielectric (IPD) layer 328 is also illustrated.Control gates 302, 312, and 322 are sections of the word line. A cross-sectional view along the contact line connector 329 is shown in [reference]. Fig. 3B provided.

[0063] The control gate 302, 312, 322 surrounds the floating gate 304, 314, 321, thereby increasing the surface contact area between the control gate 302, 312, 322 and the floating gate 304, 314, 321. This results in a higher IPD capacity, leading to a higher coupling ratio, which facilitates programming and erasing. However, as NAND flash memory devices are miniaturized, the distance between adjacent cells 300, 310, 320 decreases, leaving almost no space between two adjacent floating gates 302, 312, 322 for the control gate 302, 312, 322 and the IPD layer 328.

[0064] As an alternative, as in Fig. 4A and Fig. Figure 4B shows the flat or planar memory cell 400, 410, 420 developed, in which the control gate 402, 412, 422 is flat or planar; that is, it does not enclose the floating gate and only makes contact with the charge storage layer 428 from above. In this case, a tall floating gate is not advantageous. Instead, the floating gate is made significantly thinner. Furthermore, the floating gate can be used for charge storage, or a thin charge trap layer can be used to trap charge. This approach can avoid the problem of ballistic electron transport, in which an electron can migrate through the floating gate during programming after tunneling through the tunnel oxide.

[0065] Fig. Figure 4A shows a cross-section of exemplary charge-trapping memory cells 400, 410, 420 in NAND chains. The view is in a word-direction direction of memory cells 400, 410, 420, which includes a flat control gate and charge-trapping regions as a two-dimensional example of memory cells 400, 410, 420 in the memory array 126. Fig. 1. The charge-capture memory can be used in a NOR and NAND flash memory device. In this technology, an insulator such as a SiN film is used to store electrons, in contrast to a floating-gate MOSFET technology, which uses a conductor such as doped polycrystalline silicon to store electrons. For example, a word line 424 extends across NAND chains, enclosing respective channel regions 406, 416, and 426. Sections of the word line provide control gates 402, 412, and 422. Below the word lead are an IPD layer 428, charge-trapping layers 404, 414, 421, polysilicon layers 405, 415, 425, and tunnel layers 409, 407, 408. Each charge-trapping layer 404, 414, 421 extends continuously in its respective NAND chain. The flat configuration of the control gate allows for a thinner profile than a floating gate.Furthermore, the memory cells can be placed closer together.

[0066] Fig. 4B illustrates a cross-section of the structure of Fig. 4A along the contact line connector 429. The NAND chain 430 includes an SGS transistor 431, exemplary memory cells 400, 433, ... 435, and an SGD transistor 436. Through-holes in the IPD layer 428 in the SGS and SGD transistors 431 and 436 enable communication between the control gate layers 402 and the floating gate layers. The control gate 402 layers and floating gate layers can be made of polysilicon, and the tunnel oxide layer can be made of silicon oxide, for example. The IPD layer 428 can be a stack of nitrides (N) and oxides (O), as in a NONON configuration.

[0067] The NAND chain can be formed on a substrate containing a p-type substrate region 455, an n-type well 456, and a p-type well 457. N-type source / drain diffusion regions sd1, sd2, sd3, sd4, sd5, sd6, and sd7 are formed in the p-type well. A channel voltage, Vch, can be applied directly to the channel region of the substrate.

[0068] Fig. Figure 5 illustrates an example block diagram of the data acquisition block SB1 from Fig. 1. In one approach, a data acquisition block has multiple acquisition circuits. Each acquisition circuit is assigned data storage. For example, acquisition circuits 550a, 551a, 552a, and 553a are assigned to data storage 550b, 551b, 552b, and 553b, respectively. In this approach, different subsets of bit lines can be sampled using different acquisition blocks. This allows the processor load associated with the acquisition circuits to be distributed and handled by a separate processor in each acquisition block. For example, the acquisition circuit controller 560 in SB1 can communicate with the set of acquisition circuits and storage. The acquisition circuit controller 560 can include a preload circuit 561, which provides each acquisition circuit with a voltage for setting a preload voltage.In one possible approach, the voltage for each acquisition circuit is provided independently, for example, via the data bus and a local bus. In another possible approach, a common voltage is provided to each acquisition circuit simultaneously. The acquisition circuit controller 560 can also include a preload circuit 561, a memory 562, and a processor 563. The memory 562 can store codes that can be executed by the processor to perform the functions described herein. These functions can include reading the hold memories 550b, 551b, 552b, 553b associated with the acquisition circuits 550a, 551a, 552a, 553a, setting bit values ​​in the hold memories, and providing voltages to set preload levels in the acquisition nodes of the acquisition circuits 550a, 551a, 552a, 553a.Further example details for the control of the detection circuit 560 and the detection circuits 550a, 551a, 552a, 553a are provided below.

[0069] In some embodiments, a memory cell may include a flag register, which includes a set of hold memories for storing flag bits. In some embodiments, a set of flag registers may correspond to a set of data states. In some embodiments, one or more flag registers may be used to control a type of verification technique for verifying memory cells. In some embodiments, the output of a flag bit may modify the associated logic of the device, such as the address decoding switching logic, to select a specific block of cells. A bulk operation (such as an erase operation) may be performed using the flags set in the flag register, or a combination of the flag register with the address register, as in implicit addressing, or alternatively, by direct addressing using the address register alone.

[0070] Fig. Figure 6A is a perspective view of a set of blocks 600 in an exemplary three-dimensional configuration of the memory array 126. Fig. 1. The substrate contains exemplary memory cell (memory element) blocks BLK0, BLK1, BLK2, and BLK3, and a peripheral region 604 with switching logic for use by blocks BLK0, BLK1, BLK2, and BLK3. For example, the circuits can include voltage drivers 605, which can be connected to control gate layers of blocks BLK0, BLK1, BLK2, and BLK3. In one approach, control gate layers at a common level in blocks BLK0, BLK1, BLK2, and BLK3 are jointly controlled. The substrate 601 can also support switching logic beneath blocks BLK0, BLK1, BLK2, and BLK3, along with one or more lower metal layers structured in conductor tracks to transmit signals from the switching logic. Blocks BLK0, BLK1, BLK2, and BLK3 are formed in an intermediate region 602 of the memory device.In an upper region 603 of the memory device, one or more upper metal layers are structured in conductive traces to carry signals from the switching logic. Each block BLK0, BLK1, BLK2, BLK3 has a stacked memory cell region, with alternating levels of the stack representing word lines. In one possible approach, each block BLK0, BLK1, BLK2, BLK3 has opposite stepped sides from which vertical contacts extend upward to an upper metal layer to connect to conductive traces. While four blocks BLK0, BLK1, BLK2, BLK3 are illustrated by way of example, two or more blocks extending in the x and / or y direction can be used.

[0071] In one possible approach, the length of the plane in the x-direction represents a direction in which signal paths extend to word lines in one or more of the upper metal layers (a word line or SGD line direction), and the width of the plane in the y-direction represents a direction in which signal paths extend to bit lines in one or more of the upper metal layers (a bit line direction). The z-direction represents a height of the storage device.

[0072] Fig. Figure 6B illustrates an exemplary cross-section of a section from one of the blocks BLK0, BLK1, BLK2, BLK3. Fig. 6A. The block has a stack 610 consisting of alternating conductive and dielectric layers. In this example, the conductive layers have two SGD layers, two SGS layers, and four dummy word line layers DWLD0, DWLD1, DWLS0, and DWLS1, in addition to the data word line layers (word lines) WLL0–WLL10. The dielectric layers are designated DL0 to DL19. Furthermore, regions of the stack 610 are illustrated that contain the NAND chains NS1 and NS2. Each NAND chain includes a memory hole 618, 619, which is filled with materials that form memory cells adjacent to the word lines. A region 622 of the stack 610 is shown in Fig. 6D is shown in more detail and discussed in more detail below.

[0073] The 610 stack includes a substrate 611, an insulating layer 612 on the substrate 611, and a section of a source line SL. NS1 has a source end 613 on a bottom surface 614 of the stack and a drain end 615 on a top surface 616 of the stack 610. Contact line connectors (e.g., slots, such as metal-filled slots) 617, 620 can be provided periodically across the stack 610 as connections extending through the stack 610, such as for connecting the source line to a specific contact line above the stack 610. The contact line connectors 617, 620 can be used in forming the word lines and subsequently filled with metal. A section of a bit line BL0 is also illustrated. A conductive via 621 connects the drain end 615 to BL0.

[0074] Fig. Figure 6C illustrates a graphical representation of the memory hole diameter in the stack of Fig. 6B. The vertical axis is on the stack of Fig. 6B is aligned and illustrates a width (wMH), e.g., the diameter of memory holes 618 and 619. The word line layers WLL0-WLL10 of Fig. 6A are repeated as an example and are located at the respective heights z0-z10 in the stack. In such a storage device, the storage holes etched through the stack have a very high aspect ratio. For example, a depth-to-diameter ratio of about 25 to 30 is common. The storage holes may have a circular cross-section. Due to the etching process, the storage hole width can vary along the length of the hole. Typically, the diameter decreases from top to bottom in the storage hole. That is, the storage holes taper, narrowing at the bottom of the stack. In some cases, there is a slight narrowing at the top of the hole near the select gate, so the diameter becomes somewhat wider before decreasing from top to bottom of the storage hole.

[0075] Due to the uneven width of the memory hole, the programming speed, including the programming edge and erase speed of the memory cells, can vary depending on their position along the memory hole, e.g., their height in the stack. With a smaller memory hole diameter, the electric field across the tunnel oxide is relatively stronger, resulting in relatively higher programming and erase speeds. One approach is to define groups of adjacent word lines for which the memory hole diameter is similar, e.g., within a defined diameter range, and to apply an optimized verification scheme to each word line in a group. Different groups may have differently optimized verification schemes.

[0076] Fig. Figure 6D illustrates a close-up of region 622 of stack 610. Fig. 6B. Memory cells are formed at the various levels of the stack at the intersection of a word line layer and a memory hole. In this example, the SGD transistors 680, 681 are provided above the dummy memory cells 682, 683 and a data memory cell MC. A series of layers can be deposited along the side wall (SW) of the memory hole 630 and / or within each word line layer, for example, using atomic layer deposition. For example, each column (e.g., the column formed by the materials within a memory hole 630) can include a charge-trapping layer or film 663 such as SiN or another nitride, a tunnel layer 664, a polysilicon body or channel 665, and a dielectric core 666. A word conduction layer can include a blocking oxide / block high-k material 660, a metal barrier 661, and a conductive metal 662 such as tungsten as a control gate.For example, control gates 690, 691, 692, 693, and 694 are provided. In this example, all layers except the metal layer are provided in memory hole 630. In other approaches, some of the layers may be located in the control gate layer. Additional columns are similarly formed in the various memory holes. A column can form a columnar active area (AA) of a NAND flash memory.

[0077] When a memory cell MC is programmed, electrons are stored in a section of the charge-trapping layer 663 that is assigned to the memory cell MC. These electrons are drawn into the charge-trapping layer 663 from channel 665 and through tunneling layer 664. The Vth of a memory cell MC is increased proportionally to the amount of stored charge. During an erase operation, the electrons return to channel 665.

[0078] Each of the storage holes 630 can be filled with a variety of ring-shaped layers, comprising a blocking oxide layer, a charge-trapping layer 663, a tunneling layer 664, and a channeling layer 665. A core region of each of the storage holes 630 is filled with a body material, and the variety of ring-shaped layers is located between the core region and the word line in each of the storage holes 630.

[0079] The NAND chain can be viewed as a floating-body channel 665, since the length of the channel 665 is not formed on a substrate. Furthermore, the NAND chain is provided by a multitude of word conduction layers stacked on top of each other and separated by dielectric layers.

[0080] Fig. Figure 7A shows a schematic top view of a memory array 700 with multiple memory holes 722, which may be vertical memory cell strands as described herein, and multiple dummy holes 705 that do not require a complete memory structure. A shallow trench etch or shallow etch feature (SHE) 710 extends through a plurality of word lines (e.g., five) but not completely through the chip to electrically isolate adjacent strands from one another. The SHE extends directly through a group of aligned dummy holes 705, thus preventing these dummy holes 705 from storing data or otherwise being functional memory cells.

[0081] Referring now to Fig. 8A and Fig. There are no dummy holes in 8B. Unlike the 700 memory architecture from Fig. 7A and Fig. In 7B, the SHE 810 is located in a gap between two adjacent rows of memory cells 825 and overlaps with memory holes 825, creating a working strand that has a trench etched into at least one side of the upper SGD switch of the working memory strand, shown here as memory holes 825. This configuration significantly improves the yield and memory density, as all memory holes 822 and 825 are functional, meaning fewer memory holes are wasted.

[0082] Unlike the fully circular memory holes 822, the memory holes 825 and the SGD switches, which are partially intersected by the SHE 810, have a semicircular shape, which can be either a full semicircle or more or less than a semicircle. In some cases, the memory holes 825 and SGD switches may be fewer than semicircles on one side of the SHE 810 and more than semicircles on the other side of the SHE 810.

[0083] Memory holes 822 and 825 are connected to multiple bit lines 830 (in Fig. 8A (designated as bit lines 0-7) are connected. For simplicity, only eight bit lines 830 are shown. The bit lines 830 extend across the memory holes and are connected to selected memory holes via connection points. The memory holes in each strand are also connected at one end to an SGD switch and at the other end to an SGS switch. The SHE trench 810 can be etched into a section of the SGD switch.

[0084] Referring now to Fig. 9. Due to variations and imperfections in a manufacturing process, the SHE may not be centered between adjacent rows of storage holes. When this occurs, the semicircular SGDs on one side of the SHE trench may be dimensionally larger than the semicircular SGDs on the other side of the SHE trench. The storage holes containing the dimensionally larger SGDs are referred to as "undershifted SGDs," and the storage holes containing the dimensionally smaller SGDs are referred to as "overshifted storage holes." As illustrated, each chain has one row of undershifted semicircular SGDs, two rows of full-circle SGDs, and one row of overshifted semicircular SGDs.Referring to chain 1, row 0 includes overshifted semicircle SGDs 925b; rows 1 and 2 include full circle SGDs 922; and row 3 includes undershifted semicircle SGDs 925a.

[0085] Fig. Figure 10 illustrates a memory structure 1000, which shows several memory holes cut by an SHE 1010, according to some described embodiments. The memory structure 1000 includes several FC-SGD memory holes 1022 (representative of several additional FC-SGDs) as well as several SC-SGD memory holes 1025a and 1025b (representative of several additional SC-SGDs) with the SC-SGD memory holes 1025a and 1025b cut by the SHE 1010. In addition, the memory holes of the memory structure 1000 are surrounded by a metal layer 1032, such as a tungsten metal layer. During certain operations (e.g., a read operation), a bias is applied to two regions (divided by the SHE 1010). For example, during a read option, a bias is applied to a region 1030a of memory holes so that memory chains connected to the memory holes in region 1030a can be read.This region 1030a can be referred to as a selected SGD. Simultaneously, however, a bias is applied to a region 1030b of memory holes that is not selected for reading. This region 1030a can be referred to as an unselected SGD.

[0086] The SHE 1010 creates electrical insulation, thus separating regions 1030a and 1030b. However, as shown in the enlarged view, the SHE 1010 cuts and removes parts of the SC-SGD, such as the storage hole 1025b. For example, the storage hole 1025b includes a channel 1034 (used as a passage for electrons), a charge-trap layer 1036 (used to store electrons and determine Vt), and a dielectric layer 1038, such as aluminum oxide (used to block external electrical voltages). Additionally, an oxide layer 1040 extends into the storage hole 1025b and separates the channel 1034 from the charge-trap layer 1036, and also separates the charge-trap layer 1036 from the dielectric layer 1038. These features mentioned above—channel 1034, charge-trap layer 1036, and dielectric layer 1038—are found in both FC-SGD and SC-SGD.

[0087] In full-circle memory holes, the respective channels, charge-trap layers, and metal layers each resemble a ring. However, due to the SHE 1010, sections of channel 1034, charge-trap layer 1036, and dielectric layer 1038 are partially removed. While memory 1025b remains functional with these partially removed features, certain problems arise. For example, due to the partial removal of dielectric layer 1038, both channel 1034 and charge-trap layer 1036 are exposed to an electric field 1042 (represented by longer dashed arrows) due to the bias applied to region 1030b (unselected SGD) during the read operation. As a result, the end regions 1044a and 1044b (or peaks) of channel 1034 can essentially be activated during the read operation, causing the end regions 1044a and 1044b to become conductive.A diagram of a transistor (unlabeled) represents a gate of end regions 1044a and 1044b that can be activated. This, in turn, can effectively lower the Vt of memory hole 1025b required to activate channel 1034. This illustrates a problem of NSI. It should also be noted that memory hole 1025b is generally representative of other SC-SGD memory holes in . Fig. 10 is the number. However, the extent to which each memory hole is cut by the SHE 1010 can vary.

[0088] Fig. Figure 11 illustrates a graph 1100 showing the Vt distribution for a memory structure with memory holes according to some described embodiments. The counts (program erase cycles) versus Vt are shown. A curve 1110a represents the Vt distribution for all SGD memory holes. A curve 1110b also represents the Vt distribution for all FC-SGD memory holes, while a curve 1110c represents the Vt distribution for all SC-SGD memory holes. In this respect, curves 1110b and 1110c represent the components of curve 1110a. Curve 1110c shows that the Vt distribution will "switch down" or reduce the overall Vt distribution. Furthermore, the effect of SC-SGD broadens curve 1110a (the overall curve), making the Vt distribution less predictable. Several modifications shown and described below are used to overcome these challenges when using SC-SGD.

[0089] Fig. Figure 12 illustrates a circuit diagram 1200, which depicts transistors for a selected gate and an unselected gate. As shown, transistor 1250a represents a selected SC-SGD memory hole, such as memory hole 1025b (shown in Figure 12). Fig. 10). In particular, transistor 1250a represents the end regions 1044a and 1044b (shown in Fig. 10). The 1250a transistor is designed to operate based on a predetermined select-gate voltage V. SEL to activate. A transistor 1250a also represents an unselected SC-SGD memory hole, such as memory hole 1025a (shown in Fig. 10) Additionally, a 1250c transistor (a parasitic transistor) is connected in parallel to the 1250a transistor. Ideally, the circuit conducts current when V SELThe voltage at transistor 1250a is sufficiently high. However, if a bias voltage is applied to transistor 1250b (for example, during a read operation), an electric field 1242, referred to as NSI, can cause transistor 1250c to turn on. When this occurs, leakage current flows to the source, causing a read amplifier 1260 to determine that transistor 1250a is conducting when transistor 1250a is not turned on, while transistor 1250c, acting as a parasitic transistor, is conducting.

[0090] The equation for determining whether the electric field 1242 is sufficient to switch on the transistor 1250c can be determined by: VOD=α*VATTACKER−VSELSRC where V OD the overload voltage, α is a coupling factor (based on the width of the SHE and described below), V ATTACKER the “attacking” or interference voltage due to NSI is, and V SELSRCThe source line voltage is V. ATTACKER This is also based on the resulting voltage due to the bias applied to the unselected gate. It is evident that V OD similar to a conventional transistor formula, such as a gate-source voltage ("V"). GS “). Furthermore, it is evident that V OD by V ATTACKER is dependent and proportional to it (provided α is greater than 0). Accordingly, it switches on. The transistor 1250c is switched on when V OD is sufficiently high, which corresponds to a sufficiently high V ATTACKER corresponds.

[0091] To V OD To sufficiently reduce the electric field 1242 from the switching on of the transistor, V ATTACKERis manipulated. For example, by applying a negative bias voltage, such as -2 V, to the unselected gate, the voltage induced by the electric field in transistor 1250c can be sufficiently reduced (in some cases to 0 V). As a result, transistor 1250c does not switch on accidentally, and current may only flow through transistor 1250a under the condition that V SEL is sufficiently high. To provide the negative voltage, additional modifications, such as a triple-well transistor, can be used.

[0092] As discussed above and on Fig. 10, referring back, in storage holes or chains, including semicircular SGD or -SC-SGD, both the channel 1034 and the charge-trap layer 1036 are exposed to the electric field 1042 (represented by longer dashed arrows in Fig. 10) exposed to the bias applied to region 1030 b (unselected SGD) during a read operation, for example due to the partial removal of the dielectric layer 1038. The electric field 1042 helps to cause the NSI or NSI effect, which is referred to in Fig. 12 is described. In addition to interference experienced by the SC-SGD from the neighboring SGD, there is also the neighbor cross-coupling effect (NCC effect) 1046 (represented by shorter dashed arrows in Fig. 10), where an unselected secondary neighbor SGDT / dummy can cross-couple with the SGD layer (i.e., selected SGD). This neighbor cross-coupling also causes the in Fig. Figure 11 illustrates the SGD downshift problem. Since the threshold voltages Vt of SC-SGD are lower, NSI and NCC together can influence the drive-up / lock-out process during programming operations. NSI and NCC can also introduce leakage current, thus affecting sensing operations. Fig. Figure 13 shows a cross-sectional view of adjacent selected and unselected chains, including SGD transistors, a memory hole cut by the SHO 1310, and the resulting NSI, V primary attacker and NCC effects, V secondary attacker , are assigned.

[0093] Fig. Figure 14 shows another cross-sectional view of adjacent selected and unselected chains, including SGD transistors associated with a memory hole cut by the SHW 1310, along with a corresponding top view of a section of the memory device. To demonstrate the presence of the secondary coupling or NCC effect, the unselected SGD bias is set, but the DD0 bias is changed from 4.2 V to 8.6 V. Fig. Figure 15 shows a threshold voltage Vt distribution of semicircular SGD transistors and full-circle SGD transistors. Fig. Figure 16 shows the threshold voltage Vt for a sub-threshold of the threshold voltage Vt for the semicircular SGD transistors (diagram on the far right of Fig. 16) and full-circle SGD transistors (diagram on the far left of Fig. 16) As shown, when a higher dummy WL bias is applied to the half-circle SGD, the threshold voltage Vt of the SGD transistor begins to switch down. The sensitivity is much higher than with the full-circle SGD, as can be seen from the different in Fig. The curves shown in the 16 diagrams demonstrate the presence of neighboring cross-coupling (NCC). This diagonal coupling can lead to a significant SGD downshift.

[0094] Fig. Figure 17A shows another cross-sectional view of adjacent selected and unselected chains, including SGD transistors associated with a memory hole cut by the SHW 1310, along with a corresponding top view of a section of the memory device during a programming operation. As shown, each of the chains has a plurality of drain-side select-gate transistors (SGD and SGDT transistors) on a drain side of one of the chains. The plurality of drain-side select-gate transistors includes one of a plurality of upper drain-side select-gate SGDT transistors. Fig. Figure 17B shows a corresponding perspective view of the adjacent selected chains and unselected chains of Fig. 17A, including the multitude of drain-side select-gate transistors (SGD and SGDT transistors) that are coupled to a multitude of bit lines BL during program execution. From one perspective, one of the multitude of upper drain-side select-gate SGDT transistors is connected to one of the multitude of bit lines BL and coupled to the memory cells of one of the chains. Due to the NCC effect, V couples secondary attackeron the unselected chain with the selected chain SGD, resulting in more leakage current. Thus, while a selected member of the multitude of upper drain-side select-gate transistors and an unselected member of the multitude of upper drain-side select-gate SGDT transistors are physically separated, they are electrically short-circuited during the program operation (sharing the same bias for all chains). Similarly, while a selected member of a multitude of dummy word lines (DWL) and an unselected member of the multitude of dummy word lines (DWL) are physically separated, they are electrically short-circuited during the program operation (sharing the same bias for all chains).More precisely, if a neighbor (selected from one of the many upper drain-side select-gate SGDT transistors) and / or one of the many dummy word lines (DWL) are highly biased, an electric field can cross-couple with the SGD layer (layer N+1 with N-diagonal coupling and / or layer N-1 with N-diagonal coupling), resulting in leakage current in selected drain-side select-gate SGD transistors (equivalent to SGD downshift). This leads to significant NCC in OPS (on-pitch SGD) technology. This NCC effect, or interference effect, is weaker than the NSI effect (coupling within the same physical layer).

[0095] Fig. Figure 18A shows another cross-sectional view of adjacent selected and unselected chains including SGD transistors associated with a memory hole cut by the SHW 1310, together with a corresponding top view of a section of the memory device during a read operation. Fig. Figure 18B shows a perspective view of the adjacent selected chains and unselected chains of Fig. 18A, including the SGD transistors that are coupled to the BL bit line during the read operation. As in program operation, V couples secondary attackeron the unselected chain during the read operation with the selected chain SGDT, resulting in more leakage current. Therefore, if a selected member of the multitude of upper drain-side select-gate SGDT transistors and an unselected member of the multitude of drain-side select-gate SGDT transistors are physically separated, they will be electrically short-circuited during the program (sharing the same bias for all chains). Likewise, if a selected member of a multitude of dummy word lines (DWL) and an unselected member of the multitude of dummy word lines (DWL) are physically separated, they will be electrically short-circuited during the read operation (sharing the same bias for all chains).More precisely, if a neighbor (selected from one of the many upper drain-side select-gate SGDT transistors) and / or one of the many dummy word lines (DWL) are highly biased, an electric field can cross-couple with the SGD layer (layer N+1 with N-diagonal coupling and / or layer N-1 with N-diagonal coupling), resulting in leakage current in selected drain-side select-gate SGD transistors (equivalent to SGD downshift). This leads to significant NCC in OPS technology. This NCC effect, or interference effect, is weaker than the NSI effect (coupling within the same physical layer).

[0096] Consequently, this includes a storage device (e.g., storage device 100 of Fig. 1A) described the memory cells (e.g. data memory cell MC and dummy memory cells 682, 683 of Fig. 6D) includes one of a variety of word lines (e.g., data word line layers (word lines) WLL0-WLL10 of Fig. 6B or WLL10 from Fig. 6D). The memory cells are connected in one or more chains (e.g., NAND chains NS1 and NS2 of Fig. 6B) arranged and configured to maintain a threshold voltage Vt or Vth corresponding to one of a plurality of memory states. Again, each of the chains has a plurality of drain-side select-gate transistors (SGD and SGDT transistors) on a drain side of one of the chains, including one of a plurality of upper drain-side select-gate SGDT transistors. The plurality of upper drain-side select-gate SGDT transistors is connected to one of a plurality of bit lines and coupled to the memory cells of one of the chains. The setup also includes a control circuit or means (e.g., one or any combination of control circuit 110, decoder 114 / 132, power control module 116, capture blocks SBb, SB2, ..., sBp, read / write circuits 128, control 122 of Fig. 1A, control circuit 150 of Fig. 1B and / or detection circuit control 560 from Fig. 5 and so on), which are coupled to the multitude of word lines, the multitude of bit lines, and the multitude of drain-side select-gate transistors. The control means are configured to apply an unselected high voltage to an unselected portion of the multitude of upper drain-side select-gate SGDT transistors during a storage operation. The control means are also configured to simultaneously apply a selected high voltage to selected portions of the multitude of upper drain-side select-gate SGDT transistors during the storage operation. The unselected high voltage is electrically isolated from (i.e., intentionally electrically different from) the selected high voltage. From one point of view, the unselected high voltage is lower than the selected high voltage. In particular, the unselected high voltage may be approximately zero volts or a negative voltage.

[0097] As discussed above and on Fig. 6D, Fig. 17A and Fig. Referring back to 18A, for example, the multitude of word lines and a multitude of dielectric layers extend horizontally and overlap alternately in a stack, and the chains extend vertically through the stack. The multitude of drain-side select-gate transistors (SGD and SGDT transistors) includes one of a multitude of other drain-side select-gate SGD transistors connected in series between the one of the multitude of upper drain-side select-gate SGDT transistors and the memory cells for each of the chains. The control means are further arranged to apply a selected other voltage to selected of the multitude of other drain-side select-gate SGD transistors during the storage operation. From one point of view, the unselected upper voltage is lower than the selected other voltage.In other words, the unselected SGDT bias is lower than the selected SGD bias during the storage process. Subsequently, control mechanisms are set up to minimize the neighbor feedback (NCC) effect between the unselected and selected upper drain-side select-gate SGDT transistors.

[0098] From one perspective, the storage process is a program process. Therefore, during the program process, the control means are still configured to apply at least one program pulse of a program voltage to selected word lines, while a forward voltage is applied to unselected word lines. Fig. Figure 19A shows another cross-sectional view of adjacent selected chains and non-selected chains including SGD transistors associated with a memory hole cut by the SHE 1310, together with a corresponding top view of a section of the memory device during a program operation in which the non-selected high voltage is electrically separated (i.e., intentionally electrically different) from the selected high voltage. Fig. Figure 19B shows a perspective view of the adjacent selected chains and unselected chains of Fig. 19A, including the SGD transistors that are coupled to the BL bit line with different unselected and selected upper voltages during the program operation. While due to the NCC effect V secondary attackerOn unselected chains, coupling with a selected chain SGD results in more leakage current. Electrically isolated or intentionally different (i.e., intentionally electrically different) unselected SGDT bias (i.e., unselected upper voltage) and selected SGDT bias (selected upper voltage) during the programming process reduce the NCC effect in the diagonal direction.

[0099] Alternatively or additionally, the storage process consists of a read operation and a verification operation. Thus, the control means during the read operation and the verification operation are still configured to apply a read voltage and a verification voltage to selected of the multitude of word lines, while a pass voltage is applied to unselected of the multitude of word lines. Fig. Figure 20A shows another cross-sectional view of adjacent selected chains and non-selected chains, including SGD transistors associated with a memory hole cut by the SHO 1310, together with a corresponding top view of a section of the memory device during one of the read and verification operations, in which the non-selected high voltage is electrically separated (i.e., intentionally electrically different) from the selected high voltage. Fig. Figure 20B shows a perspective view of the adjacent selected and unselected chains of Fig. 20A, which include the SGD transistors that are coupled to the BL bit line with a different unselected high voltage and a selected high voltage during one of the read and verification operations. Again, while V secondary attackerOn selected chains, the NCC effect is coupled to the selected chain SGD. Electrically isolated or intentionally different non-selected SGDT bias (i.e., non-selected peak voltage) and selected SGDT bias (selected peak voltage) during one of the read and verification processes reduce the NCC effect.

[0100] From another perspective, the control means are still configured to adaptively adjust the selected upper voltage based on a transistor threshold voltage of the plurality of upper drain-side select-gate SGDT transistors. More precisely, the control means are still configured to detect a threshold voltage V DETECT as predetermined detection threshold voltage V DETECT to initialize in response to receiving a memory operation instruction. The control means are also set up to initialize an upper drain-side select gate set N.DETECT from one of the many drain-side select-gate SGDT transistors with the transistor threshold voltage above the detection threshold voltage V DETECT to count. By counting the upper drain-side select gate quantity N DETECT from one of the many upper drain-side select-gate (SGDT) transistors with the transistor threshold voltage above the detection threshold voltage V DETECT The control devices detect an SGDT upper threshold voltage Vt. Fig. Figure 21 shows threshold voltage Vt distributions of the SGDT transistors with relatively lower and higher threshold voltages Vt, together with corresponding upper threshold voltages Vt. The control means determine whether the upper drain-side select-gate quantity N DETECT The level is smaller than the detection threshold of the upper drain-side select gate quantity. The control means additionally increment the detection threshold voltage V. DETECTthrough a delta detection threshold voltage Δ and return to counting the upper drain-side select-gate quantity N DETECT the multitude of upper drain-side select-gate SGDT transistors with the transistor threshold voltage above the detection threshold voltage V DETECT in response to the upper drain-side select gate quantity N DETECT , which is not less than an upper drain-side select-gate quantity sensing threshold. The control means are also configured to set the selected upper voltage as an adaptive non-selected upper voltage VSGDT, which corresponds to the sensing threshold voltage V DETECT plus a predetermined fixed overdrive voltage (e.g. 2 au) in response to the upper drain-side select gate quantity N DETECT, which is smaller than an upper drain-side select-gate quantity sensing threshold. Exemplary adaptive non-selected upper voltages for the SGDT transistors with relatively lower and higher threshold voltages Vt are also given in Fig. Figure 21 shows that the control means then continue the storage process using the adaptive selected high voltage VSGDT. Thus, the selected SGDT bias is reduced using an adaptive method where the selected SGDT bias (i.e., selected high voltage) is adaptive to the threshold voltage Vt of the SGDT transistors. This can minimize the diagonal matching of the neighboring cross-coupling (NCC) between the unselected SGDT and selected SGD and better isolate unselected strings. Such a strategy can also greatly reduce the voltage difference between the SGDT and SGD layers, resulting in less concern about disturbances during SGDT storage.

[0101] The chains can be grouped into a set of chains, which includes a set of chains. The storage device further includes a plurality of drivers, each coupled to one or more of the chains in the set of chains. Fig. 22 and Fig. Figure 23 shows exemplary groups of chains and corresponding NCC and NSI effects when each of the chains is selected. As in Fig. 23 compared to Fig. As shown in Figure 22, the NCC and NSI effects can be reduced due to unselected chains that are electrically distinct or separated (i.e., SGDT separation). Fig. 23) Furthermore, the set of chains can be larger than the set of drivers of the multitude of drivers. From one perspective, the control means are therefore additionally configured to select at least one of the unselected and selected high voltages, based on which of the multitude of drivers is coupled to each of the one or more of the chains of the group of chains.

[0102] Fig. 24 and Fig. Figure 25 illustrates steps of a procedure for operating a storage device. As discussed above, the storage device (e.g., storage device 100 of Fig. 1A) Memory cells (e.g. data memory cell MC and dummy memory cells 682, 683 of Fig. 6D) which is connected to one of a multitude of word lines (e.g. data word line layers (word lines) WLL0-WLL10 of Fig. 6B or WLL10 from Fig. 6D). The memory cells are connected in one or more chains (e.g., NAND chains NS1 and NS2 of Fig. 6B) arranged and configured to maintain a threshold voltage Vt or Vth corresponding to one of a plurality of memory states. Each of the chains has a plurality of drain-side select-gate transistors (SGD and SGDT transistors) on a drain side of one of the chains, including one of a plurality of upper drain-side select-gate SGDT transistors. The plurality of upper drain-side select-gate SGDT transistors is connected to one of a plurality of bit lines and coupled to the memory cells of one of the chains. With reference to Fig. The method includes step 1400 of applying an unselected high voltage to unselected members of the plurality of upper drain-side select-gate SGDT transistors during a storage operation. The method also includes step 1402 of simultaneously applying a selected high voltage to selected members of the plurality of upper drain-side select-gate SGDT transistors during the storage operation, wherein the unselected high voltage is intentionally different from the selected high voltage. Again, from one perspective, the unselected high voltage is lower than the selected high voltage. For example, the unselected high voltage may be approximately zero volts or a negative voltage.

[0103] As discussed, the plurality of word lines and the plurality of dielectric layers extend horizontally and overlap alternately in the stack, and the chains extend vertically through the stack. The plurality of drain-side select-gate transistors includes one of a plurality of other drain-side select-gate SGD transistors connected in series between the one of the plurality of upper drain-side select-gate SGD transistors and the memory cells for each of the chains. The method further includes the step of applying a selected other voltage to selected of the plurality of other drain-side select-gate SGD transistors during the storage operation, the unselected upper voltage being lower than the selected other voltage.The neighbor cross-coupling effect between the unselected and selected upper drain-side-select-gate SGDT transistors is minimized.

[0104] Now, with reference to Fig. 25 The procedure further includes step 1404 of adaptively adjusting the selected upper voltage based on a transistor threshold voltage of the plurality of upper drain-side select-gate SGDT transistors. More specifically, the procedure further includes step 1406 of receiving a memory operation instruction (e.g., a program instruction or one from a read or verification instruction). Next, step 1408 initializes a capture threshold voltage V. DETECTas a predetermined detection threshold voltage (e.g., 2 au) in response to receiving a memory operation command. The procedure continues with step 1410, which defines an upper drain-side select gate quantity N. DETECT from one of the many upper drain-side select-gate (SGDT) transistors with the transistor threshold voltage above the detection threshold voltage V DETECT counts. The procedure also includes step 1412 of determining whether the upper drain-side select gate quantity N DETECT smaller than a detection threshold of the upper drain-side select-gate quantity. The procedure additionally includes step 1414 of incrementing the detection threshold voltage V. DETECT through a delta detection threshold voltage Δ and returns to counting the upper drain-side select-gate quantity N DETECTone of the many upper drain-side select-gate SGDT transistors with the transistor threshold voltage above the detection threshold voltage V DETECT in response to the upper drain-side select gate quantity N DETECT , which is not less than an upper drain-side select-gate quantity sensing threshold. The procedure also includes step 1416, which sets the selected upper voltage as an adaptive non-selected upper voltage VSGDT, which corresponds to the sensing threshold voltage V. DETECT plus a predetermined fixed overdrive voltage in response to the upper drain-side select-gate quantity N DETECT, which is less than an upper drain-side select-gate quantity threshold. Next, 1418 continues the storage operation using the adaptive selected upper voltage VSGDT. The SGDT upper threshold voltage Vt is detected prior to the conventional storage operation, and the selected SGDT bias is adaptively set (e.g., SGDT upper threshold 2 au). This ensures sufficient selected SGDT overdrive and a minimal NCC effect between selected SGDT and unselected SGD. The procedure can be easily extended to adjust the bias also applied to dummy word lines.

[0105] As discussed, and according to one viewpoint, the storage operation is a program operation. Therefore, the procedure further includes the step of applying at least one program pulse of a program voltage to selected of the multitude of word lines, while a pass voltage is applied to unselected of the multitude of word lines during the program operation. Alternatively and / or additionally, the storage operation is a read operation and a verification operation, and the procedure further includes the steps of applying a read voltage and a verification voltage to selected of the multitude of word lines, while a pass voltage is applied to unselected of the multitude of word lines during one of the read operation and the verification operation.

[0106] Again, the chains can be grouped into a set of chains, which includes a set of chains. The storage device can further include a plurality of drivers, each coupled to one or more of the chains in the set of chains, and the set of chains can be larger than a driver size of the plurality of drivers. The method thus still includes the step of selecting at least one of the unselected and selected upper voltages, based on which of the plurality of drivers is coupled to each of the one or more chains in the set of chains.

[0107] The advantages of the storage device and method disclosed herein include a reduction of the NCC effect during data word line operations (e.g., programming or read / verification operations). Since the storage device and method disclosed herein do not use selected high voltages that are electrically isolated (i.e., intentionally electrically different) compared to the selected high voltages, the semicircular SGD technology becomes more practical.

[0108] Of course, modifications may be made to what is described and illustrated herein, without, however, deviating from the scope of protection defined in the appended claims. The foregoing description of the embodiments serves the purposes of illustration and description. It is not intended to be exhaustive or to limit the disclosure. Individual elements or features of a particular embodiment are generally not limited to that particular embodiment, but are interchangeable as appropriate and may be used in a selected embodiment, even if this is not specifically shown or described. They may also be varied in many ways. Such variations are not to be considered a deviation from the disclosure, and all such modifications are intended to be included within the scope of protection of the disclosure.

Claims

[1] Storage device (100), comprising: Memory cells (MC, 682, 683) connected to one of a plurality of word lines (WLLO-WLL10) and arranged in chains (NS1, NS2) and configured to maintain a threshold voltage; wherein each of the chains (NS1, NS2) has a plurality of drain-side select-gate transistors (SGD, SGDT) on a drain-side of one of the chain strings and includes one of a plurality of upper drain-side select-gate transistors (SGDT) connected to one of a plurality of bit lines (BL0, BL1, ...) and coupled to the memory cells (MC, 682, 683) of one of the chains (NS1, NS2); and Control means (110, 122) which are coupled to the multitude of word lines (WLL0-WLL10) and the multitude of bit lines (BL0, BL1, ...) and the multitude of drain-side select-gate transistors (SGDT) and are configured for: Applying an unselected overvoltage to an unselected plurality of upper drain-side select-gate (SGDT) transistors during a storage operation, and Simultaneous application of a selected overvoltage to selected of the plurality of upper drain-side select-gate transistors (SGDTs) during the storage operation, wherein the unselected overvoltage is intentionally different from the selected overvoltage, wherein the control means (110, 122) are further set up to adaptively adjust the selected overvoltage based on a transistor threshold voltage of the plurality of upper drain-side select-gate transistors (SGDTs). [2] Storage device (100) according to claim 1, wherein the unselected overvoltage is lower than the selected overvoltage. [3] Storage device (100) according to claim 1, wherein the plurality of word lines (WLL0-WLL10) and a plurality of dielectric layers (DL0-DL19) extend horizontally and overlap alternately in a stack (610), and the chains (NS1, NS2) extend vertically through the stack (610), wherein the plurality of drain-side select-gate transistors (SGD, SGDT) include one of a plurality of other drain-side select-gate transistors (SGD) connected in series between one of the plurality of upper drain-side select-gate transistors (SGDT) and the memory cells (MC, 682, 683) for each of the chains (NS1, NS2), and the control means (110, 122) are further arranged to apply a selected other voltage to selected of the plurality of other drain-side select-gate transistors (SGDT) during the storage process, where the unselected upper voltage is lower than the selected other voltage. [4] Storage device (100) according to claim 1, wherein the control means (110, 122) are further configured to: Initializing a detection threshold voltage as a predetermined detection threshold voltage in response to receiving a memory operation command; Counting an upper drain-side select-gate quantity from one of the plurality of upper drain-side select-gate transistors (SGDTs) with the transistor threshold voltage above the detection threshold voltage; Determine if the upper drain-side select gate quantity is less than a detection threshold of the upper drain-side select gate quantity; Incrementing the detection threshold voltage by a delta detection threshold voltage and returning to counting the upper drain-side select-gate quantity of the plurality of upper drain-side select-gate transistors (SGDTs) with the transistor threshold voltage above the detection threshold voltage in response to the upper drain-side select-gate quantity not being less than an upper detection threshold of the drain-side select-gate quantity; Setting the selected overvoltage as an adaptive selected overvoltage equal to the detection threshold voltage plus a predetermined fixed overdrive voltage in response to the upper drain-side select gate quantity being less than an upper detection threshold of the drain-side select gate quantity; and Continue the storage process using the adaptive selected overvoltage. [5] Storage device (100) according to claim 1, wherein the storage process is a program process and the control means (110, 122) are further configured to apply at least one program pulse of a program voltage to selected of the plurality of word lines (WLL0-WLL10), while a forward voltage is applied to unselected of the plurality of word lines (WLL0-WLL10) during the program process. [6] Storage device (100) according to claim 1, wherein the storage process is one of a read operation and a verification operation, and the control means (110, 122) are further configured to apply a read voltage and a verification voltage to selected of the plurality of word lines (WLL0-WLL10), while a forward voltage is applied to unselected of the plurality of word lines (WLL0-WLL10) during one of the read operation and the verification operation. [7] Storage device (100) according to claim 1, wherein the chains (NS1, NS2) are grouped into a group of chains that includes a set of chains, wherein the storage device (100) further includes a plurality of drivers (605) that are each coupled to one or more of the chains of the group of chains, wherein the set of chains is greater than a driver size of the plurality of drivers (605), and the control means (110, 122) are further configured to select at least one of the unselected voltage and the selected voltage based on which of the plurality of drivers (605) is coupled to each of the one or more of the chains of the group of chains. [8] Controller (110, 122) in communication with a memory device (100) which includes memory cells (MC, 682, 683) connected by one of a plurality of word lines (WLL0-WLL10) and arranged in chains (NS1, NS2) and configured to store a threshold voltage, each of the chains (NS1, NS2) having a plurality of drain-side select-gate transistors (SGD, SGDT) on a drain side of one of the chains (NS1, NS2) and having one of a plurality of upper drain-side select-gate transistors (SGDT) connected by one of a plurality of bit lines (BL0, BL1, ...) and coupled to the memory cells (MC, 682, 683) of one of the chains (NS1, NS2), the controller (110, 122) being configured to: Instructing the storage device (100) to apply an unselected upper voltage to unselected of the plurality of upper drain-side select-gate transistors (SGDTs) during a storage operation; and Simultaneously instructing the storage device (100) to apply a selected overvoltage to selected of the plurality of upper drain-side select-gate transistors (SGDTs) during the storage operation, wherein the unselected overvoltage is intentionally different from the selected overvoltage, wherein the control (110, 122) is further configured to adaptively adjust the selected overvoltage based on a transistor threshold voltage of the plurality of upper drain-side select-gate transistors (SGDTs). [9] Controller (110, 122) according to claim 8, wherein the plurality of word lines (WLL0-WLL10) and a plurality of dielectric layers (DL0-DL19) extend horizontally and overlap alternately in a stack (610), and the chains (NS1, NS2) extend vertically through the stack (610), wherein the plurality of drain-side select-gate transistors (SGD, SGDT) include one of a plurality of other drain-side select-gate transistors (SGD) connected in series between one of the plurality of upper drain-side select-gate transistors (SGDT) and the memory cells (MC, 682, 683) for each of the chains (NS1, NS2), and the controller (110, 122) is further configured to instruct the storage device (100) to apply a selected other voltage to selected of the plurality of other to create drain-side select-gate transistors (SGDs) during the storage process,where the unselected upper voltage is lower than the selected other voltage. [10] Control unit (110, 122) according to claim 8, wherein the control unit (110, 122) is further configured to: Initializing a detection threshold voltage as a predetermined detection threshold voltage in response to receiving a memory operation command; Instructing the storage device (100) to count an upper drain-side select-gate quantity from one of the plurality of upper drain-side select-gate transistors (SGDTs) with the transistor threshold voltage above the detection threshold voltage; Determine if the upper drain-side select gate quantity is less than a detection threshold of the upper drain-side select gate quantity; Instructing the storage device (100) to increment the detection threshold voltage by a delta detection threshold voltage and to return to counting the upper drain-side select-gate quantity of the plurality of upper drain-side select-gate transistors (SGDTs) with the transistor threshold voltage above the detection threshold voltage in response to the fact that the upper drain-side select-gate quantity is not less than an upper drain-side select-gate quantity detection threshold; Instructing the storage device (100) to apply the selected overvoltage as an adaptive selected overvoltage equal to the detection threshold voltage plus a predetermined fixed overdrive voltage in response to the upper drain-side select gate quantity being less than a detection threshold of the upper drain-side select gate quantity; and Instructing the storage device (100) to continue the storage operation using the adaptive unselected overvoltage. [11] Method for operating a storage device (100) comprising memory cells (MC, 682, 683) connected by one of a plurality of word lines (WLL0-WLL10) and arranged in chains (NS1, NS2) and configured to store a threshold voltage, wherein each of the chains (NS1, NS2) has a plurality of drain-side select-gate transistors (SGD, SGDT) on a drain side of one of the chains (NS1, NS2) and includes one of a plurality of upper drain-side select-gate transistors (SGDT) connected by one of a plurality of bit lines (BL0, BL1, ...) and coupled to the memory cells (MC, 682, 683) of one of the chains (NS1, NS2), the method comprising the following steps: Applying an unselected overvoltage to an unselected plurality of upper drain-side select-gate (SGDT) transistors during a storage operation; and Simultaneous application of a selected overvoltage to selected of the plurality of upper drain-side select-gate transistors (SGDTs) during the storage process, wherein the unselected overvoltage is intentionally different from the selected overvoltage, the method further including the step of adaptively adjusting the selected overvoltage based on a transistor threshold voltage of the plurality of upper drain-side select-gate transistors (SGDTs). [12] Method according to claim 11, wherein the unselected upper voltage is lower than the selected upper voltage. [13] The method of claim 11, wherein the plurality of word lines (WLL0-WLL10) and a plurality of dielectric layers (DL0-DL19) extend horizontally and alternately overlap in a stack (610), and the chains (NS1, NS2) extend vertically through the stack (610), wherein the plurality of drain-side select-gate transistors (SGD, SGDT) includes one of a plurality of other drain-side select-gate transistors (SGD) connected in series between one of the plurality of upper drain-side select-gate transistors (SGDT) and the memory cells (MC, 682, 683) for each of the chains (NS1, NS2), wherein the method further includes the step of applying a selected other voltage to selected of the plurality of other drain-side select-gate transistors (SGD) during the storage operation, wherein The unselected upper voltage is lower than the selected other voltage. [14] The method of claim 11, further comprising the following steps: Initializing a detection threshold voltage as a predetermined detection threshold voltage in response to receiving a memory operation command; Counting an upper drain-side select-gate quantity from one of the plurality of upper drain-side select-gate transistors (SGDTs) with the transistor threshold voltage above the detection threshold voltage; Determine if the upper drain-side select gate quantity is less than a detection threshold of the upper drain-side select gate quantity; Incrementing the detection threshold voltage by a delta detection threshold voltage and returning to counting the upper drain-side select-gate quantity of the plurality of upper drain-side select-gate transistors (SGDTs) with the transistor threshold voltage above the detection threshold voltage in response to the upper drain-side select-gate quantity not being less than an upper detection threshold of the drain-side select-gate quantity; Setting the selected overvoltage as an adaptive selected overvoltage equal to the detection threshold voltage plus a predetermined fixed overdrive voltage in response to the upper drain-side select gate quantity being less than an upper detection threshold of the drain-side select gate quantity; and Continue the storage process using the adaptive selected overvoltage. [15] Method according to claim 11, wherein the storage process is a program process and the method further includes the step of applying at least one program pulse of a program voltage to selected of the plurality of word lines (WLL0-WLL10), while a forward voltage is applied to unselected of the plurality of word lines (WLL0-WLL10) during the program process. [16] Method according to claim 11, wherein the storage process is one of a read process and a verification process, and the method further includes the steps of applying a read voltage and a verification voltage to selected of the plurality of word lines (WLL0-WLL10), while a forward voltage is applied to unselected of the plurality of word lines (WLL0-WLL10) during the read process and the verification process. [17] Method according to claim 11, wherein the chains (NS1, NS2) are grouped into a group of chains comprising a set of chains, wherein the storage device (100) further comprises a plurality of drivers (605) each coupled to one or more of the chains of the group of chains, wherein the set of chains is greater than a driver size of the plurality of drivers (605), and the method further comprises the step of selecting at least one of the unselected upper voltages and the selected upper voltage based on which of the plurality of drivers (605) is coupled to each of the one or more of the chains of the group of chains.

Images