LATERAL BIPOLAR TRANSISTOR WITH GATE-CONTROLLED COLLECTOR

Abstract

Structure comprehensive: an extrinsic base region (17) vertically above a semiconductor substrate (12) and comprising asymmetric sidewall spacers on opposite sidewalls of the extrinsic base region (17); a collector region (32) on the semiconductor substrate (12) and separated from the extrinsic base region (17) by at least a first spacer (20) of the asymmetric sidewall spacers; an emitter region (30) on the semiconductor substrate (12) and separated from the extrinsic base region (17) by a second spacer (28) of the asymmetric sidewall spacers; a gate structure (19) adjacent to the collector region (32); and a sidewall spacer (28) on the gate structure (19), wherein the sidewall spacer (28) separates the gate structure (19) from the collector region (32) and the first spacer (20) separates the gate structure (19) from the extrinsic base region (17).

Description

FIELD OF THE INVENTION

[0001] The present disclosure relates to semiconductor structures and, more particularly, to a gate-controlled collector lateral bipolar transistor and fabrication methods. BACKGROUND

[0002] Bipolar transistors can be vertical or lateral transistors. In a vertical bipolar transistor, carriers flow in a vertical direction. Since a collector region is formed at a position deep from a wafer surface, the collector resistance increases, thus limiting the transistor performance, especially for high-speed operation. Additionally, the transistor requires a high-concentration buried layer, an epitaxial collector layer, and deep trench isolation. Consequently, the number of process steps increases, and so does the cost. On the other hand, the lateral bipolar transistor is simpler in construction than the vertical bipolar transistor. Also, in a lateral bipolar transistor, a collector electrode can be brought into direct contact with a collector region, which is advantageous for high-speed operation.

[0003] US 2004 / 0 188 802 A1 discloses a lateral heterojunction bipolar transistor formed on an SOI substrate; the transistor has an emitter electrode, a collector electrode, and a base electrode arranged laterally therebetween; the base electrode is separated from the emitter electrode and the collector electrode by respective insulator portions.

[0004] US 2014 / 0 312 356 A1 further discloses a vertical bipolar transistor comprising an emitter, a base arranged above the emitter, and a collector arranged above the base; a gate structure may be formed on a portion of the collector to shape the electric field in the collector region. BRIEF SUMMARY

[0005] In one aspect of the disclosure, a structure comprises: an extrinsic base region vertically above a semiconductor substrate and comprising asymmetric sidewall spacers on opposite sidewalls of the extrinsic base region; a collector region on the semiconductor substrate and separated from the extrinsic base region by at least a first one of the asymmetric sidewall spacers; an emitter region on the semiconductor substrate and separated from the extrinsic base region by a second one of the asymmetric sidewall spacers; a gate structure adjacent to the collector region; and a sidewall spacer on the gate structure, wherein the sidewall spacer separates the gate structure from the collector region and the first spacer separates the gate structure from the extrinsic base.

[0006] In one aspect of the disclosure, a structure comprises: an extrinsic base region vertically above a semiconductor substrate and comprising asymmetric sidewall spacers on opposite sidewalls of the extrinsic base region; a collector region on the semiconductor substrate and separated from the extrinsic base region by at least a first one of the asymmetric sidewall spacers; an emitter region on the semiconductor substrate and separated from the extrinsic base region by a second one of the asymmetric sidewall spacers; and a polysilicon spacer adjacent to the first sidewall spacer and electrically in contact with the collector region.

[0007] In one aspect of the disclosure, a structure comprises: an extrinsic base region vertically above an intrinsic base region comprising semiconductor-on-insulator substrate material; a raised collector region on the semiconductor-on-insulator substrate material; a raised emitter region on the semiconductor-on-insulator substrate material; a first structure electrically isolating the extrinsic base region from the raised emitter region; and a second structure electrically isolating the extrinsic base region from the raised collector region, wherein the second structure is of a different composition than the first structure.

[0008] In one aspect of the disclosure, a method comprises: forming an extrinsic base region vertically above a semiconductor substrate and comprising asymmetric sidewall spacers on opposite sidewalls of the extrinsic base region; forming a collector region on the semiconductor substrate and separated from the extrinsic base region by at least a first spacer of the asymmetric sidewall spacers; forming an emitter region on the semiconductor substrate and separated from the extrinsic base region by a second spacer of the asymmetric sidewall spacers; forming a gate structure adjacent to the collector region; and forming a sidewall spacer on the gate structure, wherein the sidewall spacer separates the gate structure from the collector region and the first spacer separates the gate structure from the extrinsic base region. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The present disclosure is described in the following detailed description with reference to the aforementioned plurality of drawings by way of non-limiting examples of exemplary embodiments of the present disclosure. Fig. 1 shows a substrate having shallow trench isolation structures, among other features, and respective manufacturing processes according to aspects of the present disclosure. Fig. 2 shows a gate dielectric material and gate material formed on the substrate, among other features, and respective manufacturing processes according to aspects of the present disclosure. Fig. 3 illustrates extrinsic base polysilicon material formed on a sidewall spacer of the patterned gate dielectric material and the gate material, among other features, and respective manufacturing processes in accordance with aspects of the present disclosure. Fig. 4 shows a cap material on the extrinsic base polysilicon material, among other features, and respective manufacturing processes according to aspects of the present disclosure. Fig. 5 shows sidewalls at the extrinsic base region and gate structure, among other features, and respective manufacturing processes according to aspects of the present disclosure. Fig. 6 illustrates a rapid thermal anneal process, among other features, and respective manufacturing processes in accordance with aspects of the present disclosure. Fig. 7 shows a silicide and contacts to the extrinsic base region, collector region, emitter region, and gate structure, among other features, and respective manufacturing processes according to aspects of the present disclosure. Fig. 8-11 illustrate an alternative structure and respective manufacturing processes in accordance with aspects of the present disclosure. DETAILED DESCRIPTION

[0010] The present disclosure relates to semiconductor structures, and more particularly, to a lateral bipolar transistor with a gate-controlled collector and a method of fabrication. In particular, the lateral bipolar transistor includes a gate-controlled collector with an asymmetric profile. Additionally, the collector region includes a depleted collector region for high-voltage RF device applications (e.g., low-noise amplifiers and power amplifiers).

[0011] In more specific embodiments, the lateral bipolar transistor may be a lateral SiGe heterojunction bipolar transistor. The lateral SiGe heterojunction bipolar transistor comprises, for example, an intrinsic SiGe base within a semiconductor-on-insulator (SOI) layer. A raised emitter region and raised collector region comprising an N+ semiconductor material, e.g., Si, are above the above SOI layer, with an extrinsic P+ base region vertically contacting the intrinsic SiGe base. A gate structure, e.g., a transistor, separates the extrinsic base from a collector contact. To enhance performance, the gate structure may include an optional contact, e.g., an extra terminal. Also, the collector region (collector contact) formed beneath the gate structure may be a lightly doped semiconductor material.A spacer isolates the gate structure from the extrinsic base, which can have different shapes or a different material compared to external spacers.

[0012] In alternative embodiments, a spacer comprising polysilicon may isolate the collector region from the extrinsic base region. A contact may be provided on the sidewall polysilicon, and two spacers of different materials may be provided around the extrinsic base region and the polysilicon spacer. In any layout scheme described herein, the collector region is highly configurable by using the gate structure or the polysilicon spacer, as examples.

[0013] The lateral gate-controlled collector bipolar transistor of the present disclosure can be fabricated in several ways using several different tools. However, the methodologies and tools used to form structures with dimensions on the micrometer and nanometer scale are generally used. The methodologies, i.e., technologies, used to fabricate the lateral gate-controlled collector bipolar transistor of the present disclosure were adopted from integrated circuit (IC) technology. For example, the structures are fabricated on wafers and realized in material films patterned on top of a wafer using photolithographic processes.In particular, the fabrication of the gate-controlled collector lateral bipolar transistor uses three basic building blocks: (i) deposition of thin films of material on a substrate, (ii) application of a patterned mask on top of the films by photolithographic imaging, and (iii) etching the films selectively with respect to the mask.

[0014] Fig. 1 shows a substrate with shallow trench isolation structures and respective manufacturing processes according to aspects of the present disclosure. In particular, the structure 10 of Fig. 1, a substrate 12 and shallow trench isolation regions 14 formed within the substrate 12. In embodiments, the substrate 12 comprises a semiconductor-on-insulator (SOI) substrate. In particular, the substrate 12 includes a semiconductor handle wafer 12a, an insulator layer 12b, and a semiconductor layer 12c on the insulator layer 12b. The semiconductor handle wafer 12a provides mechanical support for the insulator layer 12b and the semiconductor layer 12c.

[0015] In the SOI implementation, the semiconductor handle wafer 12a and the semiconductor layer 12c may be composed of any suitable semiconductor material, including, but not limited to, Si, SiGe, SiGeC, SiC, GaAs, InAs, InP, and other III / V or II / VI compound semiconductors. Furthermore, the semiconductor handle wafer 12a and the semiconductor layer 12c may comprise any suitable single crystallographic orientation (e.g., a (100), (110), (111), or (001) crystallographic orientation). In further embodiments, the semiconductor layer 12c may be lightly doped Si material or SiGe, which partially forms the collector contact and the intrinsic base region. In embodiments, the dopant may be an N+ type dopant, such as, for example, arsenic or phosphorus. The semiconductor layer 12c may be deposited by a deposition process, such as, for example,chemical vapor deposition (CVD) or plasma-enhanced CVD (PECVD). Alternatively, the semiconductor layer 12c can be formed using a smart-cut process, where two semiconductor wafers are bonded together with an insulator material between the two semiconductor wafers.

[0016] The insulator layer 12b may comprise a dielectric material such as silicon dioxide, silicon nitride, silicon oxynitride, boron nitride, or a combination thereof. In a preferred embodiment, the insulator layer 12b may be a buried oxide layer (BOX). The insulator layer 12b may be formed by a deposition process such as CVD, PECVD, or physical vapor deposition (PVD). In another embodiment, the insulator layer 12b may be formed using a thermal growth process, such as thermal oxidation, to convert a surface portion of the semiconductor handle wafer 12a into an oxide material, e.g., the insulator layer 12b. In yet another embodiment, the insulator layer 12b may be formed by implanting oxygen atoms into a bulk semiconductor substrate and then annealing the structure.

[0017] Still referring to Fig. 1, shallow trench isolation structures 14 are formed within the semiconductor layer 12c and extend to the insulator layer 12b. In embodiments, the shallow trench isolation structures 14 may be formed by conventional lithography, etching, and deposition techniques known to those skilled in the art. For example, a resist formed over the semiconductor layer 12c is exposed to energy (light) to form a structure (opening). An etching process with a selective chemistry, e.g., reactive ion etching (RIE), is used to form one or more trenches in the semiconductor layer 12c through the openings of the resist. Following resist removal by a conventional oxygen ashing process or other known stripping means, insulator material (e.g., SiO2) may be deposited within the trenches by any conventional deposition process, e.g., chemical vapor deposition (CVD) processes.Any remaining insulating material on the surface of the semiconductor layer 12c can be removed by conventional chemical mechanical polishing (CMP) processes.

[0018] As further stated in Fig. 2, a gate dielectric material 16 may be formed on the semiconductor layer 12c and over the shallow trench isolation structures 14. In embodiments, the gate dielectric material 16 may be a gate oxide. Alternatively, the gate dielectric material 16 may be any suitable low-k gate dielectric material. A gate material 18 may be formed over the gate dielectric material 16. The gate material 18 may include work function metal(s) and polysilicon material over the work function metal(s). The gate dielectric material 16 and the gate material 18 may be deposited by conventional deposition techniques, such as CVD. In embodiments, the gate dielectric material 16 may be deposited to different thicknesses depending on the desired device performance.The gate dielectric material 16 and the gate material 18 may be patterned using conventional lithography and etch (RIE) processes, as previously described herein.

[0019] In Fig. 3, a sidewall spacer 20 may be formed on a sidewall of the patterned gate dielectric material 16 and the gate material 18. In embodiments, the sidewall spacer 20 may be a nitride spacer with a thin oxide layer 22 deposited by a conventional deposition process, e.g., CVD. The spacer material 20, 22 may be subjected to an anisotropic etch process, as known in the art, so no further explanation is required for a complete understanding of the present disclosure.

[0020] Additionally, a polysilicon material 24 may be deposited as a blanket over the sidewall spacer 20 and the oxide 22, adjacent to the gate material 18. The polysilicon material 24 may be a P+ doped material, which may be used to form an extrinsic base region of the lateral heterojunction bipolar transistor. The polysilicon material 24 may be separated from the patterned gate dielectric material 16 and the gate material 18 by the sidewall spacer 20 and the oxide material 22. The polysilicon material 24 may also be in direct contact with the semiconductor layer 12c, e.g., an intrinsic base region.

[0021] In Fig. 4, the polysilicon material 24 may be planarized to a level with the gate material 18. In embodiments, the planarization process may be a CMP process, as known in the art. In this way, a top surface of the gate material 18 is exposed. Following the planarization process, a cap material 26 may be deposited on the gate material 18 and the polysilicon material 24. The cap material 26 may be a nitride material deposited as a blanket by a conventional CVD process.

[0022] As further stated in Fig. As shown in Figure 5, the polysilicon material 24 and the cap material 26 may be patterned by conventional lithography and etching processes, as previously described herein. In this way, the polysilicon material 24 may be patterned into an extrinsic base region 17 of the lateral heterojunction bipolar transistor; whereas the gate material 18 and the gate dielectric material 16 may be formed into a gate structure 19 over a collector contact region 15, e.g., the lightly doped semiconductor layer 12c, electrically connecting the gate structure to a raised collector region 32.

[0023] A sidewall spacer 28 may be formed on the outer sidewalls of the polysilicon material 24 and the gate structure 19 (e.g., the patterned gate material 18 and the gate dielectric material 16). The sidewall spacer 28 may be a nitride material deposited by a conventional deposition process, e.g., CVD, followed by an isotropic etching process, as previously described herein. The sidewall spacer 28 may have a different shape and / or a different material than the sidewall spacer 20. In this way, the gate structure 19 may be an asymmetric gate structure. Also, both the gate structure 19 and the extrinsic base region 17 may have asymmetric sidewall spacers.

[0024] Still referring to Fig. 5, an emitter region 30 and a collector region 32 (e.g., raised extrinsic collector region) are formed on the semiconductor layer 12c, adjacent to the sidewall spacer 28 of the extrinsic base region 17 and the gate structure 19. As shown in Fig. As shown in Figure 5, the collector region 32 and the emitter region 30 may be raised through an epitaxial growth process. The raised collector region 32 is in electrical contact with the collector contact region 15 (e.g., intrinsic collector region) and the gate structure 19. In embodiments, the collector contact region 15 may be a Si material or a SiGe material. The SiGe material may be formed by subjecting the semiconductor layer 12c to a conventional Ge condensation process, as is known in the art. Also, the gate structure 19 separates the raised collector region 32 from the extrinsic base region 17.

[0025] Still referring to Fig. 5, the raised emitter region 30 and the raised collector region 32 may be epitaxial semiconductor material grown on the semiconductor layer 12c. The epitaxial semiconductor material may be, for example, a Si material. In more specific embodiments, the epitaxial semiconductor material may be a SiP material lightly doped with N+ dopants. In embodiments, the sidewall spacers 20, 28 electrically isolate each of the raised emitter region 30, the raised collector region 32, the extrinsic base region 17, and the gate structure 19 from each other, as will be apparent to those skilled in the art.

[0026] As in Fig. 6, the cap material 26 may be removed by a conventional etching process, e.g., CMP. In this way, the polysilicon material 24 of the extrinsic base region 17 and the gate material 18 of the gate structure 19 may be exposed. The structure may also undergo a rapid thermal anneal process. In this way, the P+ dopant of the polysilicon material 24, e.g., of the extrinsic base 17, may be driven into the semiconductor layer 12c, thereby forming an intrinsic base region 21. The N+ dopants of the raised emitter region 30 and raised collector region 32 may also be driven into the semiconductor layer 12c, where the N+ dopants of the raised collector region 32 contact the lightly doped semiconductor layer 12c beneath the gate structure 19, e.g., the collector contact region 15.Accordingly, the gate structure 19 is now in contact with the raised collector region 32 via the collector contact region 15 below the gate structure 19. In this way, the collector region 32 is a gate-controlled collector region.

[0027] In Fig. 7, a silicide 34 may be formed over the raised emitter region 30 and the raised collector region 32, in addition to over the polysilicon material 24 of the extrinsic base region 17 and the gate material 18 of the gate structure 19. As should be appreciated by those skilled in the art, the silicide process begins with a deposition of a thin transition metal layer, e.g., nickel, cobalt, or titanium, over fully formed and patterned semiconductor devices (e.g., extrinsic base region 17, emitter region 30, collector region 32, and gate structure 19). After deposition of the material, the structure is annealed, allowing the transition metal to react with exposed silicon (or another semiconductor material as described herein) in the active areas of the semiconductor device, thereby forming a low-resistance transition metal silicide.Following the reaction, any remaining transition metal is removed by chemical etching, leaving silicide contacts 34 in the active regions of the device.

[0028] Contacts 36 may be formed on the silicide 34. In embodiments, the contacts 36 may be tungsten or aluminum formed by conventional lithography, etching, and deposition processes. For example, an interlevel dielectric material 38 may be deposited over the structure, followed by via formation to expose the underlying silicide 34. The vias may be formed by conventional lithography and etching processes. A conductive material, e.g., tungsten or aluminum, may be deposited within the vias to form the contacts 36. Any residual material on the interlevel dielectric material 38 may be removed by a CMP process.

[0029] Fig. 8-11 show an alternative structure and respective manufacturing processes according to aspects of the present disclosure. In particular, Fig. 8 shows a structure 10a comprising an extrinsic base region 17a formed on a substrate 12. In embodiments, the substrate 12 includes the semiconductor handle wafer 12a, the insulator layer 12b, and the semiconductor layer 12c on the insulator layer 12b, as described above. In embodiments, the semiconductor layer 12c may be Si or SiGe material. In embodiments, the SiGe material may be formed by a conventional Ge condensation process, as previously noted herein.

[0030] The extrinsic base 17a may comprise polysilicon material 24 with a sidewall spacer 42 and cap material 40, as previously described herein. For example, the polysilicon material 24 and cap material 40 may be deposited over the substrate 12 as a blanket, followed by a patterning process and sidewall spacer formation. The polysilicon material 24 may be a P+ doped material used as an extrinsic base region of the lateral heterojunction bipolar transistor.

[0031] As further stated in Fig. As shown in Figure 9, a polysilicon material 44 may be formed on the sidewall spacer 42. In embodiments, the polysilicon material 44 may be epitaxially grown on the semiconductor layer 12c, followed by a patterning process. In this way, the polysilicon material 44 forms a sidewall of the extrinsic base 17a. Then, a sidewall spacer 46 may be formed over the polysilicon material 44 and the spacer 42. The sidewall spacers 46 may be a nitride material and / or oxide material formed by a conventional blanket deposition process followed by an anisotropic etch process.

[0032] The sidewall spacers 42 / 46 electrically isolate the extrinsic base region 17a from the raised emitter region 30. Also, the sidewall spacers 42 / 46 are thicker than the sidewall spacer 46, which electrically isolates the polysilicon material 44 from the raised collector region 32. Thus, the combination of the polysilicon material 44, the extrinsic base region 17a, and the respective sidewall spacers 42 / 46 forms an asymmetric structure.

[0033] In Fig. 10, the raised emitter region 30 and raised collector region 32 (e.g., raised extrinsic collector region) may be formed on the semiconductor layer 12c, adjacent to the sidewall spacer 46 of the extrinsic base region 17a and the polysilicon material 44. As shown in Fig. As shown in Figure 10, the raised collector region 32 is in electrical contact with the collector contact region 15 (e.g., intrinsic collector region). In embodiments, the collector contact region 15 may be Si material or SiGe material, as known in the art and previously described herein. The raised emitter region 30 and the raised collector region 32 may be an epitaxial semiconductor material grown on the semiconductor layer 12c, e.g., SiP material lightly doped with N+ dopants.

[0034] As further stated in Fig. As shown in Figure 11, the cap material 40 can be removed by a conventional etching process, e.g., CMP. In this way, the polysilicon materials 24, 44 are now exposed. The structure can also undergo a rapid thermal annealing process. In this way, the P+ dopant of the polysilicon material 24, e.g., the extrinsic base 17a, can be driven into the semiconductor layer 12c, thereby forming an intrinsic base region 21. The N+ dopants of the raised emitter region 30 and the raised collector region 32 are also driven into the semiconductor layer 12c, where the N+ dopants of the raised collector region 32 contact the lightly doped semiconductor layer 12c beneath the polysilicon material 44.

[0035] In Fig.11, a silicide 34 may be formed over the raised emitter region 30 and the raised collector region 32, in addition to over the polysilicon materials 24, 44. Contacts 36 may be formed contacting the silicide 34 as previously described herein, so no further explanation is necessary for understanding the present disclosure.

[0036] The transistor can be used in a system-on-chip (SoC) technology. The SoC is an integrated circuit (also known as a "chip") that integrates all the components of an electronic system on a single chip or substrate. Because the components are integrated on a single substrate, SoCs consume much less power and take up much less space than multi-chip designs with equivalent functionality. For this reason, SoCs are becoming the dominant force in the mobile computing (such as smartphones) and edge computing markets. SoCs are also used in embedded systems and the Internet of Things.

[0037] The process(es) described above are used in the fabrication of integrated circuit chips. The resulting integrated circuit chips may be distributed by the manufacturer in raw wafer form (i.e., a single wafer containing multiple unpackaged chips), as a bare die, or in packaged form. In the latter case, the chip is mounted in a single-chip package (such as a plastic carrier, with conductors attached to a motherboard or other higher-level carrier) or in a multi-chip package (such as a ceramic carrier containing one or both surface interconnects or buried interconnects). In either case, the chip is then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) a final product.The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products that include a display, a keyboard or other input device, and a central processor.

Claims

[1] Structure comprising: an extrinsic base region (17) vertically above a semiconductor substrate (12) and comprising asymmetric sidewall spacers on opposite sidewalls of the extrinsic base region (17); a collector region (32) on the semiconductor substrate (12) and separated from the extrinsic base region (17) by at least a first spacer (20) of the asymmetric sidewall spacers; an emitter region (30) on the semiconductor substrate (12) and separated from the extrinsic base region (17) by a second spacer (28) of the asymmetric sidewall spacers; a gate structure (19) adjacent to the collector region (32); and a sidewall spacer (28) on the gate structure (19), wherein the sidewall spacer (28) separates the gate structure (19) from the collector region (32) and the first spacer (20) separates the gate structure (19) from the extrinsic base region (17). [2] The structure of claim 1, wherein the extrinsic base region (17) comprises P+ doped polysilicon material. [3] The structure of claim 2, wherein the gate structure (19) is adjacent to and electrically connected to the collector region (32), the gate structure (19) also separating the collector region (32) from the extrinsic base region (17). [4] The structure of claim 3, further comprising a doped semiconductor collector contact region (15) under the gate structure (19), the doped semiconductor collector contact region (15) electrically connecting the gate structure (19) to the collector region (32). [5] The structure of claim 4, further comprising a gate contact to the gate structure (19). [6] Structure according to one of claims 1 to 5, wherein the first spacer (20) is different from the sidewall spacer (28). [7] Structure according to one of claims 1 to 6, wherein the sidewall spacer (28) and the second spacer (28) are made of a same material. [8] The structure of any one of claims 1 to 7, further comprising an intrinsic base region (21) vertically below the extrinsic base region (17), the intrinsic base region (21) comprising SiGe. [9] Structure comprising: an extrinsic base region (17a) vertically above a semiconductor substrate (12) and comprising asymmetric sidewall spacers on opposite sidewalls of the extrinsic base region (17a); a collector region (32) on the semiconductor substrate (12) and separated from the extrinsic base region (17a) by at least a first spacer (42) of the asymmetric sidewall spacers; an emitter region (30) on the semiconductor substrate (12) and separated from the extrinsic base region (17a) by a second spacer (42 / 46) of the asymmetric sidewall spacers; and a polysilicon spacer (44) adjacent to the first sidewall spacer (42) and electrically in contact with the collector region (32). [10] The structure of claim 9, further comprising a sidewall spacer (46) on the polysilicon spacer (44), wherein the sidewall spacer (46) separates the collector region (32) from the polysilicon spacer (44) and the first spacer (42) separates the polysilicon spacer (44) from the extrinsic base structure (17a). [11] The structure of claim 9, further comprising a doped semiconductor contact region under the polysilicon spacer (44), the doped semiconductor contact region connecting the polysilicon spacer (44) to the collector region (32). [12] The structure of claim 11, further comprising a contact electrically connected to the polysilicon spacer (44). [13] The structure of any one of claims 9 to 12, further comprising an intrinsic base region (21) vertically below the extrinsic base region (17a), the intrinsic base region (21) comprising SiGe. [14] Structure comprising: an extrinsic base region (17, 17a) vertically above an intrinsic base region (21) comprising semiconductor-on-insulator substrate material; a raised collector region (32) on the semiconductor-on-insulator substrate material; a raised emitter region (30) on the semiconductor-on-insulator substrate material; a first structure electrically isolating the extrinsic base region (17, 17a) from the raised emitter region (30); and a second structure electrically isolating the extrinsic base region (17, 17a) from the raised collector region (32), the second structure being of a different composition than the first structure, the first structure comprising a sidewall spacer (28, 42 / 46) and the second structure comprising a gate structure (19) with asymmetric sidewall spacers, the gate structure (19) being electrically connected to the raised collector region (32), and the sidewall spacer (28, 42 / 46) being different from one of the asymmetric sidewall spacers between the gate structure (19) and the extrinsic base region (17, 17a). [15] The structure of claim 14, wherein the second structure comprises a polysilicon spacer (44) electrically connected to the raised collector region (32). [16] The structure of claim 15, wherein the polysilicon spacer (44) comprises spacer material on opposite sidewalls, the spacer material being thinner than the spacer (28, 42 / 46) at the extrinsic base region (17, 17a) isolating the extrinsic base region (17, 17a) from the raised emitter region (30). [17] Structure according to one of claims 14 to 16, wherein the intrinsic base region (21) comprises SiGe. [18] Procedure comprising: Forming an extrinsic base region (17) vertically above a semiconductor substrate (12) and comprising asymmetric sidewall spacers (20, 28) on opposite sidewalls of the extrinsic base region (17); Forming a collector region (32) on the semiconductor substrate (12) and separated from the extrinsic base region (17) by at least a first spacer (20) of the asymmetric sidewall spacers; Forming an emitter region (30) on the semiconductor substrate (12) and separated from the extrinsic base region (32) by a second spacer (28) of the asymmetric sidewall spacers; Forming a gate structure (19) adjacent to the collector region (32); and Forming a sidewall spacer (28) on the gate structure (17), wherein the sidewall spacer (28) separates the gate structure (17) from the collector region (32) and the first spacer (20) separates the gate structure (19) from the extrinsic base region (17).

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